1 /*
2 * QEMU Sun Happy Meal Ethernet emulation
3 *
4 * Copyright (c) 2017 Mark Cave-Ayland
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/pci/pci_device.h"
27 #include "hw/qdev-properties.h"
28 #include "migration/vmstate.h"
29 #include "hw/net/mii.h"
30 #include "net/net.h"
31 #include "qemu/module.h"
32 #include "net/checksum.h"
33 #include "net/eth.h"
34 #include "system/system.h"
35 #include "trace.h"
36 #include "qom/object.h"
37
38 #define HME_REG_SIZE 0x8000
39
40 #define HME_SEB_REG_SIZE 0x2000
41
42 #define HME_SEBI_RESET 0x0
43 #define HME_SEB_RESET_ETX 0x1
44 #define HME_SEB_RESET_ERX 0x2
45
46 #define HME_SEBI_STAT 0x100
47 #define HME_SEBI_STAT_LINUXBUG 0x108
48 #define HME_SEB_STAT_RXTOHOST 0x10000
49 #define HME_SEB_STAT_NORXD 0x20000
50 #define HME_SEB_STAT_MIFIRQ 0x800000
51 #define HME_SEB_STAT_HOSTTOTX 0x1000000
52 #define HME_SEB_STAT_TXALL 0x2000000
53
54 #define HME_SEBI_IMASK 0x104
55 #define HME_SEBI_IMASK_LINUXBUG 0x10c
56
57 #define HME_ETX_REG_SIZE 0x2000
58
59 #define HME_ETXI_PENDING 0x0
60
61 #define HME_ETXI_RING 0x8
62 #define HME_ETXI_RING_ADDR 0xffffff00
63 #define HME_ETXI_RING_OFFSET 0xff
64
65 #define HME_ETXI_RSIZE 0x2c
66
67 #define HME_ERX_REG_SIZE 0x2000
68
69 #define HME_ERXI_CFG 0x0
70 #define HME_ERX_CFG_RINGSIZE 0x600
71 #define HME_ERX_CFG_RINGSIZE_SHIFT 9
72 #define HME_ERX_CFG_BYTEOFFSET 0x38
73 #define HME_ERX_CFG_BYTEOFFSET_SHIFT 3
74 #define HME_ERX_CFG_CSUMSTART 0x7f0000
75 #define HME_ERX_CFG_CSUMSHIFT 16
76
77 #define HME_ERXI_RING 0x4
78 #define HME_ERXI_RING_ADDR 0xffffff00
79 #define HME_ERXI_RING_OFFSET 0xff
80
81 #define HME_MAC_REG_SIZE 0x1000
82
83 #define HME_MACI_TXCFG 0x20c
84 #define HME_MAC_TXCFG_ENABLE 0x1
85
86 #define HME_MACI_RXCFG 0x30c
87 #define HME_MAC_RXCFG_ENABLE 0x1
88 #define HME_MAC_RXCFG_PMISC 0x40
89 #define HME_MAC_RXCFG_HENABLE 0x800
90
91 #define HME_MACI_MACADDR2 0x318
92 #define HME_MACI_MACADDR1 0x31c
93 #define HME_MACI_MACADDR0 0x320
94
95 #define HME_MACI_HASHTAB3 0x340
96 #define HME_MACI_HASHTAB2 0x344
97 #define HME_MACI_HASHTAB1 0x348
98 #define HME_MACI_HASHTAB0 0x34c
99
100 #define HME_MIF_REG_SIZE 0x20
101
102 #define HME_MIFI_FO 0xc
103 #define HME_MIF_FO_ST 0xc0000000
104 #define HME_MIF_FO_ST_SHIFT 30
105 #define HME_MIF_FO_OPC 0x30000000
106 #define HME_MIF_FO_OPC_SHIFT 28
107 #define HME_MIF_FO_PHYAD 0x0f800000
108 #define HME_MIF_FO_PHYAD_SHIFT 23
109 #define HME_MIF_FO_REGAD 0x007c0000
110 #define HME_MIF_FO_REGAD_SHIFT 18
111 #define HME_MIF_FO_TAMSB 0x20000
112 #define HME_MIF_FO_TALSB 0x10000
113 #define HME_MIF_FO_DATA 0xffff
114
115 #define HME_MIFI_CFG 0x10
116 #define HME_MIF_CFG_MDI0 0x100
117 #define HME_MIF_CFG_MDI1 0x200
118
119 #define HME_MIFI_IMASK 0x14
120
121 #define HME_MIFI_STAT 0x18
122
123
124 /* Wired HME PHY addresses */
125 #define HME_PHYAD_INTERNAL 1
126 #define HME_PHYAD_EXTERNAL 0
127
128 #define MII_COMMAND_START 0x1
129 #define MII_COMMAND_READ 0x2
130 #define MII_COMMAND_WRITE 0x1
131
132 #define TYPE_SUNHME "sunhme"
133 OBJECT_DECLARE_SIMPLE_TYPE(SunHMEState, SUNHME)
134
135 /* Maximum size of buffer */
136 #define HME_FIFO_SIZE 0x800
137
138 /* Size of TX/RX descriptor */
139 #define HME_DESC_SIZE 0x8
140
141 #define HME_XD_OWN 0x80000000
142 #define HME_XD_OFL 0x40000000
143 #define HME_XD_SOP 0x40000000
144 #define HME_XD_EOP 0x20000000
145 #define HME_XD_RXLENMSK 0x3fff0000
146 #define HME_XD_RXLENSHIFT 16
147 #define HME_XD_RXCKSUM 0xffff
148 #define HME_XD_TXLENMSK 0x00001fff
149 #define HME_XD_TXCKSUM 0x10000000
150 #define HME_XD_TXCSSTUFF 0xff00000
151 #define HME_XD_TXCSSTUFFSHIFT 20
152 #define HME_XD_TXCSSTART 0xfc000
153 #define HME_XD_TXCSSTARTSHIFT 14
154
155 #define HME_MII_REGS_SIZE 0x20
156
157 struct SunHMEState {
158 /*< private >*/
159 PCIDevice parent_obj;
160
161 NICState *nic;
162 NICConf conf;
163
164 MemoryRegion hme;
165 MemoryRegion sebreg;
166 MemoryRegion etxreg;
167 MemoryRegion erxreg;
168 MemoryRegion macreg;
169 MemoryRegion mifreg;
170
171 uint32_t sebregs[HME_SEB_REG_SIZE >> 2];
172 uint32_t etxregs[HME_ETX_REG_SIZE >> 2];
173 uint32_t erxregs[HME_ERX_REG_SIZE >> 2];
174 uint32_t macregs[HME_MAC_REG_SIZE >> 2];
175 uint32_t mifregs[HME_MIF_REG_SIZE >> 2];
176
177 uint16_t miiregs[HME_MII_REGS_SIZE];
178 };
179
180 static const Property sunhme_properties[] = {
181 DEFINE_NIC_PROPERTIES(SunHMEState, conf),
182 };
183
sunhme_reset_tx(SunHMEState * s)184 static void sunhme_reset_tx(SunHMEState *s)
185 {
186 /* Indicate TX reset complete */
187 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ETX;
188 }
189
sunhme_reset_rx(SunHMEState * s)190 static void sunhme_reset_rx(SunHMEState *s)
191 {
192 /* Indicate RX reset complete */
193 s->sebregs[HME_SEBI_RESET] &= ~HME_SEB_RESET_ERX;
194 }
195
sunhme_update_irq(SunHMEState * s)196 static void sunhme_update_irq(SunHMEState *s)
197 {
198 PCIDevice *d = PCI_DEVICE(s);
199 int level;
200
201 /* MIF interrupt mask (16-bit) */
202 uint32_t mifmask = ~(s->mifregs[HME_MIFI_IMASK >> 2]) & 0xffff;
203 uint32_t mif = s->mifregs[HME_MIFI_STAT >> 2] & mifmask;
204
205 /* Main SEB interrupt mask (include MIF status from above) */
206 uint32_t sebmask = ~(s->sebregs[HME_SEBI_IMASK >> 2]) &
207 ~HME_SEB_STAT_MIFIRQ;
208 uint32_t seb = s->sebregs[HME_SEBI_STAT >> 2] & sebmask;
209 if (mif) {
210 seb |= HME_SEB_STAT_MIFIRQ;
211 }
212
213 level = (seb ? 1 : 0);
214 trace_sunhme_update_irq(mifmask, mif, sebmask, seb, level);
215
216 pci_set_irq(d, level);
217 }
218
sunhme_seb_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)219 static void sunhme_seb_write(void *opaque, hwaddr addr,
220 uint64_t val, unsigned size)
221 {
222 SunHMEState *s = SUNHME(opaque);
223
224 trace_sunhme_seb_write(addr, val);
225
226 /* Handly buggy Linux drivers before 4.13 which have
227 the wrong offsets for HME_SEBI_STAT and HME_SEBI_IMASK */
228 switch (addr) {
229 case HME_SEBI_STAT_LINUXBUG:
230 addr = HME_SEBI_STAT;
231 break;
232 case HME_SEBI_IMASK_LINUXBUG:
233 addr = HME_SEBI_IMASK;
234 break;
235 default:
236 break;
237 }
238
239 switch (addr) {
240 case HME_SEBI_RESET:
241 if (val & HME_SEB_RESET_ETX) {
242 sunhme_reset_tx(s);
243 }
244 if (val & HME_SEB_RESET_ERX) {
245 sunhme_reset_rx(s);
246 }
247 val = s->sebregs[HME_SEBI_RESET >> 2];
248 break;
249 }
250
251 s->sebregs[addr >> 2] = val;
252 }
253
sunhme_seb_read(void * opaque,hwaddr addr,unsigned size)254 static uint64_t sunhme_seb_read(void *opaque, hwaddr addr,
255 unsigned size)
256 {
257 SunHMEState *s = SUNHME(opaque);
258 uint64_t val;
259
260 /* Handly buggy Linux drivers before 4.13 which have
261 the wrong offsets for HME_SEBI_STAT and HME_SEBI_IMASK */
262 switch (addr) {
263 case HME_SEBI_STAT_LINUXBUG:
264 addr = HME_SEBI_STAT;
265 break;
266 case HME_SEBI_IMASK_LINUXBUG:
267 addr = HME_SEBI_IMASK;
268 break;
269 default:
270 break;
271 }
272
273 val = s->sebregs[addr >> 2];
274
275 switch (addr) {
276 case HME_SEBI_STAT:
277 /* Autoclear status (except MIF) */
278 s->sebregs[HME_SEBI_STAT >> 2] &= HME_SEB_STAT_MIFIRQ;
279 sunhme_update_irq(s);
280 break;
281 }
282
283 trace_sunhme_seb_read(addr, val);
284
285 return val;
286 }
287
288 static const MemoryRegionOps sunhme_seb_ops = {
289 .read = sunhme_seb_read,
290 .write = sunhme_seb_write,
291 .endianness = DEVICE_LITTLE_ENDIAN,
292 .valid = {
293 .min_access_size = 4,
294 .max_access_size = 4,
295 },
296 };
297
298 static void sunhme_transmit(SunHMEState *s);
299
sunhme_etx_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)300 static void sunhme_etx_write(void *opaque, hwaddr addr,
301 uint64_t val, unsigned size)
302 {
303 SunHMEState *s = SUNHME(opaque);
304
305 trace_sunhme_etx_write(addr, val);
306
307 switch (addr) {
308 case HME_ETXI_PENDING:
309 if (val) {
310 sunhme_transmit(s);
311 }
312 break;
313 }
314
315 s->etxregs[addr >> 2] = val;
316 }
317
sunhme_etx_read(void * opaque,hwaddr addr,unsigned size)318 static uint64_t sunhme_etx_read(void *opaque, hwaddr addr,
319 unsigned size)
320 {
321 SunHMEState *s = SUNHME(opaque);
322 uint64_t val;
323
324 val = s->etxregs[addr >> 2];
325
326 trace_sunhme_etx_read(addr, val);
327
328 return val;
329 }
330
331 static const MemoryRegionOps sunhme_etx_ops = {
332 .read = sunhme_etx_read,
333 .write = sunhme_etx_write,
334 .endianness = DEVICE_LITTLE_ENDIAN,
335 .valid = {
336 .min_access_size = 4,
337 .max_access_size = 4,
338 },
339 };
340
sunhme_erx_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)341 static void sunhme_erx_write(void *opaque, hwaddr addr,
342 uint64_t val, unsigned size)
343 {
344 SunHMEState *s = SUNHME(opaque);
345
346 trace_sunhme_erx_write(addr, val);
347
348 s->erxregs[addr >> 2] = val;
349 }
350
sunhme_erx_read(void * opaque,hwaddr addr,unsigned size)351 static uint64_t sunhme_erx_read(void *opaque, hwaddr addr,
352 unsigned size)
353 {
354 SunHMEState *s = SUNHME(opaque);
355 uint64_t val;
356
357 val = s->erxregs[addr >> 2];
358
359 trace_sunhme_erx_read(addr, val);
360
361 return val;
362 }
363
364 static const MemoryRegionOps sunhme_erx_ops = {
365 .read = sunhme_erx_read,
366 .write = sunhme_erx_write,
367 .endianness = DEVICE_LITTLE_ENDIAN,
368 .valid = {
369 .min_access_size = 4,
370 .max_access_size = 4,
371 },
372 };
373
sunhme_mac_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)374 static void sunhme_mac_write(void *opaque, hwaddr addr,
375 uint64_t val, unsigned size)
376 {
377 SunHMEState *s = SUNHME(opaque);
378 uint64_t oldval = s->macregs[addr >> 2];
379
380 trace_sunhme_mac_write(addr, val);
381
382 s->macregs[addr >> 2] = val;
383
384 switch (addr) {
385 case HME_MACI_RXCFG:
386 if (!(oldval & HME_MAC_RXCFG_ENABLE) &&
387 (val & HME_MAC_RXCFG_ENABLE)) {
388 qemu_flush_queued_packets(qemu_get_queue(s->nic));
389 }
390 break;
391 }
392 }
393
sunhme_mac_read(void * opaque,hwaddr addr,unsigned size)394 static uint64_t sunhme_mac_read(void *opaque, hwaddr addr,
395 unsigned size)
396 {
397 SunHMEState *s = SUNHME(opaque);
398 uint64_t val;
399
400 val = s->macregs[addr >> 2];
401
402 trace_sunhme_mac_read(addr, val);
403
404 return val;
405 }
406
407 static const MemoryRegionOps sunhme_mac_ops = {
408 .read = sunhme_mac_read,
409 .write = sunhme_mac_write,
410 .endianness = DEVICE_LITTLE_ENDIAN,
411 .valid = {
412 .min_access_size = 4,
413 .max_access_size = 4,
414 },
415 };
416
sunhme_mii_write(SunHMEState * s,uint8_t reg,uint16_t data)417 static void sunhme_mii_write(SunHMEState *s, uint8_t reg, uint16_t data)
418 {
419 trace_sunhme_mii_write(reg, data);
420
421 switch (reg) {
422 case MII_BMCR:
423 if (data & MII_BMCR_RESET) {
424 /* Autoclear reset bit, enable auto negotiation */
425 data &= ~MII_BMCR_RESET;
426 data |= MII_BMCR_AUTOEN;
427 }
428 if (data & MII_BMCR_ANRESTART) {
429 /* Autoclear auto negotiation restart */
430 data &= ~MII_BMCR_ANRESTART;
431
432 /* Indicate negotiation complete */
433 s->miiregs[MII_BMSR] |= MII_BMSR_AN_COMP;
434
435 if (!qemu_get_queue(s->nic)->link_down) {
436 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD;
437 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST;
438 }
439 }
440 break;
441 }
442
443 s->miiregs[reg] = data;
444 }
445
sunhme_mii_read(SunHMEState * s,uint8_t reg)446 static uint16_t sunhme_mii_read(SunHMEState *s, uint8_t reg)
447 {
448 uint16_t data = s->miiregs[reg];
449
450 trace_sunhme_mii_read(reg, data);
451
452 return data;
453 }
454
sunhme_mif_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)455 static void sunhme_mif_write(void *opaque, hwaddr addr,
456 uint64_t val, unsigned size)
457 {
458 SunHMEState *s = SUNHME(opaque);
459 uint8_t cmd, reg;
460 uint16_t data;
461
462 trace_sunhme_mif_write(addr, val);
463
464 switch (addr) {
465 case HME_MIFI_CFG:
466 /* Mask the read-only bits */
467 val &= ~(HME_MIF_CFG_MDI0 | HME_MIF_CFG_MDI1);
468 val |= s->mifregs[HME_MIFI_CFG >> 2] &
469 (HME_MIF_CFG_MDI0 | HME_MIF_CFG_MDI1);
470 break;
471 case HME_MIFI_FO:
472 /* Detect start of MII command */
473 if ((val & HME_MIF_FO_ST) >> HME_MIF_FO_ST_SHIFT
474 != MII_COMMAND_START) {
475 val |= HME_MIF_FO_TALSB;
476 break;
477 }
478
479 /* Internal phy only */
480 if ((val & HME_MIF_FO_PHYAD) >> HME_MIF_FO_PHYAD_SHIFT
481 != HME_PHYAD_INTERNAL) {
482 val |= HME_MIF_FO_TALSB;
483 break;
484 }
485
486 cmd = (val & HME_MIF_FO_OPC) >> HME_MIF_FO_OPC_SHIFT;
487 reg = (val & HME_MIF_FO_REGAD) >> HME_MIF_FO_REGAD_SHIFT;
488 data = (val & HME_MIF_FO_DATA);
489
490 switch (cmd) {
491 case MII_COMMAND_WRITE:
492 sunhme_mii_write(s, reg, data);
493 break;
494
495 case MII_COMMAND_READ:
496 val &= ~HME_MIF_FO_DATA;
497 val |= sunhme_mii_read(s, reg);
498 break;
499 }
500
501 val |= HME_MIF_FO_TALSB;
502 break;
503 }
504
505 s->mifregs[addr >> 2] = val;
506 }
507
sunhme_mif_read(void * opaque,hwaddr addr,unsigned size)508 static uint64_t sunhme_mif_read(void *opaque, hwaddr addr,
509 unsigned size)
510 {
511 SunHMEState *s = SUNHME(opaque);
512 uint64_t val;
513
514 val = s->mifregs[addr >> 2];
515
516 switch (addr) {
517 case HME_MIFI_STAT:
518 /* Autoclear MIF interrupt status */
519 s->mifregs[HME_MIFI_STAT >> 2] = 0;
520 sunhme_update_irq(s);
521 break;
522 }
523
524 trace_sunhme_mif_read(addr, val);
525
526 return val;
527 }
528
529 static const MemoryRegionOps sunhme_mif_ops = {
530 .read = sunhme_mif_read,
531 .write = sunhme_mif_write,
532 .endianness = DEVICE_LITTLE_ENDIAN,
533 .valid = {
534 .min_access_size = 4,
535 .max_access_size = 4,
536 },
537 };
538
sunhme_transmit_frame(SunHMEState * s,uint8_t * buf,int size)539 static void sunhme_transmit_frame(SunHMEState *s, uint8_t *buf, int size)
540 {
541 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
542 }
543
sunhme_get_tx_ring_count(SunHMEState * s)544 static inline int sunhme_get_tx_ring_count(SunHMEState *s)
545 {
546 return (s->etxregs[HME_ETXI_RSIZE >> 2] + 1) << 4;
547 }
548
sunhme_get_tx_ring_nr(SunHMEState * s)549 static inline int sunhme_get_tx_ring_nr(SunHMEState *s)
550 {
551 return s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_OFFSET;
552 }
553
sunhme_set_tx_ring_nr(SunHMEState * s,int i)554 static inline void sunhme_set_tx_ring_nr(SunHMEState *s, int i)
555 {
556 uint32_t ring = s->etxregs[HME_ETXI_RING >> 2] & ~HME_ETXI_RING_OFFSET;
557 ring |= i & HME_ETXI_RING_OFFSET;
558
559 s->etxregs[HME_ETXI_RING >> 2] = ring;
560 }
561
sunhme_transmit(SunHMEState * s)562 static void sunhme_transmit(SunHMEState *s)
563 {
564 PCIDevice *d = PCI_DEVICE(s);
565 dma_addr_t tb, addr;
566 uint32_t intstatus, status, buffer, sum = 0;
567 int cr, nr, len, xmit_pos, csum_offset = 0, csum_stuff_offset = 0;
568 uint16_t csum = 0;
569 uint8_t xmit_buffer[HME_FIFO_SIZE];
570
571 tb = s->etxregs[HME_ETXI_RING >> 2] & HME_ETXI_RING_ADDR;
572 nr = sunhme_get_tx_ring_count(s);
573 cr = sunhme_get_tx_ring_nr(s);
574
575 pci_dma_read(d, tb + cr * HME_DESC_SIZE, &status, 4);
576 pci_dma_read(d, tb + cr * HME_DESC_SIZE + 4, &buffer, 4);
577
578 xmit_pos = 0;
579 while (status & HME_XD_OWN) {
580 trace_sunhme_tx_desc(buffer, status, cr, nr);
581
582 /* Copy data into transmit buffer */
583 addr = buffer;
584 len = status & HME_XD_TXLENMSK;
585
586 if (xmit_pos + len > HME_FIFO_SIZE) {
587 len = HME_FIFO_SIZE - xmit_pos;
588 }
589
590 pci_dma_read(d, addr, &xmit_buffer[xmit_pos], len);
591 xmit_pos += len;
592
593 /* Detect start of packet for TX checksum */
594 if (status & HME_XD_SOP) {
595 sum = 0;
596 csum_offset = (status & HME_XD_TXCSSTART) >> HME_XD_TXCSSTARTSHIFT;
597 csum_stuff_offset = (status & HME_XD_TXCSSTUFF) >>
598 HME_XD_TXCSSTUFFSHIFT;
599 }
600
601 if (status & HME_XD_TXCKSUM) {
602 /* Only start calculation from csum_offset */
603 if (xmit_pos - len <= csum_offset && xmit_pos > csum_offset) {
604 sum += net_checksum_add(xmit_pos - csum_offset,
605 xmit_buffer + csum_offset);
606 trace_sunhme_tx_xsum_add(csum_offset, xmit_pos - csum_offset);
607 } else {
608 sum += net_checksum_add(len, xmit_buffer + xmit_pos - len);
609 trace_sunhme_tx_xsum_add(xmit_pos - len, len);
610 }
611 }
612
613 /* Detect end of packet for TX checksum */
614 if (status & HME_XD_EOP) {
615 /* Stuff the checksum if required */
616 if (status & HME_XD_TXCKSUM) {
617 csum = net_checksum_finish(sum);
618 stw_be_p(xmit_buffer + csum_stuff_offset, csum);
619 trace_sunhme_tx_xsum_stuff(csum, csum_stuff_offset);
620 }
621
622 if (s->macregs[HME_MACI_TXCFG >> 2] & HME_MAC_TXCFG_ENABLE) {
623 sunhme_transmit_frame(s, xmit_buffer, xmit_pos);
624 trace_sunhme_tx_done(xmit_pos);
625 }
626 }
627
628 /* Update status */
629 status &= ~HME_XD_OWN;
630 pci_dma_write(d, tb + cr * HME_DESC_SIZE, &status, 4);
631
632 /* Move onto next descriptor */
633 cr++;
634 if (cr >= nr) {
635 cr = 0;
636 }
637 sunhme_set_tx_ring_nr(s, cr);
638
639 pci_dma_read(d, tb + cr * HME_DESC_SIZE, &status, 4);
640 pci_dma_read(d, tb + cr * HME_DESC_SIZE + 4, &buffer, 4);
641
642 /* Indicate TX complete */
643 intstatus = s->sebregs[HME_SEBI_STAT >> 2];
644 intstatus |= HME_SEB_STAT_HOSTTOTX;
645 s->sebregs[HME_SEBI_STAT >> 2] = intstatus;
646
647 /* Autoclear TX pending */
648 s->etxregs[HME_ETXI_PENDING >> 2] = 0;
649
650 sunhme_update_irq(s);
651 }
652
653 /* TX FIFO now clear */
654 intstatus = s->sebregs[HME_SEBI_STAT >> 2];
655 intstatus |= HME_SEB_STAT_TXALL;
656 s->sebregs[HME_SEBI_STAT >> 2] = intstatus;
657 sunhme_update_irq(s);
658 }
659
sunhme_can_receive(NetClientState * nc)660 static bool sunhme_can_receive(NetClientState *nc)
661 {
662 SunHMEState *s = qemu_get_nic_opaque(nc);
663
664 return !!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE);
665 }
666
sunhme_link_status_changed(NetClientState * nc)667 static void sunhme_link_status_changed(NetClientState *nc)
668 {
669 SunHMEState *s = qemu_get_nic_opaque(nc);
670
671 if (nc->link_down) {
672 s->miiregs[MII_ANLPAR] &= ~MII_ANLPAR_TXFD;
673 s->miiregs[MII_BMSR] &= ~MII_BMSR_LINK_ST;
674 } else {
675 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD;
676 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST;
677 }
678
679 /* Exact bits unknown */
680 s->mifregs[HME_MIFI_STAT >> 2] = 0xffff;
681 sunhme_update_irq(s);
682 }
683
sunhme_get_rx_ring_count(SunHMEState * s)684 static inline int sunhme_get_rx_ring_count(SunHMEState *s)
685 {
686 uint32_t rings = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_RINGSIZE)
687 >> HME_ERX_CFG_RINGSIZE_SHIFT;
688
689 switch (rings) {
690 case 0:
691 return 32;
692 case 1:
693 return 64;
694 case 2:
695 return 128;
696 case 3:
697 return 256;
698 }
699
700 return 0;
701 }
702
sunhme_get_rx_ring_nr(SunHMEState * s)703 static inline int sunhme_get_rx_ring_nr(SunHMEState *s)
704 {
705 return s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_OFFSET;
706 }
707
sunhme_set_rx_ring_nr(SunHMEState * s,int i)708 static inline void sunhme_set_rx_ring_nr(SunHMEState *s, int i)
709 {
710 uint32_t ring = s->erxregs[HME_ERXI_RING >> 2] & ~HME_ERXI_RING_OFFSET;
711 ring |= i & HME_ERXI_RING_OFFSET;
712
713 s->erxregs[HME_ERXI_RING >> 2] = ring;
714 }
715
sunhme_receive(NetClientState * nc,const uint8_t * buf,size_t size)716 static ssize_t sunhme_receive(NetClientState *nc, const uint8_t *buf,
717 size_t size)
718 {
719 SunHMEState *s = qemu_get_nic_opaque(nc);
720 PCIDevice *d = PCI_DEVICE(s);
721 dma_addr_t rb, addr;
722 uint32_t intstatus, status, buffer, buffersize, sum;
723 uint16_t csum;
724 int nr, cr, len, rxoffset, csum_offset;
725
726 trace_sunhme_rx_incoming(size);
727
728 /* Do nothing if MAC RX disabled */
729 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_ENABLE)) {
730 return 0;
731 }
732
733 trace_sunhme_rx_filter_destmac(buf[0], buf[1], buf[2],
734 buf[3], buf[4], buf[5]);
735
736 /* Check destination MAC address */
737 if (!(s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_PMISC)) {
738 /* Try and match local MAC address */
739 if (((s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff00) >> 8) == buf[0] &&
740 (s->macregs[HME_MACI_MACADDR0 >> 2] & 0xff) == buf[1] &&
741 ((s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff00) >> 8) == buf[2] &&
742 (s->macregs[HME_MACI_MACADDR1 >> 2] & 0xff) == buf[3] &&
743 ((s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff00) >> 8) == buf[4] &&
744 (s->macregs[HME_MACI_MACADDR2 >> 2] & 0xff) == buf[5]) {
745 /* Matched local MAC address */
746 trace_sunhme_rx_filter_local_match();
747 } else if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
748 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
749 /* Matched broadcast address */
750 trace_sunhme_rx_filter_bcast_match();
751 } else if (s->macregs[HME_MACI_RXCFG >> 2] & HME_MAC_RXCFG_HENABLE) {
752 /* Didn't match local address, check hash filter */
753 int mcast_idx = net_crc32_le(buf, ETH_ALEN) >> 26;
754 if (!(s->macregs[(HME_MACI_HASHTAB0 >> 2) - (mcast_idx >> 4)] &
755 (1 << (mcast_idx & 0xf)))) {
756 /* Didn't match hash filter */
757 trace_sunhme_rx_filter_hash_nomatch();
758 trace_sunhme_rx_filter_reject();
759 return -1;
760 } else {
761 trace_sunhme_rx_filter_hash_match();
762 }
763 } else {
764 /* Not for us */
765 trace_sunhme_rx_filter_reject();
766 return -1;
767 }
768 } else {
769 trace_sunhme_rx_filter_promisc_match();
770 }
771
772 trace_sunhme_rx_filter_accept();
773
774 rb = s->erxregs[HME_ERXI_RING >> 2] & HME_ERXI_RING_ADDR;
775 nr = sunhme_get_rx_ring_count(s);
776 cr = sunhme_get_rx_ring_nr(s);
777
778 pci_dma_read(d, rb + cr * HME_DESC_SIZE, &status, 4);
779 pci_dma_read(d, rb + cr * HME_DESC_SIZE + 4, &buffer, 4);
780
781 /* If we don't own the current descriptor then indicate overflow error */
782 if (!(status & HME_XD_OWN)) {
783 s->sebregs[HME_SEBI_STAT >> 2] |= HME_SEB_STAT_NORXD;
784 sunhme_update_irq(s);
785 trace_sunhme_rx_norxd();
786 return -1;
787 }
788
789 rxoffset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_BYTEOFFSET) >>
790 HME_ERX_CFG_BYTEOFFSET_SHIFT;
791
792 addr = buffer + rxoffset;
793 buffersize = (status & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT;
794
795 /* Detect receive overflow */
796 len = size;
797 if (size > buffersize) {
798 status |= HME_XD_OFL;
799 len = buffersize;
800 }
801
802 pci_dma_write(d, addr, buf, len);
803
804 trace_sunhme_rx_desc(buffer, rxoffset, status, len, cr, nr);
805
806 /* Calculate the receive checksum */
807 csum_offset = (s->erxregs[HME_ERXI_CFG >> 2] & HME_ERX_CFG_CSUMSTART) >>
808 HME_ERX_CFG_CSUMSHIFT << 1;
809 sum = 0;
810 sum += net_checksum_add(len - csum_offset, (uint8_t *)buf + csum_offset);
811 csum = net_checksum_finish(sum);
812
813 trace_sunhme_rx_xsum_calc(csum);
814
815 /* Update status */
816 status &= ~HME_XD_OWN;
817 status &= ~HME_XD_RXLENMSK;
818 status |= len << HME_XD_RXLENSHIFT;
819 status &= ~HME_XD_RXCKSUM;
820 status |= csum;
821
822 pci_dma_write(d, rb + cr * HME_DESC_SIZE, &status, 4);
823
824 cr++;
825 if (cr >= nr) {
826 cr = 0;
827 }
828
829 sunhme_set_rx_ring_nr(s, cr);
830
831 /* Indicate RX complete */
832 intstatus = s->sebregs[HME_SEBI_STAT >> 2];
833 intstatus |= HME_SEB_STAT_RXTOHOST;
834 s->sebregs[HME_SEBI_STAT >> 2] = intstatus;
835
836 sunhme_update_irq(s);
837
838 return len;
839 }
840
841 static NetClientInfo net_sunhme_info = {
842 .type = NET_CLIENT_DRIVER_NIC,
843 .size = sizeof(NICState),
844 .can_receive = sunhme_can_receive,
845 .receive = sunhme_receive,
846 .link_status_changed = sunhme_link_status_changed,
847 };
848
sunhme_realize(PCIDevice * pci_dev,Error ** errp)849 static void sunhme_realize(PCIDevice *pci_dev, Error **errp)
850 {
851 SunHMEState *s = SUNHME(pci_dev);
852 DeviceState *d = DEVICE(pci_dev);
853 uint8_t *pci_conf;
854
855 pci_conf = pci_dev->config;
856 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
857
858 memory_region_init(&s->hme, OBJECT(pci_dev), "sunhme", HME_REG_SIZE);
859 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->hme);
860
861 memory_region_init_io(&s->sebreg, OBJECT(pci_dev), &sunhme_seb_ops, s,
862 "sunhme.seb", HME_SEB_REG_SIZE);
863 memory_region_add_subregion(&s->hme, 0, &s->sebreg);
864
865 memory_region_init_io(&s->etxreg, OBJECT(pci_dev), &sunhme_etx_ops, s,
866 "sunhme.etx", HME_ETX_REG_SIZE);
867 memory_region_add_subregion(&s->hme, 0x2000, &s->etxreg);
868
869 memory_region_init_io(&s->erxreg, OBJECT(pci_dev), &sunhme_erx_ops, s,
870 "sunhme.erx", HME_ERX_REG_SIZE);
871 memory_region_add_subregion(&s->hme, 0x4000, &s->erxreg);
872
873 memory_region_init_io(&s->macreg, OBJECT(pci_dev), &sunhme_mac_ops, s,
874 "sunhme.mac", HME_MAC_REG_SIZE);
875 memory_region_add_subregion(&s->hme, 0x6000, &s->macreg);
876
877 memory_region_init_io(&s->mifreg, OBJECT(pci_dev), &sunhme_mif_ops, s,
878 "sunhme.mif", HME_MIF_REG_SIZE);
879 memory_region_add_subregion(&s->hme, 0x7000, &s->mifreg);
880
881 qemu_macaddr_default_if_unset(&s->conf.macaddr);
882 s->nic = qemu_new_nic(&net_sunhme_info, &s->conf,
883 object_get_typename(OBJECT(d)), d->id,
884 &d->mem_reentrancy_guard, s);
885 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
886 }
887
sunhme_instance_init(Object * obj)888 static void sunhme_instance_init(Object *obj)
889 {
890 SunHMEState *s = SUNHME(obj);
891
892 device_add_bootindex_property(obj, &s->conf.bootindex,
893 "bootindex", "/ethernet-phy@0",
894 DEVICE(obj));
895 }
896
sunhme_reset(DeviceState * ds)897 static void sunhme_reset(DeviceState *ds)
898 {
899 SunHMEState *s = SUNHME(ds);
900
901 /* Configure internal transceiver */
902 s->mifregs[HME_MIFI_CFG >> 2] |= HME_MIF_CFG_MDI0;
903
904 /* Advertise auto, 100Mbps FD */
905 s->miiregs[MII_ANAR] = MII_ANAR_TXFD;
906 s->miiregs[MII_BMSR] = MII_BMSR_AUTONEG | MII_BMSR_100TX_FD |
907 MII_BMSR_AN_COMP;
908
909 if (!qemu_get_queue(s->nic)->link_down) {
910 s->miiregs[MII_ANLPAR] |= MII_ANLPAR_TXFD;
911 s->miiregs[MII_BMSR] |= MII_BMSR_LINK_ST;
912 }
913
914 /* Set manufacturer */
915 s->miiregs[MII_PHYID1] = DP83840_PHYID1;
916 s->miiregs[MII_PHYID2] = DP83840_PHYID2;
917
918 /* Configure default interrupt mask */
919 s->mifregs[HME_MIFI_IMASK >> 2] = 0xffff;
920 s->sebregs[HME_SEBI_IMASK >> 2] = 0xff7fffff;
921 }
922
923 static const VMStateDescription vmstate_hme = {
924 .name = "sunhme",
925 .version_id = 0,
926 .minimum_version_id = 0,
927 .fields = (const VMStateField[]) {
928 VMSTATE_PCI_DEVICE(parent_obj, SunHMEState),
929 VMSTATE_MACADDR(conf.macaddr, SunHMEState),
930 VMSTATE_UINT32_ARRAY(sebregs, SunHMEState, (HME_SEB_REG_SIZE >> 2)),
931 VMSTATE_UINT32_ARRAY(etxregs, SunHMEState, (HME_ETX_REG_SIZE >> 2)),
932 VMSTATE_UINT32_ARRAY(erxregs, SunHMEState, (HME_ERX_REG_SIZE >> 2)),
933 VMSTATE_UINT32_ARRAY(macregs, SunHMEState, (HME_MAC_REG_SIZE >> 2)),
934 VMSTATE_UINT32_ARRAY(mifregs, SunHMEState, (HME_MIF_REG_SIZE >> 2)),
935 VMSTATE_UINT16_ARRAY(miiregs, SunHMEState, HME_MII_REGS_SIZE),
936 VMSTATE_END_OF_LIST()
937 }
938 };
939
sunhme_class_init(ObjectClass * klass,const void * data)940 static void sunhme_class_init(ObjectClass *klass, const void *data)
941 {
942 DeviceClass *dc = DEVICE_CLASS(klass);
943 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
944
945 k->realize = sunhme_realize;
946 k->vendor_id = PCI_VENDOR_ID_SUN;
947 k->device_id = PCI_DEVICE_ID_SUN_HME;
948 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
949 dc->vmsd = &vmstate_hme;
950 device_class_set_legacy_reset(dc, sunhme_reset);
951 device_class_set_props(dc, sunhme_properties);
952 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
953 }
954
955 static const TypeInfo sunhme_info = {
956 .name = TYPE_SUNHME,
957 .parent = TYPE_PCI_DEVICE,
958 .class_init = sunhme_class_init,
959 .instance_size = sizeof(SunHMEState),
960 .instance_init = sunhme_instance_init,
961 .interfaces = (const InterfaceInfo[]) {
962 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
963 { }
964 }
965 };
966
sunhme_register_types(void)967 static void sunhme_register_types(void)
968 {
969 type_register_static(&sunhme_info);
970 }
971
972 type_init(sunhme_register_types)
973