1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */
3
4 #ifndef _HINIC3_HW_INTF_H_
5 #define _HINIC3_HW_INTF_H_
6
7 #include <linux/bits.h>
8 #include <linux/types.h>
9
10 #define MGMT_MSG_CMD_OP_SET 1
11 #define MGMT_MSG_CMD_OP_GET 0
12
13 #define MGMT_STATUS_PF_SET_VF_ALREADY 0x4
14 #define MGMT_STATUS_EXIST 0x6
15 #define MGMT_STATUS_CMD_UNSUPPORTED 0xFF
16
17 #define MGMT_MSG_POLLING_TIMEOUT 0
18
19 struct mgmt_msg_head {
20 u8 status;
21 u8 version;
22 u8 rsvd0[6];
23 };
24
25 struct mgmt_msg_params {
26 const void *buf_in;
27 u32 in_size;
28 void *buf_out;
29 u32 expected_out_size;
30 u32 timeout_ms;
31 };
32
33 /* CMDQ MODULE_TYPE */
34 enum mgmt_mod_type {
35 /* HW communication module */
36 MGMT_MOD_COMM = 0,
37 /* L2NIC module */
38 MGMT_MOD_L2NIC = 1,
39 /* Configuration module */
40 MGMT_MOD_CFGM = 7,
41 MGMT_MOD_HILINK = 14,
42 /* hardware max module id */
43 MGMT_MOD_HW_MAX = 20,
44 };
45
mgmt_msg_params_init_default(struct mgmt_msg_params * msg_params,void * inout_buf,u32 buf_size)46 static inline void mgmt_msg_params_init_default(struct mgmt_msg_params *msg_params,
47 void *inout_buf, u32 buf_size)
48 {
49 msg_params->buf_in = inout_buf;
50 msg_params->buf_out = inout_buf;
51 msg_params->in_size = buf_size;
52 msg_params->expected_out_size = buf_size;
53 msg_params->timeout_ms = 0;
54 }
55
56 enum cfg_cmd {
57 CFG_CMD_GET_DEV_CAP = 0,
58 };
59
60 /* Device capabilities, defined by hw */
61 struct cfg_cmd_dev_cap {
62 struct mgmt_msg_head head;
63
64 u16 func_id;
65 u16 rsvd1;
66
67 /* Public resources */
68 u8 host_id;
69 u8 ep_id;
70 u8 er_id;
71 u8 port_id;
72
73 u16 host_total_func;
74 u8 host_pf_num;
75 u8 pf_id_start;
76 u16 host_vf_num;
77 u16 vf_id_start;
78 u8 host_oq_id_mask_val;
79 u8 timer_en;
80 u8 host_valid_bitmap;
81 u8 rsvd_host;
82
83 u16 svc_cap_en;
84 u16 max_vf;
85 u8 flexq_en;
86 u8 valid_cos_bitmap;
87 u8 port_cos_valid_bitmap;
88 u8 rsvd2[45];
89
90 /* l2nic */
91 u16 nic_max_sq_id;
92 u16 nic_max_rq_id;
93 u16 nic_default_num_queues;
94
95 u8 rsvd3[250];
96 };
97
98 /* COMM Commands between Driver to fw */
99 enum comm_cmd {
100 /* Commands for clearing FLR and resources */
101 COMM_CMD_FUNC_RESET = 0,
102 COMM_CMD_FEATURE_NEGO = 1,
103 COMM_CMD_FLUSH_DOORBELL = 2,
104 COMM_CMD_START_FLUSH = 3,
105 COMM_CMD_GET_GLOBAL_ATTR = 5,
106 COMM_CMD_SET_FUNC_SVC_USED_STATE = 7,
107
108 /* Driver Configuration Commands */
109 COMM_CMD_SET_CMDQ_CTXT = 20,
110 COMM_CMD_SET_VAT = 21,
111 COMM_CMD_CFG_PAGESIZE = 22,
112 COMM_CMD_CFG_MSIX_CTRL_REG = 23,
113 COMM_CMD_SET_CEQ_CTRL_REG = 24,
114 COMM_CMD_SET_DMA_ATTR = 25,
115
116 /* Commands for obtaining information */
117 COMM_CMD_SYNC_TIME = 62,
118 COMM_CMD_SEND_BDF_INFO = 64,
119 };
120
121 struct comm_cmd_cfg_msix_ctrl_reg {
122 struct mgmt_msg_head head;
123 u16 func_id;
124 u8 opcode;
125 u8 rsvd1;
126 u16 msix_index;
127 u8 pending_cnt;
128 u8 coalesce_timer_cnt;
129 u8 resend_timer_cnt;
130 u8 lli_timer_cnt;
131 u8 lli_credit_cnt;
132 u8 rsvd2[5];
133 };
134
135 enum comm_func_reset_bits {
136 COMM_FUNC_RESET_BIT_FLUSH = BIT(0),
137 COMM_FUNC_RESET_BIT_MQM = BIT(1),
138 COMM_FUNC_RESET_BIT_SMF = BIT(2),
139 COMM_FUNC_RESET_BIT_PF_BW_CFG = BIT(3),
140
141 COMM_FUNC_RESET_BIT_COMM = BIT(10),
142 /* clear mbox and aeq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
143 COMM_FUNC_RESET_BIT_COMM_MGMT_CH = BIT(11),
144 /* clear cmdq and ceq, The COMM_FUNC_RESET_BIT_COMM bit must be set */
145 COMM_FUNC_RESET_BIT_COMM_CMD_CH = BIT(12),
146 COMM_FUNC_RESET_BIT_NIC = BIT(13),
147 };
148
149 #define COMM_FUNC_RESET_FLAG \
150 (COMM_FUNC_RESET_BIT_COMM | COMM_FUNC_RESET_BIT_COMM_CMD_CH | \
151 COMM_FUNC_RESET_BIT_FLUSH | COMM_FUNC_RESET_BIT_MQM | \
152 COMM_FUNC_RESET_BIT_SMF | COMM_FUNC_RESET_BIT_PF_BW_CFG)
153
154 struct comm_cmd_func_reset {
155 struct mgmt_msg_head head;
156 u16 func_id;
157 u16 rsvd1[3];
158 u64 reset_flag;
159 };
160
161 #define COMM_MAX_FEATURE_QWORD 4
162 struct comm_cmd_feature_nego {
163 struct mgmt_msg_head head;
164 u16 func_id;
165 u8 opcode;
166 u8 rsvd;
167 u64 s_feature[COMM_MAX_FEATURE_QWORD];
168 };
169
170 struct comm_global_attr {
171 u8 max_host_num;
172 u8 max_pf_num;
173 u16 vf_id_start;
174 /* for api cmd to mgmt cpu */
175 u8 mgmt_host_node_id;
176 u8 cmdq_num;
177 u8 rsvd1[34];
178 };
179
180 struct comm_cmd_get_glb_attr {
181 struct mgmt_msg_head head;
182 struct comm_global_attr attr;
183 };
184
185 enum comm_func_svc_type {
186 COMM_FUNC_SVC_T_COMM = 0,
187 COMM_FUNC_SVC_T_NIC = 1,
188 };
189
190 struct comm_cmd_set_func_svc_used_state {
191 struct mgmt_msg_head head;
192 u16 func_id;
193 u16 svc_type;
194 u8 used_state;
195 u8 rsvd[35];
196 };
197
198 struct comm_cmd_set_dma_attr {
199 struct mgmt_msg_head head;
200 u16 func_id;
201 u8 entry_idx;
202 u8 st;
203 u8 at;
204 u8 ph;
205 u8 no_snooping;
206 u8 tph_en;
207 u32 resv1;
208 };
209
210 struct comm_cmd_set_ceq_ctrl_reg {
211 struct mgmt_msg_head head;
212 u16 func_id;
213 u16 q_id;
214 u32 ctrl0;
215 u32 ctrl1;
216 u32 rsvd1;
217 };
218
219 struct comm_cmd_cfg_wq_page_size {
220 struct mgmt_msg_head head;
221 u16 func_id;
222 u8 opcode;
223 /* real_size=4KB*2^page_size, range(0~20) must be checked by driver */
224 u8 page_size;
225 u32 rsvd1;
226 };
227
228 struct comm_cmd_set_root_ctxt {
229 struct mgmt_msg_head head;
230 u16 func_id;
231 u8 set_cmdq_depth;
232 u8 cmdq_depth;
233 u16 rx_buf_sz;
234 u8 lro_en;
235 u8 rsvd1;
236 u16 sq_depth;
237 u16 rq_depth;
238 u64 rsvd2;
239 };
240
241 struct comm_cmdq_ctxt_info {
242 __le64 curr_wqe_page_pfn;
243 __le64 wq_block_pfn;
244 };
245
246 struct comm_cmd_set_cmdq_ctxt {
247 struct mgmt_msg_head head;
248 u16 func_id;
249 u8 cmdq_id;
250 u8 rsvd1[5];
251 struct comm_cmdq_ctxt_info ctxt;
252 };
253
254 struct comm_cmd_clear_resource {
255 struct mgmt_msg_head head;
256 u16 func_id;
257 u16 rsvd1[3];
258 };
259
260 struct comm_cmd_sync_time {
261 struct mgmt_msg_head head;
262
263 u64 mstime;
264 u64 rsvd1;
265 };
266
267 struct comm_cmd_bdf_info {
268 struct mgmt_msg_head head;
269
270 u16 function_idx;
271 u8 rsvd1[2];
272 u8 bus;
273 u8 device;
274 u8 function;
275 u8 rsvd2[5];
276 };
277
278 /* Services supported by HW. HW uses these values when delivering events.
279 * HW supports multiple services that are not yet supported by driver
280 * (e.g. RoCE).
281 */
282 enum hinic3_service_type {
283 HINIC3_SERVICE_T_NIC = 0,
284 /* MAX is only used by SW for array sizes. */
285 HINIC3_SERVICE_T_MAX = 1,
286 };
287
288 #endif
289