1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright 2010 Matt Turner.
4 * Copyright 2012 Red Hat
5 *
6 * Authors: Matthew Garrett
7 * Matt Turner
8 * Dave Airlie
9 */
10
11 #include <linux/delay.h>
12 #include <linux/iosys-map.h>
13
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_color_mgmt.h>
17 #include <drm/drm_damage_helper.h>
18 #include <drm/drm_edid.h>
19 #include <drm/drm_format_helper.h>
20 #include <drm/drm_fourcc.h>
21 #include <drm/drm_framebuffer.h>
22 #include <drm/drm_gem_atomic_helper.h>
23 #include <drm/drm_gem_framebuffer_helper.h>
24 #include <drm/drm_panic.h>
25 #include <drm/drm_print.h>
26
27 #include "mgag200_ddc.h"
28 #include "mgag200_drv.h"
29
30 /*
31 * This file contains setup code for the CRTC.
32 */
33
mgag200_set_gamma_lut(struct drm_crtc * crtc,unsigned int index,u16 red,u16 green,u16 blue)34 static void mgag200_set_gamma_lut(struct drm_crtc *crtc, unsigned int index,
35 u16 red, u16 green, u16 blue)
36 {
37 struct drm_device *dev = crtc->dev;
38 struct mga_device *mdev = to_mga_device(dev);
39 u8 i8 = index & 0xff;
40 u8 r8 = red >> 8;
41 u8 g8 = green >> 8;
42 u8 b8 = blue >> 8;
43
44 if (drm_WARN_ON_ONCE(dev, index != i8))
45 return; /* driver bug */
46
47 WREG8(DAC_INDEX + MGA1064_INDEX, i8);
48 WREG8(DAC_INDEX + MGA1064_COL_PAL, r8);
49 WREG8(DAC_INDEX + MGA1064_COL_PAL, g8);
50 WREG8(DAC_INDEX + MGA1064_COL_PAL, b8);
51 }
52
mgag200_crtc_fill_gamma(struct mga_device * mdev,const struct drm_format_info * format)53 void mgag200_crtc_fill_gamma(struct mga_device *mdev,
54 const struct drm_format_info *format)
55 {
56 struct drm_crtc *crtc = &mdev->crtc;
57
58 switch (format->format) {
59 case DRM_FORMAT_RGB565:
60 drm_crtc_fill_gamma_565(crtc, mgag200_set_gamma_lut);
61 break;
62 case DRM_FORMAT_RGB888:
63 case DRM_FORMAT_XRGB8888:
64 drm_crtc_fill_gamma_888(crtc, mgag200_set_gamma_lut);
65 break;
66 default:
67 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n",
68 &format->format);
69 break;
70 }
71 }
72
mgag200_crtc_load_gamma(struct mga_device * mdev,const struct drm_format_info * format,struct drm_color_lut * lut)73 void mgag200_crtc_load_gamma(struct mga_device *mdev,
74 const struct drm_format_info *format,
75 struct drm_color_lut *lut)
76 {
77 struct drm_crtc *crtc = &mdev->crtc;
78
79 switch (format->format) {
80 case DRM_FORMAT_RGB565:
81 drm_crtc_load_gamma_565_from_888(crtc, lut, mgag200_set_gamma_lut);
82 break;
83 case DRM_FORMAT_RGB888:
84 case DRM_FORMAT_XRGB8888:
85 drm_crtc_load_gamma_888(crtc, lut, mgag200_set_gamma_lut);
86 break;
87 default:
88 drm_warn_once(&mdev->base, "Unsupported format %p4cc for gamma correction\n",
89 &format->format);
90 break;
91 }
92 }
93
mga_wait_vsync(struct mga_device * mdev)94 static inline void mga_wait_vsync(struct mga_device *mdev)
95 {
96 unsigned long timeout = jiffies + HZ/10;
97 unsigned int status = 0;
98
99 do {
100 status = RREG32(MGAREG_STATUS);
101 } while ((status & 0x08) && time_before(jiffies, timeout));
102 timeout = jiffies + HZ/10;
103 status = 0;
104 do {
105 status = RREG32(MGAREG_STATUS);
106 } while (!(status & 0x08) && time_before(jiffies, timeout));
107 }
108
mga_wait_busy(struct mga_device * mdev)109 static inline void mga_wait_busy(struct mga_device *mdev)
110 {
111 unsigned long timeout = jiffies + HZ;
112 unsigned int status = 0;
113 do {
114 status = RREG8(MGAREG_STATUS + 2);
115 } while ((status & 0x01) && time_before(jiffies, timeout));
116 }
117
118 /*
119 * This is how the framebuffer base address is stored in g200 cards:
120 * * Assume @offset is the gpu_addr variable of the framebuffer object
121 * * Then addr is the number of _pixels_ (not bytes) from the start of
122 * VRAM to the first pixel we want to display. (divided by 2 for 32bit
123 * framebuffers)
124 * * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
125 * addr<20> -> CRTCEXT0<6>
126 * addr<19-16> -> CRTCEXT0<3-0>
127 * addr<15-8> -> CRTCC<7-0>
128 * addr<7-0> -> CRTCD<7-0>
129 *
130 * CRTCEXT0 has to be programmed last to trigger an update and make the
131 * new addr variable take effect.
132 */
mgag200_set_startadd(struct mga_device * mdev,unsigned long offset)133 static void mgag200_set_startadd(struct mga_device *mdev,
134 unsigned long offset)
135 {
136 struct drm_device *dev = &mdev->base;
137 u32 startadd;
138 u8 crtcc, crtcd, crtcext0;
139
140 startadd = offset / 8;
141
142 if (startadd > 0)
143 drm_WARN_ON_ONCE(dev, mdev->info->bug_no_startadd);
144
145 /*
146 * Can't store addresses any higher than that, but we also
147 * don't have more than 16 MiB of memory, so it should be fine.
148 */
149 drm_WARN_ON(dev, startadd > 0x1fffff);
150
151 RREG_ECRT(0x00, crtcext0);
152
153 crtcc = (startadd >> 8) & 0xff;
154 crtcd = startadd & 0xff;
155 crtcext0 &= 0xb0;
156 crtcext0 |= ((startadd >> 14) & BIT(6)) |
157 ((startadd >> 16) & 0x0f);
158
159 WREG_CRT(0x0c, crtcc);
160 WREG_CRT(0x0d, crtcd);
161 WREG_ECRT(0x00, crtcext0);
162 }
163
mgag200_init_registers(struct mga_device * mdev)164 void mgag200_init_registers(struct mga_device *mdev)
165 {
166 u8 crtc11, misc;
167
168 WREG_SEQ(2, 0x0f);
169 WREG_SEQ(3, 0x00);
170 WREG_SEQ(4, 0x0e);
171
172 WREG_CRT(10, 0);
173 WREG_CRT(11, 0);
174 WREG_CRT(12, 0);
175 WREG_CRT(13, 0);
176 WREG_CRT(14, 0);
177 WREG_CRT(15, 0);
178
179 RREG_CRT(0x11, crtc11);
180 crtc11 &= ~(MGAREG_CRTC11_CRTCPROTECT |
181 MGAREG_CRTC11_VINTEN |
182 MGAREG_CRTC11_VINTCLR);
183 WREG_CRT(0x11, crtc11);
184
185 misc = RREG8(MGA_MISC_IN);
186 misc |= MGAREG_MISC_IOADSEL;
187 WREG8(MGA_MISC_OUT, misc);
188 }
189
mgag200_set_mode_regs(struct mga_device * mdev,const struct drm_display_mode * mode,bool set_vidrst)190 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode,
191 bool set_vidrst)
192 {
193 unsigned int hdispend, hsyncstr, hsyncend, htotal, hblkstr, hblkend;
194 unsigned int vdispend, vsyncstr, vsyncend, vtotal, vblkstr, vblkend;
195 unsigned int linecomp;
196 u8 misc, crtcext1, crtcext2, crtcext5;
197
198 hdispend = mode->crtc_hdisplay / 8 - 1;
199 hsyncstr = mode->crtc_hsync_start / 8 - 1;
200 hsyncend = mode->crtc_hsync_end / 8 - 1;
201 htotal = mode->crtc_htotal / 8 - 1;
202 /* Work around hardware quirk */
203 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
204 htotal++;
205 hblkstr = mode->crtc_hblank_start / 8 - 1;
206 hblkend = htotal;
207
208 vdispend = mode->crtc_vdisplay - 1;
209 vsyncstr = mode->crtc_vsync_start - 1;
210 vsyncend = mode->crtc_vsync_end - 1;
211 vtotal = mode->crtc_vtotal - 2;
212 vblkstr = mode->crtc_vblank_start - 1;
213 vblkend = vtotal + 1;
214
215 linecomp = vdispend;
216
217 misc = RREG8(MGA_MISC_IN);
218
219 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
220 misc |= MGAREG_MISC_HSYNCPOL;
221 else
222 misc &= ~MGAREG_MISC_HSYNCPOL;
223
224 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
225 misc |= MGAREG_MISC_VSYNCPOL;
226 else
227 misc &= ~MGAREG_MISC_VSYNCPOL;
228
229 crtcext1 = (((htotal - 4) & 0x100) >> 8) |
230 ((hblkstr & 0x100) >> 7) |
231 ((hsyncstr & 0x100) >> 6) |
232 (hblkend & 0x40);
233 if (set_vidrst)
234 crtcext1 |= MGAREG_CRTCEXT1_VRSTEN |
235 MGAREG_CRTCEXT1_HRSTEN;
236
237 crtcext2 = ((vtotal & 0xc00) >> 10) |
238 ((vdispend & 0x400) >> 8) |
239 ((vblkstr & 0xc00) >> 7) |
240 ((vsyncstr & 0xc00) >> 5) |
241 ((linecomp & 0x400) >> 3);
242 crtcext5 = 0x00;
243
244 WREG_CRT(0x00, htotal - 4);
245 WREG_CRT(0x01, hdispend);
246 WREG_CRT(0x02, hblkstr);
247 WREG_CRT(0x03, (hblkend & 0x1f) | 0x80);
248 WREG_CRT(0x04, hsyncstr);
249 WREG_CRT(0x05, ((hblkend & 0x20) << 2) | (hsyncend & 0x1f));
250 WREG_CRT(0x06, vtotal & 0xff);
251 WREG_CRT(0x07, ((vtotal & 0x100) >> 8) |
252 ((vdispend & 0x100) >> 7) |
253 ((vsyncstr & 0x100) >> 6) |
254 ((vblkstr & 0x100) >> 5) |
255 ((linecomp & 0x100) >> 4) |
256 ((vtotal & 0x200) >> 4) |
257 ((vdispend & 0x200) >> 3) |
258 ((vsyncstr & 0x200) >> 2));
259 WREG_CRT(0x09, ((vblkstr & 0x200) >> 4) |
260 ((linecomp & 0x200) >> 3));
261 WREG_CRT(0x10, vsyncstr & 0xff);
262 WREG_CRT(0x11, (vsyncend & 0x0f) | 0x20);
263 WREG_CRT(0x12, vdispend & 0xff);
264 WREG_CRT(0x14, 0);
265 WREG_CRT(0x15, vblkstr & 0xff);
266 WREG_CRT(0x16, vblkend & 0xff);
267 WREG_CRT(0x17, 0xc3);
268 WREG_CRT(0x18, linecomp & 0xff);
269
270 WREG_ECRT(0x01, crtcext1);
271 WREG_ECRT(0x02, crtcext2);
272 WREG_ECRT(0x05, crtcext5);
273
274 WREG8(MGA_MISC_OUT, misc);
275 }
276
mgag200_get_bpp_shift(const struct drm_format_info * format)277 static u8 mgag200_get_bpp_shift(const struct drm_format_info *format)
278 {
279 static const u8 bpp_shift[] = {0, 1, 0, 2};
280
281 return bpp_shift[format->cpp[0] - 1];
282 }
283
284 /*
285 * Calculates the HW offset value from the framebuffer's pitch. The
286 * offset is a multiple of the pixel size and depends on the display
287 * format.
288 */
mgag200_calculate_offset(struct mga_device * mdev,const struct drm_framebuffer * fb)289 static u32 mgag200_calculate_offset(struct mga_device *mdev,
290 const struct drm_framebuffer *fb)
291 {
292 u32 offset = fb->pitches[0] / fb->format->cpp[0];
293 u8 bppshift = mgag200_get_bpp_shift(fb->format);
294
295 if (fb->format->cpp[0] * 8 == 24)
296 offset = (offset * 3) >> (4 - bppshift);
297 else
298 offset = offset >> (4 - bppshift);
299
300 return offset;
301 }
302
mgag200_set_offset(struct mga_device * mdev,const struct drm_framebuffer * fb)303 static void mgag200_set_offset(struct mga_device *mdev,
304 const struct drm_framebuffer *fb)
305 {
306 u8 crtc13, crtcext0;
307 u32 offset = mgag200_calculate_offset(mdev, fb);
308
309 RREG_ECRT(0, crtcext0);
310
311 crtc13 = offset & 0xff;
312
313 crtcext0 &= ~MGAREG_CRTCEXT0_OFFSET_MASK;
314 crtcext0 |= (offset >> 4) & MGAREG_CRTCEXT0_OFFSET_MASK;
315
316 WREG_CRT(0x13, crtc13);
317 WREG_ECRT(0x00, crtcext0);
318 }
319
mgag200_set_format_regs(struct mga_device * mdev,const struct drm_format_info * format)320 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format)
321 {
322 struct drm_device *dev = &mdev->base;
323 unsigned int bpp, bppshift, scale;
324 u8 crtcext3, xmulctrl;
325
326 bpp = format->cpp[0] * 8;
327
328 bppshift = mgag200_get_bpp_shift(format);
329 switch (bpp) {
330 case 24:
331 scale = ((1 << bppshift) * 3) - 1;
332 break;
333 default:
334 scale = (1 << bppshift) - 1;
335 break;
336 }
337
338 RREG_ECRT(3, crtcext3);
339
340 switch (bpp) {
341 case 8:
342 xmulctrl = MGA1064_MUL_CTL_8bits;
343 break;
344 case 16:
345 if (format->depth == 15)
346 xmulctrl = MGA1064_MUL_CTL_15bits;
347 else
348 xmulctrl = MGA1064_MUL_CTL_16bits;
349 break;
350 case 24:
351 xmulctrl = MGA1064_MUL_CTL_24bits;
352 break;
353 case 32:
354 xmulctrl = MGA1064_MUL_CTL_32_24bits;
355 break;
356 default:
357 /* BUG: We should have caught this problem already. */
358 drm_WARN_ON(dev, "invalid format depth\n");
359 return;
360 }
361
362 crtcext3 &= ~GENMASK(2, 0);
363 crtcext3 |= scale;
364
365 WREG_DAC(MGA1064_MUL_CTL, xmulctrl);
366
367 WREG_GFX(0, 0x00);
368 WREG_GFX(1, 0x00);
369 WREG_GFX(2, 0x00);
370 WREG_GFX(3, 0x00);
371 WREG_GFX(4, 0x00);
372 WREG_GFX(5, 0x40);
373 /* GCTL6 should be 0x05, but we configure memmapsl to 0xb8000 (text mode),
374 * so that it doesn't hang when running kexec/kdump on G200_SE rev42.
375 */
376 WREG_GFX(6, 0x0d);
377 WREG_GFX(7, 0x0f);
378 WREG_GFX(8, 0x0f);
379
380 WREG_ECRT(3, crtcext3);
381 }
382
mgag200_enable_display(struct mga_device * mdev)383 void mgag200_enable_display(struct mga_device *mdev)
384 {
385 u8 seq0, crtcext1;
386
387 RREG_SEQ(0x00, seq0);
388 seq0 |= MGAREG_SEQ0_SYNCRST |
389 MGAREG_SEQ0_ASYNCRST;
390 WREG_SEQ(0x00, seq0);
391
392 /*
393 * TODO: replace busy waiting with vblank IRQ; put
394 * msleep(50) before changing SCROFF
395 */
396 mga_wait_vsync(mdev);
397 mga_wait_busy(mdev);
398
399 RREG_ECRT(0x01, crtcext1);
400 crtcext1 &= ~MGAREG_CRTCEXT1_VSYNCOFF;
401 crtcext1 &= ~MGAREG_CRTCEXT1_HSYNCOFF;
402 WREG_ECRT(0x01, crtcext1);
403 }
404
mgag200_disable_display(struct mga_device * mdev)405 static void mgag200_disable_display(struct mga_device *mdev)
406 {
407 u8 seq0, crtcext1;
408
409 RREG_SEQ(0x00, seq0);
410 seq0 &= ~MGAREG_SEQ0_SYNCRST;
411 WREG_SEQ(0x00, seq0);
412
413 /*
414 * TODO: replace busy waiting with vblank IRQ; put
415 * msleep(50) before changing SCROFF
416 */
417 mga_wait_vsync(mdev);
418 mga_wait_busy(mdev);
419
420 RREG_ECRT(0x01, crtcext1);
421 crtcext1 |= MGAREG_CRTCEXT1_VSYNCOFF |
422 MGAREG_CRTCEXT1_HSYNCOFF;
423 WREG_ECRT(0x01, crtcext1);
424 }
425
mgag200_handle_damage(struct mga_device * mdev,const struct iosys_map * vmap,struct drm_framebuffer * fb,struct drm_rect * clip)426 static void mgag200_handle_damage(struct mga_device *mdev, const struct iosys_map *vmap,
427 struct drm_framebuffer *fb, struct drm_rect *clip)
428 {
429 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram);
430
431 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
432 drm_fb_memcpy(&dst, fb->pitches, vmap, fb, clip);
433 }
434
435 /*
436 * Primary plane
437 */
438
439 const uint32_t mgag200_primary_plane_formats[] = {
440 DRM_FORMAT_XRGB8888,
441 DRM_FORMAT_RGB565,
442 DRM_FORMAT_RGB888,
443 };
444
445 const size_t mgag200_primary_plane_formats_size = ARRAY_SIZE(mgag200_primary_plane_formats);
446
447 const uint64_t mgag200_primary_plane_fmtmods[] = {
448 DRM_FORMAT_MOD_LINEAR,
449 DRM_FORMAT_MOD_INVALID
450 };
451
mgag200_primary_plane_helper_atomic_check(struct drm_plane * plane,struct drm_atomic_state * new_state)452 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane,
453 struct drm_atomic_state *new_state)
454 {
455 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane);
456 struct drm_framebuffer *new_fb = new_plane_state->fb;
457 struct drm_framebuffer *fb = NULL;
458 struct drm_crtc *new_crtc = new_plane_state->crtc;
459 struct drm_crtc_state *new_crtc_state = NULL;
460 struct mgag200_crtc_state *new_mgag200_crtc_state;
461 int ret;
462
463 if (new_crtc)
464 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_crtc);
465
466 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
467 DRM_PLANE_NO_SCALING,
468 DRM_PLANE_NO_SCALING,
469 false, true);
470 if (ret)
471 return ret;
472 else if (!new_plane_state->visible)
473 return 0;
474
475 if (plane->state)
476 fb = plane->state->fb;
477
478 if (!fb || (fb->format != new_fb->format))
479 new_crtc_state->mode_changed = true; /* update PLL settings */
480
481 new_mgag200_crtc_state = to_mgag200_crtc_state(new_crtc_state);
482 new_mgag200_crtc_state->format = new_fb->format;
483
484 return 0;
485 }
486
mgag200_primary_plane_helper_atomic_update(struct drm_plane * plane,struct drm_atomic_state * old_state)487 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
488 struct drm_atomic_state *old_state)
489 {
490 struct drm_device *dev = plane->dev;
491 struct mga_device *mdev = to_mga_device(dev);
492 struct drm_plane_state *plane_state = plane->state;
493 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane);
494 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
495 struct drm_framebuffer *fb = plane_state->fb;
496 struct drm_atomic_helper_damage_iter iter;
497 struct drm_rect damage;
498
499 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
500 drm_atomic_for_each_plane_damage(&iter, &damage) {
501 mgag200_handle_damage(mdev, shadow_plane_state->data, fb, &damage);
502 }
503
504 /* Always scanout image at VRAM offset 0 */
505 mgag200_set_startadd(mdev, (u32)0);
506 mgag200_set_offset(mdev, fb);
507 }
508
mgag200_primary_plane_helper_atomic_enable(struct drm_plane * plane,struct drm_atomic_state * state)509 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane,
510 struct drm_atomic_state *state)
511 {
512 struct drm_device *dev = plane->dev;
513 struct mga_device *mdev = to_mga_device(dev);
514 u8 seq1;
515
516 RREG_SEQ(0x01, seq1);
517 seq1 &= ~MGAREG_SEQ1_SCROFF;
518 WREG_SEQ(0x01, seq1);
519 msleep(20);
520 }
521
mgag200_primary_plane_helper_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * old_state)522 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,
523 struct drm_atomic_state *old_state)
524 {
525 struct drm_device *dev = plane->dev;
526 struct mga_device *mdev = to_mga_device(dev);
527 u8 seq1;
528
529 RREG_SEQ(0x01, seq1);
530 seq1 |= MGAREG_SEQ1_SCROFF;
531 WREG_SEQ(0x01, seq1);
532 msleep(20);
533 }
534
mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane * plane,struct drm_scanout_buffer * sb)535 int mgag200_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane,
536 struct drm_scanout_buffer *sb)
537 {
538 struct mga_device *mdev = to_mga_device(plane->dev);
539 struct iosys_map map = IOSYS_MAP_INIT_VADDR_IOMEM(mdev->vram);
540
541 if (plane->state && plane->state->fb) {
542 sb->format = plane->state->fb->format;
543 sb->width = plane->state->fb->width;
544 sb->height = plane->state->fb->height;
545 sb->pitch[0] = plane->state->fb->pitches[0];
546 sb->map[0] = map;
547 return 0;
548 }
549 return -ENODEV;
550 }
551
552 /*
553 * CRTC
554 */
555
mgag200_crtc_helper_mode_valid(struct drm_crtc * crtc,const struct drm_display_mode * mode)556 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
557 const struct drm_display_mode *mode)
558 {
559 struct mga_device *mdev = to_mga_device(crtc->dev);
560 const struct mgag200_device_info *info = mdev->info;
561
562 /*
563 * Some devices have additional limits on the size of the
564 * display mode.
565 */
566 if (mode->hdisplay > info->max_hdisplay)
567 return MODE_VIRTUAL_X;
568 if (mode->vdisplay > info->max_vdisplay)
569 return MODE_VIRTUAL_Y;
570
571 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
572 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
573 return MODE_H_ILLEGAL;
574 }
575
576 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
577 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
578 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
579 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
580 return MODE_BAD;
581 }
582
583 return MODE_OK;
584 }
585
mgag200_crtc_helper_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * new_state)586 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state)
587 {
588 struct drm_device *dev = crtc->dev;
589 struct mga_device *mdev = to_mga_device(dev);
590 const struct mgag200_device_funcs *funcs = mdev->funcs;
591 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc);
592 struct drm_property_blob *new_gamma_lut = new_crtc_state->gamma_lut;
593 int ret;
594
595 if (!new_crtc_state->enable)
596 return 0;
597
598 ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state);
599 if (ret)
600 return ret;
601
602 if (new_crtc_state->mode_changed) {
603 if (funcs->pixpllc_atomic_check) {
604 ret = funcs->pixpllc_atomic_check(crtc, new_state);
605 if (ret)
606 return ret;
607 }
608 }
609
610 if (new_crtc_state->color_mgmt_changed && new_gamma_lut) {
611 if (new_gamma_lut->length != MGAG200_LUT_SIZE * sizeof(struct drm_color_lut)) {
612 drm_dbg(dev, "Wrong size for gamma_lut %zu\n", new_gamma_lut->length);
613 return -EINVAL;
614 }
615 }
616
617 return 0;
618 }
619
mgag200_crtc_helper_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * old_state)620 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state)
621 {
622 struct drm_crtc_state *crtc_state = crtc->state;
623 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
624 struct drm_device *dev = crtc->dev;
625 struct mga_device *mdev = to_mga_device(dev);
626
627 if (crtc_state->enable && crtc_state->color_mgmt_changed) {
628 const struct drm_format_info *format = mgag200_crtc_state->format;
629
630 if (crtc_state->gamma_lut)
631 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);
632 else
633 mgag200_crtc_fill_gamma(mdev, format);
634 }
635 }
636
mgag200_crtc_helper_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * old_state)637 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state)
638 {
639 struct drm_device *dev = crtc->dev;
640 struct mga_device *mdev = to_mga_device(dev);
641 const struct mgag200_device_funcs *funcs = mdev->funcs;
642 struct drm_crtc_state *crtc_state = crtc->state;
643 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
644 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
645 const struct drm_format_info *format = mgag200_crtc_state->format;
646
647 mgag200_set_format_regs(mdev, format);
648 mgag200_set_mode_regs(mdev, adjusted_mode, mgag200_crtc_state->set_vidrst);
649
650 if (funcs->pixpllc_atomic_update)
651 funcs->pixpllc_atomic_update(crtc, old_state);
652
653 if (crtc_state->gamma_lut)
654 mgag200_crtc_load_gamma(mdev, format, crtc_state->gamma_lut->data);
655 else
656 mgag200_crtc_fill_gamma(mdev, format);
657
658 mgag200_enable_display(mdev);
659 }
660
mgag200_crtc_helper_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * old_state)661 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state)
662 {
663 struct mga_device *mdev = to_mga_device(crtc->dev);
664
665 mgag200_disable_display(mdev);
666 }
667
mgag200_crtc_reset(struct drm_crtc * crtc)668 void mgag200_crtc_reset(struct drm_crtc *crtc)
669 {
670 struct mgag200_crtc_state *mgag200_crtc_state;
671
672 if (crtc->state)
673 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
674
675 mgag200_crtc_state = kzalloc(sizeof(*mgag200_crtc_state), GFP_KERNEL);
676 if (mgag200_crtc_state)
677 __drm_atomic_helper_crtc_reset(crtc, &mgag200_crtc_state->base);
678 else
679 __drm_atomic_helper_crtc_reset(crtc, NULL);
680 }
681
mgag200_crtc_atomic_duplicate_state(struct drm_crtc * crtc)682 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
683 {
684 struct drm_crtc_state *crtc_state = crtc->state;
685 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
686 struct mgag200_crtc_state *new_mgag200_crtc_state;
687
688 if (!crtc_state)
689 return NULL;
690
691 new_mgag200_crtc_state = kzalloc(sizeof(*new_mgag200_crtc_state), GFP_KERNEL);
692 if (!new_mgag200_crtc_state)
693 return NULL;
694 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_mgag200_crtc_state->base);
695
696 new_mgag200_crtc_state->format = mgag200_crtc_state->format;
697 memcpy(&new_mgag200_crtc_state->pixpllc, &mgag200_crtc_state->pixpllc,
698 sizeof(new_mgag200_crtc_state->pixpllc));
699 new_mgag200_crtc_state->set_vidrst = mgag200_crtc_state->set_vidrst;
700
701 return &new_mgag200_crtc_state->base;
702 }
703
mgag200_crtc_atomic_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * crtc_state)704 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state)
705 {
706 struct mgag200_crtc_state *mgag200_crtc_state = to_mgag200_crtc_state(crtc_state);
707
708 __drm_atomic_helper_crtc_destroy_state(&mgag200_crtc_state->base);
709 kfree(mgag200_crtc_state);
710 }
711
712 /*
713 * Mode config
714 */
715
mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state * state)716 static void mgag200_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state)
717 {
718 struct mga_device *mdev = to_mga_device(state->dev);
719
720 /*
721 * Concurrent operations could possibly trigger a call to
722 * drm_connector_helper_funcs.get_modes by trying to read the
723 * display modes. Protect access to I/O registers by acquiring
724 * the I/O-register lock.
725 */
726 mutex_lock(&mdev->rmmio_lock);
727 drm_atomic_helper_commit_tail(state);
728 mutex_unlock(&mdev->rmmio_lock);
729 }
730
731 static const struct drm_mode_config_helper_funcs mgag200_mode_config_helper_funcs = {
732 .atomic_commit_tail = mgag200_mode_config_helper_atomic_commit_tail,
733 };
734
735 /* Calculates a mode's required memory bandwidth (in KiB/sec). */
mgag200_calculate_mode_bandwidth(const struct drm_display_mode * mode,unsigned int bits_per_pixel)736 static uint32_t mgag200_calculate_mode_bandwidth(const struct drm_display_mode *mode,
737 unsigned int bits_per_pixel)
738 {
739 uint32_t total_area, divisor;
740 uint64_t active_area, pixels_per_second, bandwidth;
741 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
742
743 divisor = 1024;
744
745 if (!mode->htotal || !mode->vtotal || !mode->clock)
746 return 0;
747
748 active_area = mode->hdisplay * mode->vdisplay;
749 total_area = mode->htotal * mode->vtotal;
750
751 pixels_per_second = active_area * mode->clock * 1000;
752 do_div(pixels_per_second, total_area);
753
754 bandwidth = pixels_per_second * bytes_per_pixel * 100;
755 do_div(bandwidth, divisor);
756
757 return (uint32_t)bandwidth;
758 }
759
mgag200_mode_config_mode_valid(struct drm_device * dev,const struct drm_display_mode * mode)760 static enum drm_mode_status mgag200_mode_config_mode_valid(struct drm_device *dev,
761 const struct drm_display_mode *mode)
762 {
763 static const unsigned int max_bpp = 4; // DRM_FORMAT_XRGB8888
764 struct mga_device *mdev = to_mga_device(dev);
765 unsigned long fbsize, fbpages, max_fbpages;
766 const struct mgag200_device_info *info = mdev->info;
767
768 max_fbpages = mdev->vram_available >> PAGE_SHIFT;
769
770 fbsize = mode->hdisplay * mode->vdisplay * max_bpp;
771 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE);
772
773 if (fbpages > max_fbpages)
774 return MODE_MEM;
775
776 /*
777 * Test the mode's required memory bandwidth if the device
778 * specifies a maximum. Not all devices do though.
779 */
780 if (info->max_mem_bandwidth) {
781 uint32_t mode_bandwidth = mgag200_calculate_mode_bandwidth(mode, max_bpp * 8);
782
783 if (mode_bandwidth > (info->max_mem_bandwidth * 1024))
784 return MODE_BAD;
785 }
786
787 return MODE_OK;
788 }
789
790 static const struct drm_mode_config_funcs mgag200_mode_config_funcs = {
791 .fb_create = drm_gem_fb_create_with_dirty,
792 .mode_valid = mgag200_mode_config_mode_valid,
793 .atomic_check = drm_atomic_helper_check,
794 .atomic_commit = drm_atomic_helper_commit,
795 };
796
mgag200_mode_config_init(struct mga_device * mdev,resource_size_t vram_available)797 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available)
798 {
799 struct drm_device *dev = &mdev->base;
800 int ret;
801
802 mdev->vram_available = vram_available;
803
804 ret = drmm_mode_config_init(dev);
805 if (ret) {
806 drm_err(dev, "drmm_mode_config_init() failed: %d\n", ret);
807 return ret;
808 }
809
810 dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
811 dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
812 dev->mode_config.preferred_depth = 24;
813 dev->mode_config.funcs = &mgag200_mode_config_funcs;
814 dev->mode_config.helper_private = &mgag200_mode_config_helper_funcs;
815
816 return 0;
817 }
818