1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #include <drm/drm_atomic.h>
9 #include <drm/drm_blend.h>
10 #include <drm/drm_damage_helper.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_framebuffer.h>
13 #include <drm/drm_gem_atomic_helper.h>
14 #include <drm/drm_print.h>
15
16 #include "mdp5_kms.h"
17
18 struct mdp5_plane {
19 struct drm_plane base;
20 };
21 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
22
23 static int mdp5_plane_mode_set(struct drm_plane *plane,
24 struct drm_crtc *crtc, struct drm_framebuffer *fb,
25 struct drm_rect *src, struct drm_rect *dest);
26
get_kms(struct drm_plane * plane)27 static struct mdp5_kms *get_kms(struct drm_plane *plane)
28 {
29 struct msm_drm_private *priv = plane->dev->dev_private;
30 return to_mdp5_kms(to_mdp_kms(priv->kms));
31 }
32
plane_enabled(struct drm_plane_state * state)33 static bool plane_enabled(struct drm_plane_state *state)
34 {
35 return state->visible;
36 }
37
38 /* helper to install properties which are common to planes and crtcs */
mdp5_plane_install_properties(struct drm_plane * plane,struct drm_mode_object * obj)39 static void mdp5_plane_install_properties(struct drm_plane *plane,
40 struct drm_mode_object *obj)
41 {
42 unsigned int zpos;
43
44 drm_plane_create_rotation_property(plane,
45 DRM_MODE_ROTATE_0,
46 DRM_MODE_ROTATE_0 |
47 DRM_MODE_ROTATE_180 |
48 DRM_MODE_REFLECT_X |
49 DRM_MODE_REFLECT_Y);
50 drm_plane_create_alpha_property(plane);
51 drm_plane_create_blend_mode_property(plane,
52 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
53 BIT(DRM_MODE_BLEND_PREMULTI) |
54 BIT(DRM_MODE_BLEND_COVERAGE));
55
56 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
57 zpos = STAGE_BASE;
58 else
59 zpos = STAGE0 + drm_plane_index(plane);
60 drm_plane_create_zpos_property(plane, zpos, 1, 255);
61 }
62
63 static void
mdp5_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)64 mdp5_plane_atomic_print_state(struct drm_printer *p,
65 const struct drm_plane_state *state)
66 {
67 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
68 struct mdp5_kms *mdp5_kms = get_kms(state->plane);
69
70 drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
71 pstate->hwpipe->name : "(null)");
72 if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT)
73 drm_printf(p, "\tright-hwpipe=%s\n",
74 pstate->r_hwpipe ? pstate->r_hwpipe->name :
75 "(null)");
76 drm_printf(p, "\tblend_mode=%u\n", pstate->base.pixel_blend_mode);
77 drm_printf(p, "\tzpos=%u\n", pstate->base.zpos);
78 drm_printf(p, "\tnormalized_zpos=%u\n", pstate->base.normalized_zpos);
79 drm_printf(p, "\talpha=%u\n", pstate->base.alpha);
80 drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
81 }
82
mdp5_plane_reset(struct drm_plane * plane)83 static void mdp5_plane_reset(struct drm_plane *plane)
84 {
85 struct mdp5_plane_state *mdp5_state;
86
87 if (plane->state)
88 __drm_atomic_helper_plane_destroy_state(plane->state);
89
90 kfree(to_mdp5_plane_state(plane->state));
91 plane->state = NULL;
92 mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
93 if (!mdp5_state)
94 return;
95 __drm_atomic_helper_plane_reset(plane, &mdp5_state->base);
96 }
97
98 static struct drm_plane_state *
mdp5_plane_duplicate_state(struct drm_plane * plane)99 mdp5_plane_duplicate_state(struct drm_plane *plane)
100 {
101 struct mdp5_plane_state *mdp5_state;
102
103 if (WARN_ON(!plane->state))
104 return NULL;
105
106 mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
107 sizeof(*mdp5_state), GFP_KERNEL);
108 if (!mdp5_state)
109 return NULL;
110
111 __drm_atomic_helper_plane_duplicate_state(plane, &mdp5_state->base);
112
113 return &mdp5_state->base;
114 }
115
mdp5_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)116 static void mdp5_plane_destroy_state(struct drm_plane *plane,
117 struct drm_plane_state *state)
118 {
119 struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
120
121 __drm_atomic_helper_plane_destroy_state(state);
122
123 kfree(pstate);
124 }
125
126 static const struct drm_plane_funcs mdp5_plane_funcs = {
127 .update_plane = drm_atomic_helper_update_plane,
128 .disable_plane = drm_atomic_helper_disable_plane,
129 .reset = mdp5_plane_reset,
130 .atomic_duplicate_state = mdp5_plane_duplicate_state,
131 .atomic_destroy_state = mdp5_plane_destroy_state,
132 .atomic_print_state = mdp5_plane_atomic_print_state,
133 };
134
mdp5_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)135 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
136 struct drm_plane_state *new_state)
137 {
138 bool needs_dirtyfb = to_mdp5_plane_state(new_state)->needs_dirtyfb;
139
140 if (!new_state->fb)
141 return 0;
142
143 drm_gem_plane_helper_prepare_fb(plane, new_state);
144
145 return msm_framebuffer_prepare(new_state->fb, needs_dirtyfb);
146 }
147
mdp5_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)148 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
149 struct drm_plane_state *old_state)
150 {
151 struct drm_framebuffer *fb = old_state->fb;
152 bool needed_dirtyfb = to_mdp5_plane_state(old_state)->needs_dirtyfb;
153
154 if (!fb)
155 return;
156
157 DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
158 msm_framebuffer_cleanup(fb, needed_dirtyfb);
159 }
160
mdp5_plane_atomic_check_with_state(struct drm_crtc_state * crtc_state,struct drm_plane_state * state)161 static int mdp5_plane_atomic_check_with_state(struct drm_crtc_state *crtc_state,
162 struct drm_plane_state *state)
163 {
164 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
165 struct drm_plane *plane = state->plane;
166 struct drm_plane_state *old_state = plane->state;
167 struct mdp5_cfg *config = mdp5_cfg_get_config(get_kms(plane)->cfg);
168 bool new_hwpipe = false;
169 bool need_right_hwpipe = false;
170 uint32_t max_width, max_height;
171 bool out_of_bounds = false;
172 uint32_t caps = 0;
173 int min_scale, max_scale;
174 int ret;
175
176 DBG("%s: check (%d -> %d)", plane->name,
177 plane_enabled(old_state), plane_enabled(state));
178
179 max_width = config->hw->lm.max_width << 16;
180 max_height = config->hw->lm.max_height << 16;
181
182 /* Make sure source dimensions are within bounds. */
183 if (state->src_h > max_height)
184 out_of_bounds = true;
185
186 if (state->src_w > max_width) {
187 /* If source split is supported, we can go up to 2x
188 * the max LM width, but we'd need to stage another
189 * hwpipe to the right LM. So, the drm_plane would
190 * consist of 2 hwpipes.
191 */
192 if (config->hw->mdp.caps & MDP_CAP_SRC_SPLIT &&
193 (state->src_w <= 2 * max_width))
194 need_right_hwpipe = true;
195 else
196 out_of_bounds = true;
197 }
198
199 if (out_of_bounds) {
200 struct drm_rect src = drm_plane_state_src(state);
201 DBG("Invalid source size "DRM_RECT_FP_FMT,
202 DRM_RECT_FP_ARG(&src));
203 return -ERANGE;
204 }
205
206 min_scale = FRAC_16_16(1, 8);
207 max_scale = FRAC_16_16(8, 1);
208
209 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
210 min_scale, max_scale,
211 true, true);
212 if (ret)
213 return ret;
214
215 if (plane_enabled(state)) {
216 unsigned int rotation;
217 const struct msm_format *format;
218 struct mdp5_kms *mdp5_kms = get_kms(plane);
219 uint32_t blkcfg = 0;
220
221 format = msm_framebuffer_format(state->fb);
222 if (MSM_FORMAT_IS_YUV(format))
223 caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
224
225 if (((state->src_w >> 16) != state->crtc_w) ||
226 ((state->src_h >> 16) != state->crtc_h))
227 caps |= MDP_PIPE_CAP_SCALE;
228
229 rotation = drm_rotation_simplify(state->rotation,
230 DRM_MODE_ROTATE_0 |
231 DRM_MODE_REFLECT_X |
232 DRM_MODE_REFLECT_Y);
233
234 if (rotation & DRM_MODE_REFLECT_X)
235 caps |= MDP_PIPE_CAP_HFLIP;
236
237 if (rotation & DRM_MODE_REFLECT_Y)
238 caps |= MDP_PIPE_CAP_VFLIP;
239
240 if (plane->type == DRM_PLANE_TYPE_CURSOR)
241 caps |= MDP_PIPE_CAP_CURSOR;
242
243 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
244 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
245 new_hwpipe = true;
246
247 /*
248 * (re)allocte hw pipe if we're either requesting for 2 hw pipes
249 * or we're switching from 2 hw pipes to 1 hw pipe because the
250 * new src_w can be supported by 1 hw pipe itself.
251 */
252 if ((need_right_hwpipe && !mdp5_state->r_hwpipe) ||
253 (!need_right_hwpipe && mdp5_state->r_hwpipe))
254 new_hwpipe = true;
255
256 if (mdp5_kms->smp) {
257 const struct msm_format *format =
258 msm_framebuffer_format(state->fb);
259
260 blkcfg = mdp5_smp_calculate(mdp5_kms->smp, format,
261 state->src_w >> 16, false);
262
263 if (mdp5_state->hwpipe && (mdp5_state->hwpipe->blkcfg != blkcfg))
264 new_hwpipe = true;
265 }
266
267 /* (re)assign hwpipe if needed, otherwise keep old one: */
268 if (new_hwpipe) {
269 /* TODO maybe we want to re-assign hwpipe sometimes
270 * in cases when we no-longer need some caps to make
271 * it available for other planes?
272 */
273 struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
274 struct mdp5_hw_pipe *old_right_hwpipe =
275 mdp5_state->r_hwpipe;
276 struct mdp5_hw_pipe *new_hwpipe = NULL;
277 struct mdp5_hw_pipe *new_right_hwpipe = NULL;
278
279 ret = mdp5_pipe_assign(state->state, plane, caps,
280 blkcfg, &new_hwpipe,
281 need_right_hwpipe ?
282 &new_right_hwpipe : NULL);
283 if (ret) {
284 DBG("%s: failed to assign hwpipe(s)!",
285 plane->name);
286 return ret;
287 }
288
289 mdp5_state->hwpipe = new_hwpipe;
290 if (need_right_hwpipe)
291 mdp5_state->r_hwpipe = new_right_hwpipe;
292 else
293 /*
294 * set it to NULL so that the driver knows we
295 * don't have a right hwpipe when committing a
296 * new state
297 */
298 mdp5_state->r_hwpipe = NULL;
299
300
301 ret = mdp5_pipe_release(state->state, old_hwpipe);
302 if (ret)
303 return ret;
304
305 ret = mdp5_pipe_release(state->state, old_right_hwpipe);
306 if (ret)
307 return ret;
308
309 }
310 } else {
311 ret = mdp5_pipe_release(state->state, mdp5_state->hwpipe);
312 if (ret)
313 return ret;
314
315 ret = mdp5_pipe_release(state->state, mdp5_state->r_hwpipe);
316 if (ret)
317 return ret;
318
319 mdp5_state->hwpipe = mdp5_state->r_hwpipe = NULL;
320 }
321
322 return 0;
323 }
324
mdp5_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)325 static int mdp5_plane_atomic_check(struct drm_plane *plane,
326 struct drm_atomic_state *state)
327 {
328 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state,
329 plane);
330 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
331 plane);
332 struct drm_crtc *crtc;
333 struct drm_crtc_state *crtc_state;
334
335 crtc = new_plane_state->crtc ? new_plane_state->crtc : old_plane_state->crtc;
336 if (!crtc)
337 return 0;
338
339 crtc_state = drm_atomic_get_existing_crtc_state(state,
340 crtc);
341 if (WARN_ON(!crtc_state))
342 return -EINVAL;
343
344 return mdp5_plane_atomic_check_with_state(crtc_state, new_plane_state);
345 }
346
mdp5_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)347 static void mdp5_plane_atomic_update(struct drm_plane *plane,
348 struct drm_atomic_state *state)
349 {
350 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
351 plane);
352
353 DBG("%s: update", plane->name);
354
355 if (plane_enabled(new_state)) {
356 int ret;
357
358 ret = mdp5_plane_mode_set(plane,
359 new_state->crtc, new_state->fb,
360 &new_state->src, &new_state->dst);
361 /* atomic_check should have ensured that this doesn't fail */
362 WARN_ON(ret < 0);
363 }
364 }
365
mdp5_plane_atomic_async_check(struct drm_plane * plane,struct drm_atomic_state * state,bool flip)366 static int mdp5_plane_atomic_async_check(struct drm_plane *plane,
367 struct drm_atomic_state *state, bool flip)
368 {
369 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
370 plane);
371 struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(new_plane_state);
372 struct drm_crtc_state *crtc_state;
373 int min_scale, max_scale;
374 int ret;
375
376 crtc_state = drm_atomic_get_existing_crtc_state(state,
377 new_plane_state->crtc);
378 if (WARN_ON(!crtc_state))
379 return -EINVAL;
380
381 if (!crtc_state->active)
382 return -EINVAL;
383
384 /* don't use fast path if we don't have a hwpipe allocated yet */
385 if (!mdp5_state->hwpipe)
386 return -EINVAL;
387
388 /* only allow changing of position(crtc x/y or src x/y) in fast path */
389 if (plane->state->crtc != new_plane_state->crtc ||
390 plane->state->src_w != new_plane_state->src_w ||
391 plane->state->src_h != new_plane_state->src_h ||
392 plane->state->crtc_w != new_plane_state->crtc_w ||
393 plane->state->crtc_h != new_plane_state->crtc_h ||
394 !plane->state->fb ||
395 plane->state->fb != new_plane_state->fb)
396 return -EINVAL;
397
398 min_scale = FRAC_16_16(1, 8);
399 max_scale = FRAC_16_16(8, 1);
400
401 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
402 min_scale, max_scale,
403 true, true);
404 if (ret)
405 return ret;
406
407 /*
408 * if the visibility of the plane changes (i.e, if the cursor is
409 * clipped out completely, we can't take the async path because
410 * we need to stage/unstage the plane from the Layer Mixer(s). We
411 * also assign/unassign the hwpipe(s) tied to the plane. We avoid
412 * taking the fast path for both these reasons.
413 */
414 if (new_plane_state->visible != plane->state->visible)
415 return -EINVAL;
416
417 return 0;
418 }
419
mdp5_plane_atomic_async_update(struct drm_plane * plane,struct drm_atomic_state * state)420 static void mdp5_plane_atomic_async_update(struct drm_plane *plane,
421 struct drm_atomic_state *state)
422 {
423 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
424 plane);
425 struct drm_framebuffer *old_fb = plane->state->fb;
426
427 plane->state->src_x = new_state->src_x;
428 plane->state->src_y = new_state->src_y;
429 plane->state->crtc_x = new_state->crtc_x;
430 plane->state->crtc_y = new_state->crtc_y;
431
432 if (plane_enabled(new_state)) {
433 struct mdp5_ctl *ctl;
434 struct mdp5_pipeline *pipeline =
435 mdp5_crtc_get_pipeline(new_state->crtc);
436 int ret;
437
438 ret = mdp5_plane_mode_set(plane, new_state->crtc, new_state->fb,
439 &new_state->src, &new_state->dst);
440 WARN_ON(ret < 0);
441
442 ctl = mdp5_crtc_get_ctl(new_state->crtc);
443
444 mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true);
445 }
446
447 *to_mdp5_plane_state(plane->state) =
448 *to_mdp5_plane_state(new_state);
449
450 new_state->fb = old_fb;
451 }
452
453 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
454 .prepare_fb = mdp5_plane_prepare_fb,
455 .cleanup_fb = mdp5_plane_cleanup_fb,
456 .atomic_check = mdp5_plane_atomic_check,
457 .atomic_update = mdp5_plane_atomic_update,
458 .atomic_async_check = mdp5_plane_atomic_async_check,
459 .atomic_async_update = mdp5_plane_atomic_async_update,
460 };
461
set_scanout_locked(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct drm_framebuffer * fb)462 static void set_scanout_locked(struct mdp5_kms *mdp5_kms,
463 enum mdp5_pipe pipe,
464 struct drm_framebuffer *fb)
465 {
466 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
467 MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
468 MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
469
470 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
471 MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
472 MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
473
474 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
475 msm_framebuffer_iova(fb, 0));
476 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
477 msm_framebuffer_iova(fb, 1));
478 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
479 msm_framebuffer_iova(fb, 2));
480 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
481 msm_framebuffer_iova(fb, 3));
482 }
483
484 /* Note: mdp5_plane->pipe_lock must be locked */
csc_disable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe)485 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
486 {
487 uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
488 ~MDP5_PIPE_OP_MODE_CSC_1_EN;
489
490 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
491 }
492
493 /* Note: mdp5_plane->pipe_lock must be locked */
csc_enable(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,struct csc_cfg * csc)494 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
495 struct csc_cfg *csc)
496 {
497 uint32_t i, mode = 0; /* RGB, no CSC */
498 uint32_t *matrix;
499
500 if (unlikely(!csc))
501 return;
502
503 if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
504 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
505 if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
506 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
507 mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
508 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
509
510 matrix = csc->matrix;
511 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
512 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
513 MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
514 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
515 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
516 MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
517 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
518 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
519 MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
520 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
521 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
522 MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
523 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
524 MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
525
526 for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
527 uint32_t *pre_clamp = csc->pre_clamp;
528 uint32_t *post_clamp = csc->post_clamp;
529
530 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
531 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
532 MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
533
534 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
535 MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
536 MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
537
538 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
539 MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
540
541 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
542 MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
543 }
544 }
545
546 #define PHASE_STEP_SHIFT 21
547 #define DOWN_SCALE_RATIO_MAX 32 /* 2^(26-21) */
548
calc_phase_step(uint32_t src,uint32_t dst,uint32_t * out_phase)549 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
550 {
551 uint32_t unit;
552
553 if (src == 0 || dst == 0)
554 return -EINVAL;
555
556 /*
557 * PHASE_STEP_X/Y is coded on 26 bits (25:0),
558 * where 2^21 represents the unity "1" in fixed-point hardware design.
559 * This leaves 5 bits for the integer part (downscale case):
560 * -> maximum downscale ratio = 0b1_1111 = 31
561 */
562 if (src > (dst * DOWN_SCALE_RATIO_MAX))
563 return -EOVERFLOW;
564
565 unit = 1 << PHASE_STEP_SHIFT;
566 *out_phase = mult_frac(unit, src, dst);
567
568 return 0;
569 }
570
calc_scalex_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasex_steps[COMP_MAX])571 static int calc_scalex_steps(struct drm_plane *plane,
572 uint32_t pixel_format, uint32_t src, uint32_t dest,
573 uint32_t phasex_steps[COMP_MAX])
574 {
575 const struct drm_format_info *info = drm_format_info(pixel_format);
576 struct mdp5_kms *mdp5_kms = get_kms(plane);
577 struct device *dev = mdp5_kms->dev->dev;
578 uint32_t phasex_step;
579 int ret;
580
581 ret = calc_phase_step(src, dest, &phasex_step);
582 if (ret) {
583 DRM_DEV_ERROR(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
584 return ret;
585 }
586
587 phasex_steps[COMP_0] = phasex_step;
588 phasex_steps[COMP_3] = phasex_step;
589 phasex_steps[COMP_1_2] = phasex_step / info->hsub;
590
591 return 0;
592 }
593
calc_scaley_steps(struct drm_plane * plane,uint32_t pixel_format,uint32_t src,uint32_t dest,uint32_t phasey_steps[COMP_MAX])594 static int calc_scaley_steps(struct drm_plane *plane,
595 uint32_t pixel_format, uint32_t src, uint32_t dest,
596 uint32_t phasey_steps[COMP_MAX])
597 {
598 const struct drm_format_info *info = drm_format_info(pixel_format);
599 struct mdp5_kms *mdp5_kms = get_kms(plane);
600 struct device *dev = mdp5_kms->dev->dev;
601 uint32_t phasey_step;
602 int ret;
603
604 ret = calc_phase_step(src, dest, &phasey_step);
605 if (ret) {
606 DRM_DEV_ERROR(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
607 return ret;
608 }
609
610 phasey_steps[COMP_0] = phasey_step;
611 phasey_steps[COMP_3] = phasey_step;
612 phasey_steps[COMP_1_2] = phasey_step / info->vsub;
613
614 return 0;
615 }
616
get_scale_config(const struct msm_format * format,uint32_t src,uint32_t dst,bool horz)617 static uint32_t get_scale_config(const struct msm_format *format,
618 uint32_t src, uint32_t dst, bool horz)
619 {
620 const struct drm_format_info *info = drm_format_info(format->pixel_format);
621 bool yuv = MSM_FORMAT_IS_YUV(format);
622 bool scaling = yuv ? true : (src != dst);
623 uint32_t sub;
624 uint32_t ya_filter, uv_filter;
625
626 if (!scaling)
627 return 0;
628
629 if (yuv) {
630 sub = horz ? info->hsub : info->vsub;
631 uv_filter = ((src / sub) <= dst) ?
632 SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
633 }
634 ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
635
636 if (horz)
637 return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
638 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
639 MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
640 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
641 else
642 return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
643 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
644 MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
645 COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
646 }
647
calc_pixel_ext(const struct msm_format * format,uint32_t src,uint32_t dst,uint32_t phase_step[2],int pix_ext_edge1[COMP_MAX],int pix_ext_edge2[COMP_MAX],bool horz)648 static void calc_pixel_ext(const struct msm_format *format,
649 uint32_t src, uint32_t dst, uint32_t phase_step[2],
650 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
651 bool horz)
652 {
653 bool scaling = MSM_FORMAT_IS_YUV(format) ? true : (src != dst);
654 int i;
655
656 /*
657 * Note:
658 * We assume here that:
659 * 1. PCMN filter is used for downscale
660 * 2. bilinear filter is used for upscale
661 * 3. we are in a single pipe configuration
662 */
663
664 for (i = 0; i < COMP_MAX; i++) {
665 pix_ext_edge1[i] = 0;
666 pix_ext_edge2[i] = scaling ? 1 : 0;
667 }
668 }
669
mdp5_write_pixel_ext(struct mdp5_kms * mdp5_kms,enum mdp5_pipe pipe,const struct msm_format * format,uint32_t src_w,int pe_left[COMP_MAX],int pe_right[COMP_MAX],uint32_t src_h,int pe_top[COMP_MAX],int pe_bottom[COMP_MAX])670 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
671 const struct msm_format *format,
672 uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
673 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
674 {
675 const struct drm_format_info *info = drm_format_info(format->pixel_format);
676 uint32_t lr, tb, req;
677 int i;
678
679 for (i = 0; i < COMP_MAX; i++) {
680 uint32_t roi_w = src_w;
681 uint32_t roi_h = src_h;
682
683 if (MSM_FORMAT_IS_YUV(format) && i == COMP_1_2) {
684 roi_w /= info->hsub;
685 roi_h /= info->vsub;
686 }
687
688 lr = (pe_left[i] >= 0) ?
689 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
690 MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
691
692 lr |= (pe_right[i] >= 0) ?
693 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
694 MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
695
696 tb = (pe_top[i] >= 0) ?
697 MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
698 MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
699
700 tb |= (pe_bottom[i] >= 0) ?
701 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
702 MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
703
704 req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
705 pe_left[i] + pe_right[i]);
706
707 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
708 pe_top[i] + pe_bottom[i]);
709
710 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
711 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
712 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
713
714 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
715 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
716 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
717 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
718 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
719 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
720
721 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
722 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
723 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
724 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
725 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
726 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
727 }
728 }
729
730 struct pixel_ext {
731 int left[COMP_MAX];
732 int right[COMP_MAX];
733 int top[COMP_MAX];
734 int bottom[COMP_MAX];
735 };
736
737 struct phase_step {
738 u32 x[COMP_MAX];
739 u32 y[COMP_MAX];
740 };
741
mdp5_hwpipe_mode_set(struct mdp5_kms * mdp5_kms,struct mdp5_hw_pipe * hwpipe,struct drm_framebuffer * fb,struct phase_step * step,struct pixel_ext * pe,u32 scale_config,u32 hdecm,u32 vdecm,bool hflip,bool vflip,int crtc_x,int crtc_y,unsigned int crtc_w,unsigned int crtc_h,u32 src_img_w,u32 src_img_h,u32 src_x,u32 src_y,u32 src_w,u32 src_h)742 static void mdp5_hwpipe_mode_set(struct mdp5_kms *mdp5_kms,
743 struct mdp5_hw_pipe *hwpipe,
744 struct drm_framebuffer *fb,
745 struct phase_step *step,
746 struct pixel_ext *pe,
747 u32 scale_config, u32 hdecm, u32 vdecm,
748 bool hflip, bool vflip,
749 int crtc_x, int crtc_y,
750 unsigned int crtc_w, unsigned int crtc_h,
751 u32 src_img_w, u32 src_img_h,
752 u32 src_x, u32 src_y,
753 u32 src_w, u32 src_h)
754 {
755 enum mdp5_pipe pipe = hwpipe->pipe;
756 bool has_pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
757 const struct msm_format *format =
758 msm_framebuffer_format(fb);
759
760 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
761 MDP5_PIPE_SRC_IMG_SIZE_WIDTH(src_img_w) |
762 MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(src_img_h));
763
764 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
765 MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
766 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
767
768 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
769 MDP5_PIPE_SRC_XY_X(src_x) |
770 MDP5_PIPE_SRC_XY_Y(src_y));
771
772 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
773 MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
774 MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
775
776 mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
777 MDP5_PIPE_OUT_XY_X(crtc_x) |
778 MDP5_PIPE_OUT_XY_Y(crtc_y));
779
780 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
781 MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
782 MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r_cr) |
783 MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g_y) |
784 MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b_cb) |
785 COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
786 MDP5_PIPE_SRC_FORMAT_CPP(format->bpp - 1) |
787 MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
788 COND(format->flags & MSM_FORMAT_FLAG_UNPACK_TIGHT,
789 MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
790 MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
791 MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
792
793 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
794 MDP5_PIPE_SRC_UNPACK_ELEM0(format->element[0]) |
795 MDP5_PIPE_SRC_UNPACK_ELEM1(format->element[1]) |
796 MDP5_PIPE_SRC_UNPACK_ELEM2(format->element[2]) |
797 MDP5_PIPE_SRC_UNPACK_ELEM3(format->element[3]));
798
799 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
800 (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
801 (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
802 COND(has_pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
803 MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
804
805 /* not using secure mode: */
806 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
807
808 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
809 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
810 src_w, pe->left, pe->right,
811 src_h, pe->top, pe->bottom);
812
813 if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
814 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
815 step->x[COMP_0]);
816 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
817 step->y[COMP_0]);
818 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
819 step->x[COMP_1_2]);
820 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
821 step->y[COMP_1_2]);
822 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
823 MDP5_PIPE_DECIMATION_VERT(vdecm) |
824 MDP5_PIPE_DECIMATION_HORZ(hdecm));
825 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe),
826 scale_config);
827 }
828
829 if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
830 if (MSM_FORMAT_IS_YUV(format))
831 csc_enable(mdp5_kms, pipe,
832 mdp_get_default_csc_cfg(CSC_YUV2RGB));
833 else
834 csc_disable(mdp5_kms, pipe);
835 }
836
837 set_scanout_locked(mdp5_kms, pipe, fb);
838 }
839
mdp5_plane_mode_set(struct drm_plane * plane,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_rect * src,struct drm_rect * dest)840 static int mdp5_plane_mode_set(struct drm_plane *plane,
841 struct drm_crtc *crtc, struct drm_framebuffer *fb,
842 struct drm_rect *src, struct drm_rect *dest)
843 {
844 struct drm_plane_state *pstate = plane->state;
845 struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
846 struct mdp5_kms *mdp5_kms = get_kms(plane);
847 enum mdp5_pipe pipe = hwpipe->pipe;
848 struct mdp5_hw_pipe *right_hwpipe;
849 const struct msm_format *format;
850 uint32_t nplanes, config = 0;
851 struct phase_step step = { { 0 } };
852 struct pixel_ext pe = { { 0 } };
853 uint32_t hdecm = 0, vdecm = 0;
854 uint32_t pix_format;
855 unsigned int rotation;
856 bool vflip, hflip;
857 int crtc_x, crtc_y;
858 unsigned int crtc_w, crtc_h;
859 uint32_t src_x, src_y;
860 uint32_t src_w, src_h;
861 uint32_t src_img_w, src_img_h;
862 int ret;
863
864 nplanes = fb->format->num_planes;
865
866 /* bad formats should already be rejected: */
867 if (WARN_ON(nplanes > pipe2nclients(pipe)))
868 return -EINVAL;
869
870 format = msm_framebuffer_format(fb);
871 pix_format = format->pixel_format;
872
873 src_x = src->x1;
874 src_y = src->y1;
875 src_w = drm_rect_width(src);
876 src_h = drm_rect_height(src);
877
878 crtc_x = dest->x1;
879 crtc_y = dest->y1;
880 crtc_w = drm_rect_width(dest);
881 crtc_h = drm_rect_height(dest);
882
883 /* src values are in Q16 fixed point, convert to integer: */
884 src_x = src_x >> 16;
885 src_y = src_y >> 16;
886 src_w = src_w >> 16;
887 src_h = src_h >> 16;
888
889 src_img_w = min(fb->width, src_w);
890 src_img_h = min(fb->height, src_h);
891
892 DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
893 fb->base.id, src_x, src_y, src_w, src_h,
894 crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
895
896 right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
897 if (right_hwpipe) {
898 /*
899 * if the plane comprises of 2 hw pipes, assume that the width
900 * is split equally across them. The only parameters that varies
901 * between the 2 pipes are src_x and crtc_x
902 */
903 crtc_w /= 2;
904 src_w /= 2;
905 src_img_w /= 2;
906 }
907
908 ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, step.x);
909 if (ret)
910 return ret;
911
912 ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, step.y);
913 if (ret)
914 return ret;
915
916 if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
917 calc_pixel_ext(format, src_w, crtc_w, step.x,
918 pe.left, pe.right, true);
919 calc_pixel_ext(format, src_h, crtc_h, step.y,
920 pe.top, pe.bottom, false);
921 }
922
923 /* TODO calc hdecm, vdecm */
924
925 /* SCALE is used to both scale and up-sample chroma components */
926 config |= get_scale_config(format, src_w, crtc_w, true);
927 config |= get_scale_config(format, src_h, crtc_h, false);
928 DBG("scale config = %x", config);
929
930 rotation = drm_rotation_simplify(pstate->rotation,
931 DRM_MODE_ROTATE_0 |
932 DRM_MODE_REFLECT_X |
933 DRM_MODE_REFLECT_Y);
934 hflip = !!(rotation & DRM_MODE_REFLECT_X);
935 vflip = !!(rotation & DRM_MODE_REFLECT_Y);
936
937 mdp5_hwpipe_mode_set(mdp5_kms, hwpipe, fb, &step, &pe,
938 config, hdecm, vdecm, hflip, vflip,
939 crtc_x, crtc_y, crtc_w, crtc_h,
940 src_img_w, src_img_h,
941 src_x, src_y, src_w, src_h);
942 if (right_hwpipe)
943 mdp5_hwpipe_mode_set(mdp5_kms, right_hwpipe, fb, &step, &pe,
944 config, hdecm, vdecm, hflip, vflip,
945 crtc_x + crtc_w, crtc_y, crtc_w, crtc_h,
946 src_img_w, src_img_h,
947 src_x + src_w, src_y, src_w, src_h);
948
949 return ret;
950 }
951
952 /*
953 * Use this func and the one below only after the atomic state has been
954 * successfully swapped
955 */
mdp5_plane_pipe(struct drm_plane * plane)956 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
957 {
958 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
959
960 if (WARN_ON(!pstate->hwpipe))
961 return SSPP_NONE;
962
963 return pstate->hwpipe->pipe;
964 }
965
mdp5_plane_right_pipe(struct drm_plane * plane)966 enum mdp5_pipe mdp5_plane_right_pipe(struct drm_plane *plane)
967 {
968 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
969
970 if (!pstate->r_hwpipe)
971 return SSPP_NONE;
972
973 return pstate->r_hwpipe->pipe;
974 }
975
mdp5_plane_get_flush(struct drm_plane * plane)976 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
977 {
978 struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
979 u32 mask;
980
981 if (WARN_ON(!pstate->hwpipe))
982 return 0;
983
984 mask = pstate->hwpipe->flush_mask;
985
986 if (pstate->r_hwpipe)
987 mask |= pstate->r_hwpipe->flush_mask;
988
989 return mask;
990 }
991
992 static const uint32_t mdp5_plane_formats[] = {
993 DRM_FORMAT_ARGB8888,
994 DRM_FORMAT_ABGR8888,
995 DRM_FORMAT_RGBA8888,
996 DRM_FORMAT_BGRA8888,
997 DRM_FORMAT_XRGB8888,
998 DRM_FORMAT_XBGR8888,
999 DRM_FORMAT_RGBX8888,
1000 DRM_FORMAT_BGRX8888,
1001 DRM_FORMAT_RGB888,
1002 DRM_FORMAT_BGR888,
1003 DRM_FORMAT_RGB565,
1004 DRM_FORMAT_BGR565,
1005
1006 DRM_FORMAT_NV12,
1007 DRM_FORMAT_NV21,
1008 DRM_FORMAT_NV16,
1009 DRM_FORMAT_NV61,
1010 DRM_FORMAT_VYUY,
1011 DRM_FORMAT_UYVY,
1012 DRM_FORMAT_YUYV,
1013 DRM_FORMAT_YVYU,
1014 DRM_FORMAT_YUV420,
1015 DRM_FORMAT_YVU420,
1016 };
1017
1018 /* initialize plane */
mdp5_plane_init(struct drm_device * dev,enum drm_plane_type type)1019 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
1020 enum drm_plane_type type)
1021 {
1022 struct drm_plane *plane = NULL;
1023 struct mdp5_plane *mdp5_plane;
1024
1025 mdp5_plane = drmm_universal_plane_alloc(dev, struct mdp5_plane, base,
1026 0xff, &mdp5_plane_funcs,
1027 mdp5_plane_formats, ARRAY_SIZE(mdp5_plane_formats),
1028 NULL, type, NULL);
1029 if (IS_ERR(mdp5_plane))
1030 return ERR_CAST(mdp5_plane);
1031
1032 plane = &mdp5_plane->base;
1033
1034 drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
1035
1036 mdp5_plane_install_properties(plane, &plane->base);
1037
1038 drm_plane_enable_fb_damage_clips(plane);
1039
1040 return plane;
1041 }
1042