1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver
4 //
5 // Copyright (c) 2019, 2020, 2021, 2023 Pengutronix,
6 // Marc Kleine-Budde <kernel@pengutronix.de>
7 //
8 // Based on:
9 //
10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
11 //
12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
13 //
14
15 #include <linux/unaligned.h>
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/property.h>
23
24 #include "mcp251xfd.h"
25
26 #define DEVICE_NAME "mcp251xfd"
27
28 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
29 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
30 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
31 MCP251XFD_QUIRK_ECC,
32 .model = MCP251XFD_MODEL_MCP2517FD,
33 };
34
35 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
36 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
37 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
38 .model = MCP251XFD_MODEL_MCP2518FD,
39 };
40
41 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
42 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
43 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
44 .model = MCP251XFD_MODEL_MCP251863,
45 };
46
47 /* Autodetect model, start with CRC enabled. */
48 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
49 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
50 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
51 .model = MCP251XFD_MODEL_MCP251XFD,
52 };
53
54 static const struct can_bittiming_const mcp251xfd_bittiming_const = {
55 .name = DEVICE_NAME,
56 .tseg1_min = 2,
57 .tseg1_max = 256,
58 .tseg2_min = 1,
59 .tseg2_max = 128,
60 .sjw_max = 128,
61 .brp_min = 1,
62 .brp_max = 256,
63 .brp_inc = 1,
64 };
65
66 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
67 .name = DEVICE_NAME,
68 .tseg1_min = 1,
69 .tseg1_max = 32,
70 .tseg2_min = 1,
71 .tseg2_max = 16,
72 .sjw_max = 16,
73 .brp_min = 1,
74 .brp_max = 256,
75 .brp_inc = 1,
76 };
77
78 /* The datasheet of the mcp2518fd (DS20006027B) specifies a range of
79 * [-64,63] for TDCO, indicating a relative TDCO.
80 *
81 * Manual tests have shown, that using a relative TDCO configuration
82 * results in bus off, while an absolute configuration works.
83 *
84 * For TDCO use the max value (63) from the data sheet, but 0 as the
85 * minimum.
86 */
87 static const struct can_tdc_const mcp251xfd_tdc_const = {
88 .tdcv_min = 0,
89 .tdcv_max = 63,
90 .tdco_min = 0,
91 .tdco_max = 63,
92 .tdcf_min = 0,
93 .tdcf_max = 0,
94 };
95
__mcp251xfd_get_model_str(enum mcp251xfd_model model)96 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
97 {
98 switch (model) {
99 case MCP251XFD_MODEL_MCP2517FD:
100 return "MCP2517FD";
101 case MCP251XFD_MODEL_MCP2518FD:
102 return "MCP2518FD";
103 case MCP251XFD_MODEL_MCP251863:
104 return "MCP251863";
105 case MCP251XFD_MODEL_MCP251XFD:
106 return "MCP251xFD";
107 }
108
109 return "<unknown>";
110 }
111
112 static inline const char *
mcp251xfd_get_model_str(const struct mcp251xfd_priv * priv)113 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
114 {
115 return __mcp251xfd_get_model_str(priv->devtype_data.model);
116 }
117
mcp251xfd_get_mode_str(const u8 mode)118 static const char *mcp251xfd_get_mode_str(const u8 mode)
119 {
120 switch (mode) {
121 case MCP251XFD_REG_CON_MODE_MIXED:
122 return "Mixed (CAN FD/CAN 2.0)";
123 case MCP251XFD_REG_CON_MODE_SLEEP:
124 return "Sleep";
125 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
126 return "Internal Loopback";
127 case MCP251XFD_REG_CON_MODE_LISTENONLY:
128 return "Listen Only";
129 case MCP251XFD_REG_CON_MODE_CONFIG:
130 return "Configuration";
131 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
132 return "External Loopback";
133 case MCP251XFD_REG_CON_MODE_CAN2_0:
134 return "CAN 2.0";
135 case MCP251XFD_REG_CON_MODE_RESTRICTED:
136 return "Restricted Operation";
137 }
138
139 return "<unknown>";
140 }
141
142 static const char *
mcp251xfd_get_osc_str(const u32 osc,const u32 osc_reference)143 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
144 {
145 switch (~osc & osc_reference &
146 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
147 case MCP251XFD_REG_OSC_PLLRDY:
148 return "PLL";
149 case MCP251XFD_REG_OSC_OSCRDY:
150 return "Oscillator";
151 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
152 return "Oscillator/PLL";
153 }
154
155 return "<unknown>";
156 }
157
mcp251xfd_vdd_enable(const struct mcp251xfd_priv * priv)158 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
159 {
160 if (!priv->reg_vdd)
161 return 0;
162
163 return regulator_enable(priv->reg_vdd);
164 }
165
mcp251xfd_vdd_disable(const struct mcp251xfd_priv * priv)166 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
167 {
168 if (!priv->reg_vdd)
169 return 0;
170
171 return regulator_disable(priv->reg_vdd);
172 }
173
174 static inline int
mcp251xfd_transceiver_enable(const struct mcp251xfd_priv * priv)175 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
176 {
177 if (!priv->reg_xceiver)
178 return 0;
179
180 return regulator_enable(priv->reg_xceiver);
181 }
182
183 static inline int
mcp251xfd_transceiver_disable(const struct mcp251xfd_priv * priv)184 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
185 {
186 if (!priv->reg_xceiver)
187 return 0;
188
189 return regulator_disable(priv->reg_xceiver);
190 }
191
mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv * priv)192 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
193 {
194 int err;
195
196 err = clk_prepare_enable(priv->clk);
197 if (err)
198 return err;
199
200 err = mcp251xfd_vdd_enable(priv);
201 if (err)
202 clk_disable_unprepare(priv->clk);
203
204 /* Wait for oscillator stabilisation time after power up */
205 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
206 2 * MCP251XFD_OSC_STAB_SLEEP_US);
207
208 return err;
209 }
210
mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv * priv)211 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
212 {
213 int err;
214
215 err = mcp251xfd_vdd_disable(priv);
216 if (err)
217 return err;
218
219 clk_disable_unprepare(priv->clk);
220
221 return 0;
222 }
223
mcp251xfd_reg_invalid(u32 reg)224 static inline bool mcp251xfd_reg_invalid(u32 reg)
225 {
226 return reg == 0x0 || reg == 0xffffffff;
227 }
228
229 static inline int
mcp251xfd_chip_get_mode(const struct mcp251xfd_priv * priv,u8 * mode)230 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
231 {
232 u32 val;
233 int err;
234
235 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
236 if (err)
237 return err;
238
239 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
240
241 return 0;
242 }
243
244 static int
__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req,bool nowait)245 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
246 const u8 mode_req, bool nowait)
247 {
248 const struct can_bittiming *bt = &priv->can.bittiming;
249 unsigned long timeout_us = MCP251XFD_POLL_TIMEOUT_US;
250 u32 con = 0, con_reqop, osc = 0;
251 u8 mode;
252 int err;
253
254 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
255 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
256 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
257 if (err == -EBADMSG) {
258 netdev_err(priv->ndev,
259 "Failed to set Requested Operation Mode.\n");
260
261 return -ENODEV;
262 } else if (err) {
263 return err;
264 }
265
266 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
267 return 0;
268
269 if (bt->bitrate)
270 timeout_us = max_t(unsigned long, timeout_us,
271 MCP251XFD_FRAME_LEN_MAX_BITS * USEC_PER_SEC /
272 bt->bitrate);
273
274 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
275 !mcp251xfd_reg_invalid(con) &&
276 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
277 con) == mode_req,
278 MCP251XFD_POLL_SLEEP_US, timeout_us);
279 if (err != -ETIMEDOUT && err != -EBADMSG)
280 return err;
281
282 /* Ignore return value.
283 * Print below error messages, even if this fails.
284 */
285 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
286
287 if (mcp251xfd_reg_invalid(con)) {
288 netdev_err(priv->ndev,
289 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
290 con, osc);
291
292 return -ENODEV;
293 }
294
295 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
296 netdev_err(priv->ndev,
297 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
298 mcp251xfd_get_mode_str(mode_req), mode_req,
299 mcp251xfd_get_mode_str(mode), mode,
300 con, osc);
301
302 return -ETIMEDOUT;
303 }
304
305 static inline int
mcp251xfd_chip_set_mode(const struct mcp251xfd_priv * priv,const u8 mode_req)306 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
307 const u8 mode_req)
308 {
309 return __mcp251xfd_chip_set_mode(priv, mode_req, false);
310 }
311
312 static inline int __maybe_unused
mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv * priv,const u8 mode_req)313 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
314 const u8 mode_req)
315 {
316 return __mcp251xfd_chip_set_mode(priv, mode_req, true);
317 }
318
319 static int
mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv * priv,u32 osc_reference,u32 osc_mask)320 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
321 u32 osc_reference, u32 osc_mask)
322 {
323 u32 osc;
324 int err;
325
326 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
327 !mcp251xfd_reg_invalid(osc) &&
328 (osc & osc_mask) == osc_reference,
329 MCP251XFD_OSC_STAB_SLEEP_US,
330 MCP251XFD_OSC_STAB_TIMEOUT_US);
331 if (err != -ETIMEDOUT)
332 return err;
333
334 if (mcp251xfd_reg_invalid(osc)) {
335 netdev_err(priv->ndev,
336 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
337 osc);
338 return -ENODEV;
339 }
340
341 netdev_err(priv->ndev,
342 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
343 mcp251xfd_get_osc_str(osc, osc_reference),
344 osc, osc_reference, osc_mask);
345
346 return -ETIMEDOUT;
347 }
348
mcp251xfd_chip_wake(const struct mcp251xfd_priv * priv)349 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
350 {
351 u32 osc, osc_reference, osc_mask;
352 int err;
353
354 /* For normal sleep on MCP2517FD and MCP2518FD, clearing
355 * "Oscillator Disable" will wake the chip. For low power mode
356 * on MCP2518FD, asserting the chip select will wake the
357 * chip. Writing to the Oscillator register will wake it in
358 * both cases.
359 */
360 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
361 MCP251XFD_REG_OSC_CLKODIV_10);
362
363 /* We cannot check for the PLL ready bit (either set or
364 * unset), as the PLL might be enabled. This can happen if the
365 * system reboots, while the mcp251xfd stays powered.
366 */
367 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
368 osc_mask = MCP251XFD_REG_OSC_OSCRDY;
369
370 /* If the controller is in Sleep Mode the following write only
371 * removes the "Oscillator Disable" bit and powers it up. All
372 * other bits are unaffected.
373 */
374 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
375 if (err)
376 return err;
377
378 /* Sometimes the PLL is stuck enabled, the controller never
379 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
380 * caller takes care of retry.
381 */
382 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
383 }
384
mcp251xfd_chip_sleep(const struct mcp251xfd_priv * priv)385 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
386 {
387 if (priv->pll_enable) {
388 u32 osc;
389 int err;
390
391 /* Turn off PLL */
392 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
393 MCP251XFD_REG_OSC_CLKODIV_10);
394 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
395 if (err)
396 netdev_err(priv->ndev,
397 "Failed to disable PLL.\n");
398
399 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
400 }
401
402 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
403 }
404
mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv * priv)405 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
406 {
407 const __be16 cmd = mcp251xfd_cmd_reset();
408 int err;
409
410 /* The Set Mode and SPI Reset command only works if the
411 * controller is not in Sleep Mode.
412 */
413 err = mcp251xfd_chip_wake(priv);
414 if (err)
415 return err;
416
417 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
418 if (err)
419 return err;
420
421 /* spi_write_then_read() works with non DMA-safe buffers */
422 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
423 }
424
mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv * priv)425 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
426 {
427 u32 osc_reference, osc_mask;
428 u8 mode;
429 int err;
430
431 /* Check for reset defaults of OSC reg.
432 * This will take care of stabilization period.
433 */
434 osc_reference = MCP251XFD_REG_OSC_OSCRDY |
435 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
436 MCP251XFD_REG_OSC_CLKODIV_10);
437 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
438 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
439 if (err)
440 return err;
441
442 err = mcp251xfd_chip_get_mode(priv, &mode);
443 if (err)
444 return err;
445
446 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
447 netdev_info(priv->ndev,
448 "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
449 mcp251xfd_get_mode_str(mode), mode);
450 return -ETIMEDOUT;
451 }
452
453 return 0;
454 }
455
mcp251xfd_chip_softreset(const struct mcp251xfd_priv * priv)456 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
457 {
458 int err, i;
459
460 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
461 if (i)
462 netdev_info(priv->ndev,
463 "Retrying to reset controller.\n");
464
465 err = mcp251xfd_chip_softreset_do(priv);
466 if (err == -ETIMEDOUT)
467 continue;
468 if (err)
469 return err;
470
471 err = mcp251xfd_chip_softreset_check(priv);
472 if (err == -ETIMEDOUT)
473 continue;
474 if (err)
475 return err;
476
477 return 0;
478 }
479
480 return err;
481 }
482
mcp251xfd_chip_clock_init(const struct mcp251xfd_priv * priv)483 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
484 {
485 u32 osc, osc_reference, osc_mask;
486 int err;
487
488 /* Activate Low Power Mode on Oscillator Disable. This only
489 * works on the MCP2518FD. The MCP2517FD will go into normal
490 * Sleep Mode instead.
491 */
492 osc = MCP251XFD_REG_OSC_LPMEN |
493 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
494 MCP251XFD_REG_OSC_CLKODIV_10);
495 osc_reference = MCP251XFD_REG_OSC_OSCRDY;
496 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
497
498 if (priv->pll_enable) {
499 osc |= MCP251XFD_REG_OSC_PLLEN;
500 osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
501 }
502
503 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
504 if (err)
505 return err;
506
507 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
508 if (err)
509 return err;
510
511 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
512
513 return 0;
514 }
515
mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv * priv)516 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
517 {
518 /* Set Time Base Counter Prescaler to 1.
519 *
520 * This means an overflow of the 32 bit Time Base Counter
521 * register at 40 MHz every 107 seconds.
522 */
523 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
524 MCP251XFD_REG_TSCON_TBCEN);
525 }
526
mcp251xfd_set_bittiming(const struct mcp251xfd_priv * priv)527 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
528 {
529 const struct can_bittiming *bt = &priv->can.bittiming;
530 const struct can_bittiming *dbt = &priv->can.data_bittiming;
531 u32 tdcmod, val = 0;
532 int err;
533
534 /* CAN Control Register
535 *
536 * - no transmit bandwidth sharing
537 * - config mode
538 * - disable transmit queue
539 * - store in transmit FIFO event
540 * - transition to restricted operation mode on system error
541 * - ESI is transmitted recessive when ESI of message is high or
542 * CAN controller error passive
543 * - restricted retransmission attempts,
544 * use TQXCON_TXAT and FIFOCON_TXAT
545 * - wake-up filter bits T11FILTER
546 * - use CAN bus line filter for wakeup
547 * - protocol exception is treated as a form error
548 * - Do not compare data bytes
549 */
550 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
551 MCP251XFD_REG_CON_MODE_CONFIG) |
552 MCP251XFD_REG_CON_STEF |
553 MCP251XFD_REG_CON_ESIGM |
554 MCP251XFD_REG_CON_RTXAT |
555 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
556 MCP251XFD_REG_CON_WFT_T11FILTER) |
557 MCP251XFD_REG_CON_WAKFIL |
558 MCP251XFD_REG_CON_PXEDIS;
559
560 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
561 val |= MCP251XFD_REG_CON_ISOCRCEN;
562
563 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
564 if (err)
565 return err;
566
567 /* Nominal Bit Time */
568 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
569 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
570 bt->prop_seg + bt->phase_seg1 - 1) |
571 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
572 bt->phase_seg2 - 1) |
573 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
574
575 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
576 if (err)
577 return err;
578
579 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
580 return 0;
581
582 /* Data Bit Time */
583 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
584 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
585 dbt->prop_seg + dbt->phase_seg1 - 1) |
586 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
587 dbt->phase_seg2 - 1) |
588 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
589
590 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
591 if (err)
592 return err;
593
594 /* Transmitter Delay Compensation */
595 if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_AUTO)
596 tdcmod = MCP251XFD_REG_TDC_TDCMOD_AUTO;
597 else if (priv->can.ctrlmode & CAN_CTRLMODE_TDC_MANUAL)
598 tdcmod = MCP251XFD_REG_TDC_TDCMOD_MANUAL;
599 else
600 tdcmod = MCP251XFD_REG_TDC_TDCMOD_DISABLED;
601
602 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, tdcmod) |
603 FIELD_PREP(MCP251XFD_REG_TDC_TDCV_MASK, priv->can.tdc.tdcv) |
604 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, priv->can.tdc.tdco);
605
606 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
607 }
608
mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv * priv)609 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
610 {
611 u32 val;
612
613 if (!priv->rx_int)
614 return 0;
615
616 /* Configure GPIOs:
617 * - PIN0: GPIO Input
618 * - PIN1: GPIO Input/RX Interrupt
619 *
620 * PIN1 must be Input, otherwise there is a glitch on the
621 * rx-INT line. It happens between setting the PIN as output
622 * (in the first byte of the SPI transfer) and configuring the
623 * PIN as interrupt (in the last byte of the SPI transfer).
624 */
625 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
626 MCP251XFD_REG_IOCON_TRIS0;
627 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
628 }
629
mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv * priv)630 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
631 {
632 u32 val;
633
634 if (!priv->rx_int)
635 return 0;
636
637 /* Configure GPIOs:
638 * - PIN0: GPIO Input
639 * - PIN1: GPIO Input
640 */
641 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
642 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
643 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
644 }
645
mcp251xfd_chip_ecc_init(struct mcp251xfd_priv * priv)646 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
647 {
648 struct mcp251xfd_ecc *ecc = &priv->ecc;
649 void *ram;
650 u32 val = 0;
651 int err;
652
653 ecc->ecc_stat = 0;
654
655 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
656 val = MCP251XFD_REG_ECCCON_ECCEN;
657
658 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
659 MCP251XFD_REG_ECCCON_ECCEN, val);
660 if (err)
661 return err;
662
663 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
664 if (!ram)
665 return -ENOMEM;
666
667 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
668 MCP251XFD_RAM_SIZE);
669 kfree(ram);
670
671 return err;
672 }
673
mcp251xfd_get_normal_mode(const struct mcp251xfd_priv * priv)674 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
675 {
676 u8 mode;
677
678 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
679 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
680 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
681 mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
682 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
683 mode = MCP251XFD_REG_CON_MODE_MIXED;
684 else
685 mode = MCP251XFD_REG_CON_MODE_CAN2_0;
686
687 return mode;
688 }
689
690 static int
__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv,bool nowait)691 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
692 bool nowait)
693 {
694 u8 mode;
695
696 mode = mcp251xfd_get_normal_mode(priv);
697
698 return __mcp251xfd_chip_set_mode(priv, mode, nowait);
699 }
700
701 static inline int
mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv * priv)702 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
703 {
704 return __mcp251xfd_chip_set_normal_mode(priv, false);
705 }
706
707 static inline int
mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv * priv)708 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
709 {
710 return __mcp251xfd_chip_set_normal_mode(priv, true);
711 }
712
mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv * priv)713 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
714 {
715 u32 val;
716 int err;
717
718 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
719 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
720 if (err)
721 return err;
722
723 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
724 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
725 if (err)
726 return err;
727
728 val = MCP251XFD_REG_INT_CERRIE |
729 MCP251XFD_REG_INT_SERRIE |
730 MCP251XFD_REG_INT_RXOVIE |
731 MCP251XFD_REG_INT_TXATIE |
732 MCP251XFD_REG_INT_SPICRCIE |
733 MCP251XFD_REG_INT_ECCIE |
734 MCP251XFD_REG_INT_TEFIE |
735 MCP251XFD_REG_INT_MODIE |
736 MCP251XFD_REG_INT_RXIE;
737
738 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
739 val |= MCP251XFD_REG_INT_IVMIE;
740
741 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
742 }
743
mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv * priv)744 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
745 {
746 int err;
747 u32 mask;
748
749 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
750 if (err)
751 return err;
752
753 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
754 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
755 mask, 0x0);
756 if (err)
757 return err;
758
759 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
760 }
761
mcp251xfd_chip_stop(struct mcp251xfd_priv * priv,const enum can_state state)762 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
763 const enum can_state state)
764 {
765 priv->can.state = state;
766
767 mcp251xfd_chip_interrupts_disable(priv);
768 mcp251xfd_chip_rx_int_disable(priv);
769 mcp251xfd_timestamp_stop(priv);
770 mcp251xfd_chip_sleep(priv);
771 }
772
mcp251xfd_chip_start(struct mcp251xfd_priv * priv)773 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
774 {
775 int err;
776
777 err = mcp251xfd_chip_softreset(priv);
778 if (err)
779 goto out_chip_stop;
780
781 err = mcp251xfd_chip_clock_init(priv);
782 if (err)
783 goto out_chip_stop;
784
785 err = mcp251xfd_chip_timestamp_init(priv);
786 if (err)
787 goto out_chip_stop;
788
789 mcp251xfd_timestamp_start(priv);
790
791 err = mcp251xfd_set_bittiming(priv);
792 if (err)
793 goto out_chip_stop;
794
795 err = mcp251xfd_chip_rx_int_enable(priv);
796 if (err)
797 goto out_chip_stop;
798
799 err = mcp251xfd_chip_ecc_init(priv);
800 if (err)
801 goto out_chip_stop;
802
803 err = mcp251xfd_ring_init(priv);
804 if (err)
805 goto out_chip_stop;
806
807 err = mcp251xfd_chip_fifo_init(priv);
808 if (err)
809 goto out_chip_stop;
810
811 priv->can.state = CAN_STATE_ERROR_ACTIVE;
812
813 err = mcp251xfd_chip_set_normal_mode(priv);
814 if (err)
815 goto out_chip_stop;
816
817 return 0;
818
819 out_chip_stop:
820 mcp251xfd_dump(priv);
821 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
822
823 return err;
824 }
825
mcp251xfd_set_mode(struct net_device * ndev,enum can_mode mode)826 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
827 {
828 struct mcp251xfd_priv *priv = netdev_priv(ndev);
829 int err;
830
831 switch (mode) {
832 case CAN_MODE_START:
833 err = mcp251xfd_chip_start(priv);
834 if (err)
835 return err;
836
837 err = mcp251xfd_chip_interrupts_enable(priv);
838 if (err) {
839 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
840 return err;
841 }
842
843 netif_wake_queue(ndev);
844 break;
845
846 default:
847 return -EOPNOTSUPP;
848 }
849
850 return 0;
851 }
852
__mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)853 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
854 struct can_berr_counter *bec)
855 {
856 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
857 u32 trec;
858 int err;
859
860 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
861 if (err)
862 return err;
863
864 if (trec & MCP251XFD_REG_TREC_TXBO)
865 bec->txerr = CAN_BUS_OFF_THRESHOLD;
866 else
867 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
868 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
869
870 return 0;
871 }
872
mcp251xfd_get_berr_counter(const struct net_device * ndev,struct can_berr_counter * bec)873 static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
874 struct can_berr_counter *bec)
875 {
876 const struct mcp251xfd_priv *priv = netdev_priv(ndev);
877
878 /* Avoid waking up the controller if the interface is down */
879 if (!(ndev->flags & IFF_UP))
880 return 0;
881
882 /* The controller is powered down during Bus Off, use saved
883 * bec values.
884 */
885 if (priv->can.state == CAN_STATE_BUS_OFF) {
886 *bec = priv->bec;
887 return 0;
888 }
889
890 return __mcp251xfd_get_berr_counter(ndev, bec);
891 }
892
893 static struct sk_buff *
mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv * priv,struct can_frame ** cf,u32 * ts_raw)894 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
895 struct can_frame **cf, u32 *ts_raw)
896 {
897 struct sk_buff *skb;
898 int err;
899
900 err = mcp251xfd_get_timestamp_raw(priv, ts_raw);
901 if (err)
902 return NULL;
903
904 skb = alloc_can_err_skb(priv->ndev, cf);
905 if (skb)
906 mcp251xfd_skb_set_timestamp_raw(priv, skb, *ts_raw);
907
908 return skb;
909 }
910
mcp251xfd_handle_rxovif(struct mcp251xfd_priv * priv)911 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
912 {
913 struct net_device_stats *stats = &priv->ndev->stats;
914 struct mcp251xfd_rx_ring *ring;
915 struct sk_buff *skb;
916 struct can_frame *cf;
917 u32 ts_raw, rxovif;
918 int err, i;
919
920 stats->rx_over_errors++;
921 stats->rx_errors++;
922
923 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
924 if (err)
925 return err;
926
927 mcp251xfd_for_each_rx_ring(priv, ring, i) {
928 if (!(rxovif & BIT(ring->fifo_nr)))
929 continue;
930
931 /* If SERRIF is active, there was a RX MAB overflow. */
932 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
933 if (net_ratelimit())
934 netdev_dbg(priv->ndev,
935 "RX-%d: MAB overflow detected.\n",
936 ring->nr);
937 } else {
938 if (net_ratelimit())
939 netdev_dbg(priv->ndev,
940 "RX-%d: FIFO overflow.\n",
941 ring->nr);
942 }
943
944 err = regmap_update_bits(priv->map_reg,
945 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
946 MCP251XFD_REG_FIFOSTA_RXOVIF,
947 0x0);
948 if (err)
949 return err;
950 }
951
952 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);
953 if (!skb)
954 return 0;
955
956 cf->can_id |= CAN_ERR_CRTL;
957 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
958
959 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
960 if (err)
961 stats->rx_fifo_errors++;
962
963 return 0;
964 }
965
mcp251xfd_handle_txatif(struct mcp251xfd_priv * priv)966 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
967 {
968 netdev_info(priv->ndev, "%s\n", __func__);
969
970 return 0;
971 }
972
mcp251xfd_handle_ivmif(struct mcp251xfd_priv * priv)973 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
974 {
975 struct net_device_stats *stats = &priv->ndev->stats;
976 u32 bdiag1, ts_raw;
977 struct sk_buff *skb;
978 struct can_frame *cf = NULL;
979 int err;
980
981 err = mcp251xfd_get_timestamp_raw(priv, &ts_raw);
982 if (err)
983 return err;
984
985 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
986 if (err)
987 return err;
988
989 /* Write 0s to clear error bits, don't write 1s to non active
990 * bits, as they will be set.
991 */
992 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
993 if (err)
994 return err;
995
996 priv->can.can_stats.bus_error++;
997
998 skb = alloc_can_err_skb(priv->ndev, &cf);
999 if (cf)
1000 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
1001
1002 /* Controller misconfiguration */
1003 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
1004 netdev_err(priv->ndev,
1005 "recv'd DLC is larger than PLSIZE of FIFO element.");
1006
1007 /* RX errors */
1008 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
1009 MCP251XFD_REG_BDIAG1_NCRCERR)) {
1010 netdev_dbg(priv->ndev, "CRC error\n");
1011
1012 stats->rx_errors++;
1013 if (cf)
1014 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1015 }
1016 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
1017 MCP251XFD_REG_BDIAG1_NSTUFERR)) {
1018 netdev_dbg(priv->ndev, "Stuff error\n");
1019
1020 stats->rx_errors++;
1021 if (cf)
1022 cf->data[2] |= CAN_ERR_PROT_STUFF;
1023 }
1024 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
1025 MCP251XFD_REG_BDIAG1_NFORMERR)) {
1026 netdev_dbg(priv->ndev, "Format error\n");
1027
1028 stats->rx_errors++;
1029 if (cf)
1030 cf->data[2] |= CAN_ERR_PROT_FORM;
1031 }
1032
1033 /* TX errors */
1034 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1035 netdev_dbg(priv->ndev, "NACK error\n");
1036
1037 stats->tx_errors++;
1038 if (cf) {
1039 cf->can_id |= CAN_ERR_ACK;
1040 cf->data[2] |= CAN_ERR_PROT_TX;
1041 }
1042 }
1043 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1044 MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1045 netdev_dbg(priv->ndev, "Bit1 error\n");
1046
1047 stats->tx_errors++;
1048 if (cf)
1049 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1050 }
1051 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1052 MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1053 netdev_dbg(priv->ndev, "Bit0 error\n");
1054
1055 stats->tx_errors++;
1056 if (cf)
1057 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1058 }
1059
1060 if (!cf)
1061 return 0;
1062
1063 mcp251xfd_skb_set_timestamp_raw(priv, skb, ts_raw);
1064 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
1065 if (err)
1066 stats->rx_fifo_errors++;
1067
1068 return 0;
1069 }
1070
mcp251xfd_handle_cerrif(struct mcp251xfd_priv * priv)1071 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1072 {
1073 struct net_device_stats *stats = &priv->ndev->stats;
1074 struct sk_buff *skb;
1075 struct can_frame *cf = NULL;
1076 enum can_state new_state, rx_state, tx_state;
1077 u32 trec, ts_raw;
1078 int err;
1079
1080 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1081 if (err)
1082 return err;
1083
1084 if (trec & MCP251XFD_REG_TREC_TXBO)
1085 tx_state = CAN_STATE_BUS_OFF;
1086 else if (trec & MCP251XFD_REG_TREC_TXBP)
1087 tx_state = CAN_STATE_ERROR_PASSIVE;
1088 else if (trec & MCP251XFD_REG_TREC_TXWARN)
1089 tx_state = CAN_STATE_ERROR_WARNING;
1090 else
1091 tx_state = CAN_STATE_ERROR_ACTIVE;
1092
1093 if (trec & MCP251XFD_REG_TREC_RXBP)
1094 rx_state = CAN_STATE_ERROR_PASSIVE;
1095 else if (trec & MCP251XFD_REG_TREC_RXWARN)
1096 rx_state = CAN_STATE_ERROR_WARNING;
1097 else
1098 rx_state = CAN_STATE_ERROR_ACTIVE;
1099
1100 new_state = max(tx_state, rx_state);
1101 if (new_state == priv->can.state)
1102 return 0;
1103
1104 /* The skb allocation might fail, but can_change_state()
1105 * handles cf == NULL.
1106 */
1107 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &ts_raw);
1108 can_change_state(priv->ndev, cf, tx_state, rx_state);
1109
1110 if (new_state == CAN_STATE_BUS_OFF) {
1111 /* As we're going to switch off the chip now, let's
1112 * save the error counters and return them to
1113 * userspace, if do_get_berr_counter() is called while
1114 * the chip is in Bus Off.
1115 */
1116 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1117 if (err)
1118 return err;
1119
1120 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1121 can_bus_off(priv->ndev);
1122 }
1123
1124 if (!skb)
1125 return 0;
1126
1127 if (new_state != CAN_STATE_BUS_OFF) {
1128 struct can_berr_counter bec;
1129
1130 err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1131 if (err)
1132 return err;
1133 cf->can_id |= CAN_ERR_CNT;
1134 cf->data[6] = bec.txerr;
1135 cf->data[7] = bec.rxerr;
1136 }
1137
1138 err = can_rx_offload_queue_timestamp(&priv->offload, skb, ts_raw);
1139 if (err)
1140 stats->rx_fifo_errors++;
1141
1142 return 0;
1143 }
1144
1145 static int
mcp251xfd_handle_modif(const struct mcp251xfd_priv * priv,bool * set_normal_mode)1146 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1147 {
1148 const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1149 u8 mode;
1150 int err;
1151
1152 err = mcp251xfd_chip_get_mode(priv, &mode);
1153 if (err)
1154 return err;
1155
1156 if (mode == mode_reference) {
1157 netdev_dbg(priv->ndev,
1158 "Controller changed into %s Mode (%u).\n",
1159 mcp251xfd_get_mode_str(mode), mode);
1160 return 0;
1161 }
1162
1163 /* According to MCP2517FD errata DS80000792C 1., during a TX
1164 * MAB underflow, the controller will transition to Restricted
1165 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1166 *
1167 * However this is not always the case. If SERR2LOM is
1168 * configured for Restricted Operation Mode (SERR2LOM not set)
1169 * the MCP2517FD will sometimes transition to Listen Only Mode
1170 * first. When polling this bit we see that it will transition
1171 * to Restricted Operation Mode shortly after.
1172 */
1173 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1174 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1175 mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1176 netdev_dbg(priv->ndev,
1177 "Controller changed into %s Mode (%u).\n",
1178 mcp251xfd_get_mode_str(mode), mode);
1179 else
1180 netdev_err(priv->ndev,
1181 "Controller changed into %s Mode (%u).\n",
1182 mcp251xfd_get_mode_str(mode), mode);
1183
1184 /* After the application requests Normal mode, the controller
1185 * will automatically attempt to retransmit the message that
1186 * caused the TX MAB underflow.
1187 *
1188 * However, if there is an ECC error in the TX-RAM, we first
1189 * have to reload the tx-object before requesting Normal
1190 * mode. This is done later in mcp251xfd_handle_eccif().
1191 */
1192 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1193 *set_normal_mode = true;
1194 return 0;
1195 }
1196
1197 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1198 }
1199
mcp251xfd_handle_serrif(struct mcp251xfd_priv * priv)1200 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1201 {
1202 struct mcp251xfd_ecc *ecc = &priv->ecc;
1203 struct net_device_stats *stats = &priv->ndev->stats;
1204 bool handled = false;
1205
1206 /* TX MAB underflow
1207 *
1208 * According to MCP2517FD Errata DS80000792C 1. a TX MAB
1209 * underflow is indicated by SERRIF and MODIF.
1210 *
1211 * In addition to the effects mentioned in the Errata, there
1212 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1213 * will be seen as well.
1214 *
1215 * Sometimes there is an ECC error in the TX-RAM, which leads
1216 * to a TX MAB underflow.
1217 *
1218 * However, probably due to a race condition, there is no
1219 * associated MODIF pending.
1220 *
1221 * Further, there are situations, where the SERRIF is caused
1222 * by an ECC error in the TX-RAM, but not even the ECCIF is
1223 * set. This only seems to happen _after_ the first occurrence
1224 * of a ECCIF (which is tracked in ecc->cnt).
1225 *
1226 * Treat all as a known system errors..
1227 */
1228 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1229 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1230 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1231 ecc->cnt) {
1232 const char *msg;
1233
1234 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1235 ecc->cnt)
1236 msg = "TX MAB underflow due to ECC error detected.";
1237 else
1238 msg = "TX MAB underflow detected.";
1239
1240 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1241 netdev_dbg(priv->ndev, "%s\n", msg);
1242 else
1243 netdev_info(priv->ndev, "%s\n", msg);
1244
1245 stats->tx_aborted_errors++;
1246 stats->tx_errors++;
1247 handled = true;
1248 }
1249
1250 /* RX MAB overflow
1251 *
1252 * According to MCP2517FD Errata DS80000792C 1. a RX MAB
1253 * overflow is indicated by SERRIF.
1254 *
1255 * In addition to the effects mentioned in the Errata, (most
1256 * of the times) a RXOVIF is raised, if the FIFO that is being
1257 * received into has the RXOVIE activated (and we have enabled
1258 * RXOVIE on all FIFOs).
1259 *
1260 * Sometimes there is no RXOVIF just a RXIF is pending.
1261 *
1262 * Treat all as a known system errors..
1263 */
1264 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1265 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1266 stats->rx_dropped++;
1267 handled = true;
1268 }
1269
1270 if (!handled)
1271 netdev_err(priv->ndev,
1272 "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1273 priv->regs_status.intf);
1274
1275 return 0;
1276 }
1277
1278 static int
mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv * priv,u8 nr)1279 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1280 {
1281 struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1282 struct mcp251xfd_ecc *ecc = &priv->ecc;
1283 struct mcp251xfd_tx_obj *tx_obj;
1284 u8 chip_tx_tail, tx_tail, offset;
1285 u16 addr;
1286 int err;
1287
1288 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1289
1290 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1291 if (err)
1292 return err;
1293
1294 tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1295 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1296
1297 /* Bail out if one of the following is met:
1298 * - tx_tail information is inconsistent
1299 * - for mcp2517fd: offset not 0
1300 * - for mcp2518fd: offset not 0 or 1
1301 */
1302 if (chip_tx_tail != tx_tail ||
1303 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1304 mcp251xfd_is_251863(priv))))) {
1305 netdev_err(priv->ndev,
1306 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1307 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1308 offset);
1309 return -EINVAL;
1310 }
1311
1312 netdev_info(priv->ndev,
1313 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1314 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1315 "Single" : "Double",
1316 addr, nr, tx_ring->tail, tx_tail, offset);
1317
1318 /* reload tx_obj into controller RAM ... */
1319 tx_obj = &tx_ring->obj[nr];
1320 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1321 if (err)
1322 return err;
1323
1324 /* ... and trigger retransmit */
1325 return mcp251xfd_chip_set_normal_mode(priv);
1326 }
1327
1328 static int
mcp251xfd_handle_eccif(struct mcp251xfd_priv * priv,bool set_normal_mode)1329 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1330 {
1331 struct mcp251xfd_ecc *ecc = &priv->ecc;
1332 const char *msg;
1333 bool in_tx_ram;
1334 u32 ecc_stat;
1335 u16 addr;
1336 u8 nr;
1337 int err;
1338
1339 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1340 if (err)
1341 return err;
1342
1343 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1344 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1345 if (err)
1346 return err;
1347
1348 /* Check if ECC error occurred in TX-RAM */
1349 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1350 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1351 if (!err)
1352 in_tx_ram = true;
1353 else if (err == -ENOENT)
1354 in_tx_ram = false;
1355 else
1356 return err;
1357
1358 /* Errata Reference:
1359 * mcp2517fd: DS80000789C 3., mcp2518fd: DS80000792E 2.,
1360 * mcp251863: DS80000984A 2.
1361 *
1362 * ECC single error correction does not work in all cases:
1363 *
1364 * Fix/Work Around:
1365 * Enable single error correction and double error detection
1366 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1367 * detection interrupt and do not rely on the error
1368 * correction. Instead, handle both interrupts as a
1369 * notification that the RAM word at ERRADDR was corrupted.
1370 */
1371 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1372 msg = "Single ECC Error detected at address";
1373 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1374 msg = "Double ECC Error detected at address";
1375 else
1376 return -EINVAL;
1377
1378 if (!in_tx_ram) {
1379 ecc->ecc_stat = 0;
1380
1381 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1382 } else {
1383 /* Re-occurring error? */
1384 if (ecc->ecc_stat == ecc_stat) {
1385 ecc->cnt++;
1386 } else {
1387 ecc->ecc_stat = ecc_stat;
1388 ecc->cnt = 1;
1389 }
1390
1391 netdev_info(priv->ndev,
1392 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1393 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1394
1395 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1396 return mcp251xfd_handle_eccif_recover(priv, nr);
1397 }
1398
1399 if (set_normal_mode)
1400 return mcp251xfd_chip_set_normal_mode_nowait(priv);
1401
1402 return 0;
1403 }
1404
mcp251xfd_handle_spicrcif(struct mcp251xfd_priv * priv)1405 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1406 {
1407 int err;
1408 u32 crc;
1409
1410 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1411 if (err)
1412 return err;
1413
1414 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1415 MCP251XFD_REG_CRC_IF_MASK,
1416 ~crc);
1417 if (err)
1418 return err;
1419
1420 if (crc & MCP251XFD_REG_CRC_FERRIF)
1421 netdev_notice(priv->ndev, "CRC write command format error.\n");
1422 else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1423 netdev_notice(priv->ndev,
1424 "CRC write error detected. CRC=0x%04lx.\n",
1425 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1426
1427 return 0;
1428 }
1429
mcp251xfd_read_regs_status(struct mcp251xfd_priv * priv)1430 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1431 {
1432 const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1433 size_t len;
1434
1435 if (priv->rx_ring_num == 1)
1436 len = sizeof(priv->regs_status.intf);
1437 else
1438 len = sizeof(priv->regs_status);
1439
1440 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1441 &priv->regs_status, len / val_bytes);
1442 }
1443
1444 #define mcp251xfd_handle(priv, irq, ...) \
1445 ({ \
1446 struct mcp251xfd_priv *_priv = (priv); \
1447 int err; \
1448 \
1449 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1450 if (err) \
1451 netdev_err(_priv->ndev, \
1452 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1453 __stringify(irq), err); \
1454 err; \
1455 })
1456
mcp251xfd_irq(int irq,void * dev_id)1457 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1458 {
1459 struct mcp251xfd_priv *priv = dev_id;
1460 irqreturn_t handled = IRQ_NONE;
1461 int err;
1462
1463 if (priv->rx_int)
1464 do {
1465 int rx_pending;
1466
1467 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1468 if (!rx_pending)
1469 break;
1470
1471 /* Assume 1st RX-FIFO pending, if other FIFOs
1472 * are pending the main IRQ handler will take
1473 * care.
1474 */
1475 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1476 err = mcp251xfd_handle(priv, rxif);
1477 if (err)
1478 goto out_fail;
1479
1480 handled = IRQ_HANDLED;
1481
1482 /* We don't know which RX-FIFO is pending, but only
1483 * handle the 1st RX-FIFO. Leave loop here if we have
1484 * more than 1 RX-FIFO to avoid starvation.
1485 */
1486 } while (priv->rx_ring_num == 1);
1487
1488 do {
1489 u32 intf_pending, intf_pending_clearable;
1490 bool set_normal_mode = false;
1491
1492 err = mcp251xfd_read_regs_status(priv);
1493 if (err)
1494 goto out_fail;
1495
1496 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1497 priv->regs_status.intf) &
1498 FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1499 priv->regs_status.intf);
1500
1501 if (!(intf_pending)) {
1502 can_rx_offload_threaded_irq_finish(&priv->offload);
1503 return handled;
1504 }
1505
1506 /* Some interrupts must be ACKed in the
1507 * MCP251XFD_REG_INT register.
1508 * - First ACK then handle, to avoid lost-IRQ race
1509 * condition on fast re-occurring interrupts.
1510 * - Write "0" to clear active IRQs, "1" to all other,
1511 * to avoid r/m/w race condition on the
1512 * MCP251XFD_REG_INT register.
1513 */
1514 intf_pending_clearable = intf_pending &
1515 MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1516 if (intf_pending_clearable) {
1517 err = regmap_update_bits(priv->map_reg,
1518 MCP251XFD_REG_INT,
1519 MCP251XFD_REG_INT_IF_MASK,
1520 ~intf_pending_clearable);
1521 if (err)
1522 goto out_fail;
1523 }
1524
1525 if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1526 err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1527 if (err)
1528 goto out_fail;
1529 }
1530
1531 if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1532 err = mcp251xfd_handle(priv, rxif);
1533 if (err)
1534 goto out_fail;
1535 }
1536
1537 if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1538 err = mcp251xfd_handle(priv, tefif);
1539 if (err)
1540 goto out_fail;
1541 }
1542
1543 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1544 err = mcp251xfd_handle(priv, rxovif);
1545 if (err)
1546 goto out_fail;
1547 }
1548
1549 if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1550 err = mcp251xfd_handle(priv, txatif);
1551 if (err)
1552 goto out_fail;
1553 }
1554
1555 if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1556 err = mcp251xfd_handle(priv, ivmif);
1557 if (err)
1558 goto out_fail;
1559 }
1560
1561 if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1562 err = mcp251xfd_handle(priv, serrif);
1563 if (err)
1564 goto out_fail;
1565 }
1566
1567 if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1568 err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1569 if (err)
1570 goto out_fail;
1571 }
1572
1573 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1574 err = mcp251xfd_handle(priv, spicrcif);
1575 if (err)
1576 goto out_fail;
1577 }
1578
1579 /* On the MCP2527FD and MCP2518FD, we don't get a
1580 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1581 * ERROR_ACTIVE.
1582 */
1583 if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1584 priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1585 err = mcp251xfd_handle(priv, cerrif);
1586 if (err)
1587 goto out_fail;
1588
1589 /* In Bus Off we completely shut down the
1590 * controller. Every subsequent register read
1591 * will read bogus data, and if
1592 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1593 * check will fail, too. So leave IRQ handler
1594 * directly.
1595 */
1596 if (priv->can.state == CAN_STATE_BUS_OFF) {
1597 can_rx_offload_threaded_irq_finish(&priv->offload);
1598 return IRQ_HANDLED;
1599 }
1600 }
1601
1602 handled = IRQ_HANDLED;
1603 } while (1);
1604
1605 out_fail:
1606 can_rx_offload_threaded_irq_finish(&priv->offload);
1607
1608 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1609 err, priv->regs_status.intf);
1610 mcp251xfd_dump(priv);
1611 mcp251xfd_chip_interrupts_disable(priv);
1612 mcp251xfd_timestamp_stop(priv);
1613
1614 return handled;
1615 }
1616
mcp251xfd_open(struct net_device * ndev)1617 static int mcp251xfd_open(struct net_device *ndev)
1618 {
1619 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1620 const struct spi_device *spi = priv->spi;
1621 int err;
1622
1623 err = open_candev(ndev);
1624 if (err)
1625 return err;
1626
1627 err = pm_runtime_resume_and_get(ndev->dev.parent);
1628 if (err)
1629 goto out_close_candev;
1630
1631 err = mcp251xfd_ring_alloc(priv);
1632 if (err)
1633 goto out_pm_runtime_put;
1634
1635 err = mcp251xfd_transceiver_enable(priv);
1636 if (err)
1637 goto out_mcp251xfd_ring_free;
1638
1639 mcp251xfd_timestamp_init(priv);
1640
1641 err = mcp251xfd_chip_start(priv);
1642 if (err)
1643 goto out_transceiver_disable;
1644
1645 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1646 can_rx_offload_enable(&priv->offload);
1647
1648 priv->wq = alloc_ordered_workqueue("%s-mcp251xfd_wq",
1649 WQ_FREEZABLE | WQ_MEM_RECLAIM,
1650 dev_name(&spi->dev));
1651 if (!priv->wq) {
1652 err = -ENOMEM;
1653 goto out_can_rx_offload_disable;
1654 }
1655 INIT_WORK(&priv->tx_work, mcp251xfd_tx_obj_write_sync);
1656
1657 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1658 IRQF_SHARED | IRQF_ONESHOT,
1659 dev_name(&spi->dev), priv);
1660 if (err)
1661 goto out_destroy_workqueue;
1662
1663 err = mcp251xfd_chip_interrupts_enable(priv);
1664 if (err)
1665 goto out_free_irq;
1666
1667 netif_start_queue(ndev);
1668
1669 return 0;
1670
1671 out_free_irq:
1672 free_irq(spi->irq, priv);
1673 out_destroy_workqueue:
1674 destroy_workqueue(priv->wq);
1675 out_can_rx_offload_disable:
1676 can_rx_offload_disable(&priv->offload);
1677 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1678 out_transceiver_disable:
1679 mcp251xfd_transceiver_disable(priv);
1680 out_mcp251xfd_ring_free:
1681 mcp251xfd_ring_free(priv);
1682 out_pm_runtime_put:
1683 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1684 pm_runtime_put(ndev->dev.parent);
1685 out_close_candev:
1686 close_candev(ndev);
1687
1688 return err;
1689 }
1690
mcp251xfd_stop(struct net_device * ndev)1691 static int mcp251xfd_stop(struct net_device *ndev)
1692 {
1693 struct mcp251xfd_priv *priv = netdev_priv(ndev);
1694
1695 netif_stop_queue(ndev);
1696 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1697 hrtimer_cancel(&priv->rx_irq_timer);
1698 hrtimer_cancel(&priv->tx_irq_timer);
1699 mcp251xfd_chip_interrupts_disable(priv);
1700 free_irq(ndev->irq, priv);
1701 destroy_workqueue(priv->wq);
1702 can_rx_offload_disable(&priv->offload);
1703 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1704 mcp251xfd_transceiver_disable(priv);
1705 mcp251xfd_ring_free(priv);
1706 close_candev(ndev);
1707
1708 pm_runtime_put(ndev->dev.parent);
1709
1710 return 0;
1711 }
1712
1713 static const struct net_device_ops mcp251xfd_netdev_ops = {
1714 .ndo_open = mcp251xfd_open,
1715 .ndo_stop = mcp251xfd_stop,
1716 .ndo_start_xmit = mcp251xfd_start_xmit,
1717 .ndo_eth_ioctl = can_eth_ioctl_hwts,
1718 .ndo_change_mtu = can_change_mtu,
1719 };
1720
1721 static void
mcp251xfd_register_quirks(struct mcp251xfd_priv * priv)1722 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1723 {
1724 const struct spi_device *spi = priv->spi;
1725 const struct spi_controller *ctlr = spi->controller;
1726
1727 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1728 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1729 }
1730
mcp251xfd_register_chip_detect(struct mcp251xfd_priv * priv)1731 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1732 {
1733 const struct net_device *ndev = priv->ndev;
1734 const struct mcp251xfd_devtype_data *devtype_data;
1735 u32 osc;
1736 int err;
1737
1738 /* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1739 * so use it to autodetect the model.
1740 */
1741 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1742 MCP251XFD_REG_OSC_LPMEN,
1743 MCP251XFD_REG_OSC_LPMEN);
1744 if (err)
1745 return err;
1746
1747 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1748 if (err)
1749 return err;
1750
1751 if (osc & MCP251XFD_REG_OSC_LPMEN) {
1752 /* We cannot distinguish between MCP2518FD and
1753 * MCP251863. If firmware specifies MCP251863, keep
1754 * it, otherwise set to MCP2518FD.
1755 */
1756 if (mcp251xfd_is_251863(priv))
1757 devtype_data = &mcp251xfd_devtype_data_mcp251863;
1758 else
1759 devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1760 } else {
1761 devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1762 }
1763
1764 if (!mcp251xfd_is_251XFD(priv) &&
1765 priv->devtype_data.model != devtype_data->model) {
1766 netdev_info(ndev,
1767 "Detected %s, but firmware specifies a %s. Fixing up.\n",
1768 __mcp251xfd_get_model_str(devtype_data->model),
1769 mcp251xfd_get_model_str(priv));
1770 }
1771 priv->devtype_data = *devtype_data;
1772
1773 /* We need to preserve the Half Duplex Quirk. */
1774 mcp251xfd_register_quirks(priv);
1775
1776 /* Re-init regmap with quirks of detected model. */
1777 return mcp251xfd_regmap_init(priv);
1778 }
1779
mcp251xfd_register_check_rx_int(struct mcp251xfd_priv * priv)1780 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1781 {
1782 int err, rx_pending;
1783
1784 if (!priv->rx_int)
1785 return 0;
1786
1787 err = mcp251xfd_chip_rx_int_enable(priv);
1788 if (err)
1789 return err;
1790
1791 /* Check if RX_INT is properly working. The RX_INT should not
1792 * be active after a softreset.
1793 */
1794 rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1795
1796 err = mcp251xfd_chip_rx_int_disable(priv);
1797 if (err)
1798 return err;
1799
1800 if (!rx_pending)
1801 return 0;
1802
1803 netdev_info(priv->ndev,
1804 "RX_INT active after softreset, disabling RX_INT support.\n");
1805 devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1806 priv->rx_int = NULL;
1807
1808 return 0;
1809 }
1810
1811 static int
mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv * priv,u32 * dev_id,u32 * effective_speed_hz_slow,u32 * effective_speed_hz_fast)1812 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1813 u32 *effective_speed_hz_slow,
1814 u32 *effective_speed_hz_fast)
1815 {
1816 struct mcp251xfd_map_buf_nocrc *buf_rx;
1817 struct mcp251xfd_map_buf_nocrc *buf_tx;
1818 struct spi_transfer xfer[2] = { };
1819 int err;
1820
1821 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1822 if (!buf_rx)
1823 return -ENOMEM;
1824
1825 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1826 if (!buf_tx) {
1827 err = -ENOMEM;
1828 goto out_kfree_buf_rx;
1829 }
1830
1831 xfer[0].tx_buf = buf_tx;
1832 xfer[0].len = sizeof(buf_tx->cmd);
1833 xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1834 xfer[1].rx_buf = buf_rx->data;
1835 xfer[1].len = sizeof(*dev_id);
1836 xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1837
1838 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
1839
1840 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
1841 if (err)
1842 goto out_kfree_buf_tx;
1843
1844 *dev_id = get_unaligned_le32(buf_rx->data);
1845 *effective_speed_hz_slow = xfer[0].effective_speed_hz;
1846 *effective_speed_hz_fast = xfer[1].effective_speed_hz;
1847
1848 out_kfree_buf_tx:
1849 kfree(buf_tx);
1850 out_kfree_buf_rx:
1851 kfree(buf_rx);
1852
1853 return err;
1854 }
1855
1856 #define MCP251XFD_QUIRK_ACTIVE(quirk) \
1857 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
1858
1859 static int
mcp251xfd_register_done(const struct mcp251xfd_priv * priv)1860 mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
1861 {
1862 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
1863 unsigned long clk_rate;
1864 int err;
1865
1866 err = mcp251xfd_register_get_dev_id(priv, &dev_id,
1867 &effective_speed_hz_slow,
1868 &effective_speed_hz_fast);
1869 if (err)
1870 return err;
1871
1872 clk_rate = clk_get_rate(priv->clk);
1873
1874 netdev_info(priv->ndev,
1875 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
1876 mcp251xfd_get_model_str(priv),
1877 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
1878 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
1879 priv->rx_int ? '+' : '-',
1880 priv->pll_enable ? '+' : '-',
1881 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
1882 MCP251XFD_QUIRK_ACTIVE(CRC_REG),
1883 MCP251XFD_QUIRK_ACTIVE(CRC_RX),
1884 MCP251XFD_QUIRK_ACTIVE(CRC_TX),
1885 MCP251XFD_QUIRK_ACTIVE(ECC),
1886 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
1887 clk_rate / 1000000,
1888 clk_rate % 1000000 / 1000 / 10,
1889 priv->can.clock.freq / 1000000,
1890 priv->can.clock.freq % 1000000 / 1000 / 10,
1891 priv->spi_max_speed_hz_orig / 1000000,
1892 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
1893 priv->spi_max_speed_hz_slow / 1000000,
1894 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
1895 effective_speed_hz_slow / 1000000,
1896 effective_speed_hz_slow % 1000000 / 1000 / 10,
1897 priv->spi_max_speed_hz_fast / 1000000,
1898 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
1899 effective_speed_hz_fast / 1000000,
1900 effective_speed_hz_fast % 1000000 / 1000 / 10);
1901
1902 return 0;
1903 }
1904
mcp251xfd_register(struct mcp251xfd_priv * priv)1905 static int mcp251xfd_register(struct mcp251xfd_priv *priv)
1906 {
1907 struct net_device *ndev = priv->ndev;
1908 int err;
1909
1910 err = mcp251xfd_clks_and_vdd_enable(priv);
1911 if (err)
1912 return err;
1913
1914 pm_runtime_get_noresume(ndev->dev.parent);
1915 err = pm_runtime_set_active(ndev->dev.parent);
1916 if (err)
1917 goto out_runtime_put_noidle;
1918 pm_runtime_enable(ndev->dev.parent);
1919
1920 mcp251xfd_register_quirks(priv);
1921
1922 err = mcp251xfd_chip_softreset(priv);
1923 if (err == -ENODEV)
1924 goto out_runtime_disable;
1925 if (err)
1926 goto out_chip_sleep;
1927
1928 err = mcp251xfd_chip_clock_init(priv);
1929 if (err == -ENODEV)
1930 goto out_runtime_disable;
1931 if (err)
1932 goto out_chip_sleep;
1933
1934 err = mcp251xfd_register_chip_detect(priv);
1935 if (err)
1936 goto out_chip_sleep;
1937
1938 err = mcp251xfd_register_check_rx_int(priv);
1939 if (err)
1940 goto out_chip_sleep;
1941
1942 mcp251xfd_ethtool_init(priv);
1943
1944 err = register_candev(ndev);
1945 if (err)
1946 goto out_chip_sleep;
1947
1948 err = mcp251xfd_register_done(priv);
1949 if (err)
1950 goto out_unregister_candev;
1951
1952 /* Put controller into sleep mode and let pm_runtime_put()
1953 * disable the clocks and vdd. If CONFIG_PM is not enabled,
1954 * the clocks and vdd will stay powered.
1955 */
1956 err = mcp251xfd_chip_sleep(priv);
1957 if (err)
1958 goto out_unregister_candev;
1959
1960 pm_runtime_put(ndev->dev.parent);
1961
1962 return 0;
1963
1964 out_unregister_candev:
1965 unregister_candev(ndev);
1966 out_chip_sleep:
1967 mcp251xfd_chip_sleep(priv);
1968 out_runtime_disable:
1969 pm_runtime_disable(ndev->dev.parent);
1970 out_runtime_put_noidle:
1971 pm_runtime_put_noidle(ndev->dev.parent);
1972 mcp251xfd_clks_and_vdd_disable(priv);
1973
1974 return err;
1975 }
1976
mcp251xfd_unregister(struct mcp251xfd_priv * priv)1977 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
1978 {
1979 struct net_device *ndev = priv->ndev;
1980
1981 unregister_candev(ndev);
1982
1983 if (pm_runtime_enabled(ndev->dev.parent))
1984 pm_runtime_disable(ndev->dev.parent);
1985 else
1986 mcp251xfd_clks_and_vdd_disable(priv);
1987 }
1988
1989 static const struct of_device_id mcp251xfd_of_match[] = {
1990 {
1991 .compatible = "microchip,mcp2517fd",
1992 .data = &mcp251xfd_devtype_data_mcp2517fd,
1993 }, {
1994 .compatible = "microchip,mcp2518fd",
1995 .data = &mcp251xfd_devtype_data_mcp2518fd,
1996 }, {
1997 .compatible = "microchip,mcp251863",
1998 .data = &mcp251xfd_devtype_data_mcp251863,
1999 }, {
2000 .compatible = "microchip,mcp251xfd",
2001 .data = &mcp251xfd_devtype_data_mcp251xfd,
2002 }, {
2003 /* sentinel */
2004 },
2005 };
2006 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
2007
2008 static const struct spi_device_id mcp251xfd_id_table[] = {
2009 {
2010 .name = "mcp2517fd",
2011 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
2012 }, {
2013 .name = "mcp2518fd",
2014 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
2015 }, {
2016 .name = "mcp251863",
2017 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
2018 }, {
2019 .name = "mcp251xfd",
2020 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
2021 }, {
2022 /* sentinel */
2023 },
2024 };
2025 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
2026
mcp251xfd_probe(struct spi_device * spi)2027 static int mcp251xfd_probe(struct spi_device *spi)
2028 {
2029 struct net_device *ndev;
2030 struct mcp251xfd_priv *priv;
2031 struct gpio_desc *rx_int;
2032 struct regulator *reg_vdd, *reg_xceiver;
2033 struct clk *clk;
2034 bool pll_enable = false;
2035 u32 freq = 0;
2036 int err;
2037
2038 if (!spi->irq)
2039 return dev_err_probe(&spi->dev, -ENXIO,
2040 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
2041
2042 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2043 GPIOD_IN);
2044 if (IS_ERR(rx_int))
2045 return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
2046 "Failed to get RX-INT!\n");
2047
2048 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2049 if (PTR_ERR(reg_vdd) == -ENODEV)
2050 reg_vdd = NULL;
2051 else if (IS_ERR(reg_vdd))
2052 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
2053 "Failed to get VDD regulator!\n");
2054
2055 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2056 if (PTR_ERR(reg_xceiver) == -ENODEV)
2057 reg_xceiver = NULL;
2058 else if (IS_ERR(reg_xceiver))
2059 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
2060 "Failed to get Transceiver regulator!\n");
2061
2062 clk = devm_clk_get_optional(&spi->dev, NULL);
2063 if (IS_ERR(clk))
2064 return dev_err_probe(&spi->dev, PTR_ERR(clk),
2065 "Failed to get Oscillator (clock)!\n");
2066 if (clk) {
2067 freq = clk_get_rate(clk);
2068 } else {
2069 err = device_property_read_u32(&spi->dev, "clock-frequency",
2070 &freq);
2071 if (err)
2072 return dev_err_probe(&spi->dev, err,
2073 "Failed to get clock-frequency!\n");
2074 }
2075
2076 /* Sanity check */
2077 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2078 freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2079 dev_err(&spi->dev,
2080 "Oscillator frequency (%u Hz) is too low or high.\n",
2081 freq);
2082 return -ERANGE;
2083 }
2084
2085 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2086 pll_enable = true;
2087
2088 ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2089 MCP251XFD_TX_OBJ_NUM_MAX);
2090 if (!ndev)
2091 return -ENOMEM;
2092
2093 SET_NETDEV_DEV(ndev, &spi->dev);
2094
2095 ndev->netdev_ops = &mcp251xfd_netdev_ops;
2096 ndev->irq = spi->irq;
2097 ndev->flags |= IFF_ECHO;
2098
2099 priv = netdev_priv(ndev);
2100 spi_set_drvdata(spi, priv);
2101 priv->can.clock.freq = freq;
2102 if (pll_enable)
2103 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2104 priv->can.do_set_mode = mcp251xfd_set_mode;
2105 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2106 priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2107 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2108 priv->can.tdc_const = &mcp251xfd_tdc_const;
2109 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2110 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2111 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2112 CAN_CTRLMODE_CC_LEN8_DLC | CAN_CTRLMODE_TDC_AUTO |
2113 CAN_CTRLMODE_TDC_MANUAL;
2114 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2115 priv->ndev = ndev;
2116 priv->spi = spi;
2117 priv->rx_int = rx_int;
2118 priv->clk = clk;
2119 priv->pll_enable = pll_enable;
2120 priv->reg_vdd = reg_vdd;
2121 priv->reg_xceiver = reg_xceiver;
2122 priv->devtype_data = *(struct mcp251xfd_devtype_data *)spi_get_device_match_data(spi);
2123
2124 /* Errata Reference:
2125 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789E 4.,
2126 * mcp251863: DS80000984A 4.
2127 *
2128 * The SPI can write corrupted data to the RAM at fast SPI
2129 * speeds:
2130 *
2131 * Simultaneous activity on the CAN bus while writing data to
2132 * RAM via the SPI interface, with high SCK frequency, can
2133 * lead to corrupted data being written to RAM.
2134 *
2135 * Fix/Work Around:
2136 * Ensure that FSCK is less than or equal to 0.85 *
2137 * (FSYSCLK/2).
2138 *
2139 * Known good combinations are:
2140 *
2141 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config
2142 *
2143 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2144 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx>
2145 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2146 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default
2147 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default
2148 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2149 *
2150 */
2151 priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2152 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2153 freq / 2 / 1000 * 850);
2154 if (priv->pll_enable)
2155 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2156 freq *
2157 MCP251XFD_OSC_PLL_MULTIPLIER /
2158 2 / 1000 * 850);
2159 else
2160 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2161 spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2162 spi->bits_per_word = 8;
2163 spi->rt = true;
2164 err = spi_setup(spi);
2165 if (err)
2166 goto out_free_candev;
2167
2168 err = mcp251xfd_regmap_init(priv);
2169 if (err)
2170 goto out_free_candev;
2171
2172 err = can_rx_offload_add_manual(ndev, &priv->offload,
2173 MCP251XFD_NAPI_WEIGHT);
2174 if (err)
2175 goto out_free_candev;
2176
2177 err = mcp251xfd_register(priv);
2178 if (err) {
2179 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2180 mcp251xfd_get_model_str(priv));
2181 goto out_can_rx_offload_del;
2182 }
2183
2184 return 0;
2185
2186 out_can_rx_offload_del:
2187 can_rx_offload_del(&priv->offload);
2188 out_free_candev:
2189 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2190
2191 free_candev(ndev);
2192
2193 return err;
2194 }
2195
mcp251xfd_remove(struct spi_device * spi)2196 static void mcp251xfd_remove(struct spi_device *spi)
2197 {
2198 struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2199 struct net_device *ndev = priv->ndev;
2200
2201 mcp251xfd_unregister(priv);
2202 can_rx_offload_del(&priv->offload);
2203 spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2204 free_candev(ndev);
2205 }
2206
mcp251xfd_runtime_suspend(struct device * device)2207 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2208 {
2209 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2210
2211 return mcp251xfd_clks_and_vdd_disable(priv);
2212 }
2213
mcp251xfd_runtime_resume(struct device * device)2214 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2215 {
2216 const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2217
2218 return mcp251xfd_clks_and_vdd_enable(priv);
2219 }
2220
2221 static const struct dev_pm_ops mcp251xfd_pm_ops = {
2222 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2223 mcp251xfd_runtime_resume, NULL)
2224 };
2225
2226 static struct spi_driver mcp251xfd_driver = {
2227 .driver = {
2228 .name = DEVICE_NAME,
2229 .pm = &mcp251xfd_pm_ops,
2230 .of_match_table = mcp251xfd_of_match,
2231 },
2232 .probe = mcp251xfd_probe,
2233 .remove = mcp251xfd_remove,
2234 .id_table = mcp251xfd_id_table,
2235 };
2236 module_spi_driver(mcp251xfd_driver);
2237
2238 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2239 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2240 MODULE_LICENSE("GPL v2");
2241