1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Synopsys DesignWare Multimedia Card Interface driver 4 * (Based on NXP driver for lpc 31xx) 5 * 6 * Copyright (C) 2009 NXP Semiconductors 7 * Copyright (C) 2009, 2010 Imagination Technologies Ltd. 8 */ 9 10 #ifndef _DW_MMC_H_ 11 #define _DW_MMC_H_ 12 13 #include <linux/scatterlist.h> 14 #include <linux/mmc/core.h> 15 #include <linux/dmaengine.h> 16 #include <linux/reset.h> 17 #include <linux/fault-inject.h> 18 #include <linux/hrtimer.h> 19 #include <linux/interrupt.h> 20 #include <linux/workqueue.h> 21 22 enum dw_mci_state { 23 STATE_IDLE = 0, 24 STATE_SENDING_CMD, 25 STATE_SENDING_DATA, 26 STATE_DATA_BUSY, 27 STATE_SENDING_STOP, 28 STATE_DATA_ERROR, 29 STATE_SENDING_CMD11, 30 STATE_WAITING_CMD11_DONE, 31 }; 32 33 enum { 34 EVENT_CMD_COMPLETE = 0, 35 EVENT_XFER_COMPLETE, 36 EVENT_DATA_COMPLETE, 37 EVENT_DATA_ERROR, 38 }; 39 40 enum dw_mci_cookie { 41 COOKIE_UNMAPPED, 42 COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */ 43 COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */ 44 }; 45 46 enum { 47 TRANS_MODE_PIO = 0, 48 TRANS_MODE_IDMAC, 49 TRANS_MODE_EDMAC 50 }; 51 52 struct dw_mci_dma_slave { 53 struct dma_chan *ch; 54 enum dma_transfer_direction direction; 55 }; 56 57 /** 58 * struct dw_mci - MMC controller state 59 * @lock: Spinlock protecting the queue and associated data. 60 * @irq_lock: Spinlock protecting the INTMASK setting. 61 * @regs: Pointer to MMIO registers. 62 * @fifo_reg: Pointer to MMIO registers for data FIFO 63 * @sg: Scatterlist entry currently being processed by PIO code, if any. 64 * @sg_miter: PIO mapping scatterlist iterator. 65 * @mrq: The request currently being processed on @host, 66 * or NULL if the controller is idle. 67 * @cmd: The command currently being sent to the card, or NULL. 68 * @data: The data currently being transferred, or NULL if no data 69 * transfer is in progress. 70 * @stop_abort: The command currently prepared for stoping transfer. 71 * @prev_blksz: The former transfer blksz record. 72 * @timing: Record of current ios timing. 73 * @use_dma: Which DMA channel is in use for the current transfer, zero 74 * denotes PIO mode. 75 * @using_dma: Whether DMA is in use for the current transfer. 76 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not. 77 * @sg_dma: Bus address of DMA buffer. 78 * @sg_cpu: Virtual address of DMA buffer. 79 * @dma_ops: Pointer to DMA callbacks. 80 * @cmd_status: Snapshot of SR taken upon completion of the current 81 * @ring_size: Buffer size for idma descriptors. 82 * command. Only valid when EVENT_CMD_COMPLETE is pending. 83 * @dms: structure of slave-dma private data. 84 * @phy_regs: physical address of controller's register map 85 * @data_status: Snapshot of SR taken upon completion of the current 86 * data transfer. Only valid when EVENT_DATA_COMPLETE or 87 * EVENT_DATA_ERROR is pending. 88 * @stop_cmdr: Value to be loaded into CMDR when the stop command is 89 * to be sent. 90 * @dir_status: Direction of current transfer. 91 * @bh_work: Work running the request state machine. 92 * @pending_events: Bitmask of events flagged by the interrupt handler 93 * to be processed by bh work. 94 * @completed_events: Bitmask of events which the state machine has 95 * processed. 96 * @state: BH work state. 97 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus 98 * rate and timeout calculations. 99 * @current_speed: Configured rate of the controller. 100 * @minimum_speed: Stored minimum rate of the controller. 101 * @fifoth_val: The value of FIFOTH register. 102 * @verid: Denote Version ID. 103 * @dev: Device associated with the MMC controller. 104 * @drv_data: Driver specific data for identified variant of the controller 105 * @priv: Implementation defined private data. 106 * @biu_clk: Pointer to bus interface unit clock instance. 107 * @ciu_clk: Pointer to card interface unit clock instance. 108 * @fifo_depth: depth of FIFO. 109 * @data_addr_override: override fifo reg offset with this value. 110 * @wm_aligned: force fifo watermark equal with data length in PIO mode. 111 * Set as true if alignment is needed. 112 * @data_shift: log2 of FIFO item size. 113 * @part_buf_start: Start index in part_buf. 114 * @part_buf_count: Bytes of partial data in part_buf. 115 * @part_buf: Simple buffer for partial fifo reads/writes. 116 * @push_data: Pointer to FIFO push function. 117 * @pull_data: Pointer to FIFO pull function. 118 * @quirks: Set of quirks that apply to specific versions of the IP. 119 * @irq_flags: The flags to be passed to request_irq. 120 * @irq: The irq value to be passed to request_irq. 121 * @sdio_irq: SDIO interrupt bit in interrupt registers. 122 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme. 123 * @cto_timer: Timer for broken command transfer over scheme. 124 * @dto_timer: Timer for broken data transfer over scheme. 125 * @mmc: The mmc_host representing this dw_mci. 126 * @flags: Random state bits associated with the host. 127 * @ctype: Card type for this host. 128 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 129 * @clk_old: The last clock value that was requested from core. 130 * @pdev: platform_device registered 131 * @rstc: Reset controller for this host. 132 * @detect_delay_ms: Delay in mS before detecting cards after interrupt. 133 * @phase_map: The map for recording in and out phases for each timing 134 * 135 * Locking 136 * ======= 137 * 138 * @lock is a softirq-safe spinlock protecting as well as 139 * @mrq and @state. These must always be updated 140 * at the same time while holding @lock. 141 * 142 * @irq_lock is an irq-safe spinlock protecting the INTMASK register 143 * to allow the interrupt handler to modify it directly. Held for only long 144 * enough to read-modify-write INTMASK and no other locks are grabbed when 145 * holding this one. 146 * 147 * @pending_events and @completed_events are accessed using atomic bit 148 * operations, so they don't need any locking. 149 * 150 * None of the fields touched by the interrupt handler need any 151 * locking. However, ordering is important: Before EVENT_DATA_ERROR or 152 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related 153 * interrupts must be disabled and @data_status updated with a 154 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the 155 * CMDRDY interrupt must be disabled and @cmd_status updated with a 156 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the 157 * bytes_xfered field of @data must be written. This is ensured by 158 * using barriers. 159 */ 160 struct dw_mci { 161 spinlock_t lock; 162 spinlock_t irq_lock; 163 void __iomem *regs; 164 void __iomem *fifo_reg; 165 u32 data_addr_override; 166 bool wm_aligned; 167 168 struct scatterlist *sg; 169 struct sg_mapping_iter sg_miter; 170 171 struct mmc_request *mrq; 172 struct mmc_command *cmd; 173 struct mmc_data *data; 174 struct mmc_command stop_abort; 175 unsigned int prev_blksz; 176 unsigned char timing; 177 178 /* DMA interface members*/ 179 int use_dma; 180 int using_dma; 181 int dma_64bit_address; 182 183 dma_addr_t sg_dma; 184 void *sg_cpu; 185 const struct dw_mci_dma_ops *dma_ops; 186 /* For idmac */ 187 unsigned int ring_size; 188 189 /* For edmac */ 190 struct dw_mci_dma_slave *dms; 191 /* Registers's physical base address */ 192 resource_size_t phy_regs; 193 194 u32 cmd_status; 195 u32 data_status; 196 u32 stop_cmdr; 197 u32 dir_status; 198 struct work_struct bh_work; 199 unsigned long pending_events; 200 unsigned long completed_events; 201 enum dw_mci_state state; 202 203 u32 bus_hz; 204 u32 current_speed; 205 u32 minimum_speed; 206 u32 fifoth_val; 207 u16 verid; 208 struct device *dev; 209 const struct dw_mci_drv_data *drv_data; 210 void *priv; 211 struct clk *biu_clk; 212 struct clk *ciu_clk; 213 struct dw_mci_slot *slot; 214 215 /* FIFO push and pull */ 216 int fifo_depth; 217 int data_shift; 218 u8 part_buf_start; 219 u8 part_buf_count; 220 union { 221 u16 part_buf16; 222 u32 part_buf32; 223 u64 part_buf; 224 }; 225 void (*push_data)(struct dw_mci *host, void *buf, int cnt); 226 void (*pull_data)(struct dw_mci *host, void *buf, int cnt); 227 228 u32 quirks; 229 unsigned long irq_flags; /* IRQ flags */ 230 int irq; 231 232 int sdio_irq; 233 234 struct timer_list cmd11_timer; 235 struct timer_list cto_timer; 236 struct timer_list dto_timer; 237 238 #ifdef CONFIG_FAULT_INJECTION 239 struct fault_attr fail_data_crc; 240 struct hrtimer fault_timer; 241 #endif 242 struct mmc_host *mmc; 243 unsigned long flags; 244 #define DW_MMC_CARD_NEED_INIT 0 245 #define DW_MMC_CARD_NO_LOW_PWR 1 246 #define DW_MMC_CARD_NO_USE_HOLD 2 247 #define DW_MMC_CARD_NEEDS_POLL 3 248 u32 ctype; 249 unsigned int clock; 250 unsigned int clk_old; 251 struct platform_device *pdev; 252 struct reset_control *rstc; 253 u32 detect_delay_ms; 254 struct mmc_clk_phase_map phase_map; 255 }; 256 257 /* DMA ops for Internal/External DMAC interface */ 258 struct dw_mci_dma_ops { 259 /* DMA Ops */ 260 int (*init)(struct dw_mci *host); 261 int (*start)(struct dw_mci *host, unsigned int sg_len); 262 void (*complete)(void *host); 263 void (*stop)(struct dw_mci *host); 264 void (*cleanup)(struct dw_mci *host); 265 void (*exit)(struct dw_mci *host); 266 }; 267 268 /* Support for longer data read timeout */ 269 #define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0) 270 /* Force 32-bit access to the FIFO */ 271 #define DW_MMC_QUIRK_FIFO64_32 BIT(1) 272 273 #define DW_MMC_240A 0x240a 274 #define DW_MMC_280A 0x280a 275 276 #define SDMMC_CTRL 0x000 277 #define SDMMC_PWREN 0x004 278 #define SDMMC_CLKDIV 0x008 279 #define SDMMC_CLKSRC 0x00c 280 #define SDMMC_CLKENA 0x010 281 #define SDMMC_TMOUT 0x014 282 #define SDMMC_CTYPE 0x018 283 #define SDMMC_BLKSIZ 0x01c 284 #define SDMMC_BYTCNT 0x020 285 #define SDMMC_INTMASK 0x024 286 #define SDMMC_CMDARG 0x028 287 #define SDMMC_CMD 0x02c 288 #define SDMMC_RESP0 0x030 289 #define SDMMC_RESP1 0x034 290 #define SDMMC_RESP2 0x038 291 #define SDMMC_RESP3 0x03c 292 #define SDMMC_MINTSTS 0x040 293 #define SDMMC_RINTSTS 0x044 294 #define SDMMC_STATUS 0x048 295 #define SDMMC_FIFOTH 0x04c 296 #define SDMMC_CDETECT 0x050 297 #define SDMMC_WRTPRT 0x054 298 #define SDMMC_GPIO 0x058 299 #define SDMMC_TCBCNT 0x05c 300 #define SDMMC_TBBCNT 0x060 301 #define SDMMC_DEBNCE 0x064 302 #define SDMMC_USRID 0x068 303 #define SDMMC_VERID 0x06c 304 #define SDMMC_HCON 0x070 305 #define SDMMC_UHS_REG 0x074 306 #define SDMMC_RST_N 0x078 307 #define SDMMC_BMOD 0x080 308 #define SDMMC_PLDMND 0x084 309 #define SDMMC_DBADDR 0x088 310 #define SDMMC_IDSTS 0x08c 311 #define SDMMC_IDINTEN 0x090 312 #define SDMMC_DSCADDR 0x094 313 #define SDMMC_BUFADDR 0x098 314 #define SDMMC_CDTHRCTL 0x100 315 #define SDMMC_UHS_REG_EXT 0x108 316 #define SDMMC_DDR_REG 0x10c 317 #define SDMMC_ENABLE_SHIFT 0x110 318 #define SDMMC_DATA(x) (x) 319 /* 320 * Registers to support idmac 64-bit address mode 321 */ 322 #define SDMMC_DBADDRL 0x088 323 #define SDMMC_DBADDRU 0x08c 324 #define SDMMC_IDSTS64 0x090 325 #define SDMMC_IDINTEN64 0x094 326 #define SDMMC_DSCADDRL 0x098 327 #define SDMMC_DSCADDRU 0x09c 328 #define SDMMC_BUFADDRL 0x0A0 329 #define SDMMC_BUFADDRU 0x0A4 330 331 /* 332 * Data offset is difference according to Version 333 * Lower than 2.40a : data register offest is 0x100 334 */ 335 #define DATA_OFFSET 0x100 336 #define DATA_240A_OFFSET 0x200 337 338 /* shift bit field */ 339 #define _SBF(f, v) ((v) << (f)) 340 341 /* Control register defines */ 342 #define SDMMC_CTRL_USE_IDMAC BIT(25) 343 #define SDMMC_CTRL_CEATA_INT_EN BIT(11) 344 #define SDMMC_CTRL_SEND_AS_CCSD BIT(10) 345 #define SDMMC_CTRL_SEND_CCSD BIT(9) 346 #define SDMMC_CTRL_ABRT_READ_DATA BIT(8) 347 #define SDMMC_CTRL_SEND_IRQ_RESP BIT(7) 348 #define SDMMC_CTRL_READ_WAIT BIT(6) 349 #define SDMMC_CTRL_DMA_ENABLE BIT(5) 350 #define SDMMC_CTRL_INT_ENABLE BIT(4) 351 #define SDMMC_CTRL_DMA_RESET BIT(2) 352 #define SDMMC_CTRL_FIFO_RESET BIT(1) 353 #define SDMMC_CTRL_RESET BIT(0) 354 /* Clock Enable register defines */ 355 #define SDMMC_CLKEN_LOW_PWR BIT(16) 356 #define SDMMC_CLKEN_ENABLE BIT(0) 357 /* time-out register defines */ 358 #define SDMMC_TMOUT_DATA(n) _SBF(8, (n)) 359 #define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00 360 #define SDMMC_TMOUT_RESP(n) ((n) & 0xFF) 361 #define SDMMC_TMOUT_RESP_MSK 0xFF 362 /* card-type register defines */ 363 #define SDMMC_CTYPE_8BIT BIT(16) 364 #define SDMMC_CTYPE_4BIT BIT(0) 365 #define SDMMC_CTYPE_1BIT 0 366 /* Interrupt status & mask register defines */ 367 #define SDMMC_INT_SDIO(n) BIT(16 + (n)) 368 #define SDMMC_INT_EBE BIT(15) 369 #define SDMMC_INT_ACD BIT(14) 370 #define SDMMC_INT_SBE BIT(13) 371 #define SDMMC_INT_HLE BIT(12) 372 #define SDMMC_INT_FRUN BIT(11) 373 #define SDMMC_INT_HTO BIT(10) 374 #define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */ 375 #define SDMMC_INT_DRTO BIT(9) 376 #define SDMMC_INT_RTO BIT(8) 377 #define SDMMC_INT_DCRC BIT(7) 378 #define SDMMC_INT_RCRC BIT(6) 379 #define SDMMC_INT_RXDR BIT(5) 380 #define SDMMC_INT_TXDR BIT(4) 381 #define SDMMC_INT_DATA_OVER BIT(3) 382 #define SDMMC_INT_CMD_DONE BIT(2) 383 #define SDMMC_INT_RESP_ERR BIT(1) 384 #define SDMMC_INT_CD BIT(0) 385 /* Command register defines */ 386 #define SDMMC_CMD_START BIT(31) 387 #define SDMMC_CMD_USE_HOLD_REG BIT(29) 388 #define SDMMC_CMD_VOLT_SWITCH BIT(28) 389 #define SDMMC_CMD_CCS_EXP BIT(23) 390 #define SDMMC_CMD_CEATA_RD BIT(22) 391 #define SDMMC_CMD_UPD_CLK BIT(21) 392 #define SDMMC_CMD_INIT BIT(15) 393 #define SDMMC_CMD_STOP BIT(14) 394 #define SDMMC_CMD_PRV_DAT_WAIT BIT(13) 395 #define SDMMC_CMD_SEND_STOP BIT(12) 396 #define SDMMC_CMD_STRM_MODE BIT(11) 397 #define SDMMC_CMD_DAT_WR BIT(10) 398 #define SDMMC_CMD_DAT_EXP BIT(9) 399 #define SDMMC_CMD_RESP_CRC BIT(8) 400 #define SDMMC_CMD_RESP_LONG BIT(7) 401 #define SDMMC_CMD_RESP_EXP BIT(6) 402 #define SDMMC_CMD_INDX(n) ((n) & 0x1F) 403 /* Status register defines */ 404 #define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF) 405 #define SDMMC_STATUS_DMA_REQ BIT(31) 406 #define SDMMC_STATUS_BUSY BIT(9) 407 /* FIFOTH register defines */ 408 #define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \ 409 ((r) & 0xFFF) << 16 | \ 410 ((t) & 0xFFF)) 411 /* HCON register defines */ 412 #define DMA_INTERFACE_IDMA (0x0) 413 #define DMA_INTERFACE_DWDMA (0x1) 414 #define DMA_INTERFACE_GDMA (0x2) 415 #define DMA_INTERFACE_NODMA (0x3) 416 #define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3) 417 #define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1) 418 #define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7) 419 #define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1) 420 /* Internal DMAC interrupt defines */ 421 #define SDMMC_IDMAC_INT_AI BIT(9) 422 #define SDMMC_IDMAC_INT_NI BIT(8) 423 #define SDMMC_IDMAC_INT_CES BIT(5) 424 #define SDMMC_IDMAC_INT_DU BIT(4) 425 #define SDMMC_IDMAC_INT_FBE BIT(2) 426 #define SDMMC_IDMAC_INT_RI BIT(1) 427 #define SDMMC_IDMAC_INT_TI BIT(0) 428 /* Internal DMAC bus mode bits */ 429 #define SDMMC_IDMAC_ENABLE BIT(7) 430 #define SDMMC_IDMAC_FB BIT(1) 431 #define SDMMC_IDMAC_SWRESET BIT(0) 432 /* H/W reset */ 433 #define SDMMC_RST_HWACTIVE 0x1 434 /* Version ID register define */ 435 #define SDMMC_GET_VERID(x) ((x) & 0xFFFF) 436 /* Card read threshold */ 437 #define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 | (x)) 438 #define SDMMC_CARD_WR_THR_EN BIT(2) 439 #define SDMMC_CARD_RD_THR_EN BIT(0) 440 /* UHS-1 register defines */ 441 #define SDMMC_UHS_DDR BIT(16) 442 #define SDMMC_UHS_18V BIT(0) 443 /* DDR register defines */ 444 #define SDMMC_DDR_HS400 BIT(31) 445 /* Enable shift register defines */ 446 #define SDMMC_ENABLE_PHASE BIT(0) 447 /* All ctrl reset bits */ 448 #define SDMMC_CTRL_ALL_RESET_FLAGS \ 449 (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET) 450 451 /* FIFO register access macros. These should not change the data endian-ness 452 * as they are written to memory to be dealt with by the upper layers 453 */ 454 #define mci_fifo_readw(__reg) __raw_readw(__reg) 455 #define mci_fifo_readl(__reg) __raw_readl(__reg) 456 #define mci_fifo_readq(__reg) __raw_readq(__reg) 457 458 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value) 459 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value) 460 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value) 461 462 /* 463 * Some dw_mmc devices have 64-bit FIFOs, but expect them to be 464 * accessed using two 32-bit accesses. If such controller is used 465 * with a 64-bit kernel, this has to be done explicitly. 466 */ 467 static inline u64 mci_fifo_l_readq(void __iomem *addr) 468 { 469 u64 ans; 470 u32 proxy[2]; 471 472 proxy[0] = mci_fifo_readl(addr); 473 proxy[1] = mci_fifo_readl(addr + 4); 474 memcpy(&ans, proxy, 8); 475 return ans; 476 } 477 478 static inline void mci_fifo_l_writeq(void __iomem *addr, u64 value) 479 { 480 u32 proxy[2]; 481 482 memcpy(proxy, &value, 8); 483 mci_fifo_writel(addr, proxy[0]); 484 mci_fifo_writel(addr + 4, proxy[1]); 485 } 486 487 /* Register access macros */ 488 #define mci_readl(dev, reg) \ 489 readl_relaxed((dev)->regs + SDMMC_##reg) 490 #define mci_writel(dev, reg, value) \ 491 writel_relaxed((value), (dev)->regs + SDMMC_##reg) 492 493 #ifndef readq 494 #define __raw_writeq(__value, __reg) \ 495 (*(volatile u64 __force *)(__reg) = (__value)) 496 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg)) 497 #endif 498 499 extern struct dw_mci *dw_mci_alloc_host(struct device *device); 500 extern int dw_mci_probe(struct dw_mci *host); 501 extern void dw_mci_remove(struct dw_mci *host); 502 extern int dw_mci_runtime_suspend(struct device *device); 503 extern int dw_mci_runtime_resume(struct device *device); 504 505 /** 506 * dw_mci driver data - dw-mshc implementation specific driver data. 507 * @caps: mmc subsystem specified capabilities of the controller(s). 508 * @num_caps: number of capabilities specified by @caps. 509 * @common_caps: mmc subsystem specified capabilities applicable to all of 510 * the controllers 511 * @init: early implementation specific initialization. 512 * @set_ios: handle bus specific extensions. 513 * @parse_dt: parse implementation specific device tree properties. 514 * @execute_tuning: implementation specific tuning procedure. 515 * @set_data_timeout: implementation specific timeout. 516 * @get_drto_clks: implementation specific cycle count for data read timeout. 517 * @hw_reset: implementation specific HW reset. 518 * 519 * Provide controller implementation specific extensions. The usage of this 520 * data structure is fully optional and usage of each member in this structure 521 * is optional as well. 522 */ 523 struct dw_mci_drv_data { 524 unsigned long *caps; 525 u32 num_caps; 526 u32 common_caps; 527 int (*init)(struct dw_mci *host); 528 void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios); 529 int (*parse_dt)(struct dw_mci *host); 530 int (*execute_tuning)(struct dw_mci *host, u32 opcode); 531 int (*prepare_hs400_tuning)(struct dw_mci *host, 532 struct mmc_ios *ios); 533 int (*switch_voltage)(struct dw_mci *host, 534 struct mmc_ios *ios); 535 void (*set_data_timeout)(struct dw_mci *host, 536 unsigned int timeout_ns); 537 u32 (*get_drto_clks)(struct dw_mci *host); 538 void (*hw_reset)(struct dw_mci *host); 539 }; 540 #endif /* _DW_MMC_H_ */ 541