1 /*
2 * Microchip PolarFire SoC DDR Memory Controller module emulation
3 *
4 * Copyright (c) 2020 Wind River Systems, Inc.
5 *
6 * Author:
7 * Bin Meng <bin.meng@windriver.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 or
12 * (at your option) version 3 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/bitops.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "hw/sysbus.h"
28 #include "hw/misc/mchp_pfsoc_dmc.h"
29
30 /* DDR SGMII PHY module */
31
32 #define SGMII_PHY_IOC_REG1 0x208
33 #define SGMII_PHY_TRAINING_STATUS 0x814
34 #define SGMII_PHY_DQ_DQS_ERR_DONE 0x834
35 #define SGMII_PHY_DQDQS_STATUS1 0x84c
36 #define SGMII_PHY_PVT_STAT 0xc20
37
mchp_pfsoc_ddr_sgmii_phy_read(void * opaque,hwaddr offset,unsigned size)38 static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
39 unsigned size)
40 {
41 uint32_t val = 0;
42 static int training_status_bit;
43
44 switch (offset) {
45 case SGMII_PHY_IOC_REG1:
46 /* See ddr_pvt_calibration() in HSS */
47 val = BIT(4) | BIT(2);
48 break;
49 case SGMII_PHY_TRAINING_STATUS:
50 /*
51 * The codes logic emulates the training status change from
52 * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
53 *
54 * See ddr_setup() in mss_ddr.c in the HSS source codes.
55 */
56 val = 1 << training_status_bit;
57 training_status_bit = (training_status_bit + 1) % 5;
58 break;
59 case SGMII_PHY_DQ_DQS_ERR_DONE:
60 /*
61 * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
62 * check that DQ/DQS training passed without error.
63 */
64 val = 8;
65 break;
66 case SGMII_PHY_DQDQS_STATUS1:
67 /*
68 * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
69 * check that DQ/DQS calculated window is above 5 taps.
70 */
71 val = 0xff;
72 break;
73 case SGMII_PHY_PVT_STAT:
74 /* See sgmii_channel_setup() in HSS */
75 val = BIT(14) | BIT(6);
76 break;
77 default:
78 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
79 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
80 __func__, size, offset);
81 break;
82 }
83
84 return val;
85 }
86
mchp_pfsoc_ddr_sgmii_phy_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)87 static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
88 uint64_t value, unsigned size)
89 {
90 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
91 "(size %d, value 0x%" PRIx64
92 ", offset 0x%" HWADDR_PRIx ")\n",
93 __func__, size, value, offset);
94 }
95
96 static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
97 .read = mchp_pfsoc_ddr_sgmii_phy_read,
98 .write = mchp_pfsoc_ddr_sgmii_phy_write,
99 .endianness = DEVICE_LITTLE_ENDIAN,
100 };
101
mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState * dev,Error ** errp)102 static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
103 {
104 MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
105
106 memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
107 &mchp_pfsoc_ddr_sgmii_phy_ops, s,
108 "mchp.pfsoc.ddr_sgmii_phy",
109 MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
110 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
111 }
112
mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass * klass,const void * data)113 static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass,
114 const void *data)
115 {
116 DeviceClass *dc = DEVICE_CLASS(klass);
117
118 dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
119 dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
120 }
121
122 static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
123 .name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
124 .parent = TYPE_SYS_BUS_DEVICE,
125 .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
126 .class_init = mchp_pfsoc_ddr_sgmii_phy_class_init,
127 };
128
mchp_pfsoc_ddr_sgmii_phy_register_types(void)129 static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
130 {
131 type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
132 }
133
type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)134 type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
135
136 /* DDR CFG module */
137
138 #define CFG_MT_DONE_ACK 0x4428
139 #define CFG_STAT_DFI_INIT_COMPLETE 0x10034
140 #define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038
141
142 static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
143 unsigned size)
144 {
145 uint32_t val = 0;
146
147 switch (offset) {
148 case CFG_MT_DONE_ACK:
149 /* memory test in MTC_test() */
150 val = BIT(0);
151 break;
152 case CFG_STAT_DFI_INIT_COMPLETE:
153 /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
154 val = BIT(0);
155 break;
156 case CFG_STAT_DFI_TRAINING_COMPLETE:
157 /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
158 val = BIT(0);
159 break;
160 default:
161 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
162 "(size %d, offset 0x%" HWADDR_PRIx ")\n",
163 __func__, size, offset);
164 break;
165 }
166
167 return val;
168 }
169
mchp_pfsoc_ddr_cfg_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)170 static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
171 uint64_t value, unsigned size)
172 {
173 qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
174 "(size %d, value 0x%" PRIx64
175 ", offset 0x%" HWADDR_PRIx ")\n",
176 __func__, size, value, offset);
177 }
178
179 static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
180 .read = mchp_pfsoc_ddr_cfg_read,
181 .write = mchp_pfsoc_ddr_cfg_write,
182 .endianness = DEVICE_LITTLE_ENDIAN,
183 };
184
mchp_pfsoc_ddr_cfg_realize(DeviceState * dev,Error ** errp)185 static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
186 {
187 MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
188
189 memory_region_init_io(&s->cfg, OBJECT(dev),
190 &mchp_pfsoc_ddr_cfg_ops, s,
191 "mchp.pfsoc.ddr_cfg",
192 MCHP_PFSOC_DDR_CFG_REG_SIZE);
193 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
194 }
195
mchp_pfsoc_ddr_cfg_class_init(ObjectClass * klass,const void * data)196 static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, const void *data)
197 {
198 DeviceClass *dc = DEVICE_CLASS(klass);
199
200 dc->desc = "Microchip PolarFire SoC DDR CFG module";
201 dc->realize = mchp_pfsoc_ddr_cfg_realize;
202 }
203
204 static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
205 .name = TYPE_MCHP_PFSOC_DDR_CFG,
206 .parent = TYPE_SYS_BUS_DEVICE,
207 .instance_size = sizeof(MchpPfSoCDdrCfgState),
208 .class_init = mchp_pfsoc_ddr_cfg_class_init,
209 };
210
mchp_pfsoc_ddr_cfg_register_types(void)211 static void mchp_pfsoc_ddr_cfg_register_types(void)
212 {
213 type_register_static(&mchp_pfsoc_ddr_cfg_info);
214 }
215
216 type_init(mchp_pfsoc_ddr_cfg_register_types)
217