1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor 4 * 5 * Multi-channel Audio Serial Port Driver 6 * 7 * Author: Nirmal Pandey <n-pandey@ti.com>, 8 * Suresh Rajashekara <suresh.r@ti.com> 9 * Steve Chen <schen@.mvista.com> 10 * 11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright: (C) 2009 Texas Instruments, India 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/delay.h> 20 #include <linux/io.h> 21 #include <linux/clk.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/platform_data/davinci_asp.h> 25 #include <linux/math64.h> 26 #include <linux/bitmap.h> 27 #include <linux/gpio/driver.h> 28 #include <linux/property.h> 29 30 #include <sound/asoundef.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/initval.h> 35 #include <sound/soc.h> 36 #include <sound/dmaengine_pcm.h> 37 38 #include "edma-pcm.h" 39 #include "sdma-pcm.h" 40 #include "udma-pcm.h" 41 #include "davinci-mcasp.h" 42 43 #define MCASP_MAX_AFIFO_DEPTH 64 44 45 #ifdef CONFIG_PM 46 static u32 context_regs[] = { 47 DAVINCI_MCASP_TXFMCTL_REG, 48 DAVINCI_MCASP_RXFMCTL_REG, 49 DAVINCI_MCASP_TXFMT_REG, 50 DAVINCI_MCASP_RXFMT_REG, 51 DAVINCI_MCASP_ACLKXCTL_REG, 52 DAVINCI_MCASP_ACLKRCTL_REG, 53 DAVINCI_MCASP_AHCLKXCTL_REG, 54 DAVINCI_MCASP_AHCLKRCTL_REG, 55 DAVINCI_MCASP_PDIR_REG, 56 DAVINCI_MCASP_PFUNC_REG, 57 DAVINCI_MCASP_RXMASK_REG, 58 DAVINCI_MCASP_TXMASK_REG, 59 DAVINCI_MCASP_RXTDM_REG, 60 DAVINCI_MCASP_TXTDM_REG, 61 }; 62 63 struct davinci_mcasp_context { 64 u32 config_regs[ARRAY_SIZE(context_regs)]; 65 u32 afifo_regs[2]; /* for read/write fifo control registers */ 66 u32 *xrsr_regs; /* for serializer configuration */ 67 bool pm_state; 68 }; 69 #endif 70 71 struct davinci_mcasp_ruledata { 72 struct davinci_mcasp *mcasp; 73 int serializers; 74 int stream; 75 }; 76 77 struct davinci_mcasp { 78 struct snd_dmaengine_dai_dma_data dma_data[2]; 79 struct davinci_mcasp_pdata *pdata; 80 void __iomem *base; 81 u32 fifo_base; 82 struct device *dev; 83 struct snd_pcm_substream *substreams[2]; 84 unsigned int dai_fmt; 85 86 u32 iec958_status; 87 88 /* Audio can not be enabled due to missing parameter(s) */ 89 bool missing_audio_param; 90 91 /* McASP specific data */ 92 int tdm_slots_tx; 93 int tdm_slots_rx; 94 u32 tdm_mask[2]; 95 int slot_width_tx; 96 int slot_width_rx; 97 u8 op_mode; 98 u8 dismod; 99 u8 num_serializer; 100 u8 *serial_dir; 101 u8 version; 102 u8 bclk_div_tx; 103 u8 bclk_div_rx; 104 int streams; 105 u32 irq_request[2]; 106 107 unsigned int sysclk_freq_tx; 108 unsigned int sysclk_freq_rx; 109 bool bclk_master; 110 bool async_mode; 111 u32 auxclk_fs_ratio_tx; 112 u32 auxclk_fs_ratio_rx; 113 114 unsigned long pdir; /* Pin direction bitfield */ 115 116 /* McASP FIFO related */ 117 u8 txnumevt; 118 u8 rxnumevt; 119 120 bool dat_port; 121 122 /* Used for comstraint setting on the second stream */ 123 u32 channels; 124 int max_format_width; 125 u8 active_serializers[2]; 126 127 #ifdef CONFIG_GPIOLIB 128 struct gpio_chip gpio_chip; 129 #endif 130 131 #ifdef CONFIG_PM 132 struct davinci_mcasp_context context; 133 #endif 134 135 struct davinci_mcasp_ruledata ruledata[2]; 136 struct snd_pcm_hw_constraint_list chconstr[2]; 137 }; 138 139 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset, 140 u32 val) 141 { 142 void __iomem *reg = mcasp->base + offset; 143 __raw_writel(__raw_readl(reg) | val, reg); 144 } 145 146 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset, 147 u32 val) 148 { 149 void __iomem *reg = mcasp->base + offset; 150 __raw_writel((__raw_readl(reg) & ~(val)), reg); 151 } 152 153 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset, 154 u32 val, u32 mask) 155 { 156 void __iomem *reg = mcasp->base + offset; 157 __raw_writel((__raw_readl(reg) & ~mask) | val, reg); 158 } 159 160 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset, 161 u32 val) 162 { 163 __raw_writel(val, mcasp->base + offset); 164 } 165 166 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset) 167 { 168 return (u32)__raw_readl(mcasp->base + offset); 169 } 170 171 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val) 172 { 173 int i = 0; 174 175 mcasp_set_bits(mcasp, ctl_reg, val); 176 177 /* programming GBLCTL needs to read back from GBLCTL and verfiy */ 178 /* loop count is to avoid the lock-up */ 179 for (i = 0; i < 1000; i++) { 180 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val) 181 break; 182 } 183 184 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val)) 185 printk(KERN_ERR "GBLCTL write error\n"); 186 } 187 188 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp) 189 { 190 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG); 191 192 return !(aclkxctl & TX_ASYNC); 193 } 194 195 static bool mcasp_is_frame_producer(struct davinci_mcasp *mcasp) 196 { 197 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG); 198 199 return rxfmctl & AFSRE; 200 } 201 202 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable) 203 { 204 u32 bit = PIN_BIT_AMUTE; 205 206 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) { 207 if (enable) 208 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 209 else 210 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 211 } 212 } 213 214 static inline void mcasp_set_clk_pdir_stream(struct davinci_mcasp *mcasp, 215 int stream, bool enable) 216 { 217 u32 bit, bit_end; 218 219 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 220 bit = PIN_BIT_ACLKX; 221 bit_end = PIN_BIT_AFSX + 1; 222 } else { 223 bit = PIN_BIT_ACLKR; 224 bit_end = PIN_BIT_AFSR + 1; 225 } 226 227 for_each_set_bit_from(bit, &mcasp->pdir, bit_end) { 228 if (enable) 229 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 230 else 231 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 232 } 233 } 234 235 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable) 236 { 237 u32 bit; 238 239 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) { 240 if (enable) 241 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 242 else 243 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit)); 244 } 245 } 246 247 static inline int mcasp_get_tdm_slots(struct davinci_mcasp *mcasp, int stream) 248 { 249 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 250 mcasp->tdm_slots_tx : mcasp->tdm_slots_rx; 251 } 252 253 static inline int mcasp_get_slot_width(struct davinci_mcasp *mcasp, int stream) 254 { 255 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 256 mcasp->slot_width_tx : mcasp->slot_width_rx; 257 } 258 259 static inline unsigned int mcasp_get_sysclk_freq(struct davinci_mcasp *mcasp, int stream) 260 { 261 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 262 mcasp->sysclk_freq_tx : mcasp->sysclk_freq_rx; 263 } 264 265 static inline unsigned int mcasp_get_bclk_div(struct davinci_mcasp *mcasp, int stream) 266 { 267 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 268 mcasp->bclk_div_tx : mcasp->bclk_div_rx; 269 } 270 271 static inline unsigned int mcasp_get_auxclk_fs_ratio(struct davinci_mcasp *mcasp, int stream) 272 { 273 return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? 274 mcasp->auxclk_fs_ratio_tx : mcasp->auxclk_fs_ratio_rx; 275 } 276 277 static inline bool mcasp_is_auxclk_enabled(struct davinci_mcasp *mcasp, int stream) 278 { 279 if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_CAPTURE) 280 return mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG) & AHCLKRE; 281 282 return mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG) & AHCLKXE; 283 } 284 285 static void mcasp_start_rx(struct davinci_mcasp *mcasp) 286 { 287 if (mcasp->rxnumevt) { /* enable FIFO */ 288 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 289 290 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 291 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 292 } 293 294 /* Start clocks */ 295 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 296 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 297 /* 298 * When ASYNC == 0 the transmit and receive sections operate 299 * synchronously from the transmit clock and frame sync. We need to make 300 * sure that the TX signals are enabled when starting reception, 301 * when the McASP is the producer. 302 */ 303 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) { 304 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 305 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 306 } 307 if (mcasp_is_synchronous(mcasp)) 308 mcasp_set_clk_pdir(mcasp, true); 309 else 310 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, true); 311 312 /* Activate serializer(s) */ 313 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 314 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 315 /* Release RX state machine */ 316 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 317 /* Release Frame Sync generator */ 318 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 319 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp)) 320 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 321 322 /* enable receive IRQs */ 323 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 324 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 325 } 326 327 static void mcasp_start_tx(struct davinci_mcasp *mcasp) 328 { 329 u32 cnt; 330 331 if (mcasp->txnumevt) { /* enable FIFO */ 332 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 333 334 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 335 mcasp_set_bits(mcasp, reg, FIFO_ENABLE); 336 } 337 338 /* Start clocks */ 339 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 340 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 341 if (mcasp_is_synchronous(mcasp)) 342 mcasp_set_clk_pdir(mcasp, true); 343 else 344 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, true); 345 346 /* Activate serializer(s) */ 347 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 348 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 349 350 /* wait for XDATA to be cleared */ 351 cnt = 0; 352 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) && 353 (cnt < 100000)) 354 cnt++; 355 356 mcasp_set_axr_pdir(mcasp, true); 357 358 /* Release TX state machine */ 359 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 360 /* Release Frame Sync generator */ 361 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 362 363 /* enable transmit IRQs */ 364 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 365 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 366 } 367 368 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream) 369 { 370 mcasp->streams++; 371 372 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 373 mcasp_start_tx(mcasp); 374 else 375 mcasp_start_rx(mcasp); 376 } 377 378 static void mcasp_stop_rx(struct davinci_mcasp *mcasp) 379 { 380 /* disable IRQ sources */ 381 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG, 382 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]); 383 384 /* 385 * In synchronous mode stop the TX clocks if no other stream is 386 * running 387 * Otherwise in async mode only stop RX clocks 388 */ 389 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 390 mcasp_set_clk_pdir(mcasp, false); 391 else if (!mcasp_is_synchronous(mcasp)) 392 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_CAPTURE, false); 393 /* 394 * When McASP is the producer and operating in synchronous mode, 395 * stop the transmit clocks if no other stream is running. As 396 * tx & rx operate synchronously from the transmit clock. 397 */ 398 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && !mcasp->streams) 399 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0); 400 401 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0); 402 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 403 404 if (mcasp->rxnumevt) { /* disable FIFO */ 405 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 406 407 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 408 } 409 } 410 411 static void mcasp_stop_tx(struct davinci_mcasp *mcasp) 412 { 413 u32 val = 0; 414 415 /* disable IRQ sources */ 416 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG, 417 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]); 418 419 /* 420 * In synchronous mode keep TX clocks running if the capture stream is 421 * still running. 422 * Otherwise in async mode only stop TX clocks 423 */ 424 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && mcasp->streams) 425 val = TXHCLKRST | TXCLKRST | TXFSRST; 426 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) 427 mcasp_set_clk_pdir(mcasp, false); 428 else if (!mcasp_is_synchronous(mcasp)) 429 mcasp_set_clk_pdir_stream(mcasp, SNDRV_PCM_STREAM_PLAYBACK, false); 430 431 432 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val); 433 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 434 435 if (mcasp->txnumevt) { /* disable FIFO */ 436 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 437 438 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE); 439 } 440 441 mcasp_set_axr_pdir(mcasp, false); 442 } 443 444 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream) 445 { 446 mcasp->streams--; 447 448 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 449 mcasp_stop_tx(mcasp); 450 else 451 mcasp_stop_rx(mcasp); 452 } 453 454 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data) 455 { 456 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 457 struct snd_pcm_substream *substream; 458 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]; 459 u32 handled_mask = 0; 460 u32 stat; 461 462 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG); 463 if (stat & XUNDRN & irq_mask) { 464 dev_warn(mcasp->dev, "Transmit buffer underflow\n"); 465 handled_mask |= XUNDRN; 466 467 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 468 if (substream) 469 snd_pcm_stop_xrun(substream); 470 } 471 472 if (!handled_mask) 473 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n", 474 stat); 475 476 if (stat & XRERR) 477 handled_mask |= XRERR; 478 479 /* Ack the handled event only */ 480 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask); 481 482 return IRQ_RETVAL(handled_mask); 483 } 484 485 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data) 486 { 487 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 488 struct snd_pcm_substream *substream; 489 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]; 490 u32 handled_mask = 0; 491 u32 stat; 492 493 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG); 494 if (stat & ROVRN & irq_mask) { 495 dev_warn(mcasp->dev, "Receive buffer overflow\n"); 496 handled_mask |= ROVRN; 497 498 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]; 499 if (substream) 500 snd_pcm_stop_xrun(substream); 501 } 502 503 if (!handled_mask) 504 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n", 505 stat); 506 507 if (stat & XRERR) 508 handled_mask |= XRERR; 509 510 /* Ack the handled event only */ 511 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask); 512 513 return IRQ_RETVAL(handled_mask); 514 } 515 516 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data) 517 { 518 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data; 519 irqreturn_t ret = IRQ_NONE; 520 521 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK]) 522 ret = davinci_mcasp_tx_irq_handler(irq, data); 523 524 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE]) 525 ret |= davinci_mcasp_rx_irq_handler(irq, data); 526 527 return ret; 528 } 529 530 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 531 unsigned int fmt) 532 { 533 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 534 int ret = 0; 535 u32 data_delay; 536 bool fs_pol_rising; 537 bool inv_fs = false; 538 539 if (!fmt) 540 return 0; 541 542 pm_runtime_get_sync(mcasp->dev); 543 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 544 case SND_SOC_DAIFMT_DSP_A: 545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 546 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 547 /* 1st data bit occur one ACLK cycle after the frame sync */ 548 data_delay = 1; 549 break; 550 case SND_SOC_DAIFMT_DSP_B: 551 case SND_SOC_DAIFMT_AC97: 552 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 553 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 554 /* No delay after FS */ 555 data_delay = 0; 556 break; 557 case SND_SOC_DAIFMT_I2S: 558 /* configure a full-word SYNC pulse (LRCLK) */ 559 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 560 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 561 /* 1st data bit occur one ACLK cycle after the frame sync */ 562 data_delay = 1; 563 /* FS need to be inverted */ 564 inv_fs = true; 565 break; 566 case SND_SOC_DAIFMT_RIGHT_J: 567 case SND_SOC_DAIFMT_LEFT_J: 568 /* configure a full-word SYNC pulse (LRCLK) */ 569 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 570 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 571 /* No delay after FS */ 572 data_delay = 0; 573 break; 574 default: 575 ret = -EINVAL; 576 goto out; 577 } 578 579 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay), 580 FSXDLY(3)); 581 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay), 582 FSRDLY(3)); 583 584 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 585 case SND_SOC_DAIFMT_BP_FP: 586 /* codec is clock and frame slave */ 587 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 588 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 589 590 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 591 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 592 593 /* BCLK */ 594 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 595 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 596 /* Frame Sync */ 597 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 598 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 599 600 mcasp->bclk_master = 1; 601 break; 602 case SND_SOC_DAIFMT_BP_FC: 603 /* codec is clock slave and frame master */ 604 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 605 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 606 607 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 608 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 609 610 /* BCLK */ 611 set_bit(PIN_BIT_ACLKX, &mcasp->pdir); 612 set_bit(PIN_BIT_ACLKR, &mcasp->pdir); 613 /* Frame Sync */ 614 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 615 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 616 617 mcasp->bclk_master = 1; 618 break; 619 case SND_SOC_DAIFMT_BC_FP: 620 /* codec is clock master and frame slave */ 621 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 622 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 623 624 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 625 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 626 627 /* BCLK */ 628 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 629 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 630 /* Frame Sync */ 631 set_bit(PIN_BIT_AFSX, &mcasp->pdir); 632 set_bit(PIN_BIT_AFSR, &mcasp->pdir); 633 634 mcasp->bclk_master = 0; 635 break; 636 case SND_SOC_DAIFMT_BC_FC: 637 /* codec is clock and frame master */ 638 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE); 639 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE); 640 641 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE); 642 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE); 643 644 /* BCLK */ 645 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir); 646 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir); 647 /* Frame Sync */ 648 clear_bit(PIN_BIT_AFSX, &mcasp->pdir); 649 clear_bit(PIN_BIT_AFSR, &mcasp->pdir); 650 651 mcasp->bclk_master = 0; 652 break; 653 default: 654 ret = -EINVAL; 655 goto out; 656 } 657 658 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 659 case SND_SOC_DAIFMT_IB_NF: 660 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 661 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 662 fs_pol_rising = true; 663 break; 664 case SND_SOC_DAIFMT_NB_IF: 665 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 666 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 667 fs_pol_rising = false; 668 break; 669 case SND_SOC_DAIFMT_IB_IF: 670 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 671 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 672 fs_pol_rising = false; 673 break; 674 case SND_SOC_DAIFMT_NB_NF: 675 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL); 676 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL); 677 fs_pol_rising = true; 678 break; 679 default: 680 ret = -EINVAL; 681 goto out; 682 } 683 684 if (inv_fs) 685 fs_pol_rising = !fs_pol_rising; 686 687 if (fs_pol_rising) { 688 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 689 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 690 } else { 691 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL); 692 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL); 693 } 694 695 mcasp->dai_fmt = fmt; 696 out: 697 pm_runtime_put(mcasp->dev); 698 return ret; 699 } 700 701 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id, 702 int div, bool explicit) 703 { 704 pm_runtime_get_sync(mcasp->dev); 705 switch (div_id) { 706 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */ 707 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 708 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 709 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 710 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 711 break; 712 713 case MCASP_CLKDIV_AUXCLK_TXONLY: /* MCLK divider for TX only */ 714 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 715 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 716 break; 717 718 case MCASP_CLKDIV_AUXCLK_RXONLY: /* MCLK divider for RX only */ 719 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 720 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 721 break; 722 723 case MCASP_CLKDIV_BCLK: /* BCLK divider */ 724 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 725 ACLKXDIV(div - 1), ACLKXDIV_MASK); 726 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 727 ACLKRDIV(div - 1), ACLKRDIV_MASK); 728 if (explicit) { 729 mcasp->bclk_div_tx = div; 730 mcasp->bclk_div_rx = div; 731 } 732 break; 733 734 case MCASP_CLKDIV_BCLK_TXONLY: /* BCLK divider for TX only */ 735 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, 736 ACLKXDIV(div - 1), ACLKXDIV_MASK); 737 if (explicit) 738 mcasp->bclk_div_tx = div; 739 break; 740 741 case MCASP_CLKDIV_BCLK_RXONLY: /* BCLK divider for RX only */ 742 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, 743 ACLKRDIV(div - 1), ACLKRDIV_MASK); 744 if (explicit) 745 mcasp->bclk_div_rx = div; 746 break; 747 748 case MCASP_CLKDIV_BCLK_FS_RATIO: 749 /* 750 * BCLK/LRCLK ratio descries how many bit-clock cycles 751 * fit into one frame. The clock ratio is given for a 752 * full period of data (for I2S format both left and 753 * right channels), so it has to be divided by number 754 * of tdm-slots (for I2S - divided by 2). 755 * Instead of storing this ratio, we calculate a new 756 * tdm_slot width by dividing the ratio by the 757 * number of configured tdm slots. 758 */ 759 mcasp->slot_width_tx = div / mcasp->tdm_slots_tx; 760 if (div % mcasp->tdm_slots_tx) 761 dev_warn(mcasp->dev, 762 "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots", 763 __func__, div, mcasp->tdm_slots_tx); 764 765 mcasp->slot_width_rx = div / mcasp->tdm_slots_rx; 766 if (div % mcasp->tdm_slots_rx) 767 dev_warn(mcasp->dev, 768 "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots", 769 __func__, div, mcasp->tdm_slots_rx); 770 break; 771 772 case MCASP_CLKDIV_BCLK_FS_RATIO_TXONLY: 773 mcasp->slot_width_tx = div / mcasp->tdm_slots_tx; 774 if (div % mcasp->tdm_slots_tx) 775 dev_warn(mcasp->dev, 776 "%s(): BCLK/LRCLK %d is not divisible by %d tx tdm slots", 777 __func__, div, mcasp->tdm_slots_tx); 778 break; 779 780 case MCASP_CLKDIV_BCLK_FS_RATIO_RXONLY: 781 mcasp->slot_width_rx = div / mcasp->tdm_slots_rx; 782 if (div % mcasp->tdm_slots_rx) 783 dev_warn(mcasp->dev, 784 "%s(): BCLK/LRCLK %d is not divisible by %d rx tdm slots", 785 __func__, div, mcasp->tdm_slots_rx); 786 break; 787 788 default: 789 return -EINVAL; 790 } 791 792 pm_runtime_put(mcasp->dev); 793 return 0; 794 } 795 796 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, 797 int div) 798 { 799 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 800 801 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1); 802 } 803 804 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 805 unsigned int freq, int dir) 806 { 807 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 808 809 pm_runtime_get_sync(mcasp->dev); 810 811 if (dir == SND_SOC_CLOCK_IN) { 812 switch (clk_id) { 813 case MCASP_CLK_HCLK_AHCLK: 814 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 815 AHCLKXE); 816 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 817 AHCLKRE); 818 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 819 mcasp->sysclk_freq_tx = freq; 820 mcasp->sysclk_freq_rx = freq; 821 break; 822 case MCASP_CLK_HCLK_AHCLK_TXONLY: 823 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 824 AHCLKXE); 825 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 826 mcasp->sysclk_freq_tx = freq; 827 break; 828 case MCASP_CLK_HCLK_AHCLK_RXONLY: 829 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 830 AHCLKRE); 831 clear_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 832 mcasp->sysclk_freq_rx = freq; 833 break; 834 case MCASP_CLK_HCLK_AUXCLK: 835 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 836 AHCLKXE); 837 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 838 AHCLKRE); 839 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 840 mcasp->sysclk_freq_tx = freq; 841 mcasp->sysclk_freq_rx = freq; 842 break; 843 case MCASP_CLK_HCLK_AUXCLK_TXONLY: 844 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 845 AHCLKXE); 846 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 847 mcasp->sysclk_freq_tx = freq; 848 break; 849 case MCASP_CLK_HCLK_AUXCLK_RXONLY: 850 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 851 AHCLKRE); 852 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 853 mcasp->sysclk_freq_rx = freq; 854 break; 855 default: 856 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id); 857 goto out; 858 } 859 } else { 860 /* McASP is clock master, select AUXCLK as HCLK */ 861 switch (clk_id) { 862 case MCASP_CLK_HCLK_AUXCLK_TXONLY: 863 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 864 AHCLKXE); 865 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 866 mcasp->sysclk_freq_tx = freq; 867 break; 868 case MCASP_CLK_HCLK_AUXCLK_RXONLY: 869 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 870 AHCLKRE); 871 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 872 mcasp->sysclk_freq_rx = freq; 873 break; 874 default: 875 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, 876 AHCLKXE); 877 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, 878 AHCLKRE); 879 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir); 880 set_bit(PIN_BIT_AHCLKR, &mcasp->pdir); 881 mcasp->sysclk_freq_tx = freq; 882 mcasp->sysclk_freq_rx = freq; 883 break; 884 } 885 } 886 /* 887 * When AHCLK X/R is selected to be output it means that the HCLK is 888 * the same clock - coming via AUXCLK. 889 */ 890 out: 891 pm_runtime_put(mcasp->dev); 892 return 0; 893 } 894 895 /* All serializers must have equal number of channels */ 896 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream, 897 int serializers) 898 { 899 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream]; 900 unsigned int *list = (unsigned int *) cl->list; 901 int slots; 902 int i, count = 0; 903 904 slots = mcasp_get_tdm_slots(mcasp, stream); 905 906 if (mcasp->tdm_mask[stream]) 907 slots = hweight32(mcasp->tdm_mask[stream]); 908 909 for (i = 1; i <= slots; i++) 910 list[count++] = i; 911 912 for (i = 2; i <= serializers; i++) 913 list[count++] = i*slots; 914 915 cl->count = count; 916 917 return 0; 918 } 919 920 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp) 921 { 922 int rx_serializers = 0, tx_serializers = 0, ret, i; 923 924 for (i = 0; i < mcasp->num_serializer; i++) 925 if (mcasp->serial_dir[i] == TX_MODE) 926 tx_serializers++; 927 else if (mcasp->serial_dir[i] == RX_MODE) 928 rx_serializers++; 929 930 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK, 931 tx_serializers); 932 if (ret) 933 return ret; 934 935 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE, 936 rx_serializers); 937 938 return ret; 939 } 940 941 942 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai, 943 unsigned int tx_mask, 944 unsigned int rx_mask, 945 int slots, int slot_width) 946 { 947 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 948 949 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 950 return 0; 951 952 dev_dbg(mcasp->dev, 953 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n", 954 __func__, tx_mask, rx_mask, slots, slot_width); 955 956 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) { 957 dev_err(mcasp->dev, 958 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n", 959 tx_mask, rx_mask, slots); 960 return -EINVAL; 961 } 962 963 if (slot_width && 964 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) { 965 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n", 966 __func__, slot_width); 967 return -EINVAL; 968 } 969 970 if (mcasp->async_mode) { 971 if (tx_mask) { 972 mcasp->tdm_slots_tx = slots; 973 mcasp->slot_width_tx = slot_width; 974 } 975 if (rx_mask) { 976 mcasp->tdm_slots_rx = slots; 977 mcasp->slot_width_rx = slot_width; 978 } 979 } else { 980 mcasp->tdm_slots_tx = slots; 981 mcasp->tdm_slots_rx = slots; 982 mcasp->slot_width_tx = slot_width; 983 mcasp->slot_width_rx = slot_width; 984 } 985 986 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask; 987 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask; 988 989 return davinci_mcasp_set_ch_constraints(mcasp); 990 } 991 992 static int davinci_config_channel_size(struct davinci_mcasp *mcasp, 993 int sample_width, int stream) 994 { 995 u32 fmt; 996 u32 tx_rotate, rx_rotate, slot_width; 997 u32 mask = (1ULL << sample_width) - 1; 998 999 slot_width = mcasp_get_slot_width(mcasp, stream); 1000 if (!slot_width) { 1001 if (mcasp->max_format_width) 1002 slot_width = mcasp->max_format_width; 1003 else 1004 slot_width = sample_width; 1005 } 1006 /* 1007 * TX rotation: 1008 * right aligned formats: rotate w/ slot_width 1009 * left aligned formats: rotate w/ sample_width 1010 * 1011 * RX rotation: 1012 * right aligned formats: no rotation needed 1013 * left aligned formats: rotate w/ (slot_width - sample_width) 1014 */ 1015 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) == 1016 SND_SOC_DAIFMT_RIGHT_J) { 1017 tx_rotate = (slot_width / 4) & 0x7; 1018 rx_rotate = 0; 1019 } else { 1020 tx_rotate = (sample_width / 4) & 0x7; 1021 rx_rotate = (slot_width - sample_width) / 4; 1022 } 1023 1024 /* mapping of the XSSZ bit-field as described in the datasheet */ 1025 fmt = (slot_width >> 1) - 1; 1026 1027 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 1028 if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_PLAYBACK) { 1029 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt), 1030 TXSSZ(0x0F)); 1031 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 1032 TXROT(7)); 1033 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 1034 } 1035 if (!mcasp->async_mode || stream == SNDRV_PCM_STREAM_CAPTURE) { 1036 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt), 1037 RXSSZ(0x0F)); 1038 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate), 1039 RXROT(7)); 1040 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask); 1041 } 1042 } else { 1043 /* 1044 * DIT mode only use TX serializers 1045 * according to the TRM it should be TXROT=0, this one works: 1046 * 16 bit to 23-8 (TXROT=6, rotate 24 bits) 1047 * 24 bit to 23-0 (TXROT=0, rotate 0 bits) 1048 * 1049 * TXROT = 0 only works with 24bit samples 1050 */ 1051 tx_rotate = (sample_width / 4 + 2) & 0x7; 1052 1053 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate), 1054 TXROT(7)); 1055 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(15), 1056 TXSSZ(0x0F)); 1057 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask); 1058 } 1059 1060 return 0; 1061 } 1062 1063 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream, 1064 int period_words, int channels) 1065 { 1066 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream]; 1067 int i; 1068 u8 tx_ser = 0; 1069 u8 rx_ser = 0; 1070 int slots; 1071 u8 max_active_serializers, max_rx_serializers, max_tx_serializers; 1072 int active_serializers, numevt; 1073 u32 reg; 1074 1075 slots = mcasp_get_tdm_slots(mcasp, stream); 1076 1077 /* In DIT mode we only allow maximum of one serializers for now */ 1078 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1079 max_active_serializers = 1; 1080 else 1081 max_active_serializers = DIV_ROUND_UP(channels, slots); 1082 1083 /* Default configuration */ 1084 if (mcasp->version < MCASP_VERSION_3) 1085 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 1086 1087 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1088 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 1089 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1090 max_tx_serializers = max_active_serializers; 1091 max_rx_serializers = 1092 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE]; 1093 } else { 1094 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 1095 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS); 1096 max_tx_serializers = 1097 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK]; 1098 max_rx_serializers = max_active_serializers; 1099 } 1100 1101 for (i = 0; i < mcasp->num_serializer; i++) { 1102 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1103 mcasp->serial_dir[i]); 1104 if (mcasp->serial_dir[i] == TX_MODE && 1105 tx_ser < max_tx_serializers) { 1106 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1107 mcasp->dismod, DISMOD_MASK); 1108 set_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1109 tx_ser++; 1110 } else if (mcasp->serial_dir[i] == RX_MODE && 1111 rx_ser < max_rx_serializers) { 1112 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1113 rx_ser++; 1114 } else { 1115 /* Inactive or unused pin, set it to inactive */ 1116 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 1117 SRMOD_INACTIVE, SRMOD_MASK); 1118 /* If unused, set DISMOD for the pin */ 1119 if (mcasp->serial_dir[i] != INACTIVE_MODE) 1120 mcasp_mod_bits(mcasp, 1121 DAVINCI_MCASP_XRSRCTL_REG(i), 1122 mcasp->dismod, DISMOD_MASK); 1123 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir); 1124 } 1125 } 1126 1127 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1128 active_serializers = tx_ser; 1129 numevt = mcasp->txnumevt; 1130 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 1131 } else { 1132 active_serializers = rx_ser; 1133 numevt = mcasp->rxnumevt; 1134 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 1135 } 1136 1137 if (active_serializers < max_active_serializers) { 1138 dev_warn(mcasp->dev, "stream has more channels (%d) than are " 1139 "enabled in mcasp (%d)\n", channels, 1140 active_serializers * slots); 1141 return -EINVAL; 1142 } 1143 1144 /* AFIFO is not in use */ 1145 if (!numevt) { 1146 /* Configure the burst size for platform drivers */ 1147 if (active_serializers > 1) { 1148 /* 1149 * If more than one serializers are in use we have one 1150 * DMA request to provide data for all serializers. 1151 * For example if three serializers are enabled the DMA 1152 * need to transfer three words per DMA request. 1153 */ 1154 dma_data->maxburst = active_serializers; 1155 } else { 1156 dma_data->maxburst = 0; 1157 } 1158 1159 goto out; 1160 } 1161 1162 if (period_words % active_serializers) { 1163 dev_err(mcasp->dev, "Invalid combination of period words and " 1164 "active serializers: %d, %d\n", period_words, 1165 active_serializers); 1166 return -EINVAL; 1167 } 1168 1169 /* 1170 * Calculate the optimal AFIFO depth for platform side: 1171 * The number of words for numevt need to be in steps of active 1172 * serializers. 1173 */ 1174 numevt = (numevt / active_serializers) * active_serializers; 1175 1176 while (period_words % numevt && numevt > 0) 1177 numevt -= active_serializers; 1178 if (numevt <= 0) 1179 numevt = active_serializers; 1180 1181 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK); 1182 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK); 1183 1184 /* Configure the burst size for platform drivers */ 1185 if (numevt == 1) 1186 numevt = 0; 1187 dma_data->maxburst = numevt; 1188 1189 out: 1190 mcasp->active_serializers[stream] = active_serializers; 1191 1192 return 0; 1193 } 1194 1195 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream, 1196 int channels) 1197 { 1198 int i, active_slots; 1199 int total_slots; 1200 int active_serializers; 1201 u32 mask = 0; 1202 u32 busel = 0; 1203 1204 total_slots = mcasp_get_tdm_slots(mcasp, stream); 1205 1206 /* 1207 * If more than one serializer is needed, then use them with 1208 * all the specified tdm_slots. Otherwise, one serializer can 1209 * cope with the transaction using just as many slots as there 1210 * are channels in the stream. 1211 */ 1212 if (mcasp->tdm_mask[stream]) { 1213 active_slots = hweight32(mcasp->tdm_mask[stream]); 1214 active_serializers = DIV_ROUND_UP(channels, active_slots); 1215 if (active_serializers == 1) 1216 active_slots = channels; 1217 for (i = 0; i < total_slots; i++) { 1218 if ((1 << i) & mcasp->tdm_mask[stream]) { 1219 mask |= (1 << i); 1220 if (--active_slots <= 0) 1221 break; 1222 } 1223 } 1224 } else { 1225 active_serializers = DIV_ROUND_UP(channels, total_slots); 1226 if (active_serializers == 1) 1227 active_slots = channels; 1228 else 1229 active_slots = total_slots; 1230 1231 for (i = 0; i < active_slots; i++) 1232 mask |= (1 << i); 1233 } 1234 1235 if (mcasp->async_mode) 1236 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1237 else 1238 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 1239 1240 if (!mcasp->dat_port) 1241 busel = TXSEL; 1242 1243 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 1244 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask); 1245 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD); 1246 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1247 FSXMOD(total_slots), FSXMOD(0x1FF)); 1248 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) { 1249 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask); 1250 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD); 1251 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, 1252 FSRMOD(total_slots), FSRMOD(0x1FF)); 1253 /* 1254 * If McASP is set to be TX/RX synchronous and the playback is 1255 * not running already we need to configure the TX slots in 1256 * order to have correct FSX on the bus 1257 */ 1258 if (mcasp_is_frame_producer(mcasp) && mcasp_is_synchronous(mcasp) && 1259 !mcasp->channels) 1260 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, 1261 FSXMOD(total_slots), FSXMOD(0x1FF)); 1262 } 1263 1264 return 0; 1265 } 1266 1267 /* S/PDIF */ 1268 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp, 1269 unsigned int rate) 1270 { 1271 u8 *cs_bytes = (u8 *)&mcasp->iec958_status; 1272 1273 if (!mcasp->dat_port) 1274 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1275 else 1276 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSEL); 1277 1278 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 1279 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180)); 1280 1281 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, 0xFFFF); 1282 1283 /* Set the TX tdm : for all the slots */ 1284 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 1285 1286 /* Set the TX clock controls : div = 1 and internal */ 1287 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC); 1288 1289 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 1290 1291 /* Set S/PDIF channel status bits */ 1292 cs_bytes[3] &= ~IEC958_AES3_CON_FS; 1293 switch (rate) { 1294 case 22050: 1295 cs_bytes[3] |= IEC958_AES3_CON_FS_22050; 1296 break; 1297 case 24000: 1298 cs_bytes[3] |= IEC958_AES3_CON_FS_24000; 1299 break; 1300 case 32000: 1301 cs_bytes[3] |= IEC958_AES3_CON_FS_32000; 1302 break; 1303 case 44100: 1304 cs_bytes[3] |= IEC958_AES3_CON_FS_44100; 1305 break; 1306 case 48000: 1307 cs_bytes[3] |= IEC958_AES3_CON_FS_48000; 1308 break; 1309 case 88200: 1310 cs_bytes[3] |= IEC958_AES3_CON_FS_88200; 1311 break; 1312 case 96000: 1313 cs_bytes[3] |= IEC958_AES3_CON_FS_96000; 1314 break; 1315 case 176400: 1316 cs_bytes[3] |= IEC958_AES3_CON_FS_176400; 1317 break; 1318 case 192000: 1319 cs_bytes[3] |= IEC958_AES3_CON_FS_192000; 1320 break; 1321 default: 1322 dev_err(mcasp->dev, "unsupported sampling rate: %d\n", rate); 1323 return -EINVAL; 1324 } 1325 1326 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, mcasp->iec958_status); 1327 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, mcasp->iec958_status); 1328 1329 /* Enable the DIT */ 1330 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN); 1331 1332 return 0; 1333 } 1334 1335 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp, 1336 unsigned int sysclk_freq, 1337 unsigned int bclk_freq, 1338 int stream, 1339 bool set) 1340 { 1341 int div = sysclk_freq / bclk_freq; 1342 int rem = sysclk_freq % bclk_freq; 1343 int error_ppm; 1344 int aux_div = 1; 1345 int bclk_div_id, auxclk_div_id; 1346 bool auxclk_enabled; 1347 1348 auxclk_enabled = mcasp_is_auxclk_enabled(mcasp, stream); 1349 1350 if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_CAPTURE) { 1351 bclk_div_id = MCASP_CLKDIV_BCLK_RXONLY; 1352 auxclk_div_id = MCASP_CLKDIV_AUXCLK_RXONLY; 1353 } else if (mcasp->async_mode && stream == SNDRV_PCM_STREAM_PLAYBACK) { 1354 bclk_div_id = MCASP_CLKDIV_BCLK_TXONLY; 1355 auxclk_div_id = MCASP_CLKDIV_AUXCLK_TXONLY; 1356 } else { 1357 bclk_div_id = MCASP_CLKDIV_BCLK; 1358 auxclk_div_id = MCASP_CLKDIV_AUXCLK; 1359 } 1360 1361 if (div > (ACLKXDIV_MASK + 1) && auxclk_enabled) { 1362 if (div <= (AHCLKXDIV_MASK + 1)) { 1363 /* aux_div absorbs entire division; bclk_div = 1 */ 1364 aux_div = div; 1365 if ((div + 1) <= (AHCLKXDIV_MASK + 1)) { 1366 unsigned int err_lo = sysclk_freq / div - 1367 bclk_freq; 1368 unsigned int err_hi = bclk_freq - 1369 sysclk_freq / (div + 1); 1370 1371 if (err_hi < err_lo) 1372 aux_div = div + 1; 1373 } 1374 } else { 1375 aux_div = DIV_ROUND_UP(div, ACLKXDIV_MASK + 1); 1376 } 1377 1378 sysclk_freq /= aux_div; 1379 div = sysclk_freq / bclk_freq; 1380 rem = sysclk_freq % bclk_freq; 1381 } else if (div > (ACLKXDIV_MASK + 1) && set) { 1382 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n", 1383 sysclk_freq); 1384 } 1385 1386 if (rem != 0) { 1387 if (div == 0 || 1388 ((sysclk_freq / div) - bclk_freq) > 1389 (bclk_freq - (sysclk_freq / (div+1)))) { 1390 div++; 1391 rem = rem - bclk_freq; 1392 } 1393 } 1394 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem, 1395 (int)bclk_freq)) / div - 1000000; 1396 1397 if (set) { 1398 if (error_ppm) 1399 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n", 1400 error_ppm); 1401 1402 __davinci_mcasp_set_clkdiv(mcasp, bclk_div_id, div, false); 1403 if (auxclk_enabled) 1404 __davinci_mcasp_set_clkdiv(mcasp, auxclk_div_id, 1405 aux_div, false); 1406 } 1407 1408 return error_ppm; 1409 } 1410 1411 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp) 1412 { 1413 if (!mcasp->txnumevt) 1414 return 0; 1415 1416 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET); 1417 } 1418 1419 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp) 1420 { 1421 if (!mcasp->rxnumevt) 1422 return 0; 1423 1424 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET); 1425 } 1426 1427 static snd_pcm_sframes_t davinci_mcasp_delay( 1428 struct snd_pcm_substream *substream, 1429 struct snd_soc_dai *cpu_dai) 1430 { 1431 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1432 u32 fifo_use; 1433 1434 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1435 fifo_use = davinci_mcasp_tx_delay(mcasp); 1436 else 1437 fifo_use = davinci_mcasp_rx_delay(mcasp); 1438 1439 /* 1440 * Divide the used locations with the channel count to get the 1441 * FIFO usage in samples (don't care about partial samples in the 1442 * buffer). 1443 */ 1444 return fifo_use / substream->runtime->channels; 1445 } 1446 1447 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 1448 struct snd_pcm_hw_params *params, 1449 struct snd_soc_dai *cpu_dai) 1450 { 1451 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1452 int word_length; 1453 int channels = params_channels(params); 1454 int period_size = params_period_size(params); 1455 int ret; 1456 unsigned int sysclk_freq = mcasp_get_sysclk_freq(mcasp, substream->stream); 1457 1458 switch (params_format(params)) { 1459 case SNDRV_PCM_FORMAT_U8: 1460 case SNDRV_PCM_FORMAT_S8: 1461 word_length = 8; 1462 break; 1463 1464 case SNDRV_PCM_FORMAT_U16_LE: 1465 case SNDRV_PCM_FORMAT_S16_LE: 1466 word_length = 16; 1467 break; 1468 1469 case SNDRV_PCM_FORMAT_U24_3LE: 1470 case SNDRV_PCM_FORMAT_S24_3LE: 1471 word_length = 24; 1472 break; 1473 1474 case SNDRV_PCM_FORMAT_U24_LE: 1475 case SNDRV_PCM_FORMAT_S24_LE: 1476 word_length = 24; 1477 break; 1478 1479 case SNDRV_PCM_FORMAT_U32_LE: 1480 case SNDRV_PCM_FORMAT_S32_LE: 1481 word_length = 32; 1482 break; 1483 1484 default: 1485 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format"); 1486 return -EINVAL; 1487 } 1488 1489 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt); 1490 if (ret) 1491 return ret; 1492 1493 /* 1494 * If mcasp is BCLK master, and a BCLK divider was not provided by 1495 * the machine driver, we need to calculate the ratio. 1496 */ 1497 if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 && 1498 sysclk_freq) { 1499 int slots, slot_width; 1500 int rate = params_rate(params); 1501 int sbits = params_width(params); 1502 unsigned int bclk_target; 1503 1504 slots = mcasp_get_tdm_slots(mcasp, substream->stream); 1505 1506 slot_width = mcasp_get_slot_width(mcasp, substream->stream); 1507 if (slot_width) 1508 sbits = slot_width; 1509 1510 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 1511 bclk_target = rate * sbits * slots; 1512 else 1513 bclk_target = rate * 128; 1514 1515 davinci_mcasp_calc_clk_div(mcasp, sysclk_freq, 1516 bclk_target, substream->stream, true); 1517 } 1518 1519 ret = mcasp_common_hw_param(mcasp, substream->stream, 1520 period_size * channels, channels); 1521 if (ret) 1522 return ret; 1523 1524 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1525 ret = mcasp_dit_hw_param(mcasp, params_rate(params)); 1526 else 1527 ret = mcasp_i2s_hw_param(mcasp, substream->stream, 1528 channels); 1529 1530 if (ret) 1531 return ret; 1532 1533 davinci_config_channel_size(mcasp, word_length, substream->stream); 1534 1535 /* Channel constraints are disabled for async mode */ 1536 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE && !mcasp->async_mode) { 1537 mcasp->channels = channels; 1538 if (!mcasp->max_format_width) 1539 mcasp->max_format_width = word_length; 1540 } 1541 1542 return 0; 1543 } 1544 1545 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 1546 int cmd, struct snd_soc_dai *cpu_dai) 1547 { 1548 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1549 int ret = 0; 1550 1551 switch (cmd) { 1552 case SNDRV_PCM_TRIGGER_RESUME: 1553 case SNDRV_PCM_TRIGGER_START: 1554 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1555 davinci_mcasp_start(mcasp, substream->stream); 1556 break; 1557 case SNDRV_PCM_TRIGGER_SUSPEND: 1558 case SNDRV_PCM_TRIGGER_STOP: 1559 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1560 davinci_mcasp_stop(mcasp, substream->stream); 1561 break; 1562 1563 default: 1564 ret = -EINVAL; 1565 } 1566 1567 return ret; 1568 } 1569 1570 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params, 1571 struct snd_pcm_hw_rule *rule) 1572 { 1573 struct davinci_mcasp_ruledata *rd = rule->private; 1574 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1575 struct snd_mask nfmt; 1576 int slot_width; 1577 snd_pcm_format_t i; 1578 1579 snd_mask_none(&nfmt); 1580 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1581 1582 pcm_for_each_format(i) { 1583 if (snd_mask_test_format(fmt, i)) { 1584 if (snd_pcm_format_width(i) <= slot_width) { 1585 snd_mask_set_format(&nfmt, i); 1586 } 1587 } 1588 } 1589 1590 return snd_mask_refine(fmt, &nfmt); 1591 } 1592 1593 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params, 1594 struct snd_pcm_hw_rule *rule) 1595 { 1596 struct davinci_mcasp_ruledata *rd = rule->private; 1597 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1598 struct snd_mask nfmt; 1599 int format_width; 1600 snd_pcm_format_t i; 1601 1602 snd_mask_none(&nfmt); 1603 format_width = rd->mcasp->max_format_width; 1604 1605 pcm_for_each_format(i) { 1606 if (snd_mask_test_format(fmt, i)) { 1607 if (snd_pcm_format_width(i) == format_width) { 1608 snd_mask_set_format(&nfmt, i); 1609 } 1610 } 1611 } 1612 1613 return snd_mask_refine(fmt, &nfmt); 1614 } 1615 1616 static const unsigned int davinci_mcasp_dai_rates[] = { 1617 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000, 1618 88200, 96000, 176400, 192000, 1619 }; 1620 1621 #define DAVINCI_MAX_RATE_ERROR_PPM 1000 1622 1623 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params, 1624 struct snd_pcm_hw_rule *rule) 1625 { 1626 struct davinci_mcasp_ruledata *rd = rule->private; 1627 struct snd_interval *ri = 1628 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 1629 int sbits = params_width(params); 1630 int slots, slot_width; 1631 struct snd_interval range; 1632 int i; 1633 1634 slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream); 1635 1636 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1637 if (slot_width) 1638 sbits = slot_width; 1639 1640 snd_interval_any(&range); 1641 range.empty = 1; 1642 1643 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) { 1644 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) { 1645 uint bclk_freq = sbits * slots * 1646 davinci_mcasp_dai_rates[i]; 1647 unsigned int sysclk_freq; 1648 unsigned int ratio; 1649 int ppm; 1650 1651 ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream); 1652 if (ratio) 1653 sysclk_freq = davinci_mcasp_dai_rates[i] * ratio; 1654 else 1655 sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream); 1656 1657 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1658 bclk_freq, rd->stream, false); 1659 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1660 if (range.empty) { 1661 range.min = davinci_mcasp_dai_rates[i]; 1662 range.empty = 0; 1663 } 1664 range.max = davinci_mcasp_dai_rates[i]; 1665 } 1666 } 1667 } 1668 1669 dev_dbg(rd->mcasp->dev, 1670 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n", 1671 ri->min, ri->max, range.min, range.max, sbits, slots); 1672 1673 return snd_interval_refine(hw_param_interval(params, rule->var), 1674 &range); 1675 } 1676 1677 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params, 1678 struct snd_pcm_hw_rule *rule) 1679 { 1680 struct davinci_mcasp_ruledata *rd = rule->private; 1681 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT); 1682 struct snd_mask nfmt; 1683 int rate = params_rate(params); 1684 int slots; 1685 int count = 0; 1686 snd_pcm_format_t i; 1687 1688 slots = mcasp_get_tdm_slots(rd->mcasp, rd->stream); 1689 1690 snd_mask_none(&nfmt); 1691 1692 pcm_for_each_format(i) { 1693 if (snd_mask_test_format(fmt, i)) { 1694 uint sbits = snd_pcm_format_width(i); 1695 unsigned int sysclk_freq; 1696 unsigned int ratio; 1697 int ppm, slot_width; 1698 1699 ratio = mcasp_get_auxclk_fs_ratio(rd->mcasp, rd->stream); 1700 if (ratio) 1701 sysclk_freq = rate * ratio; 1702 else 1703 sysclk_freq = mcasp_get_sysclk_freq(rd->mcasp, rd->stream); 1704 1705 slot_width = mcasp_get_slot_width(rd->mcasp, rd->stream); 1706 if (slot_width) 1707 sbits = slot_width; 1708 1709 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq, 1710 sbits * slots * rate, 1711 rd->stream, false); 1712 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) { 1713 snd_mask_set_format(&nfmt, i); 1714 count++; 1715 } 1716 } 1717 } 1718 dev_dbg(rd->mcasp->dev, 1719 "%d possible sample format for %d Hz and %d tdm slots\n", 1720 count, rate, slots); 1721 1722 return snd_mask_refine(fmt, &nfmt); 1723 } 1724 1725 static int davinci_mcasp_hw_rule_min_periodsize( 1726 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule) 1727 { 1728 struct snd_interval *period_size = hw_param_interval(params, 1729 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 1730 u8 numevt = *((u8 *)rule->private); 1731 struct snd_interval frames; 1732 1733 snd_interval_any(&frames); 1734 frames.min = numevt; 1735 frames.integer = 1; 1736 1737 return snd_interval_refine(period_size, &frames); 1738 } 1739 1740 static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 1741 struct snd_soc_dai *cpu_dai) 1742 { 1743 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1744 struct davinci_mcasp_ruledata *ruledata = 1745 &mcasp->ruledata[substream->stream]; 1746 u32 max_channels = 0; 1747 int i, dir, ret; 1748 int tdm_slots; 1749 u8 *numevt; 1750 1751 /* Do not allow more then one stream per direction */ 1752 if (mcasp->substreams[substream->stream]) 1753 return -EBUSY; 1754 1755 mcasp->substreams[substream->stream] = substream; 1756 1757 tdm_slots = mcasp_get_tdm_slots(mcasp, substream->stream); 1758 1759 if (mcasp->tdm_mask[substream->stream]) 1760 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]); 1761 1762 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1763 return 0; 1764 1765 /* 1766 * Limit the maximum allowed channels for the first stream: 1767 * number of serializers for the direction * tdm slots per serializer 1768 */ 1769 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 1770 dir = TX_MODE; 1771 else 1772 dir = RX_MODE; 1773 1774 for (i = 0; i < mcasp->num_serializer; i++) { 1775 if (mcasp->serial_dir[i] == dir) 1776 max_channels++; 1777 } 1778 ruledata->serializers = max_channels; 1779 ruledata->mcasp = mcasp; 1780 ruledata->stream = substream->stream; 1781 max_channels *= tdm_slots; 1782 /* 1783 * If the already active stream has less channels than the calculated 1784 * limit based on the seirializers * tdm_slots, and only one serializer 1785 * is in use we need to use that as a constraint for the second stream. 1786 * Otherwise (first stream or less allowed channels or more than one 1787 * serializer in use) we use the calculated constraint. 1788 * 1789 * However, in async mode, TX and RX have independent clocks and can 1790 * use different configurations, so don't apply the constraint. 1791 */ 1792 if (mcasp->channels && mcasp->channels < max_channels && 1793 ruledata->serializers == 1 && 1794 !mcasp->async_mode) 1795 max_channels = mcasp->channels; 1796 /* 1797 * But we can always allow channels upto the amount of 1798 * the available tdm_slots. 1799 */ 1800 if (max_channels < tdm_slots) 1801 max_channels = tdm_slots; 1802 1803 snd_pcm_hw_constraint_minmax(substream->runtime, 1804 SNDRV_PCM_HW_PARAM_CHANNELS, 1805 0, max_channels); 1806 1807 snd_pcm_hw_constraint_list(substream->runtime, 1808 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1809 &mcasp->chconstr[substream->stream]); 1810 1811 if (mcasp->max_format_width && !mcasp->async_mode) { 1812 /* 1813 * Only allow formats which require same amount of bits on the 1814 * bus as the currently running stream to ensure sync mode 1815 */ 1816 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1817 SNDRV_PCM_HW_PARAM_FORMAT, 1818 davinci_mcasp_hw_rule_format_width, 1819 ruledata, 1820 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1821 if (ret) 1822 return ret; 1823 } else if (mcasp_get_slot_width(mcasp, substream->stream)) { 1824 /* Only allow formats require <= slot_width bits on the bus */ 1825 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1826 SNDRV_PCM_HW_PARAM_FORMAT, 1827 davinci_mcasp_hw_rule_slot_width, 1828 ruledata, 1829 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1830 if (ret) 1831 return ret; 1832 } 1833 1834 /* 1835 * If we rely on implicit BCLK divider setting we should 1836 * set constraints based on what we can provide. 1837 */ 1838 if (mcasp->bclk_master && mcasp_get_bclk_div(mcasp, substream->stream) == 0 && 1839 mcasp_get_sysclk_freq(mcasp, substream->stream)) { 1840 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1841 SNDRV_PCM_HW_PARAM_RATE, 1842 davinci_mcasp_hw_rule_rate, 1843 ruledata, 1844 SNDRV_PCM_HW_PARAM_FORMAT, -1); 1845 if (ret) 1846 return ret; 1847 ret = snd_pcm_hw_rule_add(substream->runtime, 0, 1848 SNDRV_PCM_HW_PARAM_FORMAT, 1849 davinci_mcasp_hw_rule_format, 1850 ruledata, 1851 SNDRV_PCM_HW_PARAM_RATE, -1); 1852 if (ret) 1853 return ret; 1854 } 1855 1856 numevt = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? 1857 &mcasp->txnumevt : 1858 &mcasp->rxnumevt; 1859 snd_pcm_hw_rule_add(substream->runtime, 0, 1860 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 1861 davinci_mcasp_hw_rule_min_periodsize, numevt, 1862 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1); 1863 1864 return 0; 1865 } 1866 1867 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream, 1868 struct snd_soc_dai *cpu_dai) 1869 { 1870 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1871 1872 mcasp->substreams[substream->stream] = NULL; 1873 mcasp->active_serializers[substream->stream] = 0; 1874 1875 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) 1876 return; 1877 1878 if (!snd_soc_dai_active(cpu_dai)) { 1879 mcasp->channels = 0; 1880 mcasp->max_format_width = 0; 1881 } 1882 } 1883 1884 static int davinci_mcasp_iec958_info(struct snd_kcontrol *kcontrol, 1885 struct snd_ctl_elem_info *uinfo) 1886 { 1887 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1888 uinfo->count = 1; 1889 1890 return 0; 1891 } 1892 1893 static int davinci_mcasp_iec958_get(struct snd_kcontrol *kcontrol, 1894 struct snd_ctl_elem_value *uctl) 1895 { 1896 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1897 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1898 1899 memcpy(uctl->value.iec958.status, &mcasp->iec958_status, 1900 sizeof(mcasp->iec958_status)); 1901 1902 return 0; 1903 } 1904 1905 static int davinci_mcasp_iec958_put(struct snd_kcontrol *kcontrol, 1906 struct snd_ctl_elem_value *uctl) 1907 { 1908 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1909 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1910 1911 memcpy(&mcasp->iec958_status, uctl->value.iec958.status, 1912 sizeof(mcasp->iec958_status)); 1913 1914 return 0; 1915 } 1916 1917 static int davinci_mcasp_iec958_con_mask_get(struct snd_kcontrol *kcontrol, 1918 struct snd_ctl_elem_value *ucontrol) 1919 { 1920 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol); 1921 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai); 1922 1923 memset(ucontrol->value.iec958.status, 0xff, sizeof(mcasp->iec958_status)); 1924 return 0; 1925 } 1926 1927 static const struct snd_kcontrol_new davinci_mcasp_iec958_ctls[] = { 1928 { 1929 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 1930 SNDRV_CTL_ELEM_ACCESS_VOLATILE), 1931 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1932 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1933 .info = davinci_mcasp_iec958_info, 1934 .get = davinci_mcasp_iec958_get, 1935 .put = davinci_mcasp_iec958_put, 1936 }, { 1937 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1938 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1939 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1940 .info = davinci_mcasp_iec958_info, 1941 .get = davinci_mcasp_iec958_con_mask_get, 1942 }, 1943 }; 1944 1945 static void davinci_mcasp_init_iec958_status(struct davinci_mcasp *mcasp) 1946 { 1947 unsigned char *cs = (u8 *)&mcasp->iec958_status; 1948 1949 cs[0] = IEC958_AES0_CON_NOT_COPYRIGHT | IEC958_AES0_CON_EMPHASIS_NONE; 1950 cs[1] = IEC958_AES1_CON_PCM_CODER; 1951 cs[2] = IEC958_AES2_CON_SOURCE_UNSPEC | IEC958_AES2_CON_CHANNEL_UNSPEC; 1952 cs[3] = IEC958_AES3_CON_CLOCK_1000PPM; 1953 } 1954 1955 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai) 1956 { 1957 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai); 1958 int stream; 1959 1960 for_each_pcm_streams(stream) 1961 snd_soc_dai_dma_data_set(dai, stream, &mcasp->dma_data[stream]); 1962 1963 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE) { 1964 davinci_mcasp_init_iec958_status(mcasp); 1965 snd_soc_add_dai_controls(dai, davinci_mcasp_iec958_ctls, 1966 ARRAY_SIZE(davinci_mcasp_iec958_ctls)); 1967 } 1968 1969 return 0; 1970 } 1971 1972 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = { 1973 .probe = davinci_mcasp_dai_probe, 1974 .startup = davinci_mcasp_startup, 1975 .shutdown = davinci_mcasp_shutdown, 1976 .trigger = davinci_mcasp_trigger, 1977 .delay = davinci_mcasp_delay, 1978 .hw_params = davinci_mcasp_hw_params, 1979 .set_fmt = davinci_mcasp_set_dai_fmt, 1980 .set_clkdiv = davinci_mcasp_set_clkdiv, 1981 .set_sysclk = davinci_mcasp_set_sysclk, 1982 .set_tdm_slot = davinci_mcasp_set_tdm_slot, 1983 }; 1984 1985 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000 1986 1987 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \ 1988 SNDRV_PCM_FMTBIT_U8 | \ 1989 SNDRV_PCM_FMTBIT_S16_LE | \ 1990 SNDRV_PCM_FMTBIT_U16_LE | \ 1991 SNDRV_PCM_FMTBIT_S24_LE | \ 1992 SNDRV_PCM_FMTBIT_U24_LE | \ 1993 SNDRV_PCM_FMTBIT_S24_3LE | \ 1994 SNDRV_PCM_FMTBIT_U24_3LE | \ 1995 SNDRV_PCM_FMTBIT_S32_LE | \ 1996 SNDRV_PCM_FMTBIT_U32_LE) 1997 1998 static struct snd_soc_dai_driver davinci_mcasp_dai[] = { 1999 { 2000 .name = "davinci-mcasp.0", 2001 .playback = { 2002 .stream_name = "IIS Playback", 2003 .channels_min = 1, 2004 .channels_max = 32 * 16, 2005 .rates = DAVINCI_MCASP_RATES, 2006 .formats = DAVINCI_MCASP_PCM_FMTS, 2007 }, 2008 .capture = { 2009 .stream_name = "IIS Capture", 2010 .channels_min = 1, 2011 .channels_max = 32 * 16, 2012 .rates = DAVINCI_MCASP_RATES, 2013 .formats = DAVINCI_MCASP_PCM_FMTS, 2014 }, 2015 .ops = &davinci_mcasp_dai_ops, 2016 }, 2017 { 2018 .name = "davinci-mcasp.1", 2019 .playback = { 2020 .stream_name = "DIT Playback", 2021 .channels_min = 1, 2022 .channels_max = 384, 2023 .rates = DAVINCI_MCASP_RATES, 2024 .formats = SNDRV_PCM_FMTBIT_S16_LE | 2025 SNDRV_PCM_FMTBIT_S24_LE, 2026 }, 2027 .ops = &davinci_mcasp_dai_ops, 2028 }, 2029 2030 }; 2031 2032 static const struct snd_soc_component_driver davinci_mcasp_component = { 2033 .name = "davinci-mcasp", 2034 .legacy_dai_naming = 1, 2035 }; 2036 2037 /* Some HW specific values and defaults. The rest is filled in from DT. */ 2038 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = { 2039 .tx_dma_offset = 0x400, 2040 .rx_dma_offset = 0x400, 2041 .version = MCASP_VERSION_1, 2042 }; 2043 2044 static struct davinci_mcasp_pdata da830_mcasp_pdata = { 2045 .tx_dma_offset = 0x2000, 2046 .rx_dma_offset = 0x2000, 2047 .version = MCASP_VERSION_2, 2048 }; 2049 2050 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = { 2051 .tx_dma_offset = 0, 2052 .rx_dma_offset = 0, 2053 .version = MCASP_VERSION_3, 2054 }; 2055 2056 static struct davinci_mcasp_pdata dra7_mcasp_pdata = { 2057 /* The CFG port offset will be calculated if it is needed */ 2058 .tx_dma_offset = 0, 2059 .rx_dma_offset = 0, 2060 .version = MCASP_VERSION_4, 2061 }; 2062 2063 static struct davinci_mcasp_pdata omap_mcasp_pdata = { 2064 .tx_dma_offset = 0x200, 2065 .rx_dma_offset = 0, 2066 .version = MCASP_VERSION_OMAP, 2067 }; 2068 2069 static const struct of_device_id mcasp_dt_ids[] = { 2070 { 2071 .compatible = "ti,dm646x-mcasp-audio", 2072 .data = &dm646x_mcasp_pdata, 2073 }, 2074 { 2075 .compatible = "ti,da830-mcasp-audio", 2076 .data = &da830_mcasp_pdata, 2077 }, 2078 { 2079 .compatible = "ti,am33xx-mcasp-audio", 2080 .data = &am33xx_mcasp_pdata, 2081 }, 2082 { 2083 .compatible = "ti,dra7-mcasp-audio", 2084 .data = &dra7_mcasp_pdata, 2085 }, 2086 { 2087 .compatible = "ti,omap4-mcasp-audio", 2088 .data = &omap_mcasp_pdata, 2089 }, 2090 { /* sentinel */ } 2091 }; 2092 MODULE_DEVICE_TABLE(of, mcasp_dt_ids); 2093 2094 static int mcasp_reparent_fck(struct platform_device *pdev) 2095 { 2096 struct device_node *node = pdev->dev.of_node; 2097 struct clk *gfclk, *parent_clk; 2098 const char *parent_name; 2099 int ret; 2100 2101 if (!node) 2102 return 0; 2103 2104 parent_name = of_get_property(node, "fck_parent", NULL); 2105 if (!parent_name) 2106 return 0; 2107 2108 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n"); 2109 2110 gfclk = clk_get(&pdev->dev, "fck"); 2111 if (IS_ERR(gfclk)) { 2112 dev_err(&pdev->dev, "failed to get fck\n"); 2113 return PTR_ERR(gfclk); 2114 } 2115 2116 parent_clk = clk_get(NULL, parent_name); 2117 if (IS_ERR(parent_clk)) { 2118 dev_err(&pdev->dev, "failed to get parent clock\n"); 2119 ret = PTR_ERR(parent_clk); 2120 goto err1; 2121 } 2122 2123 ret = clk_set_parent(gfclk, parent_clk); 2124 if (ret) { 2125 dev_err(&pdev->dev, "failed to reparent fck\n"); 2126 goto err2; 2127 } 2128 2129 err2: 2130 clk_put(parent_clk); 2131 err1: 2132 clk_put(gfclk); 2133 return ret; 2134 } 2135 2136 static bool davinci_mcasp_have_gpiochip(struct davinci_mcasp *mcasp) 2137 { 2138 return device_property_present(mcasp->dev, "gpio-controller"); 2139 } 2140 2141 static int davinci_mcasp_get_config(struct davinci_mcasp *mcasp, 2142 struct platform_device *pdev) 2143 { 2144 struct device_node *np = pdev->dev.of_node; 2145 struct davinci_mcasp_pdata *pdata = NULL; 2146 const struct davinci_mcasp_pdata *match_pdata = 2147 device_get_match_data(&pdev->dev); 2148 const u32 *of_serial_dir32; 2149 u32 val; 2150 int i; 2151 2152 if (pdev->dev.platform_data) { 2153 pdata = pdev->dev.platform_data; 2154 pdata->dismod = DISMOD_LOW; 2155 goto out; 2156 } else if (match_pdata) { 2157 pdata = devm_kmemdup(&pdev->dev, match_pdata, sizeof(*pdata), 2158 GFP_KERNEL); 2159 if (!pdata) 2160 return -ENOMEM; 2161 } else { 2162 dev_err(&pdev->dev, "No compatible match found\n"); 2163 return -EINVAL; 2164 } 2165 2166 if (of_property_read_u32(np, "op-mode", &val) == 0) { 2167 pdata->op_mode = val; 2168 } else { 2169 mcasp->missing_audio_param = true; 2170 goto out; 2171 } 2172 2173 /* Parse TX-specific TDM slot and use it as default for RX */ 2174 if (of_property_read_u32(np, "tdm-slots", &val) == 0) { 2175 if (val < 2 || val > 32) { 2176 dev_err(&pdev->dev, "tdm-slots must be in range [2-32]\n"); 2177 return -EINVAL; 2178 } 2179 2180 pdata->tdm_slots_tx = val; 2181 pdata->tdm_slots_rx = val; 2182 } else if (pdata->op_mode == DAVINCI_MCASP_IIS_MODE) { 2183 mcasp->missing_audio_param = true; 2184 goto out; 2185 } 2186 2187 /* Parse RX-specific TDM slot count if provided */ 2188 if (of_property_read_u32(np, "tdm-slots-rx", &val) == 0) { 2189 if (val < 2 || val > 32) { 2190 dev_err(&pdev->dev, "tdm-slots-rx must be in range [2-32]\n"); 2191 return -EINVAL; 2192 } 2193 2194 pdata->tdm_slots_rx = val; 2195 } 2196 2197 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) 2198 mcasp->async_mode = of_property_read_bool(np, "ti,async-mode"); 2199 2200 of_serial_dir32 = of_get_property(np, "serial-dir", &val); 2201 val /= sizeof(u32); 2202 if (of_serial_dir32) { 2203 u8 *of_serial_dir = devm_kzalloc(&pdev->dev, 2204 (sizeof(*of_serial_dir) * val), 2205 GFP_KERNEL); 2206 if (!of_serial_dir) 2207 return -ENOMEM; 2208 2209 for (i = 0; i < val; i++) 2210 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]); 2211 2212 pdata->num_serializer = val; 2213 pdata->serial_dir = of_serial_dir; 2214 } else { 2215 mcasp->missing_audio_param = true; 2216 goto out; 2217 } 2218 2219 if (of_property_read_u32(np, "tx-num-evt", &val) == 0) 2220 pdata->txnumevt = val; 2221 2222 if (of_property_read_u32(np, "rx-num-evt", &val) == 0) 2223 pdata->rxnumevt = val; 2224 2225 /* Parse TX-specific auxclk/fs ratio and use it as default for RX */ 2226 if (of_property_read_u32(np, "auxclk-fs-ratio", &val) == 0) { 2227 mcasp->auxclk_fs_ratio_tx = val; 2228 mcasp->auxclk_fs_ratio_rx = val; 2229 } 2230 2231 /* Parse RX-specific auxclk/fs ratio if provided */ 2232 if (of_property_read_u32(np, "auxclk-fs-ratio-rx", &val) == 0) 2233 mcasp->auxclk_fs_ratio_rx = val; 2234 2235 if (of_property_read_u32(np, "dismod", &val) == 0) { 2236 if (val == 0 || val == 2 || val == 3) { 2237 pdata->dismod = DISMOD_VAL(val); 2238 } else { 2239 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val); 2240 pdata->dismod = DISMOD_LOW; 2241 } 2242 } else { 2243 pdata->dismod = DISMOD_LOW; 2244 } 2245 2246 out: 2247 mcasp->pdata = pdata; 2248 2249 if (mcasp->missing_audio_param) { 2250 if (davinci_mcasp_have_gpiochip(mcasp)) { 2251 dev_dbg(&pdev->dev, "Missing DT parameter(s) for audio\n"); 2252 return 0; 2253 } 2254 2255 dev_err(&pdev->dev, "Insufficient DT parameter(s)\n"); 2256 return -ENODEV; 2257 } 2258 2259 mcasp->op_mode = pdata->op_mode; 2260 /* sanity check for tdm slots parameter */ 2261 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) { 2262 if (pdata->tdm_slots_tx < 2) { 2263 dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n", 2264 pdata->tdm_slots_tx); 2265 mcasp->tdm_slots_tx = 2; 2266 } else if (pdata->tdm_slots_tx > 32) { 2267 dev_warn(&pdev->dev, "invalid tdm tx slots: %d\n", 2268 pdata->tdm_slots_tx); 2269 mcasp->tdm_slots_tx = 32; 2270 } else { 2271 mcasp->tdm_slots_tx = pdata->tdm_slots_tx; 2272 } 2273 2274 if (pdata->tdm_slots_rx < 2) { 2275 dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n", 2276 pdata->tdm_slots_rx); 2277 mcasp->tdm_slots_rx = 2; 2278 } else if (pdata->tdm_slots_rx > 32) { 2279 dev_warn(&pdev->dev, "invalid tdm rx slots: %d\n", 2280 pdata->tdm_slots_rx); 2281 mcasp->tdm_slots_rx = 32; 2282 } else { 2283 mcasp->tdm_slots_rx = pdata->tdm_slots_rx; 2284 } 2285 } else { 2286 mcasp->tdm_slots_tx = 32; 2287 mcasp->tdm_slots_rx = 32; 2288 } 2289 2290 /* Different TX/RX slot counts require async mode */ 2291 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE && 2292 mcasp->tdm_slots_tx != mcasp->tdm_slots_rx && !mcasp->async_mode) { 2293 dev_err(&pdev->dev, 2294 "Different TX (%d) and RX (%d) TDM slots require ti,async-mode\n", 2295 mcasp->tdm_slots_tx, mcasp->tdm_slots_rx); 2296 return -EINVAL; 2297 } 2298 2299 /* Different TX/RX auxclk-fs-ratio require async mode */ 2300 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE && 2301 mcasp->auxclk_fs_ratio_tx && mcasp->auxclk_fs_ratio_rx && 2302 mcasp->auxclk_fs_ratio_tx != mcasp->auxclk_fs_ratio_rx && !mcasp->async_mode) { 2303 dev_err(&pdev->dev, 2304 "Different TX (%d) and RX (%d) auxclk-fs-ratio require ti,async-mode\n", 2305 mcasp->auxclk_fs_ratio_tx, mcasp->auxclk_fs_ratio_rx); 2306 return -EINVAL; 2307 } 2308 2309 mcasp->num_serializer = pdata->num_serializer; 2310 #ifdef CONFIG_PM 2311 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev, 2312 mcasp->num_serializer, sizeof(u32), 2313 GFP_KERNEL); 2314 if (!mcasp->context.xrsr_regs) 2315 return -ENOMEM; 2316 #endif 2317 mcasp->serial_dir = pdata->serial_dir; 2318 mcasp->version = pdata->version; 2319 mcasp->txnumevt = pdata->txnumevt; 2320 mcasp->rxnumevt = pdata->rxnumevt; 2321 mcasp->dismod = pdata->dismod; 2322 2323 return 0; 2324 } 2325 2326 enum { 2327 PCM_EDMA, 2328 PCM_SDMA, 2329 PCM_UDMA, 2330 }; 2331 static const char *sdma_prefix = "ti,omap"; 2332 2333 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp) 2334 { 2335 struct dma_chan *chan; 2336 const char *tmp; 2337 int ret = PCM_EDMA; 2338 2339 if (!mcasp->dev->of_node) 2340 return PCM_EDMA; 2341 2342 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data; 2343 chan = dma_request_chan(mcasp->dev, tmp); 2344 if (IS_ERR(chan)) 2345 return dev_err_probe(mcasp->dev, PTR_ERR(chan), 2346 "Can't verify DMA configuration\n"); 2347 if (WARN_ON(!chan->device || !chan->device->dev)) { 2348 dma_release_channel(chan); 2349 return -EINVAL; 2350 } 2351 2352 if (chan->device->dev->of_node) 2353 ret = of_property_read_string(chan->device->dev->of_node, 2354 "compatible", &tmp); 2355 else 2356 dev_dbg(mcasp->dev, "DMA controller has no of-node\n"); 2357 2358 dma_release_channel(chan); 2359 if (ret) 2360 return ret; 2361 2362 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp); 2363 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix))) 2364 return PCM_SDMA; 2365 else if (strstr(tmp, "udmap")) 2366 return PCM_UDMA; 2367 else if (strstr(tmp, "bcdma")) 2368 return PCM_UDMA; 2369 2370 return PCM_EDMA; 2371 } 2372 2373 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata) 2374 { 2375 int i; 2376 u32 offset = 0; 2377 2378 if (pdata->version != MCASP_VERSION_4) 2379 return pdata->tx_dma_offset; 2380 2381 for (i = 0; i < pdata->num_serializer; i++) { 2382 if (pdata->serial_dir[i] == TX_MODE) { 2383 if (!offset) { 2384 offset = DAVINCI_MCASP_TXBUF_REG(i); 2385 } else { 2386 pr_err("%s: Only one serializer allowed!\n", 2387 __func__); 2388 break; 2389 } 2390 } 2391 } 2392 2393 return offset; 2394 } 2395 2396 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata) 2397 { 2398 int i; 2399 u32 offset = 0; 2400 2401 if (pdata->version != MCASP_VERSION_4) 2402 return pdata->rx_dma_offset; 2403 2404 for (i = 0; i < pdata->num_serializer; i++) { 2405 if (pdata->serial_dir[i] == RX_MODE) { 2406 if (!offset) { 2407 offset = DAVINCI_MCASP_RXBUF_REG(i); 2408 } else { 2409 pr_err("%s: Only one serializer allowed!\n", 2410 __func__); 2411 break; 2412 } 2413 } 2414 } 2415 2416 return offset; 2417 } 2418 2419 #ifdef CONFIG_GPIOLIB 2420 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset) 2421 { 2422 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2423 2424 if (mcasp->num_serializer && offset < mcasp->num_serializer && 2425 mcasp->serial_dir[offset] != INACTIVE_MODE) { 2426 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset); 2427 return -EBUSY; 2428 } 2429 2430 /* Do not change the PIN yet */ 2431 return pm_runtime_resume_and_get(mcasp->dev); 2432 } 2433 2434 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset) 2435 { 2436 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2437 2438 /* Set the direction to input */ 2439 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2440 2441 /* Set the pin as McASP pin */ 2442 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2443 2444 pm_runtime_put_sync(mcasp->dev); 2445 } 2446 2447 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip, 2448 unsigned offset, int value) 2449 { 2450 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2451 u32 val; 2452 2453 if (value) 2454 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2455 else 2456 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2457 2458 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2459 if (!(val & BIT(offset))) { 2460 /* Set the pin as GPIO pin */ 2461 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2462 2463 /* Set the direction to output */ 2464 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2465 } 2466 2467 return 0; 2468 } 2469 2470 static int davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned int offset, 2471 int value) 2472 { 2473 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2474 2475 if (value) 2476 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2477 else 2478 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset)); 2479 2480 return 0; 2481 } 2482 2483 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip, 2484 unsigned offset) 2485 { 2486 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2487 u32 val; 2488 2489 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG); 2490 if (!(val & BIT(offset))) { 2491 /* Set the direction to input */ 2492 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset)); 2493 2494 /* Set the pin as GPIO pin */ 2495 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset)); 2496 } 2497 2498 return 0; 2499 } 2500 2501 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset) 2502 { 2503 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2504 u32 val; 2505 2506 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG); 2507 if (val & BIT(offset)) 2508 return 1; 2509 2510 return 0; 2511 } 2512 2513 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip, 2514 unsigned offset) 2515 { 2516 struct davinci_mcasp *mcasp = gpiochip_get_data(chip); 2517 u32 val; 2518 2519 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG); 2520 if (val & BIT(offset)) 2521 return 0; 2522 2523 return 1; 2524 } 2525 2526 static const struct gpio_chip davinci_mcasp_template_chip = { 2527 .owner = THIS_MODULE, 2528 .request = davinci_mcasp_gpio_request, 2529 .free = davinci_mcasp_gpio_free, 2530 .direction_output = davinci_mcasp_gpio_direction_out, 2531 .set = davinci_mcasp_gpio_set, 2532 .direction_input = davinci_mcasp_gpio_direction_in, 2533 .get = davinci_mcasp_gpio_get, 2534 .get_direction = davinci_mcasp_gpio_get_direction, 2535 .base = -1, 2536 .ngpio = 32, 2537 }; 2538 2539 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2540 { 2541 if (!davinci_mcasp_have_gpiochip(mcasp)) 2542 return 0; 2543 2544 mcasp->gpio_chip = davinci_mcasp_template_chip; 2545 mcasp->gpio_chip.label = dev_name(mcasp->dev); 2546 mcasp->gpio_chip.parent = mcasp->dev; 2547 2548 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp); 2549 } 2550 2551 #else /* CONFIG_GPIOLIB */ 2552 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp) 2553 { 2554 return 0; 2555 } 2556 #endif /* CONFIG_GPIOLIB */ 2557 2558 static int davinci_mcasp_probe(struct platform_device *pdev) 2559 { 2560 struct snd_dmaengine_dai_dma_data *dma_data; 2561 struct resource *mem, *dat; 2562 struct davinci_mcasp *mcasp; 2563 char *irq_name; 2564 int irq; 2565 int ret; 2566 2567 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 2568 dev_err(&pdev->dev, "No platform data supplied\n"); 2569 return -EINVAL; 2570 } 2571 2572 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp), 2573 GFP_KERNEL); 2574 if (!mcasp) 2575 return -ENOMEM; 2576 2577 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 2578 if (!mem) { 2579 dev_warn(&pdev->dev, 2580 "\"mpu\" mem resource not found, using index 0\n"); 2581 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2582 if (!mem) { 2583 dev_err(&pdev->dev, "no mem resource?\n"); 2584 return -ENODEV; 2585 } 2586 } 2587 2588 mcasp->base = devm_ioremap_resource(&pdev->dev, mem); 2589 if (IS_ERR(mcasp->base)) 2590 return PTR_ERR(mcasp->base); 2591 2592 dev_set_drvdata(&pdev->dev, mcasp); 2593 pm_runtime_enable(&pdev->dev); 2594 2595 mcasp->dev = &pdev->dev; 2596 ret = davinci_mcasp_get_config(mcasp, pdev); 2597 if (ret) 2598 goto err; 2599 2600 /* All PINS as McASP */ 2601 pm_runtime_get_sync(mcasp->dev); 2602 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000); 2603 pm_runtime_put(mcasp->dev); 2604 2605 /* Skip audio related setup code if the configuration is not adequat */ 2606 if (mcasp->missing_audio_param) 2607 goto no_audio; 2608 2609 irq = platform_get_irq_byname_optional(pdev, "common"); 2610 if (irq > 0) { 2611 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common", 2612 dev_name(&pdev->dev)); 2613 if (!irq_name) { 2614 ret = -ENOMEM; 2615 goto err; 2616 } 2617 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2618 davinci_mcasp_common_irq_handler, 2619 IRQF_ONESHOT | IRQF_SHARED, 2620 irq_name, mcasp); 2621 if (ret) { 2622 dev_err(&pdev->dev, "common IRQ request failed\n"); 2623 goto err; 2624 } 2625 2626 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2627 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2628 } 2629 2630 irq = platform_get_irq_byname_optional(pdev, "rx"); 2631 if (irq > 0) { 2632 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx", 2633 dev_name(&pdev->dev)); 2634 if (!irq_name) { 2635 ret = -ENOMEM; 2636 goto err; 2637 } 2638 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2639 davinci_mcasp_rx_irq_handler, 2640 IRQF_ONESHOT, irq_name, mcasp); 2641 if (ret) { 2642 dev_err(&pdev->dev, "RX IRQ request failed\n"); 2643 goto err; 2644 } 2645 2646 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN; 2647 } 2648 2649 irq = platform_get_irq_byname_optional(pdev, "tx"); 2650 if (irq > 0) { 2651 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx", 2652 dev_name(&pdev->dev)); 2653 if (!irq_name) { 2654 ret = -ENOMEM; 2655 goto err; 2656 } 2657 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 2658 davinci_mcasp_tx_irq_handler, 2659 IRQF_ONESHOT, irq_name, mcasp); 2660 if (ret) { 2661 dev_err(&pdev->dev, "TX IRQ request failed\n"); 2662 goto err; 2663 } 2664 2665 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN; 2666 } 2667 2668 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 2669 if (dat) 2670 mcasp->dat_port = true; 2671 2672 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 2673 dma_data->filter_data = "tx"; 2674 if (dat) { 2675 dma_data->addr = dat->start; 2676 /* 2677 * According to the TRM there should be 0x200 offset added to 2678 * the DAT port address 2679 */ 2680 if (mcasp->version == MCASP_VERSION_OMAP) 2681 dma_data->addr += davinci_mcasp_txdma_offset(mcasp->pdata); 2682 } else { 2683 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(mcasp->pdata); 2684 } 2685 2686 2687 /* RX is not valid in DIT mode */ 2688 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) { 2689 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE]; 2690 dma_data->filter_data = "rx"; 2691 if (dat) 2692 dma_data->addr = dat->start; 2693 else 2694 dma_data->addr = 2695 mem->start + davinci_mcasp_rxdma_offset(mcasp->pdata); 2696 } 2697 2698 if (mcasp->version < MCASP_VERSION_3) { 2699 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE; 2700 /* dma_params->dma_addr is pointing to the data port address */ 2701 mcasp->dat_port = true; 2702 } else { 2703 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE; 2704 } 2705 2706 /* Allocate memory for long enough list for all possible 2707 * scenarios. Maximum number tdm slots is 32 and there cannot 2708 * be more serializers than given in the configuration. The 2709 * serializer directions could be taken into account, but it 2710 * would make code much more complex and save only couple of 2711 * bytes. 2712 */ 2713 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list = 2714 devm_kcalloc(mcasp->dev, 2715 32 + mcasp->num_serializer - 1, 2716 sizeof(unsigned int), 2717 GFP_KERNEL); 2718 2719 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list = 2720 devm_kcalloc(mcasp->dev, 2721 32 + mcasp->num_serializer - 1, 2722 sizeof(unsigned int), 2723 GFP_KERNEL); 2724 2725 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list || 2726 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) { 2727 ret = -ENOMEM; 2728 goto err; 2729 } 2730 2731 ret = davinci_mcasp_set_ch_constraints(mcasp); 2732 if (ret) 2733 goto err; 2734 2735 mcasp_reparent_fck(pdev); 2736 2737 ret = davinci_mcasp_get_dma_type(mcasp); 2738 switch (ret) { 2739 case PCM_EDMA: 2740 ret = edma_pcm_platform_register(&pdev->dev); 2741 break; 2742 case PCM_SDMA: 2743 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) 2744 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx"); 2745 else 2746 ret = sdma_pcm_platform_register(&pdev->dev, "tx", NULL); 2747 break; 2748 case PCM_UDMA: 2749 ret = udma_pcm_platform_register(&pdev->dev); 2750 break; 2751 default: 2752 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret); 2753 fallthrough; 2754 case -EPROBE_DEFER: 2755 goto err; 2756 } 2757 2758 if (ret) { 2759 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 2760 goto err; 2761 } 2762 2763 ret = devm_snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, 2764 &davinci_mcasp_dai[mcasp->op_mode], 1); 2765 2766 if (ret != 0) 2767 goto err; 2768 2769 no_audio: 2770 ret = davinci_mcasp_init_gpiochip(mcasp); 2771 if (ret) { 2772 dev_err(&pdev->dev, "gpiochip registration failed: %d\n", ret); 2773 goto err; 2774 } 2775 2776 return 0; 2777 err: 2778 pm_runtime_disable(&pdev->dev); 2779 return ret; 2780 } 2781 2782 static void davinci_mcasp_remove(struct platform_device *pdev) 2783 { 2784 pm_runtime_disable(&pdev->dev); 2785 } 2786 2787 #ifdef CONFIG_PM 2788 static int davinci_mcasp_runtime_suspend(struct device *dev) 2789 { 2790 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2791 struct davinci_mcasp_context *context = &mcasp->context; 2792 u32 reg; 2793 int i; 2794 2795 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2796 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]); 2797 2798 if (mcasp->txnumevt) { 2799 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2800 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg); 2801 } 2802 if (mcasp->rxnumevt) { 2803 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2804 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg); 2805 } 2806 2807 for (i = 0; i < mcasp->num_serializer; i++) 2808 context->xrsr_regs[i] = mcasp_get_reg(mcasp, 2809 DAVINCI_MCASP_XRSRCTL_REG(i)); 2810 2811 return 0; 2812 } 2813 2814 static int davinci_mcasp_runtime_resume(struct device *dev) 2815 { 2816 struct davinci_mcasp *mcasp = dev_get_drvdata(dev); 2817 struct davinci_mcasp_context *context = &mcasp->context; 2818 u32 reg; 2819 int i; 2820 2821 for (i = 0; i < ARRAY_SIZE(context_regs); i++) 2822 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]); 2823 2824 if (mcasp->txnumevt) { 2825 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET; 2826 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]); 2827 } 2828 if (mcasp->rxnumevt) { 2829 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET; 2830 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]); 2831 } 2832 2833 for (i = 0; i < mcasp->num_serializer; i++) 2834 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i), 2835 context->xrsr_regs[i]); 2836 2837 return 0; 2838 } 2839 2840 #endif 2841 2842 static const struct dev_pm_ops davinci_mcasp_pm_ops = { 2843 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2844 pm_runtime_force_resume) 2845 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend, 2846 davinci_mcasp_runtime_resume, 2847 NULL) 2848 }; 2849 2850 static struct platform_driver davinci_mcasp_driver = { 2851 .probe = davinci_mcasp_probe, 2852 .remove = davinci_mcasp_remove, 2853 .driver = { 2854 .name = "davinci-mcasp", 2855 .pm = &davinci_mcasp_pm_ops, 2856 .of_match_table = mcasp_dt_ids, 2857 }, 2858 }; 2859 2860 module_platform_driver(davinci_mcasp_driver); 2861 2862 MODULE_AUTHOR("Steve Chen"); 2863 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface"); 2864 MODULE_LICENSE("GPL"); 2865