1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_CORE_SHARED_TYPES_H__ 6 #define __DML2_CORE_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_display_cfg_types.h" 10 #include "dml_top_types.h" 11 12 #define __DML_VBA_DEBUG__ 13 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling 14 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling 15 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit 16 17 #define __DML2_CALCS_DPP_INVALID__ 0 18 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation 19 #define __DML2_CALCS_PIPE_NO_PLANE__ 99 20 21 struct dml2_core_ip_params { 22 unsigned int vblank_nom_default_us; 23 unsigned int remote_iommu_outstanding_translations; 24 unsigned int rob_buffer_size_kbytes; 25 unsigned int config_return_buffer_size_in_kbytes; 26 unsigned int config_return_buffer_segment_size_in_kbytes; 27 unsigned int compressed_buffer_segment_size_in_kbytes; 28 unsigned int meta_fifo_size_in_kentries; 29 unsigned int dpte_buffer_size_in_pte_reqs_luma; 30 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 31 unsigned int pixel_chunk_size_kbytes; 32 unsigned int alpha_pixel_chunk_size_kbytes; 33 unsigned int min_pixel_chunk_size_bytes; 34 unsigned int writeback_chunk_size_kbytes; 35 unsigned int line_buffer_size_bits; 36 unsigned int max_line_buffer_lines; 37 unsigned int writeback_interface_buffer_size_kbytes; 38 unsigned int max_num_dpp; 39 unsigned int max_num_otg; 40 unsigned int max_num_wb; 41 unsigned int max_dchub_pscl_bw_pix_per_clk; 42 unsigned int max_pscl_lb_bw_pix_per_clk; 43 unsigned int max_lb_vscl_bw_pix_per_clk; 44 unsigned int max_vscl_hscl_bw_pix_per_clk; 45 double max_hscl_ratio; 46 double max_vscl_ratio; 47 unsigned int max_hscl_taps; 48 unsigned int max_vscl_taps; 49 unsigned int num_dsc; 50 unsigned int maximum_dsc_bits_per_component; 51 unsigned int maximum_pixels_per_line_per_dsc_unit; 52 bool dsc422_native_support; 53 bool cursor_64bpp_support; 54 double dispclk_ramp_margin_percent; 55 unsigned int dppclk_delay_subtotal; 56 unsigned int dppclk_delay_scl; 57 unsigned int dppclk_delay_scl_lb_only; 58 unsigned int dppclk_delay_cnvc_formatter; 59 unsigned int dppclk_delay_cnvc_cursor; 60 unsigned int cursor_buffer_size; 61 unsigned int cursor_chunk_size; 62 unsigned int dispclk_delay_subtotal; 63 bool dynamic_metadata_vm_enabled; 64 unsigned int max_inter_dcn_tile_repeaters; 65 unsigned int max_num_hdmi_frl_outputs; 66 unsigned int max_num_dp2p0_outputs; 67 unsigned int max_num_dp2p0_streams; 68 bool dcc_supported; 69 bool ptoi_supported; 70 double writeback_max_hscl_ratio; 71 double writeback_max_vscl_ratio; 72 double writeback_min_hscl_ratio; 73 double writeback_min_vscl_ratio; 74 unsigned int writeback_max_hscl_taps; 75 unsigned int writeback_max_vscl_taps; 76 unsigned int writeback_line_buffer_buffer_size; 77 78 unsigned int words_per_channel; 79 bool imall_supported; 80 unsigned int max_flip_time_us; 81 unsigned int max_flip_time_lines; 82 unsigned int subvp_swath_height_margin_lines; 83 unsigned int subvp_fw_processing_delay_us; 84 unsigned int subvp_pstate_allow_width_us; 85 86 // MRQ 87 bool dcn_mrq_present; 88 unsigned int zero_size_buffer_entries; 89 unsigned int compbuf_reserved_space_zs; 90 unsigned int dcc_meta_buffer_size_bytes; 91 unsigned int meta_chunk_size_kbytes; 92 unsigned int min_meta_chunk_size_bytes; 93 94 unsigned int dchub_arb_to_ret_delay; // num of dcfclk 95 unsigned int hostvm_mode; 96 }; 97 98 struct dml2_core_internal_DmlPipe { 99 double Dppclk; 100 double Dispclk; 101 double PixelClock; 102 double DCFClkDeepSleep; 103 unsigned int DPPPerSurface; 104 bool ScalerEnabled; 105 bool UPSPEnabled; 106 enum dml2_rotation_angle RotationAngle; 107 bool mirrored; 108 unsigned int ViewportHeight; 109 unsigned int ViewportHeightC; 110 unsigned int BlockWidth256BytesY; 111 unsigned int BlockHeight256BytesY; 112 unsigned int BlockWidth256BytesC; 113 unsigned int BlockHeight256BytesC; 114 unsigned int BlockWidthY; 115 unsigned int BlockHeightY; 116 unsigned int BlockWidthC; 117 unsigned int BlockHeightC; 118 unsigned int InterlaceEnable; 119 unsigned int NumberOfCursors; 120 unsigned int VBlank; 121 unsigned int HTotal; 122 unsigned int HActive; 123 bool DCCEnable; 124 enum dml2_odm_mode ODMMode; 125 enum dml2_source_format_class SourcePixelFormat; 126 enum dml2_swizzle_mode SurfaceTiling; 127 unsigned int BytePerPixelY; 128 unsigned int BytePerPixelC; 129 bool ProgressiveToInterlaceUnitInOPP; 130 double VRatio; 131 double VRatioChroma; 132 unsigned int VTaps; 133 unsigned int VTapsChroma; 134 unsigned int PitchY; 135 unsigned int PitchC; 136 bool ViewportStationary; 137 unsigned int ViewportXStart; 138 unsigned int ViewportYStart; 139 unsigned int ViewportXStartC; 140 unsigned int ViewportYStartC; 141 bool FORCE_ONE_ROW_FOR_FRAME; 142 unsigned int SwathHeightY; 143 unsigned int SwathHeightC; 144 145 unsigned int DCCMetaPitchY; 146 unsigned int DCCMetaPitchC; 147 }; 148 149 enum dml2_core_internal_request_type { 150 dml2_core_internal_request_type_256_bytes = 0, 151 dml2_core_internal_request_type_128_bytes_non_contiguous = 1, 152 dml2_core_internal_request_type_128_bytes_contiguous = 2, 153 dml2_core_internal_request_type_na = 3 154 }; 155 enum dml2_core_internal_bw_type { 156 dml2_core_internal_bw_sdp = 0, 157 dml2_core_internal_bw_dram = 1, 158 dml2_core_internal_bw_max 159 }; 160 161 enum dml2_core_internal_soc_state_type { 162 dml2_core_internal_soc_state_sys_active = 0, 163 dml2_core_internal_soc_state_svp_prefetch = 1, 164 dml2_core_internal_soc_state_sys_idle = 2, 165 dml2_core_internal_soc_state_max 166 }; 167 168 enum dml2_core_internal_output_type { 169 dml2_core_internal_output_type_unknown = 0, 170 dml2_core_internal_output_type_dp = 1, 171 dml2_core_internal_output_type_edp = 2, 172 dml2_core_internal_output_type_dp2p0 = 3, 173 dml2_core_internal_output_type_hdmi = 4, 174 dml2_core_internal_output_type_hdmifrl = 5 175 }; 176 177 enum dml2_core_internal_output_type_rate { 178 dml2_core_internal_output_rate_unknown = 0, 179 dml2_core_internal_output_rate_dp_rate_hbr = 1, 180 dml2_core_internal_output_rate_dp_rate_hbr2 = 2, 181 dml2_core_internal_output_rate_dp_rate_hbr3 = 3, 182 dml2_core_internal_output_rate_dp_rate_uhbr10 = 4, 183 dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5, 184 dml2_core_internal_output_rate_dp_rate_uhbr20 = 6, 185 dml2_core_internal_output_rate_hdmi_rate_3x3 = 7, 186 dml2_core_internal_output_rate_hdmi_rate_6x3 = 8, 187 dml2_core_internal_output_rate_hdmi_rate_6x4 = 9, 188 dml2_core_internal_output_rate_hdmi_rate_8x4 = 10, 189 dml2_core_internal_output_rate_hdmi_rate_10x4 = 11, 190 dml2_core_internal_output_rate_hdmi_rate_12x4 = 12, 191 dml2_core_internal_output_rate_hdmi_rate_16x4 = 13, 192 dml2_core_internal_output_rate_hdmi_rate_20x4 = 14 193 }; 194 195 struct dml2_core_internal_watermarks { 196 double UrgentWatermark; 197 double WritebackUrgentWatermark; 198 double DRAMClockChangeWatermark; 199 double FCLKChangeWatermark; 200 double WritebackDRAMClockChangeWatermark; 201 double WritebackFCLKChangeWatermark; 202 double StutterExitWatermark; 203 double StutterEnterPlusExitWatermark; 204 double Z8StutterExitWatermark; 205 double Z8StutterEnterPlusExitWatermark; 206 double USRRetrainingWatermark; 207 double temp_read_or_ppt_watermark_us; 208 }; 209 210 struct dml2_core_internal_mode_support_info { 211 //----------------- 212 // Mode Support Information 213 //----------------- 214 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 215 216 // Mode Support Reason/ 217 bool WritebackLatencySupport; 218 bool ScaleRatioAndTapsSupport; 219 bool SourceFormatPixelAndScanSupport; 220 bool P2IWith420; 221 bool DSCSlicesODMModeSupported; 222 bool DSCOnlyIfNecessaryWithBPP; 223 bool DSC422NativeNotSupported; 224 bool LinkRateDoesNotMatchDPVersion; 225 bool LinkRateForMultistreamNotIndicated; 226 bool BPPForMultistreamNotIndicated; 227 bool MultistreamWithHDMIOreDP; 228 bool MSOOrODMSplitWithNonDPLink; 229 bool NotEnoughLanesForMSO; 230 bool NumberOfOTGSupport; 231 bool NumberOfHDMIFRLSupport; 232 bool NumberOfDP2p0Support; 233 bool WritebackScaleRatioAndTapsSupport; 234 bool CursorSupport; 235 bool PitchSupport; 236 bool ViewportExceedsSurface; 237 //bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 238 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 239 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 240 bool InvalidCombinationOfMALLUseForPState; 241 bool ExceededMALLSize; 242 bool EnoughWritebackUnits; 243 244 bool ExceededMultistreamSlots; 245 bool NotEnoughDSCUnits; 246 bool NotEnoughDSCSlices; 247 bool PixelsPerLinePerDSCUnitSupport; 248 bool DSCCLKRequiredMoreThanSupported; 249 bool DTBCLKRequiredMoreThanSupported; 250 bool LinkCapacitySupport; 251 252 bool ROBSupport; 253 bool OutstandingRequestsSupport; 254 bool OutstandingRequestsUrgencyAvoidance; 255 256 bool PTEBufferSizeNotExceeded; 257 bool DCCMetaBufferSizeNotExceeded; 258 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 259 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 260 bool global_dram_clock_change_supported; 261 bool global_fclk_change_supported; 262 bool USRRetrainingSupport; 263 bool AvgBandwidthSupport; 264 bool UrgVactiveBandwidthSupport; 265 bool EnoughUrgentLatencyHidingSupport; 266 bool PrefetchScheduleSupported; 267 bool PrefetchSupported; 268 bool PrefetchBandwidthSupported; 269 bool DynamicMetadataSupported; 270 bool VRatioInPrefetchSupported; 271 bool DISPCLK_DPPCLK_Support; 272 bool TotalAvailablePipesSupport; 273 bool ODMSupport; 274 bool ModeSupport; 275 bool ViewportSizeSupport; 276 277 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 278 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 279 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 280 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 281 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 282 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 283 284 double OutputBpp[DML2_MAX_PLANES]; 285 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 286 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 287 288 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 289 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 290 291 unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES]; 292 unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES]; 293 294 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 295 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 296 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 297 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 298 299 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 300 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 301 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 302 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 303 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 304 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 305 306 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 307 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 308 double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation 309 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 310 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 311 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc. 312 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 313 314 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 315 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 316 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 317 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 318 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 319 320 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 321 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 322 bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 323 double max_urgent_latency_us; 324 double max_non_urgent_latency_us; 325 double avg_non_urgent_latency_us; 326 double avg_urgent_latency_us; 327 double df_response_time_us; 328 329 bool incorrect_imall_usage; 330 331 bool g6_temp_read_support; 332 bool temp_read_or_ppt_support; 333 334 struct dml2_core_internal_watermarks watermarks; 335 bool dcfclk_support; 336 bool qos_bandwidth_support; 337 }; 338 339 struct dml2_core_internal_mode_support { 340 // Physical info; only using for programming 341 unsigned int state_idx; // <brief min clk state table index for mode support call 342 unsigned int qos_param_index; // to access the uclk dependent qos_parameters table 343 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 344 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 345 346 // Calculated Clocks 347 double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 348 double RequiredDPPCLK[DML2_MAX_PLANES]; 349 double RequiredDISPCLKPerSurface[DML2_MAX_PLANES]; 350 double RequiredDTBCLK[DML2_MAX_PLANES]; 351 352 double required_dscclk_freq_mhz[DML2_MAX_PLANES]; 353 354 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 355 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 356 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 357 double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 358 double GlobalDTBCLK; /// <brief the Max DTBCLK freq out of all pipes 359 double uclk_freq_mhz; 360 double dram_bw_mbps; 361 double max_dram_bw_mbps; 362 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 363 364 double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state 365 double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 366 double max_dispclk_freq_mhz; 367 double max_dppclk_freq_mhz; 368 double max_dscclk_freq_mhz; 369 370 bool NoTimeForPrefetch[DML2_MAX_PLANES]; 371 bool NoTimeForDynamicMetadata[DML2_MAX_PLANES]; 372 373 // ---------------------------------- 374 // Mode Support Info and fail reason 375 // ---------------------------------- 376 struct dml2_core_internal_mode_support_info support; 377 378 // These are calculated before the ModeSupport and ModeProgram step 379 // They represent the bound for the return buffer sizing 380 unsigned int MaxTotalDETInKByte; 381 unsigned int NomDETInKByte; 382 unsigned int MinCompressedBufferSizeInKByte; 383 384 // Info obtained at the end of mode support calculations 385 // The reported info is at the "optimal" state and combine setting 386 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 387 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 388 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 389 unsigned int SwathHeightY[DML2_MAX_PLANES]; 390 unsigned int SwathHeightC[DML2_MAX_PLANES]; 391 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 392 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 393 394 // ---------------------------------- 395 // Intermediates/Informational 396 // ---------------------------------- 397 unsigned int TotImmediateFlipBytes; 398 bool DCCEnabledInAnySurface; 399 double WritebackRequiredDISPCLK; 400 double TimeCalc; 401 double TWait[DML2_MAX_PLANES]; 402 403 bool UnboundedRequestEnabled; 404 unsigned int compbuf_reserved_space_64b; 405 bool hw_debug5; 406 unsigned int CompressedBufferSizeInkByte; 407 double VRatioPreY[DML2_MAX_PLANES]; 408 double VRatioPreC[DML2_MAX_PLANES]; 409 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 410 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 411 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 412 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 413 unsigned int RequiredSlots[DML2_MAX_PLANES]; 414 unsigned int vm_bytes[DML2_MAX_PLANES]; 415 unsigned int DPTEBytesPerRow[DML2_MAX_PLANES]; 416 unsigned int PrefetchLinesY[DML2_MAX_PLANES]; 417 unsigned int PrefetchLinesC[DML2_MAX_PLANES]; 418 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 419 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 420 unsigned int PrefillY[DML2_MAX_PLANES]; 421 unsigned int PrefillC[DML2_MAX_PLANES]; 422 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 423 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 424 425 bool use_one_row_for_frame[DML2_MAX_PLANES]; 426 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 427 428 double dst_y_prefetch[DML2_MAX_PLANES]; 429 double LinesForVM[DML2_MAX_PLANES]; 430 double LinesForDPTERow[DML2_MAX_PLANES]; 431 unsigned int SwathWidthYSingleDPP[DML2_MAX_PLANES]; 432 unsigned int SwathWidthCSingleDPP[DML2_MAX_PLANES]; 433 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 434 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 435 double BytePerPixelInDETY[DML2_MAX_PLANES]; 436 double BytePerPixelInDETC[DML2_MAX_PLANES]; 437 438 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 439 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 440 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 441 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 442 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 443 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 444 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 445 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 446 447 bool surf_linear128_l[DML2_MAX_PLANES]; 448 bool surf_linear128_c[DML2_MAX_PLANES]; 449 450 double PSCL_FACTOR[DML2_MAX_PLANES]; 451 double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES]; 452 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 453 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 454 double Tno_bw[DML2_MAX_PLANES]; 455 double Tno_bw_flip[DML2_MAX_PLANES]; 456 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 457 double dst_y_per_row_flip[DML2_MAX_PLANES]; 458 double WritebackDelayTime[DML2_MAX_PLANES]; 459 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 460 unsigned int dpte_row_height[DML2_MAX_PLANES]; 461 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 462 double UrgLatency; 463 double TripToMemory; 464 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 465 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 466 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 467 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 468 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 469 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 470 double MaximumSwathWidthInLineBufferLuma; 471 double MaximumSwathWidthInLineBufferChroma; 472 double ExtraLatency; 473 double ExtraLatency_sr; 474 double ExtraLatencyPrefetch; 475 476 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 477 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 478 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 479 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 480 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe 481 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 482 483 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 484 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 485 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 486 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 487 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 488 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 489 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 490 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 491 unsigned int meta_req_width[DML2_MAX_PLANES]; 492 unsigned int meta_row_width[DML2_MAX_PLANES]; 493 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 494 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 495 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 496 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 497 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 498 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 499 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 500 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 501 unsigned int meta_req_height[DML2_MAX_PLANES]; 502 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 503 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 504 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 505 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 506 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 507 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 508 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 509 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 510 double TSetup[DML2_MAX_PLANES]; 511 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 512 double Tdmdl_raw[DML2_MAX_PLANES]; 513 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 514 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 515 double MaxActiveFCLKChangeLatencySupported; 516 517 // Backend 518 bool RequiresDSC[DML2_MAX_PLANES]; 519 bool RequiresFEC[DML2_MAX_PLANES]; 520 double OutputBpp[DML2_MAX_PLANES]; 521 double DesiredOutputBpp[DML2_MAX_PLANES]; 522 double PixelClockBackEnd[DML2_MAX_PLANES]; 523 unsigned int DSCDelay[DML2_MAX_PLANES]; 524 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 525 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 526 bool TotalAvailablePipesSupportNoDSC; 527 bool TotalAvailablePipesSupportDSC; 528 unsigned int NumberOfDPPNoDSC; 529 unsigned int NumberOfDPPDSC; 530 enum dml2_odm_mode ODMModeNoDSC; 531 enum dml2_odm_mode ODMModeDSC; 532 double RequiredDISPCLKPerSurfaceNoDSC; 533 double RequiredDISPCLKPerSurfaceDSC; 534 unsigned int EstimatedNumberOfDSCSlices[DML2_MAX_PLANES]; 535 536 // Bandwidth Related Info 537 double BandwidthAvailableForImmediateFlip; 538 double vactive_sw_bw_l[DML2_MAX_PLANES]; // no dcc overhead, for the plane 539 double vactive_sw_bw_c[DML2_MAX_PLANES]; 540 double WriteBandwidth[DML2_MAX_PLANES][DML2_MAX_WRITEBACK]; 541 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 542 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 543 /* Max bandwidth calculated from prefetch schedule should be considered in addition to the pixel data bw to avoid ms/mp mismatches. 544 * 1. oto bw should also be considered when calculating peak urgent bw to avoid situations oto/equ mismatches between ms and mp 545 * 546 * 2. equ bandwidth needs to be considered for calculating peak urgent bw when equ schedule is used in mode support. 547 * Some slight difference in variables may cause the pixel data bandwidth to be higher 548 * even though overall equ prefetch bandwidths can be lower going from ms to mp 549 */ 550 double RequiredPrefetchBWMax[DML2_MAX_PLANES]; 551 double cursor_bw[DML2_MAX_PLANES]; 552 double prefetch_cursor_bw[DML2_MAX_PLANES]; 553 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 554 double final_flip_bw[DML2_MAX_PLANES]; 555 double meta_row_bw[DML2_MAX_PLANES]; 556 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 557 double dpte_row_bw[DML2_MAX_PLANES]; 558 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 559 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 560 double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 561 double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 562 563 // Something that should be feedback to caller 564 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 565 unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; 566 unsigned int NoOfDPP[DML2_MAX_PLANES]; 567 bool MPCCombine[DML2_MAX_PLANES]; 568 double dcfclk_deepsleep; 569 double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 570 bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES]; 571 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 572 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 573 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 574 bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; 575 bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; 576 unsigned int TotalNumberOfActiveDPP; 577 unsigned int TotalNumberOfSingleDPPSurfaces; 578 unsigned int TotalNumberOfDCCActiveDPP; 579 unsigned int Total3dlutActive; 580 581 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 582 double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; 583 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 584 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; 585 double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES]; 586 587 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 588 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 589 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 590 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 591 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 592 593 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 594 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 595 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 596 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 597 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 598 599 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 600 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 601 bool lc_comb_mcache[DML2_MAX_PLANES]; 602 603 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 604 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 605 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 606 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 607 608 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 609 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 610 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 611 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 612 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 613 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 614 615 unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 616 unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 617 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 618 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 619 620 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 621 622 double HostVMInefficiencyFactor; 623 double HostVMInefficiencyFactorPrefetch; 624 625 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 626 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 627 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 628 double tdlut_opt_time[DML2_MAX_PLANES]; 629 double tdlut_drain_time[DML2_MAX_PLANES]; 630 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 631 632 double Tvm_trips_flip[DML2_MAX_PLANES]; 633 double Tr0_trips_flip[DML2_MAX_PLANES]; 634 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 635 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 636 637 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 638 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 639 640 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 641 }; 642 643 /// @brief A mega structure that houses various info for model programming step. 644 struct dml2_core_internal_mode_program { 645 unsigned int qos_param_index; // to access the uclk dependent dpm table 646 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 647 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 648 //double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 649 double dram_bw_mbps; 650 double min_available_urgent_bandwidth_MBps; /// <brief Minimum guaranteed available urgent return bandwidth in MBps 651 double uclk_freq_mhz; 652 unsigned int NoOfDPP[DML2_MAX_PLANES]; 653 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 654 655 //------------- 656 // Intermediate/Informational 657 //------------- 658 double UrgentLatency; 659 double TripToMemory; 660 double MetaTripToMemory; 661 unsigned int VInitPreFillY[DML2_MAX_PLANES]; 662 unsigned int VInitPreFillC[DML2_MAX_PLANES]; 663 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; 664 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; 665 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 666 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 667 668 double BytePerPixelInDETY[DML2_MAX_PLANES]; 669 double BytePerPixelInDETC[DML2_MAX_PLANES]; 670 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 671 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 672 unsigned int SwathWidthY[DML2_MAX_PLANES]; // per-pipe 673 unsigned int SwathWidthC[DML2_MAX_PLANES]; // per-pipe 674 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 675 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 676 unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES]; 677 unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES]; 678 double vactive_sw_bw_l[DML2_MAX_PLANES]; 679 double vactive_sw_bw_c[DML2_MAX_PLANES]; 680 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 681 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 682 683 unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES]; 684 unsigned int vm_bytes[DML2_MAX_PLANES]; 685 unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES]; 686 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 687 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 688 unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES]; 689 double PSCL_THROUGHPUT[DML2_MAX_PLANES]; 690 double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES]; 691 unsigned int DSCDelay[DML2_MAX_PLANES]; 692 double DPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 693 694 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 695 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 696 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 697 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 698 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 699 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 700 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 701 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 702 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 703 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 704 705 bool surf_linear128_l[DML2_MAX_PLANES]; 706 bool surf_linear128_c[DML2_MAX_PLANES]; 707 708 unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES]; 709 double VRatioPrefetchY[DML2_MAX_PLANES]; 710 double VRatioPrefetchC[DML2_MAX_PLANES]; 711 double Tno_bw[DML2_MAX_PLANES]; 712 double Tno_bw_flip[DML2_MAX_PLANES]; 713 double final_flip_bw[DML2_MAX_PLANES]; 714 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 715 double cursor_bw[DML2_MAX_PLANES]; 716 double prefetch_cursor_bw[DML2_MAX_PLANES]; 717 double WritebackDelay[DML2_MAX_PLANES]; 718 unsigned int dpte_row_height[DML2_MAX_PLANES]; 719 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 720 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 721 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 722 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 723 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 724 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 725 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 726 727 double dpte_row_bw[DML2_MAX_PLANES]; 728 double time_per_tdlut_group[DML2_MAX_PLANES]; 729 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 730 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 731 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 732 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 733 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 734 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 735 736 double MaximumSwathWidthInLineBufferLuma; 737 double MaximumSwathWidthInLineBufferChroma; 738 739 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 740 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 741 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 742 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 743 744 double meta_row_bw[DML2_MAX_PLANES]; 745 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 746 unsigned int meta_req_width[DML2_MAX_PLANES]; 747 unsigned int meta_req_height[DML2_MAX_PLANES]; 748 unsigned int meta_row_width[DML2_MAX_PLANES]; 749 unsigned int meta_row_height[DML2_MAX_PLANES]; 750 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 751 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 752 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 753 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 754 755 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 756 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 757 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 758 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 759 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 760 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 761 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 762 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 763 764 double TWait[DML2_MAX_PLANES]; 765 double Tdmdl_vm_raw[DML2_MAX_PLANES]; 766 double Tdmdl_vm[DML2_MAX_PLANES]; 767 double Tdmdl_raw[DML2_MAX_PLANES]; 768 double Tdmdl[DML2_MAX_PLANES]; 769 double TSetup[DML2_MAX_PLANES]; 770 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 771 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 772 773 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 774 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 775 776 bool UnboundedRequestEnabled; 777 unsigned int CompressedBufferSizeInkByte; 778 unsigned int compbuf_reserved_space_64b; 779 bool hw_debug5; 780 unsigned int dcfclk_deep_sleep_hysteresis; 781 unsigned int min_return_latency_in_dcfclk; 782 783 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 784 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 785 double ExtraLatency; 786 double ExtraLatency_sr; 787 double ExtraLatencyPrefetch; 788 bool PrefetchAndImmediateFlipSupported; 789 double TotalDataReadBandwidth; 790 double BandwidthAvailableForImmediateFlip; 791 bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES]; 792 793 bool use_one_row_for_frame[DML2_MAX_PLANES]; 794 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 795 796 double TCalc; 797 unsigned int TotImmediateFlipBytes; 798 799 unsigned int MaxTotalDETInKByte; 800 unsigned int NomDETInKByte; 801 unsigned int MinCompressedBufferSizeInKByte; 802 double PixelClockBackEnd[DML2_MAX_PLANES]; 803 double OutputBpp[DML2_MAX_PLANES]; 804 bool dsc_enable[DML2_MAX_PLANES]; 805 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 806 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 807 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 808 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 809 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 810 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 811 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 812 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 813 double HostVMInefficiencyFactor; 814 double HostVMInefficiencyFactorPrefetch; 815 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 816 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 817 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 818 double tdlut_opt_time[DML2_MAX_PLANES]; 819 double tdlut_drain_time[DML2_MAX_PLANES]; 820 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 821 double Tvm_trips_flip[DML2_MAX_PLANES]; 822 double Tr0_trips_flip[DML2_MAX_PLANES]; 823 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 824 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 825 bool immediate_flip_required; // any pipes need immediate flip 826 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 827 double TotalWRBandwidth; 828 double max_urgent_latency_us; 829 double df_response_time_us; 830 831 // ------------------- 832 // Output 833 // ------------------- 834 unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 835 unsigned int num_active_pipes; 836 837 bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result 838 839 // Support 840 bool UrgVactiveBandwidthSupport; 841 bool PrefetchScheduleSupported; 842 bool UrgentBandwidthSupport; 843 bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported 844 bool ImmediateFlipSupported; 845 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 846 bool dcfclk_support; 847 848 // Clock 849 double Dcfclk; 850 double Dispclk; // <brief dispclk being used in mode programming 851 double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming 852 double GlobalDPPCLK; 853 854 double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 855 double DCFCLKDeepSleep; 856 857 // ARB reg 858 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 859 struct dml2_core_internal_watermarks Watermark; 860 861 // DCC compression control 862 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 863 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 864 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 865 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 866 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 867 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 868 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 869 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 870 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 871 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 872 873 // Stutter Efficiency 874 double StutterEfficiency; 875 double StutterEfficiencyNotIncludingVBlank; 876 unsigned int NumberOfStutterBurstsPerFrame; 877 double Z8StutterEfficiency; 878 unsigned int Z8NumberOfStutterBurstsPerFrame; 879 double Z8StutterEfficiencyNotIncludingVBlank; 880 double StutterPeriod; 881 double Z8StutterEfficiencyBestCase; 882 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; 883 double Z8StutterEfficiencyNotIncludingVBlankBestCase; 884 double StutterPeriodBestCase; 885 886 // DLG TTU reg 887 double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES]; 888 bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES]; 889 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 890 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 891 double dst_y_prefetch[DML2_MAX_PLANES]; 892 double dst_y_per_vm_vblank[DML2_MAX_PLANES]; 893 double dst_y_per_row_vblank[DML2_MAX_PLANES]; 894 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 895 double dst_y_per_row_flip[DML2_MAX_PLANES]; 896 double MinTTUVBlank[DML2_MAX_PLANES]; 897 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 898 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 899 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 900 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 901 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 902 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 903 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 904 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 905 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 906 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 907 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 908 909 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 910 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 911 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 912 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 913 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 914 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 915 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 916 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 917 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 918 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 919 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 920 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 921 922 double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES]; 923 double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES]; 924 double TimePerMetaChunkNominal[DML2_MAX_PLANES]; 925 double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES]; 926 double TimePerMetaChunkVBlank[DML2_MAX_PLANES]; 927 double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES]; 928 double TimePerMetaChunkFlip[DML2_MAX_PLANES]; 929 double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES]; 930 931 double FractionOfUrgentBandwidth; 932 double FractionOfUrgentBandwidthImmediateFlip; 933 double FractionOfUrgentBandwidthMALL; 934 935 // RQ registers 936 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 937 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 938 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 939 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 940 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 941 942 // OTG 943 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 944 unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 945 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 946 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 947 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 948 unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES]; 949 950 // Latency and Support 951 double MaxActiveFCLKChangeLatencySupported; 952 bool USRRetrainingSupport; 953 bool g6_temp_read_support; 954 bool temp_read_or_ppt_support; 955 enum dml2_pstate_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 956 enum dml2_pstate_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 957 bool global_dram_clock_change_supported; 958 bool global_fclk_change_supported; 959 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 960 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 961 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 962 963 // buffer sizing 964 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 965 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 966 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 967 unsigned int SwathHeightY[DML2_MAX_PLANES]; 968 unsigned int SwathHeightC[DML2_MAX_PLANES]; 969 970 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 971 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 972 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 973 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 974 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 975 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 976 977 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 978 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 979 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 980 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 981 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc. 982 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 983 984 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; 985 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 986 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; 987 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 988 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; 989 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 990 991 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 992 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 993 unsigned int mcache_row_bytes_per_channel_l[DML2_MAX_PLANES]; 994 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 995 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 996 997 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 998 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 999 unsigned int mcache_row_bytes_per_channel_c[DML2_MAX_PLANES]; 1000 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 1001 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 1002 1003 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 1004 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 1005 bool lc_comb_mcache[DML2_MAX_PLANES]; 1006 1007 double impacted_prefetch_margin_us[DML2_MAX_PLANES]; 1008 }; 1009 1010 struct dml2_core_internal_SOCParametersList { 1011 double UrgentLatency; 1012 double ExtraLatency_sr; 1013 double ExtraLatency; 1014 double WritebackLatency; 1015 double DRAMClockChangeLatency; 1016 double FCLKChangeLatency; 1017 double SRExitTime; 1018 double SREnterPlusExitTime; 1019 double SRExitZ8Time; 1020 double SREnterPlusExitZ8Time; 1021 double USRRetrainingLatency; 1022 double SMNLatency; 1023 double g6_temp_read_blackout_us; 1024 double temp_read_or_ppt_blackout_us; 1025 double max_urgent_latency_us; 1026 double df_response_time_us; 1027 enum dml2_qos_param_type qos_type; 1028 }; 1029 1030 struct dml2_core_calcs_mode_support_locals { 1031 double PixelClockBackEnd[DML2_MAX_PLANES]; 1032 double OutputBpp[DML2_MAX_PLANES]; 1033 1034 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 1035 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 1036 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1037 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1038 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1039 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1040 1041 bool dummy_boolean[3]; 1042 unsigned int dummy_integer[3]; 1043 unsigned int dummy_integer_array[36][DML2_MAX_PLANES]; 1044 enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES]; 1045 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1046 double dummy_single[3]; 1047 double dummy_single_array[DML2_MAX_PLANES]; 1048 struct dml2_core_internal_watermarks dummy_watermark; 1049 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1050 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1051 1052 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 1053 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 1054 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 1055 struct dml2_core_internal_SOCParametersList mSOCParameters; 1056 struct dml2_core_internal_DmlPipe myPipe; 1057 struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES]; 1058 unsigned int TotalNumberOfActiveWriteback; 1059 unsigned int MaximumSwathWidthSupportLuma; 1060 unsigned int MaximumSwathWidthSupportChroma; 1061 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; 1062 bool MPCCombineMethodAsPossible; 1063 bool TotalAvailablePipesSupportNoDSC; 1064 unsigned int NumberOfDPPNoDSC; 1065 enum dml2_odm_mode ODMModeNoDSC; 1066 double RequiredDISPCLKPerSurfaceNoDSC; 1067 bool TotalAvailablePipesSupportDSC; 1068 unsigned int NumberOfDPPDSC; 1069 enum dml2_odm_mode ODMModeDSC; 1070 double RequiredDISPCLKPerSurfaceDSC; 1071 double BWOfNonCombinedSurfaceOfMaximumBandwidth; 1072 unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; 1073 unsigned int TotalNumberOfActiveOTG; 1074 unsigned int TotalNumberOfActiveHDMIFRL; 1075 unsigned int TotalNumberOfActiveDP2p0; 1076 unsigned int TotalNumberOfActiveDP2p0Outputs; 1077 unsigned int TotalSlots; 1078 unsigned int DSCFormatFactor; 1079 unsigned int TotalDSCUnitsRequired; 1080 unsigned int ReorderingBytes; 1081 bool ImmediateFlipRequired; 1082 bool FullFrameMALLPStateMethod; 1083 bool SubViewportMALLPStateMethod; 1084 bool PhantomPipeMALLPStateMethod; 1085 bool SubViewportMALLRefreshGreaterThan120Hz; 1086 1087 double HostVMInefficiencyFactor; 1088 double HostVMInefficiencyFactorPrefetch; 1089 unsigned int MaxVStartup; 1090 double PixelClockBackEndFactor; 1091 unsigned int NumDSCUnitRequired; 1092 1093 double Tvm_trips[DML2_MAX_PLANES]; 1094 double Tr0_trips[DML2_MAX_PLANES]; 1095 double Tvm_trips_flip[DML2_MAX_PLANES]; 1096 double Tr0_trips_flip[DML2_MAX_PLANES]; 1097 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1098 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1099 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1100 1101 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1102 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1103 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1104 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1105 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1106 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1107 1108 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1109 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1110 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1111 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1112 double tdlut_opt_time[DML2_MAX_PLANES]; 1113 double tdlut_drain_time[DML2_MAX_PLANES]; 1114 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1115 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1116 1117 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1118 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1119 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1120 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1121 bool stream_visited[DML2_MAX_PLANES]; 1122 1123 unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 1124 unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 1125 1126 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1127 double Tpre_rounded[DML2_MAX_PLANES]; 1128 double Tpre_oto[DML2_MAX_PLANES]; 1129 bool recalc_prefetch_schedule; 1130 bool recalc_prefetch_done; 1131 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1132 double line_times[DML2_MAX_PLANES]; 1133 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1134 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1135 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1136 double prefetch_swath_time_us[DML2_MAX_PLANES]; 1137 }; 1138 1139 struct dml2_core_calcs_mode_programming_locals { 1140 double PixelClockBackEnd[DML2_MAX_PLANES]; 1141 double OutputBpp[DML2_MAX_PLANES]; 1142 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 1143 unsigned int MaxTotalDETInKByte; 1144 unsigned int NomDETInKByte; 1145 unsigned int MinCompressedBufferSizeInKByte; 1146 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 1147 1148 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 1149 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1150 double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1151 unsigned int dummy_integer_array[4][DML2_MAX_PLANES]; 1152 enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES]; 1153 double dummy_single_array[2][DML2_MAX_PLANES]; 1154 unsigned int dummy_long_array[8][DML2_MAX_PLANES]; 1155 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 1156 bool dummy_boolean[2]; 1157 double dummy_single[2]; 1158 struct dml2_core_internal_watermarks dummy_watermark; 1159 1160 unsigned int DSCFormatFactor; 1161 struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES]; 1162 unsigned int ReorderingBytes; 1163 double HostVMInefficiencyFactor; 1164 double HostVMInefficiencyFactorPrefetch; 1165 unsigned int TotalDCCActiveDPP; 1166 unsigned int TotalActiveDPP; 1167 unsigned int Total3dlutActive; 1168 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 1169 bool immediate_flip_required; // any pipes need immediate flip 1170 bool DestinationLineTimesForPrefetchLessThan2; 1171 bool VRatioPrefetchMoreThanMax; 1172 double MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1173 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1174 double Tvstartup_margin; 1175 double dlg_vblank_start; 1176 double LSetup; 1177 double blank_lines_remaining; 1178 double WRBandwidth; 1179 struct dml2_core_internal_DmlPipe myPipe; 1180 double PixelClockBackEndFactor; 1181 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1182 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1183 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1184 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1185 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1186 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1187 1188 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1189 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1190 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1191 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1192 1193 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1194 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1195 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1196 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1197 double tdlut_opt_time[DML2_MAX_PLANES]; 1198 double tdlut_drain_time[DML2_MAX_PLANES]; 1199 unsigned int tdlut_bytes_to_deliver[DML2_MAX_PLANES]; 1200 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1201 1202 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1203 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1204 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1205 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1206 1207 double Tvm_trips[DML2_MAX_PLANES]; 1208 double Tr0_trips[DML2_MAX_PLANES]; 1209 double Tvm_trips_flip[DML2_MAX_PLANES]; 1210 double Tr0_trips_flip[DML2_MAX_PLANES]; 1211 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1212 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1213 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1214 1215 unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 1216 unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 1217 1218 double prefetch_sw_bytes[DML2_MAX_PLANES]; 1219 double Tpre_rounded[DML2_MAX_PLANES]; 1220 double Tpre_oto[DML2_MAX_PLANES]; 1221 bool recalc_prefetch_schedule; 1222 double impacted_dst_y_pre[DML2_MAX_PLANES]; 1223 double line_times[DML2_MAX_PLANES]; 1224 enum dml2_source_format_class pixel_format[DML2_MAX_PLANES]; 1225 unsigned int lb_source_lines_l[DML2_MAX_PLANES]; 1226 unsigned int lb_source_lines_c[DML2_MAX_PLANES]; 1227 unsigned int num_dsc_slices[DML2_MAX_PLANES]; 1228 bool dsc_enable[DML2_MAX_PLANES]; 1229 }; 1230 1231 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals { 1232 double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES]; 1233 double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES]; 1234 double USRRetrainingLatencyMargin[DML2_MAX_PLANES]; 1235 double g6_temp_read_latency_margin[DML2_MAX_PLANES]; 1236 double temp_read_or_ppt_latency_margin[DML2_MAX_PLANES]; 1237 1238 double EffectiveLBLatencyHidingY; 1239 double EffectiveLBLatencyHidingC; 1240 double LinesInDETY[DML2_MAX_PLANES]; 1241 double LinesInDETC[DML2_MAX_PLANES]; 1242 unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES]; 1243 unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES]; 1244 double FullDETBufferingTimeY; 1245 double FullDETBufferingTimeC; 1246 double WritebackDRAMClockChangeLatencyMargin; 1247 double WritebackFCLKChangeLatencyMargin; 1248 double WritebackLatencyHiding; 1249 1250 unsigned int TotalActiveWriteback; 1251 unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES]; 1252 unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES]; 1253 double TotalPixelBW; 1254 double EffectiveDETBufferSizeY; 1255 double ActiveClockChangeLatencyHidingY; 1256 double ActiveClockChangeLatencyHidingC; 1257 double ActiveClockChangeLatencyHiding; 1258 unsigned int dst_y_pstate; 1259 unsigned int src_y_pstate_l; 1260 unsigned int src_y_pstate_c; 1261 unsigned int src_y_ahead_l; 1262 unsigned int src_y_ahead_c; 1263 unsigned int sub_vp_lines_l; 1264 unsigned int sub_vp_lines_c; 1265 1266 }; 1267 1268 struct dml2_core_calcs_CalculateVMRowAndSwath_locals { 1269 unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES]; 1270 unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES]; 1271 unsigned int vm_bytes_l; 1272 unsigned int vm_bytes_c; 1273 unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES]; 1274 unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES]; 1275 unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES]; 1276 unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES]; 1277 unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES]; 1278 unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES]; 1279 unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1280 unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES]; 1281 unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1282 unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES]; 1283 bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES]; 1284 unsigned int HostVMDynamicLevels; 1285 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1286 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1287 }; 1288 1289 struct dml2_core_calcs_CalculateVMRowAndSwath_params { 1290 const struct dml2_display_cfg *display_cfg; 1291 unsigned int NumberOfActiveSurfaces; 1292 struct dml2_core_internal_DmlPipe *myPipe; 1293 unsigned int *SurfaceSizeInMALL; 1294 unsigned int PTEBufferSizeInRequestsLuma; 1295 unsigned int PTEBufferSizeInRequestsChroma; 1296 unsigned int MALLAllocatedForDCN; 1297 unsigned int *SwathWidthY; 1298 unsigned int *SwathWidthC; 1299 unsigned int HostVMMinPageSize; 1300 unsigned int DCCMetaBufferSizeBytes; 1301 bool mrq_present; 1302 enum dml2_pstate_method pstate_switch_modes[DML2_MAX_PLANES]; 1303 1304 // Output 1305 bool *PTEBufferSizeNotExceeded; 1306 bool *DCCMetaBufferSizeNotExceeded; 1307 1308 unsigned int *dpte_row_width_luma_ub; 1309 unsigned int *dpte_row_width_chroma_ub; 1310 unsigned int *dpte_row_height_luma; 1311 unsigned int *dpte_row_height_chroma; 1312 unsigned int *dpte_row_height_linear_luma; // VBA_DELTA 1313 unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA 1314 1315 unsigned int *vm_group_bytes; 1316 unsigned int *dpte_group_bytes; 1317 unsigned int *PixelPTEReqWidthY; 1318 unsigned int *PixelPTEReqHeightY; 1319 unsigned int *PTERequestSizeY; 1320 unsigned int *vmpg_width_y; 1321 unsigned int *vmpg_height_y; 1322 1323 unsigned int *PixelPTEReqWidthC; 1324 unsigned int *PixelPTEReqHeightC; 1325 unsigned int *PTERequestSizeC; 1326 unsigned int *vmpg_width_c; 1327 unsigned int *vmpg_height_c; 1328 1329 unsigned int *dpde0_bytes_per_frame_ub_l; 1330 unsigned int *dpde0_bytes_per_frame_ub_c; 1331 1332 unsigned int *PrefetchSourceLinesY; 1333 unsigned int *PrefetchSourceLinesC; 1334 unsigned int *VInitPreFillY; 1335 unsigned int *VInitPreFillC; 1336 unsigned int *MaxNumSwathY; 1337 unsigned int *MaxNumSwathC; 1338 double *dpte_row_bw; 1339 unsigned int *PixelPTEBytesPerRow; 1340 unsigned int *dpte_row_bytes_per_row_l; 1341 unsigned int *dpte_row_bytes_per_row_c; 1342 unsigned int *vm_bytes; 1343 bool *use_one_row_for_frame; 1344 bool *use_one_row_for_frame_flip; 1345 bool *is_using_mall_for_ss; 1346 bool *PTE_BUFFER_MODE; 1347 unsigned int *BIGK_FRAGMENT_SIZE; 1348 1349 // MRQ 1350 unsigned int *meta_req_width_luma; 1351 unsigned int *meta_req_height_luma; 1352 unsigned int *meta_row_width_luma; 1353 unsigned int *meta_row_height_luma; 1354 unsigned int *meta_pte_bytes_per_frame_ub_l; 1355 1356 unsigned int *meta_req_width_chroma; 1357 unsigned int *meta_req_height_chroma; 1358 unsigned int *meta_row_width_chroma; 1359 unsigned int *meta_row_height_chroma; 1360 unsigned int *meta_pte_bytes_per_frame_ub_c; 1361 double *meta_row_bw; 1362 unsigned int *meta_row_bytes; 1363 unsigned int *meta_row_bytes_per_row_ub_l; 1364 unsigned int *meta_row_bytes_per_row_ub_c; 1365 }; 1366 1367 struct dml2_core_calcs_CalculatePrefetchSchedule_locals { 1368 bool NoTimeToPrefetch; 1369 unsigned int DPPCycles; 1370 unsigned int DISPCLKCycles; 1371 double DSTTotalPixelsAfterScaler; 1372 double LineTime; 1373 double dst_y_prefetch_equ; 1374 double prefetch_bw_oto; 1375 double per_pipe_vactive_sw_bw; 1376 double Tvm_oto; 1377 double Tr0_oto; 1378 double Tvm_oto_lines; 1379 double Tr0_oto_lines; 1380 double dst_y_prefetch_oto; 1381 double TimeForFetchingVM; 1382 double TimeForFetchingRowInVBlank; 1383 double LinesToRequestPrefetchPixelData; 1384 unsigned int HostVMDynamicLevelsTrips; 1385 double trip_to_mem; 1386 double Tvm_trips_rounded; 1387 double Tr0_trips_rounded; 1388 double max_Tsw; 1389 double Lsw_oto; 1390 double prefetch_bw_equ; 1391 double Tvm_equ; 1392 double Tr0_equ; 1393 double Tdmbf; 1394 double Tdmec; 1395 double Tdmsks; 1396 double total_row_bytes; 1397 double prefetch_bw_pr; 1398 double bytes_pp; 1399 double dep_bytes; 1400 double min_Lsw_oto; 1401 double min_Lsw_equ; 1402 double Tsw_est1; 1403 double Tsw_est2; 1404 double Tsw_est3; 1405 double prefetch_bw1; 1406 double prefetch_bw2; 1407 double prefetch_bw3; 1408 double prefetch_bw4; 1409 double dst_y_prefetch_equ_impacted; 1410 1411 double TWait_p; 1412 unsigned int cursor_prefetch_bytes; 1413 }; 1414 1415 struct dml2_core_shared_calculate_det_buffer_size_params { 1416 const struct dml2_display_cfg *display_cfg; 1417 bool ForceSingleDPP; 1418 unsigned int NumberOfActiveSurfaces; 1419 bool UnboundedRequestEnabled; 1420 unsigned int nomDETInKByte; 1421 unsigned int MaxTotalDETInKByte; 1422 unsigned int ConfigReturnBufferSizeInKByte; 1423 unsigned int MinCompressedBufferSizeInKByte; 1424 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1425 unsigned int CompressedBufferSegmentSizeInkByte; 1426 double *ReadBandwidthLuma; 1427 double *ReadBandwidthChroma; 1428 unsigned int *full_swath_bytes_l; 1429 unsigned int *full_swath_bytes_c; 1430 unsigned int *swath_time_value_us; 1431 unsigned int *DPPPerSurface; 1432 bool TryToAllocateForWriteLatency; 1433 unsigned int bestEffortMinActiveLatencyHidingUs; 1434 1435 // Output 1436 unsigned int *DETBufferSizeInKByte; 1437 unsigned int *CompressedBufferSizeInkByte; 1438 }; 1439 1440 struct dml2_core_shared_calculate_vm_and_row_bytes_params { 1441 bool ViewportStationary; 1442 bool DCCEnable; 1443 unsigned int NumberOfDPPs; 1444 unsigned int BlockHeight256Bytes; 1445 unsigned int BlockWidth256Bytes; 1446 enum dml2_source_format_class SourcePixelFormat; 1447 unsigned int SurfaceTiling; 1448 unsigned int BytePerPixel; 1449 enum dml2_rotation_angle RotationAngle; 1450 unsigned int SwathWidth; // per pipe 1451 unsigned int ViewportHeight; 1452 unsigned int ViewportXStart; 1453 unsigned int ViewportYStart; 1454 bool GPUVMEnable; 1455 unsigned int GPUVMMaxPageTableLevels; 1456 unsigned int GPUVMMinPageSizeKBytes; 1457 unsigned int PTEBufferSizeInRequests; 1458 unsigned int Pitch; 1459 unsigned int MacroTileWidth; 1460 unsigned int MacroTileHeight; 1461 bool is_phantom; 1462 unsigned int DCCMetaPitch; 1463 bool mrq_present; 1464 1465 // Output 1466 unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation 1467 unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check 1468 unsigned int *dpte_row_width_ub; 1469 unsigned int *dpte_row_height; 1470 unsigned int *dpte_row_height_linear; 1471 unsigned int *PixelPTEBytesPerRow_one_row_per_frame; 1472 unsigned int *dpte_row_width_ub_one_row_per_frame; 1473 unsigned int *dpte_row_height_one_row_per_frame; 1474 unsigned int *vmpg_width; 1475 unsigned int *vmpg_height; 1476 unsigned int *PixelPTEReqWidth; 1477 unsigned int *PixelPTEReqHeight; 1478 unsigned int *PTERequestSize; 1479 unsigned int *dpde0_bytes_per_frame_ub; 1480 1481 unsigned int *meta_row_bytes; 1482 unsigned int *MetaRequestWidth; 1483 unsigned int *MetaRequestHeight; 1484 unsigned int *meta_row_width; 1485 unsigned int *meta_row_height; 1486 unsigned int *meta_pte_bytes_per_frame_ub; 1487 }; 1488 1489 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals { 1490 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES]; 1491 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES]; 1492 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES]; 1493 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES]; 1494 unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES]; 1495 unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES]; 1496 unsigned int SwathTimeValueUs[DML2_MAX_PLANES]; 1497 1498 struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params; 1499 }; 1500 1501 struct dml2_core_shared_TruncToValidBPP_locals { 1502 }; 1503 1504 struct dml2_core_shared_CalculateDETBufferSize_locals { 1505 unsigned int DETBufferSizePoolInKByte; 1506 unsigned int NextDETBufferPieceInKByte; 1507 unsigned int NextSurfaceToAssignDETPiece; 1508 double TotalBandwidth; 1509 double BandwidthOfSurfacesNotAssignedDETPiece; 1510 unsigned int max_minDET; 1511 unsigned int minDET; 1512 unsigned int minDET_pipe; 1513 unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES]; 1514 unsigned int TotalPixelRate; 1515 unsigned int DETBudgetPerStream[DML2_MAX_PLANES]; 1516 unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES]; 1517 unsigned int IdealDETBudget, DeltaDETBudget; 1518 unsigned int ResidualDETAfterRounding; 1519 }; 1520 1521 struct dml2_core_shared_get_urgent_bandwidth_required_locals { 1522 double required_bandwidth_mbps; 1523 double required_bandwidth_mbps_this_surface; 1524 double adj_factor_p0; 1525 double adj_factor_p1; 1526 double adj_factor_cur; 1527 double adj_factor_p0_pre; 1528 double adj_factor_p1_pre; 1529 double adj_factor_cur_pre; 1530 double per_plane_flip_bw[DML2_MAX_PLANES]; 1531 double mall_svp_prefetch_factor; 1532 double tmp_nom_adj_factor_p0; 1533 double tmp_nom_adj_factor_p1; 1534 double tmp_pref_adj_factor_p0; 1535 double tmp_pref_adj_factor_p1; 1536 double vm_row_bw; 1537 double flip_and_active_bw; 1538 double flip_and_prefetch_bw; 1539 double flip_and_prefetch_bw_max; 1540 double active_and_excess_bw; 1541 }; 1542 1543 struct dml2_core_shared_calculate_peak_bandwidth_required_locals { 1544 double unity_array[DML2_MAX_PLANES]; 1545 double zero_array[DML2_MAX_PLANES]; 1546 double surface_dummy_bw[DML2_MAX_PLANES]; 1547 }; 1548 1549 struct dml2_core_shared_CalculateFlipSchedule_locals { 1550 double min_row_time; 1551 double Tvm_flip; 1552 double Tr0_flip; 1553 double ImmediateFlipBW; 1554 double dpte_row_bytes; 1555 double min_row_height; 1556 double min_row_height_chroma; 1557 double max_flip_time; 1558 double lb_flip_bw; 1559 double hvm_scaled_vm_bytes; 1560 double num_rows; 1561 double hvm_scaled_row_bytes; 1562 double hvm_scaled_vm_row_bytes; 1563 bool dual_plane; 1564 }; 1565 1566 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals { 1567 unsigned int plane_idx; 1568 unsigned int stream_idx; 1569 enum dml2_source_format_class source_format; 1570 const struct dml2_timing_cfg *timing; 1571 bool dual_plane; 1572 enum dml2_odm_mode odm_mode; 1573 1574 unsigned int htotal; 1575 unsigned int hactive; 1576 unsigned int hblank_end; 1577 unsigned int vblank_end; 1578 bool interlaced; 1579 double pclk_freq_in_mhz; 1580 double refclk_freq_in_mhz; 1581 double ref_freq_to_pix_freq; 1582 1583 unsigned int num_active_pipes; 1584 unsigned int first_pipe_idx_in_plane; 1585 unsigned int pipe_idx_in_combine; 1586 unsigned int odm_combine_factor; 1587 1588 double min_ttu_vblank; 1589 unsigned int min_dst_y_next_start; 1590 1591 unsigned int vready_after_vcount0; 1592 1593 unsigned int dst_x_after_scaler; 1594 unsigned int dst_y_after_scaler; 1595 1596 double dst_y_prefetch; 1597 double dst_y_per_vm_vblank; 1598 double dst_y_per_row_vblank; 1599 double dst_y_per_vm_flip; 1600 double dst_y_per_row_flip; 1601 1602 double max_dst_y_per_vm_vblank; 1603 double max_dst_y_per_row_vblank; 1604 1605 double vratio_pre_l; 1606 double vratio_pre_c; 1607 1608 double refcyc_per_line_delivery_pre_l; 1609 double refcyc_per_line_delivery_l; 1610 1611 double refcyc_per_line_delivery_pre_c; 1612 double refcyc_per_line_delivery_c; 1613 1614 double refcyc_per_req_delivery_pre_l; 1615 double refcyc_per_req_delivery_l; 1616 1617 double refcyc_per_req_delivery_pre_c; 1618 double refcyc_per_req_delivery_c; 1619 1620 double dst_y_per_pte_row_nom_l; 1621 double dst_y_per_pte_row_nom_c; 1622 double refcyc_per_pte_group_nom_l; 1623 double refcyc_per_pte_group_nom_c; 1624 double refcyc_per_pte_group_vblank_l; 1625 double refcyc_per_pte_group_vblank_c; 1626 double refcyc_per_pte_group_flip_l; 1627 double refcyc_per_pte_group_flip_c; 1628 double refcyc_per_tdlut_group; 1629 1630 double dst_y_per_meta_row_nom_l; 1631 double dst_y_per_meta_row_nom_c; 1632 double refcyc_per_meta_chunk_nom_l; 1633 double refcyc_per_meta_chunk_nom_c; 1634 double refcyc_per_meta_chunk_vblank_l; 1635 double refcyc_per_meta_chunk_vblank_c; 1636 double refcyc_per_meta_chunk_flip_l; 1637 double refcyc_per_meta_chunk_flip_c; 1638 }; 1639 1640 struct dml2_core_shared_CalculateMetaAndPTETimes_params { 1641 struct dml2_core_internal_scratch *scratch; 1642 const struct dml2_display_cfg *display_cfg; 1643 unsigned int NumberOfActiveSurfaces; 1644 bool *use_one_row_for_frame; 1645 double *dst_y_per_row_vblank; 1646 double *dst_y_per_row_flip; 1647 unsigned int *BytePerPixelY; 1648 unsigned int *BytePerPixelC; 1649 unsigned int *dpte_row_height; 1650 unsigned int *dpte_row_height_chroma; 1651 unsigned int *dpte_group_bytes; 1652 unsigned int *PTERequestSizeY; 1653 unsigned int *PTERequestSizeC; 1654 unsigned int *PixelPTEReqWidthY; 1655 unsigned int *PixelPTEReqHeightY; 1656 unsigned int *PixelPTEReqWidthC; 1657 unsigned int *PixelPTEReqHeightC; 1658 unsigned int *dpte_row_width_luma_ub; 1659 unsigned int *dpte_row_width_chroma_ub; 1660 unsigned int *tdlut_groups_per_2row_ub; 1661 bool mrq_present; 1662 unsigned int MetaChunkSize; 1663 unsigned int MinMetaChunkSizeBytes; 1664 unsigned int *meta_row_width; 1665 unsigned int *meta_row_width_chroma; 1666 unsigned int *meta_row_height; 1667 unsigned int *meta_row_height_chroma; 1668 unsigned int *meta_req_width; 1669 unsigned int *meta_req_width_chroma; 1670 unsigned int *meta_req_height; 1671 unsigned int *meta_req_height_chroma; 1672 1673 // Output 1674 double *time_per_tdlut_group; 1675 double *DST_Y_PER_PTE_ROW_NOM_L; 1676 double *DST_Y_PER_PTE_ROW_NOM_C; 1677 double *time_per_pte_group_nom_luma; 1678 double *time_per_pte_group_vblank_luma; 1679 double *time_per_pte_group_flip_luma; 1680 double *time_per_pte_group_nom_chroma; 1681 double *time_per_pte_group_vblank_chroma; 1682 double *time_per_pte_group_flip_chroma; 1683 1684 double *DST_Y_PER_META_ROW_NOM_L; 1685 double *DST_Y_PER_META_ROW_NOM_C; 1686 1687 double *TimePerMetaChunkNominal; 1688 double *TimePerChromaMetaChunkNominal; 1689 double *TimePerMetaChunkVBlank; 1690 double *TimePerChromaMetaChunkVBlank; 1691 double *TimePerMetaChunkFlip; 1692 double *TimePerChromaMetaChunkFlip; 1693 }; 1694 1695 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params { 1696 const struct dml2_display_cfg *display_cfg; 1697 bool USRRetrainingRequired; 1698 unsigned int NumberOfActiveSurfaces; 1699 unsigned int MaxLineBufferLines; 1700 unsigned int LineBufferSize; 1701 unsigned int WritebackInterfaceBufferSize; 1702 double DCFCLK; 1703 double ReturnBW; 1704 bool SynchronizeTimings; 1705 bool SynchronizeDRRDisplaysForUCLKPStateChange; 1706 unsigned int *dpte_group_bytes; 1707 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1708 unsigned int WritebackChunkSize; 1709 double SOCCLK; 1710 double DCFClkDeepSleep; 1711 unsigned int *DETBufferSizeY; 1712 unsigned int *DETBufferSizeC; 1713 unsigned int *SwathHeightY; 1714 unsigned int *SwathHeightC; 1715 unsigned int *SwathWidthY; 1716 unsigned int *SwathWidthC; 1717 unsigned int *DPPPerSurface; 1718 double *BytePerPixelDETY; 1719 double *BytePerPixelDETC; 1720 unsigned int *DSTXAfterScaler; 1721 unsigned int *DSTYAfterScaler; 1722 bool UnboundedRequestEnabled; 1723 unsigned int CompressedBufferSizeInkByte; 1724 bool max_outstanding_when_urgent_expected; 1725 unsigned int max_outstanding_requests; 1726 unsigned int max_request_size_bytes; 1727 unsigned int *meta_row_height_l; 1728 unsigned int *meta_row_height_c; 1729 1730 // Output 1731 struct dml2_core_internal_watermarks *Watermark; 1732 enum dml2_pstate_change_support *DRAMClockChangeSupport; 1733 bool *global_dram_clock_change_supported; 1734 double *MaxActiveDRAMClockChangeLatencySupported; 1735 unsigned int *SubViewportLinesNeededInMALL; 1736 enum dml2_pstate_change_support *FCLKChangeSupport; 1737 bool *global_fclk_change_supported; 1738 double *MaxActiveFCLKChangeLatencySupported; 1739 bool *USRRetrainingSupport; 1740 double *VActiveLatencyHidingMargin; 1741 double *VActiveLatencyHidingUs; 1742 bool *g6_temp_read_support; 1743 bool *temp_read_or_ppt_support; 1744 }; 1745 1746 1747 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { 1748 const struct dml2_display_cfg *display_cfg; 1749 unsigned int ConfigReturnBufferSizeInKByte; 1750 unsigned int MaxTotalDETInKByte; 1751 unsigned int MinCompressedBufferSizeInKByte; 1752 unsigned int rob_buffer_size_kbytes; 1753 unsigned int pixel_chunk_size_kbytes; 1754 bool ForceSingleDPP; 1755 unsigned int NumberOfActiveSurfaces; 1756 unsigned int nomDETInKByte; 1757 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1758 unsigned int CompressedBufferSegmentSizeInkByte; 1759 double *ReadBandwidthLuma; 1760 double *ReadBandwidthChroma; 1761 double *MaximumSwathWidthLuma; 1762 double *MaximumSwathWidthChroma; 1763 unsigned int *Read256BytesBlockHeightY; 1764 unsigned int *Read256BytesBlockHeightC; 1765 unsigned int *Read256BytesBlockWidthY; 1766 unsigned int *Read256BytesBlockWidthC; 1767 bool *surf_linear128_l; 1768 bool *surf_linear128_c; 1769 enum dml2_odm_mode *ODMMode; 1770 unsigned int *BytePerPixY; 1771 unsigned int *BytePerPixC; 1772 double *BytePerPixDETY; 1773 double *BytePerPixDETC; 1774 unsigned int *DPPPerSurface; 1775 bool mrq_present; 1776 unsigned int dummy[2][DML2_MAX_PLANES]; 1777 unsigned int swath_width_luma_ub_single_dpp[DML2_MAX_PLANES]; 1778 unsigned int swath_width_chroma_ub_single_dpp[DML2_MAX_PLANES]; 1779 1780 // output 1781 unsigned int *req_per_swath_ub_l; 1782 unsigned int *req_per_swath_ub_c; 1783 unsigned int *swath_width_luma_ub; 1784 unsigned int *swath_width_chroma_ub; 1785 unsigned int *SwathWidth; 1786 unsigned int *SwathWidthChroma; 1787 unsigned int *SwathHeightY; 1788 unsigned int *SwathHeightC; 1789 unsigned int *request_size_bytes_luma; 1790 unsigned int *request_size_bytes_chroma; 1791 unsigned int *DETBufferSizeInKByte; 1792 unsigned int *DETBufferSizeY; 1793 unsigned int *DETBufferSizeC; 1794 unsigned int *full_swath_bytes_l; 1795 unsigned int *full_swath_bytes_c; 1796 unsigned int *full_swath_bytes_single_dpp_l; 1797 unsigned int *full_swath_bytes_single_dpp_c; 1798 bool *UnboundedRequestEnabled; 1799 unsigned int *compbuf_reserved_space_64b; 1800 unsigned int *CompressedBufferSizeInkByte; 1801 bool *ViewportSizeSupportPerSurface; 1802 bool *ViewportSizeSupport; 1803 bool *hw_debug5; 1804 1805 struct dml2_core_shared_calculation_funcs *funcs; 1806 }; 1807 1808 struct dml2_core_calcs_CalculateStutterEfficiency_locals { 1809 double DETBufferingTimeY; 1810 double SwathWidthYCriticalSurface; 1811 double SwathHeightYCriticalSurface; 1812 double VActiveTimeCriticalSurface; 1813 double FrameTimeCriticalSurface; 1814 unsigned int BytePerPixelYCriticalSurface; 1815 unsigned int DETBufferSizeYCriticalSurface; 1816 double MinTTUVBlankCriticalSurface; 1817 unsigned int BlockWidth256BytesYCriticalSurface; 1818 bool SinglePlaneCriticalSurface; 1819 bool SinglePipeCriticalSurface; 1820 double TotalCompressedReadBandwidth; 1821 double TotalRowReadBandwidth; 1822 double AverageDCCCompressionRate; 1823 double EffectiveCompressedBufferSize; 1824 double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; 1825 double StutterBurstTime; 1826 unsigned int TotalActiveWriteback; 1827 double LinesInDETY; 1828 double LinesInDETYRoundedDownToSwath; 1829 double MaximumEffectiveCompressionLuma; 1830 double MaximumEffectiveCompressionChroma; 1831 double TotalZeroSizeRequestReadBandwidth; 1832 double TotalZeroSizeCompressedReadBandwidth; 1833 double AverageDCCZeroSizeFraction; 1834 double AverageZeroSizeCompressionRate; 1835 bool stream_visited[DML2_MAX_PLANES]; 1836 }; 1837 1838 struct dml2_core_calcs_CalculateStutterEfficiency_params { 1839 const struct dml2_display_cfg *display_cfg; 1840 unsigned int CompressedBufferSizeInkByte; 1841 bool UnboundedRequestEnabled; 1842 unsigned int MetaFIFOSizeInKEntries; 1843 unsigned int ZeroSizeBufferEntries; 1844 unsigned int PixelChunkSizeInKByte; 1845 unsigned int NumberOfActiveSurfaces; 1846 unsigned int ROBBufferSizeInKByte; 1847 double TotalDataReadBandwidth; 1848 double DCFCLK; 1849 double ReturnBW; 1850 unsigned int CompbufReservedSpace64B; 1851 unsigned int CompbufReservedSpaceZs; 1852 bool hw_debug5; 1853 double SRExitTime; 1854 double SRExitZ8Time; 1855 bool SynchronizeTimings; 1856 double StutterEnterPlusExitWatermark; 1857 double Z8StutterEnterPlusExitWatermark; 1858 bool ProgressiveToInterlaceUnitInOPP; 1859 double *MinTTUVBlank; 1860 unsigned int *DPPPerSurface; 1861 unsigned int *DETBufferSizeY; 1862 unsigned int *BytePerPixelY; 1863 double *BytePerPixelDETY; 1864 unsigned int *SwathWidthY; 1865 unsigned int *SwathHeightY; 1866 unsigned int *SwathHeightC; 1867 unsigned int *BlockHeight256BytesY; 1868 unsigned int *BlockWidth256BytesY; 1869 unsigned int *BlockHeight256BytesC; 1870 unsigned int *BlockWidth256BytesC; 1871 unsigned int *DCCYMaxUncompressedBlock; 1872 unsigned int *DCCCMaxUncompressedBlock; 1873 double *ReadBandwidthSurfaceLuma; 1874 double *ReadBandwidthSurfaceChroma; 1875 double *meta_row_bw; 1876 double *dpte_row_bw; 1877 bool rob_alloc_compressed; 1878 1879 // output 1880 double *StutterEfficiencyNotIncludingVBlank; 1881 double *StutterEfficiency; 1882 unsigned int *NumberOfStutterBurstsPerFrame; 1883 double *Z8StutterEfficiencyNotIncludingVBlank; 1884 double *Z8StutterEfficiency; 1885 unsigned int *Z8NumberOfStutterBurstsPerFrame; 1886 double *StutterPeriod; 1887 bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1888 }; 1889 1890 struct dml2_core_calcs_CalculatePrefetchSchedule_params { 1891 const struct dml2_display_cfg *display_cfg; 1892 double HostVMInefficiencyFactor; 1893 struct dml2_core_internal_DmlPipe *myPipe; 1894 unsigned int DSCDelay; 1895 double DPPCLKDelaySubtotalPlusCNVCFormater; 1896 double DPPCLKDelaySCL; 1897 double DPPCLKDelaySCLLBOnly; 1898 double DPPCLKDelayCNVCCursor; 1899 double DISPCLKDelaySubtotal; 1900 unsigned int DPP_RECOUT_WIDTH; 1901 enum dml2_output_format_class OutputFormat; 1902 unsigned int MaxInterDCNTileRepeaters; 1903 unsigned int VStartup; 1904 unsigned int HostVMMinPageSize; 1905 bool DynamicMetadataEnable; 1906 bool DynamicMetadataVMEnabled; 1907 unsigned int DynamicMetadataLinesBeforeActiveRequired; 1908 unsigned int DynamicMetadataTransmittedBytes; 1909 double UrgentLatency; 1910 double ExtraLatencyPrefetch; 1911 double TCalc; 1912 unsigned int vm_bytes; 1913 unsigned int PixelPTEBytesPerRow; 1914 double PrefetchSourceLinesY; 1915 unsigned int VInitPreFillY; 1916 unsigned int MaxNumSwathY; 1917 double PrefetchSourceLinesC; 1918 unsigned int VInitPreFillC; 1919 unsigned int MaxNumSwathC; 1920 unsigned int swath_width_luma_ub; // per-pipe 1921 unsigned int swath_width_chroma_ub; // per-pipe 1922 unsigned int SwathHeightY; 1923 unsigned int SwathHeightC; 1924 double TWait; 1925 double Ttrip; 1926 double Turg; 1927 bool setup_for_tdlut; 1928 unsigned int tdlut_pte_bytes_per_frame; 1929 unsigned int tdlut_bytes_per_frame; 1930 double tdlut_opt_time; 1931 double tdlut_drain_time; 1932 1933 unsigned int num_cursors; 1934 unsigned int cursor_bytes_per_chunk; 1935 unsigned int cursor_bytes_per_line; 1936 1937 // MRQ 1938 bool dcc_enable; 1939 bool mrq_present; 1940 unsigned int meta_row_bytes; 1941 double mall_prefetch_sdp_overhead_factor; 1942 1943 double impacted_dst_y_pre; 1944 double vactive_sw_bw_l; // per surface bw 1945 double vactive_sw_bw_c; // per surface bw 1946 1947 // output 1948 unsigned int *DSTXAfterScaler; 1949 unsigned int *DSTYAfterScaler; 1950 double *dst_y_prefetch; 1951 double *dst_y_per_vm_vblank; 1952 double *dst_y_per_row_vblank; 1953 double *VRatioPrefetchY; 1954 double *VRatioPrefetchC; 1955 double *RequiredPrefetchPixelDataBWLuma; 1956 double *RequiredPrefetchPixelDataBWChroma; 1957 double *RequiredPrefetchBWMax; 1958 bool *NotEnoughTimeForDynamicMetadata; 1959 double *Tno_bw; 1960 double *Tno_bw_flip; 1961 double *prefetch_vmrow_bw; 1962 double *Tdmdl_vm; 1963 double *Tdmdl; 1964 double *TSetup; 1965 double *Tpre_rounded; 1966 double *Tpre_oto; 1967 double *Tvm_trips; 1968 double *Tr0_trips; 1969 double *Tvm_trips_flip; 1970 double *Tr0_trips_flip; 1971 double *Tvm_trips_flip_rounded; 1972 double *Tr0_trips_flip_rounded; 1973 unsigned int *VUpdateOffsetPix; 1974 unsigned int *VUpdateWidthPix; 1975 unsigned int *VReadyOffsetPix; 1976 double *prefetch_cursor_bw; 1977 double *prefetch_sw_bytes; 1978 double *prefetch_swath_time_us; 1979 }; 1980 1981 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params { 1982 unsigned int num_active_planes; 1983 enum dml2_source_format_class *pixel_format; 1984 unsigned int rob_buffer_size_kbytes; 1985 unsigned int compressed_buffer_size_kbytes; 1986 unsigned int chunk_bytes_l; // same for all planes 1987 unsigned int chunk_bytes_c; 1988 unsigned int *detile_buffer_size_bytes_l; 1989 unsigned int *detile_buffer_size_bytes_c; 1990 unsigned int *full_swath_bytes_l; 1991 unsigned int *full_swath_bytes_c; 1992 unsigned int *lb_source_lines_l; 1993 unsigned int *lb_source_lines_c; 1994 unsigned int *swath_height_l; 1995 unsigned int *swath_height_c; 1996 double *prefetch_sw_bytes; 1997 double *Tpre_rounded; 1998 double *Tpre_oto; 1999 double estimated_dcfclk_mhz; 2000 double estimated_urg_bandwidth_required_mbps; 2001 double *line_time; 2002 double *dst_y_prefetch; 2003 2004 // output 2005 bool *recalc_prefetch_schedule; 2006 double *impacted_dst_y_pre; 2007 }; 2008 2009 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals { 2010 unsigned int max_Trpd_dcfclk_cycles; 2011 unsigned int burst_bytes_to_fill_det; 2012 double time_to_fill_det_us; 2013 unsigned int accumulated_return_path_dcfclk_cycles[DML2_MAX_PLANES]; 2014 bool prefetch_global_check_passed; 2015 unsigned int src_swath_bytes_l[DML2_MAX_PLANES]; 2016 unsigned int src_swath_bytes_c[DML2_MAX_PLANES]; 2017 unsigned int src_detile_buf_size_bytes_l[DML2_MAX_PLANES]; 2018 unsigned int src_detile_buf_size_bytes_c[DML2_MAX_PLANES]; 2019 }; 2020 2021 struct dml2_core_calcs_calculate_mcache_row_bytes_params { 2022 unsigned int num_chans; 2023 unsigned int mem_word_bytes; 2024 unsigned int mcache_size_bytes; 2025 unsigned int mcache_line_size_bytes; 2026 unsigned int gpuvm_enable; 2027 unsigned int gpuvm_page_size_kbytes; 2028 2029 //enum dml_rotation_angle rotation_angle; 2030 bool surf_vert; 2031 unsigned int vp_stationary; 2032 unsigned int tiling_mode; 2033 bool imall_enable; 2034 2035 unsigned int vp_start_x; 2036 unsigned int vp_start_y; 2037 unsigned int full_vp_width; 2038 unsigned int full_vp_height; 2039 unsigned int blk_width; 2040 unsigned int blk_height; 2041 unsigned int vmpg_width; 2042 unsigned int vmpg_height; 2043 unsigned int full_swath_bytes; 2044 unsigned int bytes_per_pixel; 2045 2046 // output 2047 unsigned int *num_mcaches; 2048 unsigned int *mcache_row_bytes; 2049 unsigned int *mcache_row_bytes_per_channel; 2050 unsigned int *meta_row_width_ub; 2051 double *dcc_dram_bw_nom_overhead_factor; 2052 double *dcc_dram_bw_pref_overhead_factor; 2053 unsigned int *mvmpg_width; 2054 unsigned int *mvmpg_height; 2055 unsigned int *full_vp_access_width_mvmpg_aligned; 2056 unsigned int *mvmpg_per_mcache_lb; 2057 }; 2058 2059 struct dml2_core_shared_calculate_mcache_setting_locals { 2060 struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p; 2061 struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p; 2062 2063 bool is_dual_plane; 2064 unsigned int mvmpg_width_l; 2065 unsigned int mvmpg_height_l; 2066 unsigned int full_vp_access_width_mvmpg_aligned_l; 2067 unsigned int mvmpg_per_mcache_lb_l; 2068 unsigned int meta_row_width_l; 2069 2070 unsigned int mvmpg_width_c; 2071 unsigned int mvmpg_height_c; 2072 unsigned int full_vp_access_width_mvmpg_aligned_c; 2073 unsigned int mvmpg_per_mcache_lb_c; 2074 unsigned int meta_row_width_c; 2075 2076 unsigned int lc_comb_last_mcache_size; 2077 double luma_time_factor; 2078 double mcache_remainder_l; 2079 double mcache_remainder_c; 2080 unsigned int mvmpg_access_width_l; 2081 unsigned int mvmpg_access_width_c; 2082 unsigned int avg_mcache_element_size_l; 2083 unsigned int avg_mcache_element_size_c; 2084 2085 unsigned int full_vp_access_width_l; 2086 unsigned int full_vp_access_width_c; 2087 }; 2088 2089 struct dml2_core_calcs_calculate_mcache_setting_params { 2090 bool dcc_enable; 2091 unsigned int num_chans; 2092 unsigned int mem_word_bytes; 2093 unsigned int mcache_size_bytes; 2094 unsigned int mcache_line_size_bytes; 2095 unsigned int gpuvm_enable; 2096 unsigned int gpuvm_page_size_kbytes; 2097 2098 enum dml2_source_format_class source_format; 2099 bool surf_vert; 2100 unsigned int vp_stationary; 2101 unsigned int tiling_mode; 2102 bool imall_enable; 2103 2104 unsigned int vp_start_x_l; 2105 unsigned int vp_start_y_l; 2106 unsigned int full_vp_width_l; 2107 unsigned int full_vp_height_l; 2108 unsigned int blk_width_l; 2109 unsigned int blk_height_l; 2110 unsigned int vmpg_width_l; 2111 unsigned int vmpg_height_l; 2112 unsigned int full_swath_bytes_l; 2113 unsigned int bytes_per_pixel_l; 2114 2115 unsigned int vp_start_x_c; 2116 unsigned int vp_start_y_c; 2117 unsigned int full_vp_width_c; 2118 unsigned int full_vp_height_c; 2119 unsigned int blk_width_c; 2120 unsigned int blk_height_c; 2121 unsigned int vmpg_width_c; 2122 unsigned int vmpg_height_c; 2123 unsigned int full_swath_bytes_c; 2124 unsigned int bytes_per_pixel_c; 2125 2126 // output 2127 unsigned int *num_mcaches_l; 2128 unsigned int *mcache_row_bytes_l; 2129 unsigned int *mcache_row_bytes_per_channel_l; 2130 unsigned int *mcache_offsets_l; 2131 unsigned int *mcache_shift_granularity_l; 2132 double *dcc_dram_bw_nom_overhead_factor_l; 2133 double *dcc_dram_bw_pref_overhead_factor_l; 2134 2135 unsigned int *num_mcaches_c; 2136 unsigned int *mcache_row_bytes_c; 2137 unsigned int *mcache_row_bytes_per_channel_c; 2138 unsigned int *mcache_offsets_c; 2139 unsigned int *mcache_shift_granularity_c; 2140 double *dcc_dram_bw_nom_overhead_factor_c; 2141 double *dcc_dram_bw_pref_overhead_factor_c; 2142 2143 bool *mall_comb_mcache_l; 2144 bool *mall_comb_mcache_c; 2145 bool *lc_comb_mcache; 2146 }; 2147 2148 struct dml2_core_calcs_calculate_tdlut_setting_params { 2149 // input params 2150 double dispclk_mhz; 2151 bool setup_for_tdlut; 2152 enum dml2_tdlut_width_mode tdlut_width_mode; 2153 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 2154 unsigned int cursor_buffer_size; 2155 bool gpuvm_enable; 2156 unsigned int gpuvm_page_size_kbytes; 2157 bool is_gfx11; 2158 bool tdlut_mpc_width_flag; 2159 2160 // output param 2161 unsigned int *tdlut_pte_bytes_per_frame; 2162 unsigned int *tdlut_bytes_per_frame; 2163 unsigned int *tdlut_groups_per_2row_ub; 2164 double *tdlut_opt_time; 2165 double *tdlut_drain_time; 2166 unsigned int *tdlut_bytes_to_deliver; 2167 unsigned int *tdlut_bytes_per_group; 2168 }; 2169 2170 struct dml2_core_calcs_calculate_peak_bandwidth_required_params { 2171 // output 2172 double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max]; 2173 double (*urg_bandwidth_required)[dml2_core_internal_bw_max]; 2174 double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max]; 2175 double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max]; 2176 double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2177 double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 2178 2179 // input 2180 const struct dml2_display_cfg *display_cfg; 2181 bool inc_flip_bw; 2182 unsigned int num_active_planes; 2183 unsigned int *num_of_dpp; 2184 double *dcc_dram_bw_nom_overhead_factor_p0; 2185 double *dcc_dram_bw_nom_overhead_factor_p1; 2186 double *dcc_dram_bw_pref_overhead_factor_p0; 2187 double *dcc_dram_bw_pref_overhead_factor_p1; 2188 double *mall_prefetch_sdp_overhead_factor; 2189 double *mall_prefetch_dram_overhead_factor; 2190 double *surface_read_bandwidth_l; 2191 double *surface_read_bandwidth_c; 2192 double *prefetch_bandwidth_l; 2193 double *prefetch_bandwidth_c; 2194 double *prefetch_bandwidth_max; 2195 double *excess_vactive_fill_bw_l; 2196 double *excess_vactive_fill_bw_c; 2197 double *cursor_bw; 2198 double *dpte_row_bw; 2199 double *meta_row_bw; 2200 double *prefetch_cursor_bw; 2201 double *prefetch_vmrow_bw; 2202 double *flip_bw; 2203 double *urgent_burst_factor_l; 2204 double *urgent_burst_factor_c; 2205 double *urgent_burst_factor_cursor; 2206 double *urgent_burst_factor_prefetch_l; 2207 double *urgent_burst_factor_prefetch_c; 2208 double *urgent_burst_factor_prefetch_cursor; 2209 }; 2210 2211 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params { 2212 /* inputs */ 2213 const struct dml2_display_cfg *display_cfg; 2214 bool mrq_present; 2215 unsigned int num_active_planes; 2216 unsigned int *num_of_dpp; 2217 unsigned int *meta_row_height_l; 2218 unsigned int *meta_row_height_c; 2219 unsigned int *meta_row_bytes_per_row_ub_l; 2220 unsigned int *meta_row_bytes_per_row_ub_c; 2221 unsigned int *dpte_row_height_l; 2222 unsigned int *dpte_row_height_c; 2223 unsigned int *dpte_bytes_per_row_l; 2224 unsigned int *dpte_bytes_per_row_c; 2225 unsigned int *byte_per_pix_l; 2226 unsigned int *byte_per_pix_c; 2227 unsigned int *swath_width_l; 2228 unsigned int *swath_width_c; 2229 unsigned int *swath_height_l; 2230 unsigned int *swath_height_c; 2231 double latency_to_hide_us; 2232 2233 /* outputs */ 2234 unsigned int *bytes_required_l; 2235 unsigned int *bytes_required_c; 2236 }; 2237 2238 // A list of overridable function pointers in the core 2239 // shared calculation library. 2240 struct dml2_core_shared_calculation_funcs { 2241 void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p); 2242 }; 2243 2244 struct dml2_core_internal_scratch { 2245 // Scratch space for function locals 2246 struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals; 2247 struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals; 2248 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 2249 struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals; 2250 struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals; 2251 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_locals CheckGlobalPrefetchAdmissibility_locals; 2252 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals; 2253 struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals; 2254 struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals; 2255 struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals; 2256 struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals; 2257 struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals; 2258 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals; 2259 struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals; 2260 2261 // Scratch space for function params 2262 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 2263 struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params; 2264 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params; 2265 struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params; 2266 struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params; 2267 struct dml2_core_calcs_CheckGlobalPrefetchAdmissibility_params CheckGlobalPrefetchAdmissibility_params; 2268 struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params; 2269 struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params; 2270 struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params; 2271 struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals; 2272 struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params; 2273 struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params; 2274 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params; 2275 }; 2276 2277 //struct dml2_svp_mode_override; 2278 struct dml2_core_internal_display_mode_lib { 2279 struct dml2_core_ip_params ip; 2280 struct dml2_soc_bb soc; 2281 struct dml2_ip_capabilities ip_caps; 2282 2283 //@brief Mode Support and Mode programming struct 2284 // Used to hold input; intermediate and output of the calculations 2285 struct dml2_core_internal_mode_support ms; // struct for mode support 2286 struct dml2_core_internal_mode_program mp; // struct for mode programming 2287 // Available overridable calculators for core_shared. 2288 // if null, core_shared will use default calculators. 2289 struct dml2_core_shared_calculation_funcs funcs; 2290 2291 struct dml2_core_internal_scratch scratch; 2292 }; 2293 2294 struct dml2_core_calcs_mode_support_ex { 2295 struct dml2_core_internal_display_mode_lib *mode_lib; 2296 const struct dml2_display_cfg *in_display_cfg; 2297 const struct dml2_mcg_min_clock_table *min_clk_table; 2298 int min_clk_index; 2299 //unsigned int in_state_index; 2300 struct dml2_core_internal_mode_support_info *out_evaluation_info; 2301 }; 2302 2303 struct core_display_cfg_support_info; 2304 2305 struct dml2_core_calcs_mode_programming_ex { 2306 struct dml2_core_internal_display_mode_lib *mode_lib; 2307 const struct dml2_display_cfg *in_display_cfg; 2308 const struct dml2_mcg_min_clock_table *min_clk_table; 2309 const struct core_display_cfg_support_info *cfg_support_info; 2310 int min_clk_index; 2311 struct dml2_display_cfg_programming *programming; 2312 }; 2313 2314 #endif 2315