1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2011 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/gfp.h>
11
12
13 /*
14 * qla2x00_mailbox_command
15 * Issue mailbox command and waits for completion.
16 *
17 * Input:
18 * ha = adapter block pointer.
19 * mcp = driver internal mbx struct pointer.
20 *
21 * Output:
22 * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
23 *
24 * Returns:
25 * 0 : QLA_SUCCESS = cmd performed success
26 * 1 : QLA_FUNCTION_FAILED (error encountered)
27 * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
28 *
29 * Context:
30 * Kernel context.
31 */
32 static int
qla2x00_mailbox_command(scsi_qla_host_t * vha,mbx_cmd_t * mcp)33 qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
34 {
35 int rval;
36 unsigned long flags = 0;
37 device_reg_t __iomem *reg;
38 uint8_t abort_active;
39 uint8_t io_lock_on;
40 uint16_t command = 0;
41 uint16_t *iptr;
42 uint16_t __iomem *optr;
43 uint32_t cnt;
44 uint32_t mboxes;
45 unsigned long wait_time;
46 struct qla_hw_data *ha = vha->hw;
47 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
48
49 ql_dbg(ql_dbg_mbx, base_vha, 0x1000, "Entered %s.\n", __func__);
50
51 if (ha->pdev->error_state > pci_channel_io_frozen) {
52 ql_log(ql_log_warn, base_vha, 0x1001,
53 "error_state is greater than pci_channel_io_frozen, "
54 "exiting.\n");
55 return QLA_FUNCTION_TIMEOUT;
56 }
57
58 if (vha->device_flags & DFLG_DEV_FAILED) {
59 ql_log(ql_log_warn, base_vha, 0x1002,
60 "Device in failed state, exiting.\n");
61 return QLA_FUNCTION_TIMEOUT;
62 }
63
64 reg = ha->iobase;
65 io_lock_on = base_vha->flags.init_done;
66
67 rval = QLA_SUCCESS;
68 abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
69
70
71 if (ha->flags.pci_channel_io_perm_failure) {
72 ql_log(ql_log_warn, base_vha, 0x1003,
73 "Perm failure on EEH timeout MBX, exiting.\n");
74 return QLA_FUNCTION_TIMEOUT;
75 }
76
77 if (ha->flags.isp82xx_fw_hung) {
78 /* Setting Link-Down error */
79 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
80 ql_log(ql_log_warn, base_vha, 0x1004,
81 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
82 return QLA_FUNCTION_TIMEOUT;
83 }
84
85 /*
86 * Wait for active mailbox commands to finish by waiting at most tov
87 * seconds. This is to serialize actual issuing of mailbox cmds during
88 * non ISP abort time.
89 */
90 if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
91 /* Timeout occurred. Return error. */
92 ql_log(ql_log_warn, base_vha, 0x1005,
93 "Cmd access timeout, Exiting.\n");
94 return QLA_FUNCTION_TIMEOUT;
95 }
96
97 ha->flags.mbox_busy = 1;
98 /* Save mailbox command for debug */
99 ha->mcp = mcp;
100
101 ql_dbg(ql_dbg_mbx, base_vha, 0x1006,
102 "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
103
104 spin_lock_irqsave(&ha->hardware_lock, flags);
105
106 /* Load mailbox registers. */
107 if (IS_QLA82XX(ha))
108 optr = (uint16_t __iomem *)®->isp82.mailbox_in[0];
109 else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha))
110 optr = (uint16_t __iomem *)®->isp24.mailbox0;
111 else
112 optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0);
113
114 iptr = mcp->mb;
115 command = mcp->mb[0];
116 mboxes = mcp->out_mb;
117
118 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
119 if (IS_QLA2200(ha) && cnt == 8)
120 optr =
121 (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 8);
122 if (mboxes & BIT_0)
123 WRT_REG_WORD(optr, *iptr);
124
125 mboxes >>= 1;
126 optr++;
127 iptr++;
128 }
129
130 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1111,
131 "Loaded MBX registers (displayed in bytes) =.\n");
132 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1112,
133 (uint8_t *)mcp->mb, 16);
134 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1113,
135 ".\n");
136 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1114,
137 ((uint8_t *)mcp->mb + 0x10), 16);
138 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1115,
139 ".\n");
140 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1116,
141 ((uint8_t *)mcp->mb + 0x20), 8);
142 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1117,
143 "I/O Address = %p.\n", optr);
144 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x100e);
145
146 /* Issue set host interrupt command to send cmd out. */
147 ha->flags.mbox_int = 0;
148 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
149
150 /* Unlock mbx registers and wait for interrupt */
151 ql_dbg(ql_dbg_mbx, base_vha, 0x100f,
152 "Going to unlock irq & waiting for interrupts. "
153 "jiffies=%lx.\n", jiffies);
154
155 /* Wait for mbx cmd completion until timeout */
156
157 if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
158 set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
159
160 if (IS_QLA82XX(ha)) {
161 if (RD_REG_DWORD(®->isp82.hint) &
162 HINT_MBX_INT_PENDING) {
163 spin_unlock_irqrestore(&ha->hardware_lock,
164 flags);
165 ha->flags.mbox_busy = 0;
166 ql_dbg(ql_dbg_mbx, base_vha, 0x1010,
167 "Pending mailbox timeout, exiting.\n");
168 rval = QLA_FUNCTION_TIMEOUT;
169 goto premature_exit;
170 }
171 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING);
172 } else if (IS_FWI2_CAPABLE(ha))
173 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT);
174 else
175 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT);
176 spin_unlock_irqrestore(&ha->hardware_lock, flags);
177
178 wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
179
180 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
181
182 } else {
183 ql_dbg(ql_dbg_mbx, base_vha, 0x1011,
184 "Cmd=%x Polling Mode.\n", command);
185
186 if (IS_QLA82XX(ha)) {
187 if (RD_REG_DWORD(®->isp82.hint) &
188 HINT_MBX_INT_PENDING) {
189 spin_unlock_irqrestore(&ha->hardware_lock,
190 flags);
191 ha->flags.mbox_busy = 0;
192 ql_dbg(ql_dbg_mbx, base_vha, 0x1012,
193 "Pending mailbox timeout, exiting.\n");
194 rval = QLA_FUNCTION_TIMEOUT;
195 goto premature_exit;
196 }
197 WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING);
198 } else if (IS_FWI2_CAPABLE(ha))
199 WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT);
200 else
201 WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT);
202 spin_unlock_irqrestore(&ha->hardware_lock, flags);
203
204 wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
205 while (!ha->flags.mbox_int) {
206 if (time_after(jiffies, wait_time))
207 break;
208
209 /* Check for pending interrupts. */
210 qla2x00_poll(ha->rsp_q_map[0]);
211
212 if (!ha->flags.mbox_int &&
213 !(IS_QLA2200(ha) &&
214 command == MBC_LOAD_RISC_RAM_EXTENDED))
215 msleep(10);
216 } /* while */
217 ql_dbg(ql_dbg_mbx, base_vha, 0x1013,
218 "Waited %d sec.\n",
219 (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
220 }
221
222 /* Check whether we timed out */
223 if (ha->flags.mbox_int) {
224 uint16_t *iptr2;
225
226 ql_dbg(ql_dbg_mbx, base_vha, 0x1014,
227 "Cmd=%x completed.\n", command);
228
229 /* Got interrupt. Clear the flag. */
230 ha->flags.mbox_int = 0;
231 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
232
233 if (ha->flags.isp82xx_fw_hung) {
234 ha->flags.mbox_busy = 0;
235 /* Setting Link-Down error */
236 mcp->mb[0] = MBS_LINK_DOWN_ERROR;
237 ha->mcp = NULL;
238 rval = QLA_FUNCTION_FAILED;
239 ql_log(ql_log_warn, base_vha, 0x1015,
240 "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
241 goto premature_exit;
242 }
243
244 if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
245 rval = QLA_FUNCTION_FAILED;
246
247 /* Load return mailbox registers. */
248 iptr2 = mcp->mb;
249 iptr = (uint16_t *)&ha->mailbox_out[0];
250 mboxes = mcp->in_mb;
251 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
252 if (mboxes & BIT_0)
253 *iptr2 = *iptr;
254
255 mboxes >>= 1;
256 iptr2++;
257 iptr++;
258 }
259 } else {
260
261 uint16_t mb0;
262 uint32_t ictrl;
263
264 if (IS_FWI2_CAPABLE(ha)) {
265 mb0 = RD_REG_WORD(®->isp24.mailbox0);
266 ictrl = RD_REG_DWORD(®->isp24.ictrl);
267 } else {
268 mb0 = RD_MAILBOX_REG(ha, ®->isp, 0);
269 ictrl = RD_REG_WORD(®->isp.ictrl);
270 }
271 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1119,
272 "MBX Command timeout for cmd %x.\n", command);
273 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111a,
274 "iocontrol=%x jiffies=%lx.\n", ictrl, jiffies);
275 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x111b,
276 "mb[0] = 0x%x.\n", mb0);
277 ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, base_vha, 0x1019);
278
279 rval = QLA_FUNCTION_TIMEOUT;
280 }
281
282 ha->flags.mbox_busy = 0;
283
284 /* Clean up */
285 ha->mcp = NULL;
286
287 if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
288 ql_dbg(ql_dbg_mbx, base_vha, 0x101a,
289 "Checking for additional resp interrupt.\n");
290
291 /* polling mode for non isp_abort commands. */
292 qla2x00_poll(ha->rsp_q_map[0]);
293 }
294
295 if (rval == QLA_FUNCTION_TIMEOUT &&
296 mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
297 if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
298 ha->flags.eeh_busy) {
299 /* not in dpc. schedule it for dpc to take over. */
300 ql_dbg(ql_dbg_mbx, base_vha, 0x101b,
301 "Timeout, schedule isp_abort_needed.\n");
302
303 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
304 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
305 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
306 if (IS_QLA82XX(ha)) {
307 ql_dbg(ql_dbg_mbx, vha, 0x112a,
308 "disabling pause transmit on port "
309 "0 & 1.\n");
310 qla82xx_wr_32(ha,
311 QLA82XX_CRB_NIU + 0x98,
312 CRB_NIU_XG_PAUSE_CTL_P0|
313 CRB_NIU_XG_PAUSE_CTL_P1);
314 }
315 ql_log(ql_log_info, base_vha, 0x101c,
316 "Mailbox cmd timeout occured. "
317 "Scheduling ISP abort eeh_busy=0x%x.\n",
318 ha->flags.eeh_busy);
319 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
320 qla2xxx_wake_dpc(vha);
321 }
322 } else if (!abort_active) {
323 /* call abort directly since we are in the DPC thread */
324 ql_dbg(ql_dbg_mbx, base_vha, 0x101d,
325 "Timeout, calling abort_isp.\n");
326
327 if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
328 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
329 !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
330 if (IS_QLA82XX(ha)) {
331 ql_dbg(ql_dbg_mbx, vha, 0x112b,
332 "disabling pause transmit on port "
333 "0 & 1.\n");
334 qla82xx_wr_32(ha,
335 QLA82XX_CRB_NIU + 0x98,
336 CRB_NIU_XG_PAUSE_CTL_P0|
337 CRB_NIU_XG_PAUSE_CTL_P1);
338 }
339 ql_log(ql_log_info, base_vha, 0x101e,
340 "Mailbox cmd timeout occured. "
341 "Scheduling ISP abort.\n");
342
343 set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
344 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
345 /* Allow next mbx cmd to come in. */
346 complete(&ha->mbx_cmd_comp);
347 if (ha->isp_ops->abort_isp(vha)) {
348 /* Failed. retry later. */
349 set_bit(ISP_ABORT_NEEDED,
350 &vha->dpc_flags);
351 }
352 clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
353 ql_dbg(ql_dbg_mbx, base_vha, 0x101f,
354 "Finished abort_isp.\n");
355 goto mbx_done;
356 }
357 }
358 }
359
360 premature_exit:
361 /* Allow next mbx cmd to come in. */
362 complete(&ha->mbx_cmd_comp);
363
364 mbx_done:
365 if (rval) {
366 ql_dbg(ql_dbg_mbx, base_vha, 0x1020,
367 "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, cmd=%x ****.\n",
368 mcp->mb[0], mcp->mb[1], mcp->mb[2], command);
369 } else {
370 ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
371 }
372
373 return rval;
374 }
375
376 int
qla2x00_load_ram(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t risc_addr,uint32_t risc_code_size)377 qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
378 uint32_t risc_code_size)
379 {
380 int rval;
381 struct qla_hw_data *ha = vha->hw;
382 mbx_cmd_t mc;
383 mbx_cmd_t *mcp = &mc;
384
385 ql_dbg(ql_dbg_mbx, vha, 0x1022, "Entered %s.\n", __func__);
386
387 if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
388 mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
389 mcp->mb[8] = MSW(risc_addr);
390 mcp->out_mb = MBX_8|MBX_0;
391 } else {
392 mcp->mb[0] = MBC_LOAD_RISC_RAM;
393 mcp->out_mb = MBX_0;
394 }
395 mcp->mb[1] = LSW(risc_addr);
396 mcp->mb[2] = MSW(req_dma);
397 mcp->mb[3] = LSW(req_dma);
398 mcp->mb[6] = MSW(MSD(req_dma));
399 mcp->mb[7] = LSW(MSD(req_dma));
400 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
401 if (IS_FWI2_CAPABLE(ha)) {
402 mcp->mb[4] = MSW(risc_code_size);
403 mcp->mb[5] = LSW(risc_code_size);
404 mcp->out_mb |= MBX_5|MBX_4;
405 } else {
406 mcp->mb[4] = LSW(risc_code_size);
407 mcp->out_mb |= MBX_4;
408 }
409
410 mcp->in_mb = MBX_0;
411 mcp->tov = MBX_TOV_SECONDS;
412 mcp->flags = 0;
413 rval = qla2x00_mailbox_command(vha, mcp);
414
415 if (rval != QLA_SUCCESS) {
416 ql_dbg(ql_dbg_mbx, vha, 0x1023,
417 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
418 } else {
419 ql_dbg(ql_dbg_mbx, vha, 0x1024, "Done %s.\n", __func__);
420 }
421
422 return rval;
423 }
424
425 #define EXTENDED_BB_CREDITS BIT_0
426 /*
427 * qla2x00_execute_fw
428 * Start adapter firmware.
429 *
430 * Input:
431 * ha = adapter block pointer.
432 * TARGET_QUEUE_LOCK must be released.
433 * ADAPTER_STATE_LOCK must be released.
434 *
435 * Returns:
436 * qla2x00 local function return status code.
437 *
438 * Context:
439 * Kernel context.
440 */
441 int
qla2x00_execute_fw(scsi_qla_host_t * vha,uint32_t risc_addr)442 qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
443 {
444 int rval;
445 struct qla_hw_data *ha = vha->hw;
446 mbx_cmd_t mc;
447 mbx_cmd_t *mcp = &mc;
448
449 ql_dbg(ql_dbg_mbx, vha, 0x1025, "Entered %s.\n", __func__);
450
451 mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
452 mcp->out_mb = MBX_0;
453 mcp->in_mb = MBX_0;
454 if (IS_FWI2_CAPABLE(ha)) {
455 mcp->mb[1] = MSW(risc_addr);
456 mcp->mb[2] = LSW(risc_addr);
457 mcp->mb[3] = 0;
458 if (IS_QLA81XX(ha)) {
459 struct nvram_81xx *nv = ha->nvram;
460 mcp->mb[4] = (nv->enhanced_features &
461 EXTENDED_BB_CREDITS);
462 } else
463 mcp->mb[4] = 0;
464 mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
465 mcp->in_mb |= MBX_1;
466 } else {
467 mcp->mb[1] = LSW(risc_addr);
468 mcp->out_mb |= MBX_1;
469 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
470 mcp->mb[2] = 0;
471 mcp->out_mb |= MBX_2;
472 }
473 }
474
475 mcp->tov = MBX_TOV_SECONDS;
476 mcp->flags = 0;
477 rval = qla2x00_mailbox_command(vha, mcp);
478
479 if (rval != QLA_SUCCESS) {
480 ql_dbg(ql_dbg_mbx, vha, 0x1026,
481 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
482 } else {
483 if (IS_FWI2_CAPABLE(ha)) {
484 ql_dbg(ql_dbg_mbx, vha, 0x1027,
485 "Done exchanges=%x.\n", mcp->mb[1]);
486 } else {
487 ql_dbg(ql_dbg_mbx, vha, 0x1028, "Done %s.\n", __func__);
488 }
489 }
490
491 return rval;
492 }
493
494 /*
495 * qla2x00_get_fw_version
496 * Get firmware version.
497 *
498 * Input:
499 * ha: adapter state pointer.
500 * major: pointer for major number.
501 * minor: pointer for minor number.
502 * subminor: pointer for subminor number.
503 *
504 * Returns:
505 * qla2x00 local function return status code.
506 *
507 * Context:
508 * Kernel context.
509 */
510 int
qla2x00_get_fw_version(scsi_qla_host_t * vha,uint16_t * major,uint16_t * minor,uint16_t * subminor,uint16_t * attributes,uint32_t * memory,uint8_t * mpi,uint32_t * mpi_caps,uint8_t * phy)511 qla2x00_get_fw_version(scsi_qla_host_t *vha, uint16_t *major, uint16_t *minor,
512 uint16_t *subminor, uint16_t *attributes, uint32_t *memory, uint8_t *mpi,
513 uint32_t *mpi_caps, uint8_t *phy)
514 {
515 int rval;
516 mbx_cmd_t mc;
517 mbx_cmd_t *mcp = &mc;
518
519 ql_dbg(ql_dbg_mbx, vha, 0x1029, "Entered %s.\n", __func__);
520
521 mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
522 mcp->out_mb = MBX_0;
523 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
524 if (IS_QLA81XX(vha->hw))
525 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
526 mcp->flags = 0;
527 mcp->tov = MBX_TOV_SECONDS;
528 rval = qla2x00_mailbox_command(vha, mcp);
529 if (rval != QLA_SUCCESS)
530 goto failed;
531
532 /* Return mailbox data. */
533 *major = mcp->mb[1];
534 *minor = mcp->mb[2];
535 *subminor = mcp->mb[3];
536 *attributes = mcp->mb[6];
537 if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
538 *memory = 0x1FFFF; /* Defaults to 128KB. */
539 else
540 *memory = (mcp->mb[5] << 16) | mcp->mb[4];
541 if (IS_QLA81XX(vha->hw)) {
542 mpi[0] = mcp->mb[10] & 0xff;
543 mpi[1] = mcp->mb[11] >> 8;
544 mpi[2] = mcp->mb[11] & 0xff;
545 *mpi_caps = (mcp->mb[12] << 16) | mcp->mb[13];
546 phy[0] = mcp->mb[8] & 0xff;
547 phy[1] = mcp->mb[9] >> 8;
548 phy[2] = mcp->mb[9] & 0xff;
549 }
550 failed:
551 if (rval != QLA_SUCCESS) {
552 /*EMPTY*/
553 ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
554 } else {
555 /*EMPTY*/
556 ql_dbg(ql_dbg_mbx, vha, 0x102b, "Done %s.\n", __func__);
557 }
558 return rval;
559 }
560
561 /*
562 * qla2x00_get_fw_options
563 * Set firmware options.
564 *
565 * Input:
566 * ha = adapter block pointer.
567 * fwopt = pointer for firmware options.
568 *
569 * Returns:
570 * qla2x00 local function return status code.
571 *
572 * Context:
573 * Kernel context.
574 */
575 int
qla2x00_get_fw_options(scsi_qla_host_t * vha,uint16_t * fwopts)576 qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
577 {
578 int rval;
579 mbx_cmd_t mc;
580 mbx_cmd_t *mcp = &mc;
581
582 ql_dbg(ql_dbg_mbx, vha, 0x102c, "Entered %s.\n", __func__);
583
584 mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
585 mcp->out_mb = MBX_0;
586 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
587 mcp->tov = MBX_TOV_SECONDS;
588 mcp->flags = 0;
589 rval = qla2x00_mailbox_command(vha, mcp);
590
591 if (rval != QLA_SUCCESS) {
592 /*EMPTY*/
593 ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
594 } else {
595 fwopts[0] = mcp->mb[0];
596 fwopts[1] = mcp->mb[1];
597 fwopts[2] = mcp->mb[2];
598 fwopts[3] = mcp->mb[3];
599
600 ql_dbg(ql_dbg_mbx, vha, 0x102e, "Done %s.\n", __func__);
601 }
602
603 return rval;
604 }
605
606
607 /*
608 * qla2x00_set_fw_options
609 * Set firmware options.
610 *
611 * Input:
612 * ha = adapter block pointer.
613 * fwopt = pointer for firmware options.
614 *
615 * Returns:
616 * qla2x00 local function return status code.
617 *
618 * Context:
619 * Kernel context.
620 */
621 int
qla2x00_set_fw_options(scsi_qla_host_t * vha,uint16_t * fwopts)622 qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
623 {
624 int rval;
625 mbx_cmd_t mc;
626 mbx_cmd_t *mcp = &mc;
627
628 ql_dbg(ql_dbg_mbx, vha, 0x102f, "Entered %s.\n", __func__);
629
630 mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
631 mcp->mb[1] = fwopts[1];
632 mcp->mb[2] = fwopts[2];
633 mcp->mb[3] = fwopts[3];
634 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
635 mcp->in_mb = MBX_0;
636 if (IS_FWI2_CAPABLE(vha->hw)) {
637 mcp->in_mb |= MBX_1;
638 } else {
639 mcp->mb[10] = fwopts[10];
640 mcp->mb[11] = fwopts[11];
641 mcp->mb[12] = 0; /* Undocumented, but used */
642 mcp->out_mb |= MBX_12|MBX_11|MBX_10;
643 }
644 mcp->tov = MBX_TOV_SECONDS;
645 mcp->flags = 0;
646 rval = qla2x00_mailbox_command(vha, mcp);
647
648 fwopts[0] = mcp->mb[0];
649
650 if (rval != QLA_SUCCESS) {
651 /*EMPTY*/
652 ql_dbg(ql_dbg_mbx, vha, 0x1030,
653 "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
654 } else {
655 /*EMPTY*/
656 ql_dbg(ql_dbg_mbx, vha, 0x1031, "Done %s.\n", __func__);
657 }
658
659 return rval;
660 }
661
662 /*
663 * qla2x00_mbx_reg_test
664 * Mailbox register wrap test.
665 *
666 * Input:
667 * ha = adapter block pointer.
668 * TARGET_QUEUE_LOCK must be released.
669 * ADAPTER_STATE_LOCK must be released.
670 *
671 * Returns:
672 * qla2x00 local function return status code.
673 *
674 * Context:
675 * Kernel context.
676 */
677 int
qla2x00_mbx_reg_test(scsi_qla_host_t * vha)678 qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
679 {
680 int rval;
681 mbx_cmd_t mc;
682 mbx_cmd_t *mcp = &mc;
683
684 ql_dbg(ql_dbg_mbx, vha, 0x1032, "Entered %s.\n", __func__);
685
686 mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
687 mcp->mb[1] = 0xAAAA;
688 mcp->mb[2] = 0x5555;
689 mcp->mb[3] = 0xAA55;
690 mcp->mb[4] = 0x55AA;
691 mcp->mb[5] = 0xA5A5;
692 mcp->mb[6] = 0x5A5A;
693 mcp->mb[7] = 0x2525;
694 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
695 mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
696 mcp->tov = MBX_TOV_SECONDS;
697 mcp->flags = 0;
698 rval = qla2x00_mailbox_command(vha, mcp);
699
700 if (rval == QLA_SUCCESS) {
701 if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
702 mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
703 rval = QLA_FUNCTION_FAILED;
704 if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
705 mcp->mb[7] != 0x2525)
706 rval = QLA_FUNCTION_FAILED;
707 }
708
709 if (rval != QLA_SUCCESS) {
710 /*EMPTY*/
711 ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
712 } else {
713 /*EMPTY*/
714 ql_dbg(ql_dbg_mbx, vha, 0x1034, "Done %s.\n", __func__);
715 }
716
717 return rval;
718 }
719
720 /*
721 * qla2x00_verify_checksum
722 * Verify firmware checksum.
723 *
724 * Input:
725 * ha = adapter block pointer.
726 * TARGET_QUEUE_LOCK must be released.
727 * ADAPTER_STATE_LOCK must be released.
728 *
729 * Returns:
730 * qla2x00 local function return status code.
731 *
732 * Context:
733 * Kernel context.
734 */
735 int
qla2x00_verify_checksum(scsi_qla_host_t * vha,uint32_t risc_addr)736 qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
737 {
738 int rval;
739 mbx_cmd_t mc;
740 mbx_cmd_t *mcp = &mc;
741
742 ql_dbg(ql_dbg_mbx, vha, 0x1035, "Entered %s.\n", __func__);
743
744 mcp->mb[0] = MBC_VERIFY_CHECKSUM;
745 mcp->out_mb = MBX_0;
746 mcp->in_mb = MBX_0;
747 if (IS_FWI2_CAPABLE(vha->hw)) {
748 mcp->mb[1] = MSW(risc_addr);
749 mcp->mb[2] = LSW(risc_addr);
750 mcp->out_mb |= MBX_2|MBX_1;
751 mcp->in_mb |= MBX_2|MBX_1;
752 } else {
753 mcp->mb[1] = LSW(risc_addr);
754 mcp->out_mb |= MBX_1;
755 mcp->in_mb |= MBX_1;
756 }
757
758 mcp->tov = MBX_TOV_SECONDS;
759 mcp->flags = 0;
760 rval = qla2x00_mailbox_command(vha, mcp);
761
762 if (rval != QLA_SUCCESS) {
763 ql_dbg(ql_dbg_mbx, vha, 0x1036,
764 "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
765 (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
766 } else {
767 ql_dbg(ql_dbg_mbx, vha, 0x1037, "Done %s.\n", __func__);
768 }
769
770 return rval;
771 }
772
773 /*
774 * qla2x00_issue_iocb
775 * Issue IOCB using mailbox command
776 *
777 * Input:
778 * ha = adapter state pointer.
779 * buffer = buffer pointer.
780 * phys_addr = physical address of buffer.
781 * size = size of buffer.
782 * TARGET_QUEUE_LOCK must be released.
783 * ADAPTER_STATE_LOCK must be released.
784 *
785 * Returns:
786 * qla2x00 local function return status code.
787 *
788 * Context:
789 * Kernel context.
790 */
791 int
qla2x00_issue_iocb_timeout(scsi_qla_host_t * vha,void * buffer,dma_addr_t phys_addr,size_t size,uint32_t tov)792 qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
793 dma_addr_t phys_addr, size_t size, uint32_t tov)
794 {
795 int rval;
796 mbx_cmd_t mc;
797 mbx_cmd_t *mcp = &mc;
798
799 ql_dbg(ql_dbg_mbx, vha, 0x1038, "Entered %s.\n", __func__);
800
801 mcp->mb[0] = MBC_IOCB_COMMAND_A64;
802 mcp->mb[1] = 0;
803 mcp->mb[2] = MSW(phys_addr);
804 mcp->mb[3] = LSW(phys_addr);
805 mcp->mb[6] = MSW(MSD(phys_addr));
806 mcp->mb[7] = LSW(MSD(phys_addr));
807 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
808 mcp->in_mb = MBX_2|MBX_0;
809 mcp->tov = tov;
810 mcp->flags = 0;
811 rval = qla2x00_mailbox_command(vha, mcp);
812
813 if (rval != QLA_SUCCESS) {
814 /*EMPTY*/
815 ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
816 } else {
817 sts_entry_t *sts_entry = (sts_entry_t *) buffer;
818
819 /* Mask reserved bits. */
820 sts_entry->entry_status &=
821 IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
822 ql_dbg(ql_dbg_mbx, vha, 0x103a, "Done %s.\n", __func__);
823 }
824
825 return rval;
826 }
827
828 int
qla2x00_issue_iocb(scsi_qla_host_t * vha,void * buffer,dma_addr_t phys_addr,size_t size)829 qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
830 size_t size)
831 {
832 return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
833 MBX_TOV_SECONDS);
834 }
835
836 /*
837 * qla2x00_abort_command
838 * Abort command aborts a specified IOCB.
839 *
840 * Input:
841 * ha = adapter block pointer.
842 * sp = SB structure pointer.
843 *
844 * Returns:
845 * qla2x00 local function return status code.
846 *
847 * Context:
848 * Kernel context.
849 */
850 int
qla2x00_abort_command(srb_t * sp)851 qla2x00_abort_command(srb_t *sp)
852 {
853 unsigned long flags = 0;
854 int rval;
855 uint32_t handle = 0;
856 mbx_cmd_t mc;
857 mbx_cmd_t *mcp = &mc;
858 fc_port_t *fcport = sp->fcport;
859 scsi_qla_host_t *vha = fcport->vha;
860 struct qla_hw_data *ha = vha->hw;
861 struct req_que *req = vha->req;
862
863 ql_dbg(ql_dbg_mbx, vha, 0x103b, "Entered %s.\n", __func__);
864
865 spin_lock_irqsave(&ha->hardware_lock, flags);
866 for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
867 if (req->outstanding_cmds[handle] == sp)
868 break;
869 }
870 spin_unlock_irqrestore(&ha->hardware_lock, flags);
871
872 if (handle == MAX_OUTSTANDING_COMMANDS) {
873 /* command not found */
874 return QLA_FUNCTION_FAILED;
875 }
876
877 mcp->mb[0] = MBC_ABORT_COMMAND;
878 if (HAS_EXTENDED_IDS(ha))
879 mcp->mb[1] = fcport->loop_id;
880 else
881 mcp->mb[1] = fcport->loop_id << 8;
882 mcp->mb[2] = (uint16_t)handle;
883 mcp->mb[3] = (uint16_t)(handle >> 16);
884 mcp->mb[6] = (uint16_t)sp->cmd->device->lun;
885 mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
886 mcp->in_mb = MBX_0;
887 mcp->tov = MBX_TOV_SECONDS;
888 mcp->flags = 0;
889 rval = qla2x00_mailbox_command(vha, mcp);
890
891 if (rval != QLA_SUCCESS) {
892 ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
893 } else {
894 ql_dbg(ql_dbg_mbx, vha, 0x103d, "Done %s.\n", __func__);
895 }
896
897 return rval;
898 }
899
900 int
qla2x00_abort_target(struct fc_port * fcport,unsigned int l,int tag)901 qla2x00_abort_target(struct fc_port *fcport, unsigned int l, int tag)
902 {
903 int rval, rval2;
904 mbx_cmd_t mc;
905 mbx_cmd_t *mcp = &mc;
906 scsi_qla_host_t *vha;
907 struct req_que *req;
908 struct rsp_que *rsp;
909
910 l = l;
911 vha = fcport->vha;
912
913 ql_dbg(ql_dbg_mbx, vha, 0x103e, "Entered %s.\n", __func__);
914
915 req = vha->hw->req_q_map[0];
916 rsp = req->rsp;
917 mcp->mb[0] = MBC_ABORT_TARGET;
918 mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
919 if (HAS_EXTENDED_IDS(vha->hw)) {
920 mcp->mb[1] = fcport->loop_id;
921 mcp->mb[10] = 0;
922 mcp->out_mb |= MBX_10;
923 } else {
924 mcp->mb[1] = fcport->loop_id << 8;
925 }
926 mcp->mb[2] = vha->hw->loop_reset_delay;
927 mcp->mb[9] = vha->vp_idx;
928
929 mcp->in_mb = MBX_0;
930 mcp->tov = MBX_TOV_SECONDS;
931 mcp->flags = 0;
932 rval = qla2x00_mailbox_command(vha, mcp);
933 if (rval != QLA_SUCCESS) {
934 ql_dbg(ql_dbg_mbx, vha, 0x103f, "Failed=%x.\n", rval);
935 }
936
937 /* Issue marker IOCB. */
938 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
939 MK_SYNC_ID);
940 if (rval2 != QLA_SUCCESS) {
941 ql_dbg(ql_dbg_mbx, vha, 0x1040,
942 "Failed to issue marker IOCB (%x).\n", rval2);
943 } else {
944 ql_dbg(ql_dbg_mbx, vha, 0x1041, "Done %s.\n", __func__);
945 }
946
947 return rval;
948 }
949
950 int
qla2x00_lun_reset(struct fc_port * fcport,unsigned int l,int tag)951 qla2x00_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
952 {
953 int rval, rval2;
954 mbx_cmd_t mc;
955 mbx_cmd_t *mcp = &mc;
956 scsi_qla_host_t *vha;
957 struct req_que *req;
958 struct rsp_que *rsp;
959
960 vha = fcport->vha;
961
962 ql_dbg(ql_dbg_mbx, vha, 0x1042, "Entered %s.\n", __func__);
963
964 req = vha->hw->req_q_map[0];
965 rsp = req->rsp;
966 mcp->mb[0] = MBC_LUN_RESET;
967 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
968 if (HAS_EXTENDED_IDS(vha->hw))
969 mcp->mb[1] = fcport->loop_id;
970 else
971 mcp->mb[1] = fcport->loop_id << 8;
972 mcp->mb[2] = l;
973 mcp->mb[3] = 0;
974 mcp->mb[9] = vha->vp_idx;
975
976 mcp->in_mb = MBX_0;
977 mcp->tov = MBX_TOV_SECONDS;
978 mcp->flags = 0;
979 rval = qla2x00_mailbox_command(vha, mcp);
980 if (rval != QLA_SUCCESS) {
981 ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
982 }
983
984 /* Issue marker IOCB. */
985 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
986 MK_SYNC_ID_LUN);
987 if (rval2 != QLA_SUCCESS) {
988 ql_dbg(ql_dbg_mbx, vha, 0x1044,
989 "Failed to issue marker IOCB (%x).\n", rval2);
990 } else {
991 ql_dbg(ql_dbg_mbx, vha, 0x1045, "Done %s.\n", __func__);
992 }
993
994 return rval;
995 }
996
997 /*
998 * qla2x00_get_adapter_id
999 * Get adapter ID and topology.
1000 *
1001 * Input:
1002 * ha = adapter block pointer.
1003 * id = pointer for loop ID.
1004 * al_pa = pointer for AL_PA.
1005 * area = pointer for area.
1006 * domain = pointer for domain.
1007 * top = pointer for topology.
1008 * TARGET_QUEUE_LOCK must be released.
1009 * ADAPTER_STATE_LOCK must be released.
1010 *
1011 * Returns:
1012 * qla2x00 local function return status code.
1013 *
1014 * Context:
1015 * Kernel context.
1016 */
1017 int
qla2x00_get_adapter_id(scsi_qla_host_t * vha,uint16_t * id,uint8_t * al_pa,uint8_t * area,uint8_t * domain,uint16_t * top,uint16_t * sw_cap)1018 qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
1019 uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
1020 {
1021 int rval;
1022 mbx_cmd_t mc;
1023 mbx_cmd_t *mcp = &mc;
1024
1025 ql_dbg(ql_dbg_mbx, vha, 0x1046, "Entered %s.\n", __func__);
1026
1027 mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
1028 mcp->mb[9] = vha->vp_idx;
1029 mcp->out_mb = MBX_9|MBX_0;
1030 mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1031 if (IS_QLA8XXX_TYPE(vha->hw))
1032 mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
1033 mcp->tov = MBX_TOV_SECONDS;
1034 mcp->flags = 0;
1035 rval = qla2x00_mailbox_command(vha, mcp);
1036 if (mcp->mb[0] == MBS_COMMAND_ERROR)
1037 rval = QLA_COMMAND_ERROR;
1038 else if (mcp->mb[0] == MBS_INVALID_COMMAND)
1039 rval = QLA_INVALID_COMMAND;
1040
1041 /* Return data. */
1042 *id = mcp->mb[1];
1043 *al_pa = LSB(mcp->mb[2]);
1044 *area = MSB(mcp->mb[2]);
1045 *domain = LSB(mcp->mb[3]);
1046 *top = mcp->mb[6];
1047 *sw_cap = mcp->mb[7];
1048
1049 if (rval != QLA_SUCCESS) {
1050 /*EMPTY*/
1051 ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
1052 } else {
1053 ql_dbg(ql_dbg_mbx, vha, 0x1048, "Done %s.\n", __func__);
1054
1055 if (IS_QLA8XXX_TYPE(vha->hw)) {
1056 vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
1057 vha->fcoe_fcf_idx = mcp->mb[10];
1058 vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
1059 vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
1060 vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
1061 vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
1062 vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
1063 vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
1064 }
1065 }
1066
1067 return rval;
1068 }
1069
1070 /*
1071 * qla2x00_get_retry_cnt
1072 * Get current firmware login retry count and delay.
1073 *
1074 * Input:
1075 * ha = adapter block pointer.
1076 * retry_cnt = pointer to login retry count.
1077 * tov = pointer to login timeout value.
1078 *
1079 * Returns:
1080 * qla2x00 local function return status code.
1081 *
1082 * Context:
1083 * Kernel context.
1084 */
1085 int
qla2x00_get_retry_cnt(scsi_qla_host_t * vha,uint8_t * retry_cnt,uint8_t * tov,uint16_t * r_a_tov)1086 qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
1087 uint16_t *r_a_tov)
1088 {
1089 int rval;
1090 uint16_t ratov;
1091 mbx_cmd_t mc;
1092 mbx_cmd_t *mcp = &mc;
1093
1094 ql_dbg(ql_dbg_mbx, vha, 0x1049, "Entered %s.\n", __func__);
1095
1096 mcp->mb[0] = MBC_GET_RETRY_COUNT;
1097 mcp->out_mb = MBX_0;
1098 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1099 mcp->tov = MBX_TOV_SECONDS;
1100 mcp->flags = 0;
1101 rval = qla2x00_mailbox_command(vha, mcp);
1102
1103 if (rval != QLA_SUCCESS) {
1104 /*EMPTY*/
1105 ql_dbg(ql_dbg_mbx, vha, 0x104a,
1106 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1107 } else {
1108 /* Convert returned data and check our values. */
1109 *r_a_tov = mcp->mb[3] / 2;
1110 ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
1111 if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
1112 /* Update to the larger values */
1113 *retry_cnt = (uint8_t)mcp->mb[1];
1114 *tov = ratov;
1115 }
1116
1117 ql_dbg(ql_dbg_mbx, vha, 0x104b,
1118 "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
1119 }
1120
1121 return rval;
1122 }
1123
1124 /*
1125 * qla2x00_init_firmware
1126 * Initialize adapter firmware.
1127 *
1128 * Input:
1129 * ha = adapter block pointer.
1130 * dptr = Initialization control block pointer.
1131 * size = size of initialization control block.
1132 * TARGET_QUEUE_LOCK must be released.
1133 * ADAPTER_STATE_LOCK must be released.
1134 *
1135 * Returns:
1136 * qla2x00 local function return status code.
1137 *
1138 * Context:
1139 * Kernel context.
1140 */
1141 int
qla2x00_init_firmware(scsi_qla_host_t * vha,uint16_t size)1142 qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
1143 {
1144 int rval;
1145 mbx_cmd_t mc;
1146 mbx_cmd_t *mcp = &mc;
1147 struct qla_hw_data *ha = vha->hw;
1148
1149 ql_dbg(ql_dbg_mbx, vha, 0x104c, "Entered %s.\n", __func__);
1150
1151 if (IS_QLA82XX(ha) && ql2xdbwr)
1152 qla82xx_wr_32(ha, ha->nxdb_wr_ptr,
1153 (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
1154
1155 if (ha->flags.npiv_supported)
1156 mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
1157 else
1158 mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
1159
1160 mcp->mb[1] = 0;
1161 mcp->mb[2] = MSW(ha->init_cb_dma);
1162 mcp->mb[3] = LSW(ha->init_cb_dma);
1163 mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
1164 mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
1165 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1166 if (IS_QLA81XX(ha) && ha->ex_init_cb->ex_version) {
1167 mcp->mb[1] = BIT_0;
1168 mcp->mb[10] = MSW(ha->ex_init_cb_dma);
1169 mcp->mb[11] = LSW(ha->ex_init_cb_dma);
1170 mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
1171 mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
1172 mcp->mb[14] = sizeof(*ha->ex_init_cb);
1173 mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
1174 }
1175 mcp->in_mb = MBX_0;
1176 mcp->buf_size = size;
1177 mcp->flags = MBX_DMA_OUT;
1178 mcp->tov = MBX_TOV_SECONDS;
1179 rval = qla2x00_mailbox_command(vha, mcp);
1180
1181 if (rval != QLA_SUCCESS) {
1182 /*EMPTY*/
1183 ql_dbg(ql_dbg_mbx, vha, 0x104d,
1184 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
1185 } else {
1186 /*EMPTY*/
1187 ql_dbg(ql_dbg_mbx, vha, 0x104e, "Done %s.\n", __func__);
1188 }
1189
1190 return rval;
1191 }
1192
1193 /*
1194 * qla2x00_get_port_database
1195 * Issue normal/enhanced get port database mailbox command
1196 * and copy device name as necessary.
1197 *
1198 * Input:
1199 * ha = adapter state pointer.
1200 * dev = structure pointer.
1201 * opt = enhanced cmd option byte.
1202 *
1203 * Returns:
1204 * qla2x00 local function return status code.
1205 *
1206 * Context:
1207 * Kernel context.
1208 */
1209 int
qla2x00_get_port_database(scsi_qla_host_t * vha,fc_port_t * fcport,uint8_t opt)1210 qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
1211 {
1212 int rval;
1213 mbx_cmd_t mc;
1214 mbx_cmd_t *mcp = &mc;
1215 port_database_t *pd;
1216 struct port_database_24xx *pd24;
1217 dma_addr_t pd_dma;
1218 struct qla_hw_data *ha = vha->hw;
1219
1220 ql_dbg(ql_dbg_mbx, vha, 0x104f, "Entered %s.\n", __func__);
1221
1222 pd24 = NULL;
1223 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1224 if (pd == NULL) {
1225 ql_log(ql_log_warn, vha, 0x1050,
1226 "Failed to allocate port database structure.\n");
1227 return QLA_MEMORY_ALLOC_FAILED;
1228 }
1229 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
1230
1231 mcp->mb[0] = MBC_GET_PORT_DATABASE;
1232 if (opt != 0 && !IS_FWI2_CAPABLE(ha))
1233 mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
1234 mcp->mb[2] = MSW(pd_dma);
1235 mcp->mb[3] = LSW(pd_dma);
1236 mcp->mb[6] = MSW(MSD(pd_dma));
1237 mcp->mb[7] = LSW(MSD(pd_dma));
1238 mcp->mb[9] = vha->vp_idx;
1239 mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
1240 mcp->in_mb = MBX_0;
1241 if (IS_FWI2_CAPABLE(ha)) {
1242 mcp->mb[1] = fcport->loop_id;
1243 mcp->mb[10] = opt;
1244 mcp->out_mb |= MBX_10|MBX_1;
1245 mcp->in_mb |= MBX_1;
1246 } else if (HAS_EXTENDED_IDS(ha)) {
1247 mcp->mb[1] = fcport->loop_id;
1248 mcp->mb[10] = opt;
1249 mcp->out_mb |= MBX_10|MBX_1;
1250 } else {
1251 mcp->mb[1] = fcport->loop_id << 8 | opt;
1252 mcp->out_mb |= MBX_1;
1253 }
1254 mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
1255 PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
1256 mcp->flags = MBX_DMA_IN;
1257 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1258 rval = qla2x00_mailbox_command(vha, mcp);
1259 if (rval != QLA_SUCCESS)
1260 goto gpd_error_out;
1261
1262 if (IS_FWI2_CAPABLE(ha)) {
1263 pd24 = (struct port_database_24xx *) pd;
1264
1265 /* Check for logged in state. */
1266 if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
1267 pd24->last_login_state != PDS_PRLI_COMPLETE) {
1268 ql_dbg(ql_dbg_mbx, vha, 0x1051,
1269 "Unable to verify login-state (%x/%x) for "
1270 "loop_id %x.\n", pd24->current_login_state,
1271 pd24->last_login_state, fcport->loop_id);
1272 rval = QLA_FUNCTION_FAILED;
1273 goto gpd_error_out;
1274 }
1275
1276 /* Names are little-endian. */
1277 memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
1278 memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
1279
1280 /* Get port_id of device. */
1281 fcport->d_id.b.domain = pd24->port_id[0];
1282 fcport->d_id.b.area = pd24->port_id[1];
1283 fcport->d_id.b.al_pa = pd24->port_id[2];
1284 fcport->d_id.b.rsvd_1 = 0;
1285
1286 /* If not target must be initiator or unknown type. */
1287 if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
1288 fcport->port_type = FCT_INITIATOR;
1289 else
1290 fcport->port_type = FCT_TARGET;
1291 } else {
1292 /* Check for logged in state. */
1293 if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
1294 pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
1295 ql_dbg(ql_dbg_mbx, vha, 0x100a,
1296 "Unable to verify login-state (%x/%x) - "
1297 "portid=%02x%02x%02x.\n", pd->master_state,
1298 pd->slave_state, fcport->d_id.b.domain,
1299 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1300 rval = QLA_FUNCTION_FAILED;
1301 goto gpd_error_out;
1302 }
1303
1304 /* Names are little-endian. */
1305 memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
1306 memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
1307
1308 /* Get port_id of device. */
1309 fcport->d_id.b.domain = pd->port_id[0];
1310 fcport->d_id.b.area = pd->port_id[3];
1311 fcport->d_id.b.al_pa = pd->port_id[2];
1312 fcport->d_id.b.rsvd_1 = 0;
1313
1314 /* If not target must be initiator or unknown type. */
1315 if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
1316 fcport->port_type = FCT_INITIATOR;
1317 else
1318 fcport->port_type = FCT_TARGET;
1319
1320 /* Passback COS information. */
1321 fcport->supported_classes = (pd->options & BIT_4) ?
1322 FC_COS_CLASS2: FC_COS_CLASS3;
1323 }
1324
1325 gpd_error_out:
1326 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1327
1328 if (rval != QLA_SUCCESS) {
1329 ql_dbg(ql_dbg_mbx, vha, 0x1052,
1330 "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
1331 mcp->mb[0], mcp->mb[1]);
1332 } else {
1333 ql_dbg(ql_dbg_mbx, vha, 0x1053, "Done %s.\n", __func__);
1334 }
1335
1336 return rval;
1337 }
1338
1339 /*
1340 * qla2x00_get_firmware_state
1341 * Get adapter firmware state.
1342 *
1343 * Input:
1344 * ha = adapter block pointer.
1345 * dptr = pointer for firmware state.
1346 * TARGET_QUEUE_LOCK must be released.
1347 * ADAPTER_STATE_LOCK must be released.
1348 *
1349 * Returns:
1350 * qla2x00 local function return status code.
1351 *
1352 * Context:
1353 * Kernel context.
1354 */
1355 int
qla2x00_get_firmware_state(scsi_qla_host_t * vha,uint16_t * states)1356 qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
1357 {
1358 int rval;
1359 mbx_cmd_t mc;
1360 mbx_cmd_t *mcp = &mc;
1361
1362 ql_dbg(ql_dbg_mbx, vha, 0x1054, "Entered %s.\n", __func__);
1363
1364 mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
1365 mcp->out_mb = MBX_0;
1366 if (IS_FWI2_CAPABLE(vha->hw))
1367 mcp->in_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
1368 else
1369 mcp->in_mb = MBX_1|MBX_0;
1370 mcp->tov = MBX_TOV_SECONDS;
1371 mcp->flags = 0;
1372 rval = qla2x00_mailbox_command(vha, mcp);
1373
1374 /* Return firmware states. */
1375 states[0] = mcp->mb[1];
1376 if (IS_FWI2_CAPABLE(vha->hw)) {
1377 states[1] = mcp->mb[2];
1378 states[2] = mcp->mb[3];
1379 states[3] = mcp->mb[4];
1380 states[4] = mcp->mb[5];
1381 }
1382
1383 if (rval != QLA_SUCCESS) {
1384 /*EMPTY*/
1385 ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
1386 } else {
1387 /*EMPTY*/
1388 ql_dbg(ql_dbg_mbx, vha, 0x1056, "Done %s.\n", __func__);
1389 }
1390
1391 return rval;
1392 }
1393
1394 /*
1395 * qla2x00_get_port_name
1396 * Issue get port name mailbox command.
1397 * Returned name is in big endian format.
1398 *
1399 * Input:
1400 * ha = adapter block pointer.
1401 * loop_id = loop ID of device.
1402 * name = pointer for name.
1403 * TARGET_QUEUE_LOCK must be released.
1404 * ADAPTER_STATE_LOCK must be released.
1405 *
1406 * Returns:
1407 * qla2x00 local function return status code.
1408 *
1409 * Context:
1410 * Kernel context.
1411 */
1412 int
qla2x00_get_port_name(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t * name,uint8_t opt)1413 qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
1414 uint8_t opt)
1415 {
1416 int rval;
1417 mbx_cmd_t mc;
1418 mbx_cmd_t *mcp = &mc;
1419
1420 ql_dbg(ql_dbg_mbx, vha, 0x1057, "Entered %s.\n", __func__);
1421
1422 mcp->mb[0] = MBC_GET_PORT_NAME;
1423 mcp->mb[9] = vha->vp_idx;
1424 mcp->out_mb = MBX_9|MBX_1|MBX_0;
1425 if (HAS_EXTENDED_IDS(vha->hw)) {
1426 mcp->mb[1] = loop_id;
1427 mcp->mb[10] = opt;
1428 mcp->out_mb |= MBX_10;
1429 } else {
1430 mcp->mb[1] = loop_id << 8 | opt;
1431 }
1432
1433 mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1434 mcp->tov = MBX_TOV_SECONDS;
1435 mcp->flags = 0;
1436 rval = qla2x00_mailbox_command(vha, mcp);
1437
1438 if (rval != QLA_SUCCESS) {
1439 /*EMPTY*/
1440 ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
1441 } else {
1442 if (name != NULL) {
1443 /* This function returns name in big endian. */
1444 name[0] = MSB(mcp->mb[2]);
1445 name[1] = LSB(mcp->mb[2]);
1446 name[2] = MSB(mcp->mb[3]);
1447 name[3] = LSB(mcp->mb[3]);
1448 name[4] = MSB(mcp->mb[6]);
1449 name[5] = LSB(mcp->mb[6]);
1450 name[6] = MSB(mcp->mb[7]);
1451 name[7] = LSB(mcp->mb[7]);
1452 }
1453
1454 ql_dbg(ql_dbg_mbx, vha, 0x1059, "Done %s.\n", __func__);
1455 }
1456
1457 return rval;
1458 }
1459
1460 /*
1461 * qla2x00_lip_reset
1462 * Issue LIP reset mailbox command.
1463 *
1464 * Input:
1465 * ha = adapter block pointer.
1466 * TARGET_QUEUE_LOCK must be released.
1467 * ADAPTER_STATE_LOCK must be released.
1468 *
1469 * Returns:
1470 * qla2x00 local function return status code.
1471 *
1472 * Context:
1473 * Kernel context.
1474 */
1475 int
qla2x00_lip_reset(scsi_qla_host_t * vha)1476 qla2x00_lip_reset(scsi_qla_host_t *vha)
1477 {
1478 int rval;
1479 mbx_cmd_t mc;
1480 mbx_cmd_t *mcp = &mc;
1481
1482 ql_dbg(ql_dbg_mbx, vha, 0x105a, "Entered %s.\n", __func__);
1483
1484 if (IS_QLA8XXX_TYPE(vha->hw)) {
1485 /* Logout across all FCFs. */
1486 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1487 mcp->mb[1] = BIT_1;
1488 mcp->mb[2] = 0;
1489 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1490 } else if (IS_FWI2_CAPABLE(vha->hw)) {
1491 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1492 mcp->mb[1] = BIT_6;
1493 mcp->mb[2] = 0;
1494 mcp->mb[3] = vha->hw->loop_reset_delay;
1495 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1496 } else {
1497 mcp->mb[0] = MBC_LIP_RESET;
1498 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1499 if (HAS_EXTENDED_IDS(vha->hw)) {
1500 mcp->mb[1] = 0x00ff;
1501 mcp->mb[10] = 0;
1502 mcp->out_mb |= MBX_10;
1503 } else {
1504 mcp->mb[1] = 0xff00;
1505 }
1506 mcp->mb[2] = vha->hw->loop_reset_delay;
1507 mcp->mb[3] = 0;
1508 }
1509 mcp->in_mb = MBX_0;
1510 mcp->tov = MBX_TOV_SECONDS;
1511 mcp->flags = 0;
1512 rval = qla2x00_mailbox_command(vha, mcp);
1513
1514 if (rval != QLA_SUCCESS) {
1515 /*EMPTY*/
1516 ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
1517 } else {
1518 /*EMPTY*/
1519 ql_dbg(ql_dbg_mbx, vha, 0x105c, "Done %s.\n", __func__);
1520 }
1521
1522 return rval;
1523 }
1524
1525 /*
1526 * qla2x00_send_sns
1527 * Send SNS command.
1528 *
1529 * Input:
1530 * ha = adapter block pointer.
1531 * sns = pointer for command.
1532 * cmd_size = command size.
1533 * buf_size = response/command size.
1534 * TARGET_QUEUE_LOCK must be released.
1535 * ADAPTER_STATE_LOCK must be released.
1536 *
1537 * Returns:
1538 * qla2x00 local function return status code.
1539 *
1540 * Context:
1541 * Kernel context.
1542 */
1543 int
qla2x00_send_sns(scsi_qla_host_t * vha,dma_addr_t sns_phys_address,uint16_t cmd_size,size_t buf_size)1544 qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
1545 uint16_t cmd_size, size_t buf_size)
1546 {
1547 int rval;
1548 mbx_cmd_t mc;
1549 mbx_cmd_t *mcp = &mc;
1550
1551 ql_dbg(ql_dbg_mbx, vha, 0x105d, "Entered %s.\n", __func__);
1552
1553 ql_dbg(ql_dbg_mbx, vha, 0x105e,
1554 "Retry cnt=%d ratov=%d total tov=%d.\n",
1555 vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
1556
1557 mcp->mb[0] = MBC_SEND_SNS_COMMAND;
1558 mcp->mb[1] = cmd_size;
1559 mcp->mb[2] = MSW(sns_phys_address);
1560 mcp->mb[3] = LSW(sns_phys_address);
1561 mcp->mb[6] = MSW(MSD(sns_phys_address));
1562 mcp->mb[7] = LSW(MSD(sns_phys_address));
1563 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
1564 mcp->in_mb = MBX_0|MBX_1;
1565 mcp->buf_size = buf_size;
1566 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
1567 mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
1568 rval = qla2x00_mailbox_command(vha, mcp);
1569
1570 if (rval != QLA_SUCCESS) {
1571 /*EMPTY*/
1572 ql_dbg(ql_dbg_mbx, vha, 0x105f,
1573 "Failed=%x mb[0]=%x mb[1]=%x.\n",
1574 rval, mcp->mb[0], mcp->mb[1]);
1575 } else {
1576 /*EMPTY*/
1577 ql_dbg(ql_dbg_mbx, vha, 0x1060, "Done %s.\n", __func__);
1578 }
1579
1580 return rval;
1581 }
1582
1583 int
qla24xx_login_fabric(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa,uint16_t * mb,uint8_t opt)1584 qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1585 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1586 {
1587 int rval;
1588
1589 struct logio_entry_24xx *lg;
1590 dma_addr_t lg_dma;
1591 uint32_t iop[2];
1592 struct qla_hw_data *ha = vha->hw;
1593 struct req_que *req;
1594 struct rsp_que *rsp;
1595
1596 ql_dbg(ql_dbg_mbx, vha, 0x1061, "Entered %s.\n", __func__);
1597
1598 if (ha->flags.cpu_affinity_enabled)
1599 req = ha->req_q_map[0];
1600 else
1601 req = vha->req;
1602 rsp = req->rsp;
1603
1604 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1605 if (lg == NULL) {
1606 ql_log(ql_log_warn, vha, 0x1062,
1607 "Failed to allocate login IOCB.\n");
1608 return QLA_MEMORY_ALLOC_FAILED;
1609 }
1610 memset(lg, 0, sizeof(struct logio_entry_24xx));
1611
1612 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1613 lg->entry_count = 1;
1614 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1615 lg->nport_handle = cpu_to_le16(loop_id);
1616 lg->control_flags = __constant_cpu_to_le16(LCF_COMMAND_PLOGI);
1617 if (opt & BIT_0)
1618 lg->control_flags |= __constant_cpu_to_le16(LCF_COND_PLOGI);
1619 if (opt & BIT_1)
1620 lg->control_flags |= __constant_cpu_to_le16(LCF_SKIP_PRLI);
1621 lg->port_id[0] = al_pa;
1622 lg->port_id[1] = area;
1623 lg->port_id[2] = domain;
1624 lg->vp_index = vha->vp_idx;
1625 rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
1626 if (rval != QLA_SUCCESS) {
1627 ql_dbg(ql_dbg_mbx, vha, 0x1063,
1628 "Failed to issue login IOCB (%x).\n", rval);
1629 } else if (lg->entry_status != 0) {
1630 ql_dbg(ql_dbg_mbx, vha, 0x1064,
1631 "Failed to complete IOCB -- error status (%x).\n",
1632 lg->entry_status);
1633 rval = QLA_FUNCTION_FAILED;
1634 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1635 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1636 iop[1] = le32_to_cpu(lg->io_parameter[1]);
1637
1638 ql_dbg(ql_dbg_mbx, vha, 0x1065,
1639 "Failed to complete IOCB -- completion status (%x) "
1640 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1641 iop[0], iop[1]);
1642
1643 switch (iop[0]) {
1644 case LSC_SCODE_PORTID_USED:
1645 mb[0] = MBS_PORT_ID_USED;
1646 mb[1] = LSW(iop[1]);
1647 break;
1648 case LSC_SCODE_NPORT_USED:
1649 mb[0] = MBS_LOOP_ID_USED;
1650 break;
1651 case LSC_SCODE_NOLINK:
1652 case LSC_SCODE_NOIOCB:
1653 case LSC_SCODE_NOXCB:
1654 case LSC_SCODE_CMD_FAILED:
1655 case LSC_SCODE_NOFABRIC:
1656 case LSC_SCODE_FW_NOT_READY:
1657 case LSC_SCODE_NOT_LOGGED_IN:
1658 case LSC_SCODE_NOPCB:
1659 case LSC_SCODE_ELS_REJECT:
1660 case LSC_SCODE_CMD_PARAM_ERR:
1661 case LSC_SCODE_NONPORT:
1662 case LSC_SCODE_LOGGED_IN:
1663 case LSC_SCODE_NOFLOGI_ACC:
1664 default:
1665 mb[0] = MBS_COMMAND_ERROR;
1666 break;
1667 }
1668 } else {
1669 ql_dbg(ql_dbg_mbx, vha, 0x1066, "Done %s.\n", __func__);
1670
1671 iop[0] = le32_to_cpu(lg->io_parameter[0]);
1672
1673 mb[0] = MBS_COMMAND_COMPLETE;
1674 mb[1] = 0;
1675 if (iop[0] & BIT_4) {
1676 if (iop[0] & BIT_8)
1677 mb[1] |= BIT_1;
1678 } else
1679 mb[1] = BIT_0;
1680
1681 /* Passback COS information. */
1682 mb[10] = 0;
1683 if (lg->io_parameter[7] || lg->io_parameter[8])
1684 mb[10] |= BIT_0; /* Class 2. */
1685 if (lg->io_parameter[9] || lg->io_parameter[10])
1686 mb[10] |= BIT_1; /* Class 3. */
1687 }
1688
1689 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1690
1691 return rval;
1692 }
1693
1694 /*
1695 * qla2x00_login_fabric
1696 * Issue login fabric port mailbox command.
1697 *
1698 * Input:
1699 * ha = adapter block pointer.
1700 * loop_id = device loop ID.
1701 * domain = device domain.
1702 * area = device area.
1703 * al_pa = device AL_PA.
1704 * status = pointer for return status.
1705 * opt = command options.
1706 * TARGET_QUEUE_LOCK must be released.
1707 * ADAPTER_STATE_LOCK must be released.
1708 *
1709 * Returns:
1710 * qla2x00 local function return status code.
1711 *
1712 * Context:
1713 * Kernel context.
1714 */
1715 int
qla2x00_login_fabric(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa,uint16_t * mb,uint8_t opt)1716 qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1717 uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
1718 {
1719 int rval;
1720 mbx_cmd_t mc;
1721 mbx_cmd_t *mcp = &mc;
1722 struct qla_hw_data *ha = vha->hw;
1723
1724 ql_dbg(ql_dbg_mbx, vha, 0x1067, "Entered %s.\n", __func__);
1725
1726 mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
1727 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1728 if (HAS_EXTENDED_IDS(ha)) {
1729 mcp->mb[1] = loop_id;
1730 mcp->mb[10] = opt;
1731 mcp->out_mb |= MBX_10;
1732 } else {
1733 mcp->mb[1] = (loop_id << 8) | opt;
1734 }
1735 mcp->mb[2] = domain;
1736 mcp->mb[3] = area << 8 | al_pa;
1737
1738 mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
1739 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1740 mcp->flags = 0;
1741 rval = qla2x00_mailbox_command(vha, mcp);
1742
1743 /* Return mailbox statuses. */
1744 if (mb != NULL) {
1745 mb[0] = mcp->mb[0];
1746 mb[1] = mcp->mb[1];
1747 mb[2] = mcp->mb[2];
1748 mb[6] = mcp->mb[6];
1749 mb[7] = mcp->mb[7];
1750 /* COS retrieved from Get-Port-Database mailbox command. */
1751 mb[10] = 0;
1752 }
1753
1754 if (rval != QLA_SUCCESS) {
1755 /* RLU tmp code: need to change main mailbox_command function to
1756 * return ok even when the mailbox completion value is not
1757 * SUCCESS. The caller needs to be responsible to interpret
1758 * the return values of this mailbox command if we're not
1759 * to change too much of the existing code.
1760 */
1761 if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
1762 mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
1763 mcp->mb[0] == 0x4006)
1764 rval = QLA_SUCCESS;
1765
1766 /*EMPTY*/
1767 ql_dbg(ql_dbg_mbx, vha, 0x1068,
1768 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
1769 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
1770 } else {
1771 /*EMPTY*/
1772 ql_dbg(ql_dbg_mbx, vha, 0x1069, "Done %s.\n", __func__);
1773 }
1774
1775 return rval;
1776 }
1777
1778 /*
1779 * qla2x00_login_local_device
1780 * Issue login loop port mailbox command.
1781 *
1782 * Input:
1783 * ha = adapter block pointer.
1784 * loop_id = device loop ID.
1785 * opt = command options.
1786 *
1787 * Returns:
1788 * Return status code.
1789 *
1790 * Context:
1791 * Kernel context.
1792 *
1793 */
1794 int
qla2x00_login_local_device(scsi_qla_host_t * vha,fc_port_t * fcport,uint16_t * mb_ret,uint8_t opt)1795 qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
1796 uint16_t *mb_ret, uint8_t opt)
1797 {
1798 int rval;
1799 mbx_cmd_t mc;
1800 mbx_cmd_t *mcp = &mc;
1801 struct qla_hw_data *ha = vha->hw;
1802
1803 ql_dbg(ql_dbg_mbx, vha, 0x106a, "Entered %s.\n", __func__);
1804
1805 if (IS_FWI2_CAPABLE(ha))
1806 return qla24xx_login_fabric(vha, fcport->loop_id,
1807 fcport->d_id.b.domain, fcport->d_id.b.area,
1808 fcport->d_id.b.al_pa, mb_ret, opt);
1809
1810 mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
1811 if (HAS_EXTENDED_IDS(ha))
1812 mcp->mb[1] = fcport->loop_id;
1813 else
1814 mcp->mb[1] = fcport->loop_id << 8;
1815 mcp->mb[2] = opt;
1816 mcp->out_mb = MBX_2|MBX_1|MBX_0;
1817 mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
1818 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
1819 mcp->flags = 0;
1820 rval = qla2x00_mailbox_command(vha, mcp);
1821
1822 /* Return mailbox statuses. */
1823 if (mb_ret != NULL) {
1824 mb_ret[0] = mcp->mb[0];
1825 mb_ret[1] = mcp->mb[1];
1826 mb_ret[6] = mcp->mb[6];
1827 mb_ret[7] = mcp->mb[7];
1828 }
1829
1830 if (rval != QLA_SUCCESS) {
1831 /* AV tmp code: need to change main mailbox_command function to
1832 * return ok even when the mailbox completion value is not
1833 * SUCCESS. The caller needs to be responsible to interpret
1834 * the return values of this mailbox command if we're not
1835 * to change too much of the existing code.
1836 */
1837 if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
1838 rval = QLA_SUCCESS;
1839
1840 ql_dbg(ql_dbg_mbx, vha, 0x106b,
1841 "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
1842 rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
1843 } else {
1844 /*EMPTY*/
1845 ql_dbg(ql_dbg_mbx, vha, 0x106c, "Done %s.\n", __func__);
1846 }
1847
1848 return (rval);
1849 }
1850
1851 int
qla24xx_fabric_logout(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa)1852 qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1853 uint8_t area, uint8_t al_pa)
1854 {
1855 int rval;
1856 struct logio_entry_24xx *lg;
1857 dma_addr_t lg_dma;
1858 struct qla_hw_data *ha = vha->hw;
1859 struct req_que *req;
1860 struct rsp_que *rsp;
1861
1862 ql_dbg(ql_dbg_mbx, vha, 0x106d, "Entered %s.\n", __func__);
1863
1864 lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
1865 if (lg == NULL) {
1866 ql_log(ql_log_warn, vha, 0x106e,
1867 "Failed to allocate logout IOCB.\n");
1868 return QLA_MEMORY_ALLOC_FAILED;
1869 }
1870 memset(lg, 0, sizeof(struct logio_entry_24xx));
1871
1872 if (ql2xmaxqueues > 1)
1873 req = ha->req_q_map[0];
1874 else
1875 req = vha->req;
1876 rsp = req->rsp;
1877 lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
1878 lg->entry_count = 1;
1879 lg->handle = MAKE_HANDLE(req->id, lg->handle);
1880 lg->nport_handle = cpu_to_le16(loop_id);
1881 lg->control_flags =
1882 __constant_cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
1883 LCF_FREE_NPORT);
1884 lg->port_id[0] = al_pa;
1885 lg->port_id[1] = area;
1886 lg->port_id[2] = domain;
1887 lg->vp_index = vha->vp_idx;
1888
1889 rval = qla2x00_issue_iocb(vha, lg, lg_dma, 0);
1890 if (rval != QLA_SUCCESS) {
1891 ql_dbg(ql_dbg_mbx, vha, 0x106f,
1892 "Failed to issue logout IOCB (%x).\n", rval);
1893 } else if (lg->entry_status != 0) {
1894 ql_dbg(ql_dbg_mbx, vha, 0x1070,
1895 "Failed to complete IOCB -- error status (%x).\n",
1896 lg->entry_status);
1897 rval = QLA_FUNCTION_FAILED;
1898 } else if (lg->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
1899 ql_dbg(ql_dbg_mbx, vha, 0x1071,
1900 "Failed to complete IOCB -- completion status (%x) "
1901 "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
1902 le32_to_cpu(lg->io_parameter[0]),
1903 le32_to_cpu(lg->io_parameter[1]));
1904 } else {
1905 /*EMPTY*/
1906 ql_dbg(ql_dbg_mbx, vha, 0x1072, "Done %s.\n", __func__);
1907 }
1908
1909 dma_pool_free(ha->s_dma_pool, lg, lg_dma);
1910
1911 return rval;
1912 }
1913
1914 /*
1915 * qla2x00_fabric_logout
1916 * Issue logout fabric port mailbox command.
1917 *
1918 * Input:
1919 * ha = adapter block pointer.
1920 * loop_id = device loop ID.
1921 * TARGET_QUEUE_LOCK must be released.
1922 * ADAPTER_STATE_LOCK must be released.
1923 *
1924 * Returns:
1925 * qla2x00 local function return status code.
1926 *
1927 * Context:
1928 * Kernel context.
1929 */
1930 int
qla2x00_fabric_logout(scsi_qla_host_t * vha,uint16_t loop_id,uint8_t domain,uint8_t area,uint8_t al_pa)1931 qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
1932 uint8_t area, uint8_t al_pa)
1933 {
1934 int rval;
1935 mbx_cmd_t mc;
1936 mbx_cmd_t *mcp = &mc;
1937
1938 ql_dbg(ql_dbg_mbx, vha, 0x1073, "Entered %s.\n", __func__);
1939
1940 mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
1941 mcp->out_mb = MBX_1|MBX_0;
1942 if (HAS_EXTENDED_IDS(vha->hw)) {
1943 mcp->mb[1] = loop_id;
1944 mcp->mb[10] = 0;
1945 mcp->out_mb |= MBX_10;
1946 } else {
1947 mcp->mb[1] = loop_id << 8;
1948 }
1949
1950 mcp->in_mb = MBX_1|MBX_0;
1951 mcp->tov = MBX_TOV_SECONDS;
1952 mcp->flags = 0;
1953 rval = qla2x00_mailbox_command(vha, mcp);
1954
1955 if (rval != QLA_SUCCESS) {
1956 /*EMPTY*/
1957 ql_dbg(ql_dbg_mbx, vha, 0x1074,
1958 "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
1959 } else {
1960 /*EMPTY*/
1961 ql_dbg(ql_dbg_mbx, vha, 0x1075, "Done %s.\n", __func__);
1962 }
1963
1964 return rval;
1965 }
1966
1967 /*
1968 * qla2x00_full_login_lip
1969 * Issue full login LIP mailbox command.
1970 *
1971 * Input:
1972 * ha = adapter block pointer.
1973 * TARGET_QUEUE_LOCK must be released.
1974 * ADAPTER_STATE_LOCK must be released.
1975 *
1976 * Returns:
1977 * qla2x00 local function return status code.
1978 *
1979 * Context:
1980 * Kernel context.
1981 */
1982 int
qla2x00_full_login_lip(scsi_qla_host_t * vha)1983 qla2x00_full_login_lip(scsi_qla_host_t *vha)
1984 {
1985 int rval;
1986 mbx_cmd_t mc;
1987 mbx_cmd_t *mcp = &mc;
1988
1989 ql_dbg(ql_dbg_mbx, vha, 0x1076, "Entered %s.\n", __func__);
1990
1991 mcp->mb[0] = MBC_LIP_FULL_LOGIN;
1992 mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
1993 mcp->mb[2] = 0;
1994 mcp->mb[3] = 0;
1995 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
1996 mcp->in_mb = MBX_0;
1997 mcp->tov = MBX_TOV_SECONDS;
1998 mcp->flags = 0;
1999 rval = qla2x00_mailbox_command(vha, mcp);
2000
2001 if (rval != QLA_SUCCESS) {
2002 /*EMPTY*/
2003 ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
2004 } else {
2005 /*EMPTY*/
2006 ql_dbg(ql_dbg_mbx, vha, 0x1078, "Done %s.\n", __func__);
2007 }
2008
2009 return rval;
2010 }
2011
2012 /*
2013 * qla2x00_get_id_list
2014 *
2015 * Input:
2016 * ha = adapter block pointer.
2017 *
2018 * Returns:
2019 * qla2x00 local function return status code.
2020 *
2021 * Context:
2022 * Kernel context.
2023 */
2024 int
qla2x00_get_id_list(scsi_qla_host_t * vha,void * id_list,dma_addr_t id_list_dma,uint16_t * entries)2025 qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
2026 uint16_t *entries)
2027 {
2028 int rval;
2029 mbx_cmd_t mc;
2030 mbx_cmd_t *mcp = &mc;
2031
2032 ql_dbg(ql_dbg_mbx, vha, 0x1079, "Entered %s.\n", __func__);
2033
2034 if (id_list == NULL)
2035 return QLA_FUNCTION_FAILED;
2036
2037 mcp->mb[0] = MBC_GET_ID_LIST;
2038 mcp->out_mb = MBX_0;
2039 if (IS_FWI2_CAPABLE(vha->hw)) {
2040 mcp->mb[2] = MSW(id_list_dma);
2041 mcp->mb[3] = LSW(id_list_dma);
2042 mcp->mb[6] = MSW(MSD(id_list_dma));
2043 mcp->mb[7] = LSW(MSD(id_list_dma));
2044 mcp->mb[8] = 0;
2045 mcp->mb[9] = vha->vp_idx;
2046 mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
2047 } else {
2048 mcp->mb[1] = MSW(id_list_dma);
2049 mcp->mb[2] = LSW(id_list_dma);
2050 mcp->mb[3] = MSW(MSD(id_list_dma));
2051 mcp->mb[6] = LSW(MSD(id_list_dma));
2052 mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
2053 }
2054 mcp->in_mb = MBX_1|MBX_0;
2055 mcp->tov = MBX_TOV_SECONDS;
2056 mcp->flags = 0;
2057 rval = qla2x00_mailbox_command(vha, mcp);
2058
2059 if (rval != QLA_SUCCESS) {
2060 /*EMPTY*/
2061 ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
2062 } else {
2063 *entries = mcp->mb[1];
2064 ql_dbg(ql_dbg_mbx, vha, 0x107b, "Done %s.\n", __func__);
2065 }
2066
2067 return rval;
2068 }
2069
2070 /*
2071 * qla2x00_get_resource_cnts
2072 * Get current firmware resource counts.
2073 *
2074 * Input:
2075 * ha = adapter block pointer.
2076 *
2077 * Returns:
2078 * qla2x00 local function return status code.
2079 *
2080 * Context:
2081 * Kernel context.
2082 */
2083 int
qla2x00_get_resource_cnts(scsi_qla_host_t * vha,uint16_t * cur_xchg_cnt,uint16_t * orig_xchg_cnt,uint16_t * cur_iocb_cnt,uint16_t * orig_iocb_cnt,uint16_t * max_npiv_vports,uint16_t * max_fcfs)2084 qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
2085 uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
2086 uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
2087 {
2088 int rval;
2089 mbx_cmd_t mc;
2090 mbx_cmd_t *mcp = &mc;
2091
2092 ql_dbg(ql_dbg_mbx, vha, 0x107c, "Entered %s.\n", __func__);
2093
2094 mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
2095 mcp->out_mb = MBX_0;
2096 mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
2097 if (IS_QLA81XX(vha->hw))
2098 mcp->in_mb |= MBX_12;
2099 mcp->tov = MBX_TOV_SECONDS;
2100 mcp->flags = 0;
2101 rval = qla2x00_mailbox_command(vha, mcp);
2102
2103 if (rval != QLA_SUCCESS) {
2104 /*EMPTY*/
2105 ql_dbg(ql_dbg_mbx, vha, 0x107d,
2106 "Failed mb[0]=%x.\n", mcp->mb[0]);
2107 } else {
2108 ql_dbg(ql_dbg_mbx, vha, 0x107e,
2109 "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
2110 "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
2111 mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
2112 mcp->mb[11], mcp->mb[12]);
2113
2114 if (cur_xchg_cnt)
2115 *cur_xchg_cnt = mcp->mb[3];
2116 if (orig_xchg_cnt)
2117 *orig_xchg_cnt = mcp->mb[6];
2118 if (cur_iocb_cnt)
2119 *cur_iocb_cnt = mcp->mb[7];
2120 if (orig_iocb_cnt)
2121 *orig_iocb_cnt = mcp->mb[10];
2122 if (vha->hw->flags.npiv_supported && max_npiv_vports)
2123 *max_npiv_vports = mcp->mb[11];
2124 if (IS_QLA81XX(vha->hw) && max_fcfs)
2125 *max_fcfs = mcp->mb[12];
2126 }
2127
2128 return (rval);
2129 }
2130
2131 /*
2132 * qla2x00_get_fcal_position_map
2133 * Get FCAL (LILP) position map using mailbox command
2134 *
2135 * Input:
2136 * ha = adapter state pointer.
2137 * pos_map = buffer pointer (can be NULL).
2138 *
2139 * Returns:
2140 * qla2x00 local function return status code.
2141 *
2142 * Context:
2143 * Kernel context.
2144 */
2145 int
qla2x00_get_fcal_position_map(scsi_qla_host_t * vha,char * pos_map)2146 qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
2147 {
2148 int rval;
2149 mbx_cmd_t mc;
2150 mbx_cmd_t *mcp = &mc;
2151 char *pmap;
2152 dma_addr_t pmap_dma;
2153 struct qla_hw_data *ha = vha->hw;
2154
2155 ql_dbg(ql_dbg_mbx, vha, 0x107f, "Entered %s.\n", __func__);
2156
2157 pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
2158 if (pmap == NULL) {
2159 ql_log(ql_log_warn, vha, 0x1080,
2160 "Memory alloc failed.\n");
2161 return QLA_MEMORY_ALLOC_FAILED;
2162 }
2163 memset(pmap, 0, FCAL_MAP_SIZE);
2164
2165 mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
2166 mcp->mb[2] = MSW(pmap_dma);
2167 mcp->mb[3] = LSW(pmap_dma);
2168 mcp->mb[6] = MSW(MSD(pmap_dma));
2169 mcp->mb[7] = LSW(MSD(pmap_dma));
2170 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2171 mcp->in_mb = MBX_1|MBX_0;
2172 mcp->buf_size = FCAL_MAP_SIZE;
2173 mcp->flags = MBX_DMA_IN;
2174 mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
2175 rval = qla2x00_mailbox_command(vha, mcp);
2176
2177 if (rval == QLA_SUCCESS) {
2178 ql_dbg(ql_dbg_mbx, vha, 0x1081,
2179 "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
2180 mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
2181 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
2182 pmap, pmap[0] + 1);
2183
2184 if (pos_map)
2185 memcpy(pos_map, pmap, FCAL_MAP_SIZE);
2186 }
2187 dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
2188
2189 if (rval != QLA_SUCCESS) {
2190 ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
2191 } else {
2192 ql_dbg(ql_dbg_mbx, vha, 0x1083, "Done %s.\n", __func__);
2193 }
2194
2195 return rval;
2196 }
2197
2198 /*
2199 * qla2x00_get_link_status
2200 *
2201 * Input:
2202 * ha = adapter block pointer.
2203 * loop_id = device loop ID.
2204 * ret_buf = pointer to link status return buffer.
2205 *
2206 * Returns:
2207 * 0 = success.
2208 * BIT_0 = mem alloc error.
2209 * BIT_1 = mailbox error.
2210 */
2211 int
qla2x00_get_link_status(scsi_qla_host_t * vha,uint16_t loop_id,struct link_statistics * stats,dma_addr_t stats_dma)2212 qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
2213 struct link_statistics *stats, dma_addr_t stats_dma)
2214 {
2215 int rval;
2216 mbx_cmd_t mc;
2217 mbx_cmd_t *mcp = &mc;
2218 uint32_t *siter, *diter, dwords;
2219 struct qla_hw_data *ha = vha->hw;
2220
2221 ql_dbg(ql_dbg_mbx, vha, 0x1084, "Entered %s.\n", __func__);
2222
2223 mcp->mb[0] = MBC_GET_LINK_STATUS;
2224 mcp->mb[2] = MSW(stats_dma);
2225 mcp->mb[3] = LSW(stats_dma);
2226 mcp->mb[6] = MSW(MSD(stats_dma));
2227 mcp->mb[7] = LSW(MSD(stats_dma));
2228 mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2229 mcp->in_mb = MBX_0;
2230 if (IS_FWI2_CAPABLE(ha)) {
2231 mcp->mb[1] = loop_id;
2232 mcp->mb[4] = 0;
2233 mcp->mb[10] = 0;
2234 mcp->out_mb |= MBX_10|MBX_4|MBX_1;
2235 mcp->in_mb |= MBX_1;
2236 } else if (HAS_EXTENDED_IDS(ha)) {
2237 mcp->mb[1] = loop_id;
2238 mcp->mb[10] = 0;
2239 mcp->out_mb |= MBX_10|MBX_1;
2240 } else {
2241 mcp->mb[1] = loop_id << 8;
2242 mcp->out_mb |= MBX_1;
2243 }
2244 mcp->tov = MBX_TOV_SECONDS;
2245 mcp->flags = IOCTL_CMD;
2246 rval = qla2x00_mailbox_command(vha, mcp);
2247
2248 if (rval == QLA_SUCCESS) {
2249 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2250 ql_dbg(ql_dbg_mbx, vha, 0x1085,
2251 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2252 rval = QLA_FUNCTION_FAILED;
2253 } else {
2254 /* Copy over data -- firmware data is LE. */
2255 ql_dbg(ql_dbg_mbx, vha, 0x1086, "Done %s.\n", __func__);
2256 dwords = offsetof(struct link_statistics, unused1) / 4;
2257 siter = diter = &stats->link_fail_cnt;
2258 while (dwords--)
2259 *diter++ = le32_to_cpu(*siter++);
2260 }
2261 } else {
2262 /* Failed. */
2263 ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
2264 }
2265
2266 return rval;
2267 }
2268
2269 int
qla24xx_get_isp_stats(scsi_qla_host_t * vha,struct link_statistics * stats,dma_addr_t stats_dma)2270 qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
2271 dma_addr_t stats_dma)
2272 {
2273 int rval;
2274 mbx_cmd_t mc;
2275 mbx_cmd_t *mcp = &mc;
2276 uint32_t *siter, *diter, dwords;
2277
2278 ql_dbg(ql_dbg_mbx, vha, 0x1088, "Entered %s.\n", __func__);
2279
2280 mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
2281 mcp->mb[2] = MSW(stats_dma);
2282 mcp->mb[3] = LSW(stats_dma);
2283 mcp->mb[6] = MSW(MSD(stats_dma));
2284 mcp->mb[7] = LSW(MSD(stats_dma));
2285 mcp->mb[8] = sizeof(struct link_statistics) / 4;
2286 mcp->mb[9] = vha->vp_idx;
2287 mcp->mb[10] = 0;
2288 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
2289 mcp->in_mb = MBX_2|MBX_1|MBX_0;
2290 mcp->tov = MBX_TOV_SECONDS;
2291 mcp->flags = IOCTL_CMD;
2292 rval = qla2x00_mailbox_command(vha, mcp);
2293
2294 if (rval == QLA_SUCCESS) {
2295 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
2296 ql_dbg(ql_dbg_mbx, vha, 0x1089,
2297 "Failed mb[0]=%x.\n", mcp->mb[0]);
2298 rval = QLA_FUNCTION_FAILED;
2299 } else {
2300 ql_dbg(ql_dbg_mbx, vha, 0x108a, "Done %s.\n", __func__);
2301 /* Copy over data -- firmware data is LE. */
2302 dwords = sizeof(struct link_statistics) / 4;
2303 siter = diter = &stats->link_fail_cnt;
2304 while (dwords--)
2305 *diter++ = le32_to_cpu(*siter++);
2306 }
2307 } else {
2308 /* Failed. */
2309 ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
2310 }
2311
2312 return rval;
2313 }
2314
2315 int
qla24xx_abort_command(srb_t * sp)2316 qla24xx_abort_command(srb_t *sp)
2317 {
2318 int rval;
2319 unsigned long flags = 0;
2320
2321 struct abort_entry_24xx *abt;
2322 dma_addr_t abt_dma;
2323 uint32_t handle;
2324 fc_port_t *fcport = sp->fcport;
2325 struct scsi_qla_host *vha = fcport->vha;
2326 struct qla_hw_data *ha = vha->hw;
2327 struct req_que *req = vha->req;
2328
2329 ql_dbg(ql_dbg_mbx, vha, 0x108c, "Entered %s.\n", __func__);
2330
2331 spin_lock_irqsave(&ha->hardware_lock, flags);
2332 for (handle = 1; handle < MAX_OUTSTANDING_COMMANDS; handle++) {
2333 if (req->outstanding_cmds[handle] == sp)
2334 break;
2335 }
2336 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2337 if (handle == MAX_OUTSTANDING_COMMANDS) {
2338 /* Command not found. */
2339 return QLA_FUNCTION_FAILED;
2340 }
2341
2342 abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
2343 if (abt == NULL) {
2344 ql_log(ql_log_warn, vha, 0x108d,
2345 "Failed to allocate abort IOCB.\n");
2346 return QLA_MEMORY_ALLOC_FAILED;
2347 }
2348 memset(abt, 0, sizeof(struct abort_entry_24xx));
2349
2350 abt->entry_type = ABORT_IOCB_TYPE;
2351 abt->entry_count = 1;
2352 abt->handle = MAKE_HANDLE(req->id, abt->handle);
2353 abt->nport_handle = cpu_to_le16(fcport->loop_id);
2354 abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
2355 abt->port_id[0] = fcport->d_id.b.al_pa;
2356 abt->port_id[1] = fcport->d_id.b.area;
2357 abt->port_id[2] = fcport->d_id.b.domain;
2358 abt->vp_index = fcport->vp_idx;
2359
2360 abt->req_que_no = cpu_to_le16(req->id);
2361
2362 rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
2363 if (rval != QLA_SUCCESS) {
2364 ql_dbg(ql_dbg_mbx, vha, 0x108e,
2365 "Failed to issue IOCB (%x).\n", rval);
2366 } else if (abt->entry_status != 0) {
2367 ql_dbg(ql_dbg_mbx, vha, 0x108f,
2368 "Failed to complete IOCB -- error status (%x).\n",
2369 abt->entry_status);
2370 rval = QLA_FUNCTION_FAILED;
2371 } else if (abt->nport_handle != __constant_cpu_to_le16(0)) {
2372 ql_dbg(ql_dbg_mbx, vha, 0x1090,
2373 "Failed to complete IOCB -- completion status (%x).\n",
2374 le16_to_cpu(abt->nport_handle));
2375 rval = QLA_FUNCTION_FAILED;
2376 } else {
2377 ql_dbg(ql_dbg_mbx, vha, 0x1091, "Done %s.\n", __func__);
2378 }
2379
2380 dma_pool_free(ha->s_dma_pool, abt, abt_dma);
2381
2382 return rval;
2383 }
2384
2385 struct tsk_mgmt_cmd {
2386 union {
2387 struct tsk_mgmt_entry tsk;
2388 struct sts_entry_24xx sts;
2389 } p;
2390 };
2391
2392 static int
__qla24xx_issue_tmf(char * name,uint32_t type,struct fc_port * fcport,unsigned int l,int tag)2393 __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
2394 unsigned int l, int tag)
2395 {
2396 int rval, rval2;
2397 struct tsk_mgmt_cmd *tsk;
2398 struct sts_entry_24xx *sts;
2399 dma_addr_t tsk_dma;
2400 scsi_qla_host_t *vha;
2401 struct qla_hw_data *ha;
2402 struct req_que *req;
2403 struct rsp_que *rsp;
2404
2405 vha = fcport->vha;
2406 ha = vha->hw;
2407 req = vha->req;
2408
2409 ql_dbg(ql_dbg_mbx, vha, 0x1092, "Entered %s.\n", __func__);
2410
2411 if (ha->flags.cpu_affinity_enabled)
2412 rsp = ha->rsp_q_map[tag + 1];
2413 else
2414 rsp = req->rsp;
2415 tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
2416 if (tsk == NULL) {
2417 ql_log(ql_log_warn, vha, 0x1093,
2418 "Failed to allocate task management IOCB.\n");
2419 return QLA_MEMORY_ALLOC_FAILED;
2420 }
2421 memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
2422
2423 tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
2424 tsk->p.tsk.entry_count = 1;
2425 tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
2426 tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
2427 tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
2428 tsk->p.tsk.control_flags = cpu_to_le32(type);
2429 tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
2430 tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
2431 tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
2432 tsk->p.tsk.vp_index = fcport->vp_idx;
2433 if (type == TCF_LUN_RESET) {
2434 int_to_scsilun(l, &tsk->p.tsk.lun);
2435 host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
2436 sizeof(tsk->p.tsk.lun));
2437 }
2438
2439 sts = &tsk->p.sts;
2440 rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
2441 if (rval != QLA_SUCCESS) {
2442 ql_dbg(ql_dbg_mbx, vha, 0x1094,
2443 "Failed to issue %s reset IOCB (%x).\n", name, rval);
2444 } else if (sts->entry_status != 0) {
2445 ql_dbg(ql_dbg_mbx, vha, 0x1095,
2446 "Failed to complete IOCB -- error status (%x).\n",
2447 sts->entry_status);
2448 rval = QLA_FUNCTION_FAILED;
2449 } else if (sts->comp_status !=
2450 __constant_cpu_to_le16(CS_COMPLETE)) {
2451 ql_dbg(ql_dbg_mbx, vha, 0x1096,
2452 "Failed to complete IOCB -- completion status (%x).\n",
2453 le16_to_cpu(sts->comp_status));
2454 rval = QLA_FUNCTION_FAILED;
2455 } else if (le16_to_cpu(sts->scsi_status) &
2456 SS_RESPONSE_INFO_LEN_VALID) {
2457 if (le32_to_cpu(sts->rsp_data_len) < 4) {
2458 ql_dbg(ql_dbg_mbx, vha, 0x1097,
2459 "Ignoring inconsistent data length -- not enough "
2460 "response info (%d).\n",
2461 le32_to_cpu(sts->rsp_data_len));
2462 } else if (sts->data[3]) {
2463 ql_dbg(ql_dbg_mbx, vha, 0x1098,
2464 "Failed to complete IOCB -- response (%x).\n",
2465 sts->data[3]);
2466 rval = QLA_FUNCTION_FAILED;
2467 }
2468 }
2469
2470 /* Issue marker IOCB. */
2471 rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
2472 type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
2473 if (rval2 != QLA_SUCCESS) {
2474 ql_dbg(ql_dbg_mbx, vha, 0x1099,
2475 "Failed to issue marker IOCB (%x).\n", rval2);
2476 } else {
2477 ql_dbg(ql_dbg_mbx, vha, 0x109a, "Done %s.\n", __func__);
2478 }
2479
2480 dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
2481
2482 return rval;
2483 }
2484
2485 int
qla24xx_abort_target(struct fc_port * fcport,unsigned int l,int tag)2486 qla24xx_abort_target(struct fc_port *fcport, unsigned int l, int tag)
2487 {
2488 struct qla_hw_data *ha = fcport->vha->hw;
2489
2490 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2491 return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
2492
2493 return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
2494 }
2495
2496 int
qla24xx_lun_reset(struct fc_port * fcport,unsigned int l,int tag)2497 qla24xx_lun_reset(struct fc_port *fcport, unsigned int l, int tag)
2498 {
2499 struct qla_hw_data *ha = fcport->vha->hw;
2500
2501 if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
2502 return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
2503
2504 return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
2505 }
2506
2507 int
qla2x00_system_error(scsi_qla_host_t * vha)2508 qla2x00_system_error(scsi_qla_host_t *vha)
2509 {
2510 int rval;
2511 mbx_cmd_t mc;
2512 mbx_cmd_t *mcp = &mc;
2513 struct qla_hw_data *ha = vha->hw;
2514
2515 if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
2516 return QLA_FUNCTION_FAILED;
2517
2518 ql_dbg(ql_dbg_mbx, vha, 0x109b, "Entered %s.\n", __func__);
2519
2520 mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
2521 mcp->out_mb = MBX_0;
2522 mcp->in_mb = MBX_0;
2523 mcp->tov = 5;
2524 mcp->flags = 0;
2525 rval = qla2x00_mailbox_command(vha, mcp);
2526
2527 if (rval != QLA_SUCCESS) {
2528 ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
2529 } else {
2530 ql_dbg(ql_dbg_mbx, vha, 0x109d, "Done %s.\n", __func__);
2531 }
2532
2533 return rval;
2534 }
2535
2536 /**
2537 * qla2x00_set_serdes_params() -
2538 * @ha: HA context
2539 *
2540 * Returns
2541 */
2542 int
qla2x00_set_serdes_params(scsi_qla_host_t * vha,uint16_t sw_em_1g,uint16_t sw_em_2g,uint16_t sw_em_4g)2543 qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
2544 uint16_t sw_em_2g, uint16_t sw_em_4g)
2545 {
2546 int rval;
2547 mbx_cmd_t mc;
2548 mbx_cmd_t *mcp = &mc;
2549
2550 ql_dbg(ql_dbg_mbx, vha, 0x109e, "Entered %s.\n", __func__);
2551
2552 mcp->mb[0] = MBC_SERDES_PARAMS;
2553 mcp->mb[1] = BIT_0;
2554 mcp->mb[2] = sw_em_1g | BIT_15;
2555 mcp->mb[3] = sw_em_2g | BIT_15;
2556 mcp->mb[4] = sw_em_4g | BIT_15;
2557 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2558 mcp->in_mb = MBX_0;
2559 mcp->tov = MBX_TOV_SECONDS;
2560 mcp->flags = 0;
2561 rval = qla2x00_mailbox_command(vha, mcp);
2562
2563 if (rval != QLA_SUCCESS) {
2564 /*EMPTY*/
2565 ql_dbg(ql_dbg_mbx, vha, 0x109f,
2566 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
2567 } else {
2568 /*EMPTY*/
2569 ql_dbg(ql_dbg_mbx, vha, 0x10a0, "Done %s.\n", __func__);
2570 }
2571
2572 return rval;
2573 }
2574
2575 int
qla2x00_stop_firmware(scsi_qla_host_t * vha)2576 qla2x00_stop_firmware(scsi_qla_host_t *vha)
2577 {
2578 int rval;
2579 mbx_cmd_t mc;
2580 mbx_cmd_t *mcp = &mc;
2581
2582 if (!IS_FWI2_CAPABLE(vha->hw))
2583 return QLA_FUNCTION_FAILED;
2584
2585 ql_dbg(ql_dbg_mbx, vha, 0x10a1, "Entered %s.\n", __func__);
2586
2587 mcp->mb[0] = MBC_STOP_FIRMWARE;
2588 mcp->mb[1] = 0;
2589 mcp->out_mb = MBX_1|MBX_0;
2590 mcp->in_mb = MBX_0;
2591 mcp->tov = 5;
2592 mcp->flags = 0;
2593 rval = qla2x00_mailbox_command(vha, mcp);
2594
2595 if (rval != QLA_SUCCESS) {
2596 ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
2597 if (mcp->mb[0] == MBS_INVALID_COMMAND)
2598 rval = QLA_INVALID_COMMAND;
2599 } else {
2600 ql_dbg(ql_dbg_mbx, vha, 0x10a3, "Done %s.\n", __func__);
2601 }
2602
2603 return rval;
2604 }
2605
2606 int
qla2x00_enable_eft_trace(scsi_qla_host_t * vha,dma_addr_t eft_dma,uint16_t buffers)2607 qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
2608 uint16_t buffers)
2609 {
2610 int rval;
2611 mbx_cmd_t mc;
2612 mbx_cmd_t *mcp = &mc;
2613
2614 ql_dbg(ql_dbg_mbx, vha, 0x10a4, "Entered %s.\n", __func__);
2615
2616 if (!IS_FWI2_CAPABLE(vha->hw))
2617 return QLA_FUNCTION_FAILED;
2618
2619 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2620 return QLA_FUNCTION_FAILED;
2621
2622 mcp->mb[0] = MBC_TRACE_CONTROL;
2623 mcp->mb[1] = TC_EFT_ENABLE;
2624 mcp->mb[2] = LSW(eft_dma);
2625 mcp->mb[3] = MSW(eft_dma);
2626 mcp->mb[4] = LSW(MSD(eft_dma));
2627 mcp->mb[5] = MSW(MSD(eft_dma));
2628 mcp->mb[6] = buffers;
2629 mcp->mb[7] = TC_AEN_DISABLE;
2630 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2631 mcp->in_mb = MBX_1|MBX_0;
2632 mcp->tov = MBX_TOV_SECONDS;
2633 mcp->flags = 0;
2634 rval = qla2x00_mailbox_command(vha, mcp);
2635 if (rval != QLA_SUCCESS) {
2636 ql_dbg(ql_dbg_mbx, vha, 0x10a5,
2637 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2638 rval, mcp->mb[0], mcp->mb[1]);
2639 } else {
2640 ql_dbg(ql_dbg_mbx, vha, 0x10a6, "Done %s.\n", __func__);
2641 }
2642
2643 return rval;
2644 }
2645
2646 int
qla2x00_disable_eft_trace(scsi_qla_host_t * vha)2647 qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
2648 {
2649 int rval;
2650 mbx_cmd_t mc;
2651 mbx_cmd_t *mcp = &mc;
2652
2653 ql_dbg(ql_dbg_mbx, vha, 0x10a7, "Entered %s.\n", __func__);
2654
2655 if (!IS_FWI2_CAPABLE(vha->hw))
2656 return QLA_FUNCTION_FAILED;
2657
2658 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2659 return QLA_FUNCTION_FAILED;
2660
2661 mcp->mb[0] = MBC_TRACE_CONTROL;
2662 mcp->mb[1] = TC_EFT_DISABLE;
2663 mcp->out_mb = MBX_1|MBX_0;
2664 mcp->in_mb = MBX_1|MBX_0;
2665 mcp->tov = MBX_TOV_SECONDS;
2666 mcp->flags = 0;
2667 rval = qla2x00_mailbox_command(vha, mcp);
2668 if (rval != QLA_SUCCESS) {
2669 ql_dbg(ql_dbg_mbx, vha, 0x10a8,
2670 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2671 rval, mcp->mb[0], mcp->mb[1]);
2672 } else {
2673 ql_dbg(ql_dbg_mbx, vha, 0x10a9, "Done %s.\n", __func__);
2674 }
2675
2676 return rval;
2677 }
2678
2679 int
qla2x00_enable_fce_trace(scsi_qla_host_t * vha,dma_addr_t fce_dma,uint16_t buffers,uint16_t * mb,uint32_t * dwords)2680 qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
2681 uint16_t buffers, uint16_t *mb, uint32_t *dwords)
2682 {
2683 int rval;
2684 mbx_cmd_t mc;
2685 mbx_cmd_t *mcp = &mc;
2686
2687 ql_dbg(ql_dbg_mbx, vha, 0x10aa, "Entered %s.\n", __func__);
2688
2689 if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw))
2690 return QLA_FUNCTION_FAILED;
2691
2692 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2693 return QLA_FUNCTION_FAILED;
2694
2695 mcp->mb[0] = MBC_TRACE_CONTROL;
2696 mcp->mb[1] = TC_FCE_ENABLE;
2697 mcp->mb[2] = LSW(fce_dma);
2698 mcp->mb[3] = MSW(fce_dma);
2699 mcp->mb[4] = LSW(MSD(fce_dma));
2700 mcp->mb[5] = MSW(MSD(fce_dma));
2701 mcp->mb[6] = buffers;
2702 mcp->mb[7] = TC_AEN_DISABLE;
2703 mcp->mb[8] = 0;
2704 mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
2705 mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
2706 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
2707 MBX_1|MBX_0;
2708 mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
2709 mcp->tov = MBX_TOV_SECONDS;
2710 mcp->flags = 0;
2711 rval = qla2x00_mailbox_command(vha, mcp);
2712 if (rval != QLA_SUCCESS) {
2713 ql_dbg(ql_dbg_mbx, vha, 0x10ab,
2714 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2715 rval, mcp->mb[0], mcp->mb[1]);
2716 } else {
2717 ql_dbg(ql_dbg_mbx, vha, 0x10ac, "Done %s.\n", __func__);
2718
2719 if (mb)
2720 memcpy(mb, mcp->mb, 8 * sizeof(*mb));
2721 if (dwords)
2722 *dwords = buffers;
2723 }
2724
2725 return rval;
2726 }
2727
2728 int
qla2x00_disable_fce_trace(scsi_qla_host_t * vha,uint64_t * wr,uint64_t * rd)2729 qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
2730 {
2731 int rval;
2732 mbx_cmd_t mc;
2733 mbx_cmd_t *mcp = &mc;
2734
2735 ql_dbg(ql_dbg_mbx, vha, 0x10ad, "Entered %s.\n", __func__);
2736
2737 if (!IS_FWI2_CAPABLE(vha->hw))
2738 return QLA_FUNCTION_FAILED;
2739
2740 if (unlikely(pci_channel_offline(vha->hw->pdev)))
2741 return QLA_FUNCTION_FAILED;
2742
2743 mcp->mb[0] = MBC_TRACE_CONTROL;
2744 mcp->mb[1] = TC_FCE_DISABLE;
2745 mcp->mb[2] = TC_FCE_DISABLE_TRACE;
2746 mcp->out_mb = MBX_2|MBX_1|MBX_0;
2747 mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
2748 MBX_1|MBX_0;
2749 mcp->tov = MBX_TOV_SECONDS;
2750 mcp->flags = 0;
2751 rval = qla2x00_mailbox_command(vha, mcp);
2752 if (rval != QLA_SUCCESS) {
2753 ql_dbg(ql_dbg_mbx, vha, 0x10ae,
2754 "Failed=%x mb[0]=%x mb[1]=%x.\n",
2755 rval, mcp->mb[0], mcp->mb[1]);
2756 } else {
2757 ql_dbg(ql_dbg_mbx, vha, 0x10af, "Done %s.\n", __func__);
2758
2759 if (wr)
2760 *wr = (uint64_t) mcp->mb[5] << 48 |
2761 (uint64_t) mcp->mb[4] << 32 |
2762 (uint64_t) mcp->mb[3] << 16 |
2763 (uint64_t) mcp->mb[2];
2764 if (rd)
2765 *rd = (uint64_t) mcp->mb[9] << 48 |
2766 (uint64_t) mcp->mb[8] << 32 |
2767 (uint64_t) mcp->mb[7] << 16 |
2768 (uint64_t) mcp->mb[6];
2769 }
2770
2771 return rval;
2772 }
2773
2774 int
qla2x00_get_idma_speed(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t * port_speed,uint16_t * mb)2775 qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
2776 uint16_t *port_speed, uint16_t *mb)
2777 {
2778 int rval;
2779 mbx_cmd_t mc;
2780 mbx_cmd_t *mcp = &mc;
2781
2782 ql_dbg(ql_dbg_mbx, vha, 0x10b0, "Entered %s.\n", __func__);
2783
2784 if (!IS_IIDMA_CAPABLE(vha->hw))
2785 return QLA_FUNCTION_FAILED;
2786
2787 mcp->mb[0] = MBC_PORT_PARAMS;
2788 mcp->mb[1] = loop_id;
2789 mcp->mb[2] = mcp->mb[3] = 0;
2790 mcp->mb[9] = vha->vp_idx;
2791 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
2792 mcp->in_mb = MBX_3|MBX_1|MBX_0;
2793 mcp->tov = MBX_TOV_SECONDS;
2794 mcp->flags = 0;
2795 rval = qla2x00_mailbox_command(vha, mcp);
2796
2797 /* Return mailbox statuses. */
2798 if (mb != NULL) {
2799 mb[0] = mcp->mb[0];
2800 mb[1] = mcp->mb[1];
2801 mb[3] = mcp->mb[3];
2802 }
2803
2804 if (rval != QLA_SUCCESS) {
2805 ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
2806 } else {
2807 ql_dbg(ql_dbg_mbx, vha, 0x10b2, "Done %s.\n", __func__);
2808 if (port_speed)
2809 *port_speed = mcp->mb[3];
2810 }
2811
2812 return rval;
2813 }
2814
2815 int
qla2x00_set_idma_speed(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t port_speed,uint16_t * mb)2816 qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
2817 uint16_t port_speed, uint16_t *mb)
2818 {
2819 int rval;
2820 mbx_cmd_t mc;
2821 mbx_cmd_t *mcp = &mc;
2822
2823 ql_dbg(ql_dbg_mbx, vha, 0x10b3, "Entered %s.\n", __func__);
2824
2825 if (!IS_IIDMA_CAPABLE(vha->hw))
2826 return QLA_FUNCTION_FAILED;
2827
2828 mcp->mb[0] = MBC_PORT_PARAMS;
2829 mcp->mb[1] = loop_id;
2830 mcp->mb[2] = BIT_0;
2831 if (IS_QLA8XXX_TYPE(vha->hw))
2832 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
2833 else
2834 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
2835 mcp->mb[9] = vha->vp_idx;
2836 mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
2837 mcp->in_mb = MBX_3|MBX_1|MBX_0;
2838 mcp->tov = MBX_TOV_SECONDS;
2839 mcp->flags = 0;
2840 rval = qla2x00_mailbox_command(vha, mcp);
2841
2842 /* Return mailbox statuses. */
2843 if (mb != NULL) {
2844 mb[0] = mcp->mb[0];
2845 mb[1] = mcp->mb[1];
2846 mb[3] = mcp->mb[3];
2847 }
2848
2849 if (rval != QLA_SUCCESS) {
2850 ql_dbg(ql_dbg_mbx, vha, 0x10b4, "Failed=%x.\n", rval);
2851 } else {
2852 ql_dbg(ql_dbg_mbx, vha, 0x10b5, "Done %s.\n", __func__);
2853 }
2854
2855 return rval;
2856 }
2857
2858 void
qla24xx_report_id_acquisition(scsi_qla_host_t * vha,struct vp_rpt_id_entry_24xx * rptid_entry)2859 qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
2860 struct vp_rpt_id_entry_24xx *rptid_entry)
2861 {
2862 uint8_t vp_idx;
2863 uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
2864 struct qla_hw_data *ha = vha->hw;
2865 scsi_qla_host_t *vp;
2866 unsigned long flags;
2867
2868 ql_dbg(ql_dbg_mbx, vha, 0x10b6, "Entered %s.\n", __func__);
2869
2870 if (rptid_entry->entry_status != 0)
2871 return;
2872
2873 if (rptid_entry->format == 0) {
2874 ql_dbg(ql_dbg_mbx, vha, 0x10b7,
2875 "Format 0 : Number of VPs setup %d, number of "
2876 "VPs acquired %d.\n",
2877 MSB(le16_to_cpu(rptid_entry->vp_count)),
2878 LSB(le16_to_cpu(rptid_entry->vp_count)));
2879 ql_dbg(ql_dbg_mbx, vha, 0x10b8,
2880 "Primary port id %02x%02x%02x.\n",
2881 rptid_entry->port_id[2], rptid_entry->port_id[1],
2882 rptid_entry->port_id[0]);
2883 } else if (rptid_entry->format == 1) {
2884 vp_idx = LSB(stat);
2885 ql_dbg(ql_dbg_mbx, vha, 0x10b9,
2886 "Format 1: VP[%d] enabled - status %d - with "
2887 "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
2888 rptid_entry->port_id[2], rptid_entry->port_id[1],
2889 rptid_entry->port_id[0]);
2890
2891 vp = vha;
2892 if (vp_idx == 0 && (MSB(stat) != 1))
2893 goto reg_needed;
2894
2895 if (MSB(stat) != 0) {
2896 ql_dbg(ql_dbg_mbx, vha, 0x10ba,
2897 "Could not acquire ID for VP[%d].\n", vp_idx);
2898 return;
2899 }
2900
2901 spin_lock_irqsave(&ha->vport_slock, flags);
2902 list_for_each_entry(vp, &ha->vp_list, list)
2903 if (vp_idx == vp->vp_idx)
2904 break;
2905 spin_unlock_irqrestore(&ha->vport_slock, flags);
2906
2907 if (!vp)
2908 return;
2909
2910 vp->d_id.b.domain = rptid_entry->port_id[2];
2911 vp->d_id.b.area = rptid_entry->port_id[1];
2912 vp->d_id.b.al_pa = rptid_entry->port_id[0];
2913
2914 /*
2915 * Cannot configure here as we are still sitting on the
2916 * response queue. Handle it in dpc context.
2917 */
2918 set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
2919
2920 reg_needed:
2921 set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
2922 set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
2923 set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
2924 qla2xxx_wake_dpc(vha);
2925 }
2926 }
2927
2928 /*
2929 * qla24xx_modify_vp_config
2930 * Change VP configuration for vha
2931 *
2932 * Input:
2933 * vha = adapter block pointer.
2934 *
2935 * Returns:
2936 * qla2xxx local function return status code.
2937 *
2938 * Context:
2939 * Kernel context.
2940 */
2941 int
qla24xx_modify_vp_config(scsi_qla_host_t * vha)2942 qla24xx_modify_vp_config(scsi_qla_host_t *vha)
2943 {
2944 int rval;
2945 struct vp_config_entry_24xx *vpmod;
2946 dma_addr_t vpmod_dma;
2947 struct qla_hw_data *ha = vha->hw;
2948 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2949
2950 /* This can be called by the parent */
2951
2952 ql_dbg(ql_dbg_mbx, vha, 0x10bb, "Entered %s.\n", __func__);
2953
2954 vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
2955 if (!vpmod) {
2956 ql_log(ql_log_warn, vha, 0x10bc,
2957 "Failed to allocate modify VP IOCB.\n");
2958 return QLA_MEMORY_ALLOC_FAILED;
2959 }
2960
2961 memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
2962 vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
2963 vpmod->entry_count = 1;
2964 vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
2965 vpmod->vp_count = 1;
2966 vpmod->vp_index1 = vha->vp_idx;
2967 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
2968 memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
2969 memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
2970 vpmod->entry_count = 1;
2971
2972 rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
2973 if (rval != QLA_SUCCESS) {
2974 ql_dbg(ql_dbg_mbx, vha, 0x10bd,
2975 "Failed to issue VP config IOCB (%x).\n", rval);
2976 } else if (vpmod->comp_status != 0) {
2977 ql_dbg(ql_dbg_mbx, vha, 0x10be,
2978 "Failed to complete IOCB -- error status (%x).\n",
2979 vpmod->comp_status);
2980 rval = QLA_FUNCTION_FAILED;
2981 } else if (vpmod->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
2982 ql_dbg(ql_dbg_mbx, vha, 0x10bf,
2983 "Failed to complete IOCB -- completion status (%x).\n",
2984 le16_to_cpu(vpmod->comp_status));
2985 rval = QLA_FUNCTION_FAILED;
2986 } else {
2987 /* EMPTY */
2988 ql_dbg(ql_dbg_mbx, vha, 0x10c0, "Done %s.\n", __func__);
2989 fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
2990 }
2991 dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
2992
2993 return rval;
2994 }
2995
2996 /*
2997 * qla24xx_control_vp
2998 * Enable a virtual port for given host
2999 *
3000 * Input:
3001 * ha = adapter block pointer.
3002 * vhba = virtual adapter (unused)
3003 * index = index number for enabled VP
3004 *
3005 * Returns:
3006 * qla2xxx local function return status code.
3007 *
3008 * Context:
3009 * Kernel context.
3010 */
3011 int
qla24xx_control_vp(scsi_qla_host_t * vha,int cmd)3012 qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
3013 {
3014 int rval;
3015 int map, pos;
3016 struct vp_ctrl_entry_24xx *vce;
3017 dma_addr_t vce_dma;
3018 struct qla_hw_data *ha = vha->hw;
3019 int vp_index = vha->vp_idx;
3020 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
3021
3022 ql_dbg(ql_dbg_mbx, vha, 0x10c1,
3023 "Entered %s enabling index %d.\n", __func__, vp_index);
3024
3025 if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
3026 return QLA_PARAMETER_ERROR;
3027
3028 vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
3029 if (!vce) {
3030 ql_log(ql_log_warn, vha, 0x10c2,
3031 "Failed to allocate VP control IOCB.\n");
3032 return QLA_MEMORY_ALLOC_FAILED;
3033 }
3034 memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
3035
3036 vce->entry_type = VP_CTRL_IOCB_TYPE;
3037 vce->entry_count = 1;
3038 vce->command = cpu_to_le16(cmd);
3039 vce->vp_count = __constant_cpu_to_le16(1);
3040
3041 /* index map in firmware starts with 1; decrement index
3042 * this is ok as we never use index 0
3043 */
3044 map = (vp_index - 1) / 8;
3045 pos = (vp_index - 1) & 7;
3046 mutex_lock(&ha->vport_lock);
3047 vce->vp_idx_map[map] |= 1 << pos;
3048 mutex_unlock(&ha->vport_lock);
3049
3050 rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
3051 if (rval != QLA_SUCCESS) {
3052 ql_dbg(ql_dbg_mbx, vha, 0x10c3,
3053 "Failed to issue VP control IOCB (%x).\n", rval);
3054 } else if (vce->entry_status != 0) {
3055 ql_dbg(ql_dbg_mbx, vha, 0x10c4,
3056 "Failed to complete IOCB -- error status (%x).\n",
3057 vce->entry_status);
3058 rval = QLA_FUNCTION_FAILED;
3059 } else if (vce->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
3060 ql_dbg(ql_dbg_mbx, vha, 0x10c5,
3061 "Failed to complet IOCB -- completion status (%x).\n",
3062 le16_to_cpu(vce->comp_status));
3063 rval = QLA_FUNCTION_FAILED;
3064 } else {
3065 ql_dbg(ql_dbg_mbx, vha, 0x10c6, "Done %s.\n", __func__);
3066 }
3067
3068 dma_pool_free(ha->s_dma_pool, vce, vce_dma);
3069
3070 return rval;
3071 }
3072
3073 /*
3074 * qla2x00_send_change_request
3075 * Receive or disable RSCN request from fabric controller
3076 *
3077 * Input:
3078 * ha = adapter block pointer
3079 * format = registration format:
3080 * 0 - Reserved
3081 * 1 - Fabric detected registration
3082 * 2 - N_port detected registration
3083 * 3 - Full registration
3084 * FF - clear registration
3085 * vp_idx = Virtual port index
3086 *
3087 * Returns:
3088 * qla2x00 local function return status code.
3089 *
3090 * Context:
3091 * Kernel Context
3092 */
3093
3094 int
qla2x00_send_change_request(scsi_qla_host_t * vha,uint16_t format,uint16_t vp_idx)3095 qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
3096 uint16_t vp_idx)
3097 {
3098 int rval;
3099 mbx_cmd_t mc;
3100 mbx_cmd_t *mcp = &mc;
3101
3102 ql_dbg(ql_dbg_mbx, vha, 0x10c7, "Entered %s.\n", __func__);
3103
3104 /*
3105 * This command is implicitly executed by firmware during login for the
3106 * physical hosts
3107 */
3108 if (vp_idx == 0)
3109 return QLA_FUNCTION_FAILED;
3110
3111 mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
3112 mcp->mb[1] = format;
3113 mcp->mb[9] = vp_idx;
3114 mcp->out_mb = MBX_9|MBX_1|MBX_0;
3115 mcp->in_mb = MBX_0|MBX_1;
3116 mcp->tov = MBX_TOV_SECONDS;
3117 mcp->flags = 0;
3118 rval = qla2x00_mailbox_command(vha, mcp);
3119
3120 if (rval == QLA_SUCCESS) {
3121 if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
3122 rval = BIT_1;
3123 }
3124 } else
3125 rval = BIT_1;
3126
3127 return rval;
3128 }
3129
3130 int
qla2x00_dump_ram(scsi_qla_host_t * vha,dma_addr_t req_dma,uint32_t addr,uint32_t size)3131 qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
3132 uint32_t size)
3133 {
3134 int rval;
3135 mbx_cmd_t mc;
3136 mbx_cmd_t *mcp = &mc;
3137
3138 ql_dbg(ql_dbg_mbx, vha, 0x1009, "Entered %s.\n", __func__);
3139
3140 if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
3141 mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
3142 mcp->mb[8] = MSW(addr);
3143 mcp->out_mb = MBX_8|MBX_0;
3144 } else {
3145 mcp->mb[0] = MBC_DUMP_RISC_RAM;
3146 mcp->out_mb = MBX_0;
3147 }
3148 mcp->mb[1] = LSW(addr);
3149 mcp->mb[2] = MSW(req_dma);
3150 mcp->mb[3] = LSW(req_dma);
3151 mcp->mb[6] = MSW(MSD(req_dma));
3152 mcp->mb[7] = LSW(MSD(req_dma));
3153 mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
3154 if (IS_FWI2_CAPABLE(vha->hw)) {
3155 mcp->mb[4] = MSW(size);
3156 mcp->mb[5] = LSW(size);
3157 mcp->out_mb |= MBX_5|MBX_4;
3158 } else {
3159 mcp->mb[4] = LSW(size);
3160 mcp->out_mb |= MBX_4;
3161 }
3162
3163 mcp->in_mb = MBX_0;
3164 mcp->tov = MBX_TOV_SECONDS;
3165 mcp->flags = 0;
3166 rval = qla2x00_mailbox_command(vha, mcp);
3167
3168 if (rval != QLA_SUCCESS) {
3169 ql_dbg(ql_dbg_mbx, vha, 0x1008,
3170 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3171 } else {
3172 ql_dbg(ql_dbg_mbx, vha, 0x1007, "Done %s.\n", __func__);
3173 }
3174
3175 return rval;
3176 }
3177
3178 /* 84XX Support **************************************************************/
3179
3180 struct cs84xx_mgmt_cmd {
3181 union {
3182 struct verify_chip_entry_84xx req;
3183 struct verify_chip_rsp_84xx rsp;
3184 } p;
3185 };
3186
3187 int
qla84xx_verify_chip(struct scsi_qla_host * vha,uint16_t * status)3188 qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
3189 {
3190 int rval, retry;
3191 struct cs84xx_mgmt_cmd *mn;
3192 dma_addr_t mn_dma;
3193 uint16_t options;
3194 unsigned long flags;
3195 struct qla_hw_data *ha = vha->hw;
3196
3197 ql_dbg(ql_dbg_mbx, vha, 0x10c8, "Entered %s.\n", __func__);
3198
3199 mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
3200 if (mn == NULL) {
3201 return QLA_MEMORY_ALLOC_FAILED;
3202 }
3203
3204 /* Force Update? */
3205 options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
3206 /* Diagnostic firmware? */
3207 /* options |= MENLO_DIAG_FW; */
3208 /* We update the firmware with only one data sequence. */
3209 options |= VCO_END_OF_DATA;
3210
3211 do {
3212 retry = 0;
3213 memset(mn, 0, sizeof(*mn));
3214 mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
3215 mn->p.req.entry_count = 1;
3216 mn->p.req.options = cpu_to_le16(options);
3217
3218 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
3219 "Dump of Verify Request.\n");
3220 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
3221 (uint8_t *)mn, sizeof(*mn));
3222
3223 rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
3224 if (rval != QLA_SUCCESS) {
3225 ql_dbg(ql_dbg_mbx, vha, 0x10cb,
3226 "Failed to issue verify IOCB (%x).\n", rval);
3227 goto verify_done;
3228 }
3229
3230 ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
3231 "Dump of Verify Response.\n");
3232 ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
3233 (uint8_t *)mn, sizeof(*mn));
3234
3235 status[0] = le16_to_cpu(mn->p.rsp.comp_status);
3236 status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
3237 le16_to_cpu(mn->p.rsp.failure_code) : 0;
3238 ql_dbg(ql_dbg_mbx, vha, 0x10ce,
3239 "cs=%x fc=%x.\n", status[0], status[1]);
3240
3241 if (status[0] != CS_COMPLETE) {
3242 rval = QLA_FUNCTION_FAILED;
3243 if (!(options & VCO_DONT_UPDATE_FW)) {
3244 ql_dbg(ql_dbg_mbx, vha, 0x10cf,
3245 "Firmware update failed. Retrying "
3246 "without update firmware.\n");
3247 options |= VCO_DONT_UPDATE_FW;
3248 options &= ~VCO_FORCE_UPDATE;
3249 retry = 1;
3250 }
3251 } else {
3252 ql_dbg(ql_dbg_mbx, vha, 0x10d0,
3253 "Firmware updated to %x.\n",
3254 le32_to_cpu(mn->p.rsp.fw_ver));
3255
3256 /* NOTE: we only update OP firmware. */
3257 spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
3258 ha->cs84xx->op_fw_version =
3259 le32_to_cpu(mn->p.rsp.fw_ver);
3260 spin_unlock_irqrestore(&ha->cs84xx->access_lock,
3261 flags);
3262 }
3263 } while (retry);
3264
3265 verify_done:
3266 dma_pool_free(ha->s_dma_pool, mn, mn_dma);
3267
3268 if (rval != QLA_SUCCESS) {
3269 ql_dbg(ql_dbg_mbx, vha, 0x10d1, "Failed=%x.\n", rval);
3270 } else {
3271 ql_dbg(ql_dbg_mbx, vha, 0x10d2, "Done %s.\n", __func__);
3272 }
3273
3274 return rval;
3275 }
3276
3277 int
qla25xx_init_req_que(struct scsi_qla_host * vha,struct req_que * req)3278 qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
3279 {
3280 int rval;
3281 unsigned long flags;
3282 mbx_cmd_t mc;
3283 mbx_cmd_t *mcp = &mc;
3284 struct device_reg_25xxmq __iomem *reg;
3285 struct qla_hw_data *ha = vha->hw;
3286
3287 ql_dbg(ql_dbg_mbx, vha, 0x10d3, "Entered %s.\n", __func__);
3288
3289 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3290 mcp->mb[1] = req->options;
3291 mcp->mb[2] = MSW(LSD(req->dma));
3292 mcp->mb[3] = LSW(LSD(req->dma));
3293 mcp->mb[6] = MSW(MSD(req->dma));
3294 mcp->mb[7] = LSW(MSD(req->dma));
3295 mcp->mb[5] = req->length;
3296 if (req->rsp)
3297 mcp->mb[10] = req->rsp->id;
3298 mcp->mb[12] = req->qos;
3299 mcp->mb[11] = req->vp_idx;
3300 mcp->mb[13] = req->rid;
3301
3302 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
3303 QLA_QUE_PAGE * req->id);
3304
3305 mcp->mb[4] = req->id;
3306 /* que in ptr index */
3307 mcp->mb[8] = 0;
3308 /* que out ptr index */
3309 mcp->mb[9] = 0;
3310 mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
3311 MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3312 mcp->in_mb = MBX_0;
3313 mcp->flags = MBX_DMA_OUT;
3314 mcp->tov = 60;
3315
3316 spin_lock_irqsave(&ha->hardware_lock, flags);
3317 if (!(req->options & BIT_0)) {
3318 WRT_REG_DWORD(®->req_q_in, 0);
3319 WRT_REG_DWORD(®->req_q_out, 0);
3320 }
3321 req->req_q_in = ®->req_q_in;
3322 req->req_q_out = ®->req_q_out;
3323 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3324
3325 rval = qla2x00_mailbox_command(vha, mcp);
3326 if (rval != QLA_SUCCESS) {
3327 ql_dbg(ql_dbg_mbx, vha, 0x10d4,
3328 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3329 } else {
3330 ql_dbg(ql_dbg_mbx, vha, 0x10d5, "Done %s.\n", __func__);
3331 }
3332
3333 return rval;
3334 }
3335
3336 int
qla25xx_init_rsp_que(struct scsi_qla_host * vha,struct rsp_que * rsp)3337 qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
3338 {
3339 int rval;
3340 unsigned long flags;
3341 mbx_cmd_t mc;
3342 mbx_cmd_t *mcp = &mc;
3343 struct device_reg_25xxmq __iomem *reg;
3344 struct qla_hw_data *ha = vha->hw;
3345
3346 ql_dbg(ql_dbg_mbx, vha, 0x10d6, "Entered %s.\n", __func__);
3347
3348 mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
3349 mcp->mb[1] = rsp->options;
3350 mcp->mb[2] = MSW(LSD(rsp->dma));
3351 mcp->mb[3] = LSW(LSD(rsp->dma));
3352 mcp->mb[6] = MSW(MSD(rsp->dma));
3353 mcp->mb[7] = LSW(MSD(rsp->dma));
3354 mcp->mb[5] = rsp->length;
3355 mcp->mb[14] = rsp->msix->entry;
3356 mcp->mb[13] = rsp->rid;
3357
3358 reg = (struct device_reg_25xxmq *)((void *)(ha->mqiobase) +
3359 QLA_QUE_PAGE * rsp->id);
3360
3361 mcp->mb[4] = rsp->id;
3362 /* que in ptr index */
3363 mcp->mb[8] = 0;
3364 /* que out ptr index */
3365 mcp->mb[9] = 0;
3366 mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
3367 |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3368 mcp->in_mb = MBX_0;
3369 mcp->flags = MBX_DMA_OUT;
3370 mcp->tov = 60;
3371
3372 spin_lock_irqsave(&ha->hardware_lock, flags);
3373 if (!(rsp->options & BIT_0)) {
3374 WRT_REG_DWORD(®->rsp_q_out, 0);
3375 WRT_REG_DWORD(®->rsp_q_in, 0);
3376 }
3377
3378 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3379
3380 rval = qla2x00_mailbox_command(vha, mcp);
3381 if (rval != QLA_SUCCESS) {
3382 ql_dbg(ql_dbg_mbx, vha, 0x10d7,
3383 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3384 } else {
3385 ql_dbg(ql_dbg_mbx, vha, 0x10d8, "Done %s.\n", __func__);
3386 }
3387
3388 return rval;
3389 }
3390
3391 int
qla81xx_idc_ack(scsi_qla_host_t * vha,uint16_t * mb)3392 qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
3393 {
3394 int rval;
3395 mbx_cmd_t mc;
3396 mbx_cmd_t *mcp = &mc;
3397
3398 ql_dbg(ql_dbg_mbx, vha, 0x10d9, "Entered %s.\n", __func__);
3399
3400 mcp->mb[0] = MBC_IDC_ACK;
3401 memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
3402 mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3403 mcp->in_mb = MBX_0;
3404 mcp->tov = MBX_TOV_SECONDS;
3405 mcp->flags = 0;
3406 rval = qla2x00_mailbox_command(vha, mcp);
3407
3408 if (rval != QLA_SUCCESS) {
3409 ql_dbg(ql_dbg_mbx, vha, 0x10da,
3410 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3411 } else {
3412 ql_dbg(ql_dbg_mbx, vha, 0x10db, "Done %s.\n", __func__);
3413 }
3414
3415 return rval;
3416 }
3417
3418 int
qla81xx_fac_get_sector_size(scsi_qla_host_t * vha,uint32_t * sector_size)3419 qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
3420 {
3421 int rval;
3422 mbx_cmd_t mc;
3423 mbx_cmd_t *mcp = &mc;
3424
3425 ql_dbg(ql_dbg_mbx, vha, 0x10dc, "Entered %s.\n", __func__);
3426
3427 if (!IS_QLA81XX(vha->hw))
3428 return QLA_FUNCTION_FAILED;
3429
3430 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3431 mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
3432 mcp->out_mb = MBX_1|MBX_0;
3433 mcp->in_mb = MBX_1|MBX_0;
3434 mcp->tov = MBX_TOV_SECONDS;
3435 mcp->flags = 0;
3436 rval = qla2x00_mailbox_command(vha, mcp);
3437
3438 if (rval != QLA_SUCCESS) {
3439 ql_dbg(ql_dbg_mbx, vha, 0x10dd,
3440 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3441 rval, mcp->mb[0], mcp->mb[1]);
3442 } else {
3443 ql_dbg(ql_dbg_mbx, vha, 0x10de, "Done %s.\n", __func__);
3444 *sector_size = mcp->mb[1];
3445 }
3446
3447 return rval;
3448 }
3449
3450 int
qla81xx_fac_do_write_enable(scsi_qla_host_t * vha,int enable)3451 qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
3452 {
3453 int rval;
3454 mbx_cmd_t mc;
3455 mbx_cmd_t *mcp = &mc;
3456
3457 if (!IS_QLA81XX(vha->hw))
3458 return QLA_FUNCTION_FAILED;
3459
3460 ql_dbg(ql_dbg_mbx, vha, 0x10df, "Entered %s.\n", __func__);
3461
3462 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3463 mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
3464 FAC_OPT_CMD_WRITE_PROTECT;
3465 mcp->out_mb = MBX_1|MBX_0;
3466 mcp->in_mb = MBX_1|MBX_0;
3467 mcp->tov = MBX_TOV_SECONDS;
3468 mcp->flags = 0;
3469 rval = qla2x00_mailbox_command(vha, mcp);
3470
3471 if (rval != QLA_SUCCESS) {
3472 ql_dbg(ql_dbg_mbx, vha, 0x10e0,
3473 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3474 rval, mcp->mb[0], mcp->mb[1]);
3475 } else {
3476 ql_dbg(ql_dbg_mbx, vha, 0x10e1, "Done %s.\n", __func__);
3477 }
3478
3479 return rval;
3480 }
3481
3482 int
qla81xx_fac_erase_sector(scsi_qla_host_t * vha,uint32_t start,uint32_t finish)3483 qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
3484 {
3485 int rval;
3486 mbx_cmd_t mc;
3487 mbx_cmd_t *mcp = &mc;
3488
3489 if (!IS_QLA81XX(vha->hw))
3490 return QLA_FUNCTION_FAILED;
3491
3492 ql_dbg(ql_dbg_mbx, vha, 0x10e2, "Entered %s.\n", __func__);
3493
3494 mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
3495 mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
3496 mcp->mb[2] = LSW(start);
3497 mcp->mb[3] = MSW(start);
3498 mcp->mb[4] = LSW(finish);
3499 mcp->mb[5] = MSW(finish);
3500 mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
3501 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3502 mcp->tov = MBX_TOV_SECONDS;
3503 mcp->flags = 0;
3504 rval = qla2x00_mailbox_command(vha, mcp);
3505
3506 if (rval != QLA_SUCCESS) {
3507 ql_dbg(ql_dbg_mbx, vha, 0x10e3,
3508 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3509 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
3510 } else {
3511 ql_dbg(ql_dbg_mbx, vha, 0x10e4, "Done %s.\n", __func__);
3512 }
3513
3514 return rval;
3515 }
3516
3517 int
qla81xx_restart_mpi_firmware(scsi_qla_host_t * vha)3518 qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
3519 {
3520 int rval = 0;
3521 mbx_cmd_t mc;
3522 mbx_cmd_t *mcp = &mc;
3523
3524 ql_dbg(ql_dbg_mbx, vha, 0x10e5, "Entered %s.\n", __func__);
3525
3526 mcp->mb[0] = MBC_RESTART_MPI_FW;
3527 mcp->out_mb = MBX_0;
3528 mcp->in_mb = MBX_0|MBX_1;
3529 mcp->tov = MBX_TOV_SECONDS;
3530 mcp->flags = 0;
3531 rval = qla2x00_mailbox_command(vha, mcp);
3532
3533 if (rval != QLA_SUCCESS) {
3534 ql_dbg(ql_dbg_mbx, vha, 0x10e6,
3535 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3536 rval, mcp->mb[0], mcp->mb[1]);
3537 } else {
3538 ql_dbg(ql_dbg_mbx, vha, 0x10e7, "Done %s.\n", __func__);
3539 }
3540
3541 return rval;
3542 }
3543
3544 int
qla2x00_read_sfp(scsi_qla_host_t * vha,dma_addr_t sfp_dma,uint8_t * sfp,uint16_t dev,uint16_t off,uint16_t len,uint16_t opt)3545 qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
3546 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
3547 {
3548 int rval;
3549 mbx_cmd_t mc;
3550 mbx_cmd_t *mcp = &mc;
3551 struct qla_hw_data *ha = vha->hw;
3552
3553 ql_dbg(ql_dbg_mbx, vha, 0x10e8, "Entered %s.\n", __func__);
3554
3555 if (!IS_FWI2_CAPABLE(ha))
3556 return QLA_FUNCTION_FAILED;
3557
3558 if (len == 1)
3559 opt |= BIT_0;
3560
3561 mcp->mb[0] = MBC_READ_SFP;
3562 mcp->mb[1] = dev;
3563 mcp->mb[2] = MSW(sfp_dma);
3564 mcp->mb[3] = LSW(sfp_dma);
3565 mcp->mb[6] = MSW(MSD(sfp_dma));
3566 mcp->mb[7] = LSW(MSD(sfp_dma));
3567 mcp->mb[8] = len;
3568 mcp->mb[9] = off;
3569 mcp->mb[10] = opt;
3570 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
3571 mcp->in_mb = MBX_1|MBX_0;
3572 mcp->tov = MBX_TOV_SECONDS;
3573 mcp->flags = 0;
3574 rval = qla2x00_mailbox_command(vha, mcp);
3575
3576 if (opt & BIT_0)
3577 *sfp = mcp->mb[1];
3578
3579 if (rval != QLA_SUCCESS) {
3580 ql_dbg(ql_dbg_mbx, vha, 0x10e9,
3581 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3582 } else {
3583 ql_dbg(ql_dbg_mbx, vha, 0x10ea, "Done %s.\n", __func__);
3584 }
3585
3586 return rval;
3587 }
3588
3589 int
qla2x00_write_sfp(scsi_qla_host_t * vha,dma_addr_t sfp_dma,uint8_t * sfp,uint16_t dev,uint16_t off,uint16_t len,uint16_t opt)3590 qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
3591 uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
3592 {
3593 int rval;
3594 mbx_cmd_t mc;
3595 mbx_cmd_t *mcp = &mc;
3596 struct qla_hw_data *ha = vha->hw;
3597
3598 ql_dbg(ql_dbg_mbx, vha, 0x10eb, "Entered %s.\n", __func__);
3599
3600 if (!IS_FWI2_CAPABLE(ha))
3601 return QLA_FUNCTION_FAILED;
3602
3603 if (len == 1)
3604 opt |= BIT_0;
3605
3606 if (opt & BIT_0)
3607 len = *sfp;
3608
3609 mcp->mb[0] = MBC_WRITE_SFP;
3610 mcp->mb[1] = dev;
3611 mcp->mb[2] = MSW(sfp_dma);
3612 mcp->mb[3] = LSW(sfp_dma);
3613 mcp->mb[6] = MSW(MSD(sfp_dma));
3614 mcp->mb[7] = LSW(MSD(sfp_dma));
3615 mcp->mb[8] = len;
3616 mcp->mb[9] = off;
3617 mcp->mb[10] = opt;
3618 mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
3619 mcp->in_mb = MBX_1|MBX_0;
3620 mcp->tov = MBX_TOV_SECONDS;
3621 mcp->flags = 0;
3622 rval = qla2x00_mailbox_command(vha, mcp);
3623
3624 if (rval != QLA_SUCCESS) {
3625 ql_dbg(ql_dbg_mbx, vha, 0x10ec,
3626 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3627 } else {
3628 ql_dbg(ql_dbg_mbx, vha, 0x10ed, "Done %s.\n", __func__);
3629 }
3630
3631 return rval;
3632 }
3633
3634 int
qla2x00_get_xgmac_stats(scsi_qla_host_t * vha,dma_addr_t stats_dma,uint16_t size_in_bytes,uint16_t * actual_size)3635 qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
3636 uint16_t size_in_bytes, uint16_t *actual_size)
3637 {
3638 int rval;
3639 mbx_cmd_t mc;
3640 mbx_cmd_t *mcp = &mc;
3641
3642 ql_dbg(ql_dbg_mbx, vha, 0x10ee, "Entered %s.\n", __func__);
3643
3644 if (!IS_QLA8XXX_TYPE(vha->hw))
3645 return QLA_FUNCTION_FAILED;
3646
3647 mcp->mb[0] = MBC_GET_XGMAC_STATS;
3648 mcp->mb[2] = MSW(stats_dma);
3649 mcp->mb[3] = LSW(stats_dma);
3650 mcp->mb[6] = MSW(MSD(stats_dma));
3651 mcp->mb[7] = LSW(MSD(stats_dma));
3652 mcp->mb[8] = size_in_bytes >> 2;
3653 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
3654 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3655 mcp->tov = MBX_TOV_SECONDS;
3656 mcp->flags = 0;
3657 rval = qla2x00_mailbox_command(vha, mcp);
3658
3659 if (rval != QLA_SUCCESS) {
3660 ql_dbg(ql_dbg_mbx, vha, 0x10ef,
3661 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3662 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
3663 } else {
3664 ql_dbg(ql_dbg_mbx, vha, 0x10f0, "Done %s.\n", __func__);
3665
3666
3667 *actual_size = mcp->mb[2] << 2;
3668 }
3669
3670 return rval;
3671 }
3672
3673 int
qla2x00_get_dcbx_params(scsi_qla_host_t * vha,dma_addr_t tlv_dma,uint16_t size)3674 qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
3675 uint16_t size)
3676 {
3677 int rval;
3678 mbx_cmd_t mc;
3679 mbx_cmd_t *mcp = &mc;
3680
3681 ql_dbg(ql_dbg_mbx, vha, 0x10f1, "Entered %s.\n", __func__);
3682
3683 if (!IS_QLA8XXX_TYPE(vha->hw))
3684 return QLA_FUNCTION_FAILED;
3685
3686 mcp->mb[0] = MBC_GET_DCBX_PARAMS;
3687 mcp->mb[1] = 0;
3688 mcp->mb[2] = MSW(tlv_dma);
3689 mcp->mb[3] = LSW(tlv_dma);
3690 mcp->mb[6] = MSW(MSD(tlv_dma));
3691 mcp->mb[7] = LSW(MSD(tlv_dma));
3692 mcp->mb[8] = size;
3693 mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
3694 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3695 mcp->tov = MBX_TOV_SECONDS;
3696 mcp->flags = 0;
3697 rval = qla2x00_mailbox_command(vha, mcp);
3698
3699 if (rval != QLA_SUCCESS) {
3700 ql_dbg(ql_dbg_mbx, vha, 0x10f2,
3701 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
3702 rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
3703 } else {
3704 ql_dbg(ql_dbg_mbx, vha, 0x10f3, "Done %s.\n", __func__);
3705 }
3706
3707 return rval;
3708 }
3709
3710 int
qla2x00_read_ram_word(scsi_qla_host_t * vha,uint32_t risc_addr,uint32_t * data)3711 qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
3712 {
3713 int rval;
3714 mbx_cmd_t mc;
3715 mbx_cmd_t *mcp = &mc;
3716
3717 ql_dbg(ql_dbg_mbx, vha, 0x10f4, "Entered %s.\n", __func__);
3718
3719 if (!IS_FWI2_CAPABLE(vha->hw))
3720 return QLA_FUNCTION_FAILED;
3721
3722 mcp->mb[0] = MBC_READ_RAM_EXTENDED;
3723 mcp->mb[1] = LSW(risc_addr);
3724 mcp->mb[8] = MSW(risc_addr);
3725 mcp->out_mb = MBX_8|MBX_1|MBX_0;
3726 mcp->in_mb = MBX_3|MBX_2|MBX_0;
3727 mcp->tov = 30;
3728 mcp->flags = 0;
3729 rval = qla2x00_mailbox_command(vha, mcp);
3730 if (rval != QLA_SUCCESS) {
3731 ql_dbg(ql_dbg_mbx, vha, 0x10f5,
3732 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3733 } else {
3734 ql_dbg(ql_dbg_mbx, vha, 0x10f6, "Done %s.\n", __func__);
3735 *data = mcp->mb[3] << 16 | mcp->mb[2];
3736 }
3737
3738 return rval;
3739 }
3740
3741 int
qla2x00_loopback_test(scsi_qla_host_t * vha,struct msg_echo_lb * mreq,uint16_t * mresp)3742 qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3743 uint16_t *mresp)
3744 {
3745 int rval;
3746 mbx_cmd_t mc;
3747 mbx_cmd_t *mcp = &mc;
3748 uint32_t iter_cnt = 0x1;
3749
3750 ql_dbg(ql_dbg_mbx, vha, 0x10f7, "Entered %s.\n", __func__);
3751
3752 memset(mcp->mb, 0 , sizeof(mcp->mb));
3753 mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
3754 mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
3755
3756 /* transfer count */
3757 mcp->mb[10] = LSW(mreq->transfer_size);
3758 mcp->mb[11] = MSW(mreq->transfer_size);
3759
3760 /* send data address */
3761 mcp->mb[14] = LSW(mreq->send_dma);
3762 mcp->mb[15] = MSW(mreq->send_dma);
3763 mcp->mb[20] = LSW(MSD(mreq->send_dma));
3764 mcp->mb[21] = MSW(MSD(mreq->send_dma));
3765
3766 /* receive data address */
3767 mcp->mb[16] = LSW(mreq->rcv_dma);
3768 mcp->mb[17] = MSW(mreq->rcv_dma);
3769 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
3770 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
3771
3772 /* Iteration count */
3773 mcp->mb[18] = LSW(iter_cnt);
3774 mcp->mb[19] = MSW(iter_cnt);
3775
3776 mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
3777 MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
3778 if (IS_QLA8XXX_TYPE(vha->hw))
3779 mcp->out_mb |= MBX_2;
3780 mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
3781
3782 mcp->buf_size = mreq->transfer_size;
3783 mcp->tov = MBX_TOV_SECONDS;
3784 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
3785
3786 rval = qla2x00_mailbox_command(vha, mcp);
3787
3788 if (rval != QLA_SUCCESS) {
3789 ql_dbg(ql_dbg_mbx, vha, 0x10f8,
3790 "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
3791 "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
3792 mcp->mb[3], mcp->mb[18], mcp->mb[19]);
3793 } else {
3794 ql_dbg(ql_dbg_mbx, vha, 0x10f9, "Done %s.\n", __func__);
3795 }
3796
3797 /* Copy mailbox information */
3798 memcpy( mresp, mcp->mb, 64);
3799 return rval;
3800 }
3801
3802 int
qla2x00_echo_test(scsi_qla_host_t * vha,struct msg_echo_lb * mreq,uint16_t * mresp)3803 qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
3804 uint16_t *mresp)
3805 {
3806 int rval;
3807 mbx_cmd_t mc;
3808 mbx_cmd_t *mcp = &mc;
3809 struct qla_hw_data *ha = vha->hw;
3810
3811 ql_dbg(ql_dbg_mbx, vha, 0x10fa, "Entered %s.\n", __func__);
3812
3813 memset(mcp->mb, 0 , sizeof(mcp->mb));
3814 mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
3815 mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
3816 if (IS_QLA8XXX_TYPE(ha)) {
3817 mcp->mb[1] |= BIT_15;
3818 mcp->mb[2] = vha->fcoe_fcf_idx;
3819 }
3820 mcp->mb[16] = LSW(mreq->rcv_dma);
3821 mcp->mb[17] = MSW(mreq->rcv_dma);
3822 mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
3823 mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
3824
3825 mcp->mb[10] = LSW(mreq->transfer_size);
3826
3827 mcp->mb[14] = LSW(mreq->send_dma);
3828 mcp->mb[15] = MSW(mreq->send_dma);
3829 mcp->mb[20] = LSW(MSD(mreq->send_dma));
3830 mcp->mb[21] = MSW(MSD(mreq->send_dma));
3831
3832 mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
3833 MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
3834 if (IS_QLA8XXX_TYPE(ha))
3835 mcp->out_mb |= MBX_2;
3836
3837 mcp->in_mb = MBX_0;
3838 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha))
3839 mcp->in_mb |= MBX_1;
3840 if (IS_QLA8XXX_TYPE(ha))
3841 mcp->in_mb |= MBX_3;
3842
3843 mcp->tov = MBX_TOV_SECONDS;
3844 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
3845 mcp->buf_size = mreq->transfer_size;
3846
3847 rval = qla2x00_mailbox_command(vha, mcp);
3848
3849 if (rval != QLA_SUCCESS) {
3850 ql_dbg(ql_dbg_mbx, vha, 0x10fb,
3851 "Failed=%x mb[0]=%x mb[1]=%x.\n",
3852 rval, mcp->mb[0], mcp->mb[1]);
3853 } else {
3854 ql_dbg(ql_dbg_mbx, vha, 0x10fc, "Done %s.\n", __func__);
3855 }
3856
3857 /* Copy mailbox information */
3858 memcpy(mresp, mcp->mb, 64);
3859 return rval;
3860 }
3861
3862 int
qla84xx_reset_chip(scsi_qla_host_t * vha,uint16_t enable_diagnostic)3863 qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
3864 {
3865 int rval;
3866 mbx_cmd_t mc;
3867 mbx_cmd_t *mcp = &mc;
3868
3869 ql_dbg(ql_dbg_mbx, vha, 0x10fd,
3870 "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
3871
3872 mcp->mb[0] = MBC_ISP84XX_RESET;
3873 mcp->mb[1] = enable_diagnostic;
3874 mcp->out_mb = MBX_1|MBX_0;
3875 mcp->in_mb = MBX_1|MBX_0;
3876 mcp->tov = MBX_TOV_SECONDS;
3877 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
3878 rval = qla2x00_mailbox_command(vha, mcp);
3879
3880 if (rval != QLA_SUCCESS)
3881 ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
3882 else
3883 ql_dbg(ql_dbg_mbx, vha, 0x10ff, "Done %s.\n", __func__);
3884
3885 return rval;
3886 }
3887
3888 int
qla2x00_write_ram_word(scsi_qla_host_t * vha,uint32_t risc_addr,uint32_t data)3889 qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
3890 {
3891 int rval;
3892 mbx_cmd_t mc;
3893 mbx_cmd_t *mcp = &mc;
3894
3895 ql_dbg(ql_dbg_mbx, vha, 0x1100, "Entered %s.\n", __func__);
3896
3897 if (!IS_FWI2_CAPABLE(vha->hw))
3898 return QLA_FUNCTION_FAILED;
3899
3900 mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
3901 mcp->mb[1] = LSW(risc_addr);
3902 mcp->mb[2] = LSW(data);
3903 mcp->mb[3] = MSW(data);
3904 mcp->mb[8] = MSW(risc_addr);
3905 mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
3906 mcp->in_mb = MBX_0;
3907 mcp->tov = 30;
3908 mcp->flags = 0;
3909 rval = qla2x00_mailbox_command(vha, mcp);
3910 if (rval != QLA_SUCCESS) {
3911 ql_dbg(ql_dbg_mbx, vha, 0x1101,
3912 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
3913 } else {
3914 ql_dbg(ql_dbg_mbx, vha, 0x1102, "Done %s.\n", __func__);
3915 }
3916
3917 return rval;
3918 }
3919
3920 int
qla81xx_write_mpi_register(scsi_qla_host_t * vha,uint16_t * mb)3921 qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
3922 {
3923 int rval;
3924 uint32_t stat, timer;
3925 uint16_t mb0 = 0;
3926 struct qla_hw_data *ha = vha->hw;
3927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
3928
3929 rval = QLA_SUCCESS;
3930
3931 ql_dbg(ql_dbg_mbx, vha, 0x1103, "Entered %s.\n", __func__);
3932
3933 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
3934
3935 /* Write the MBC data to the registers */
3936 WRT_REG_WORD(®->mailbox0, MBC_WRITE_MPI_REGISTER);
3937 WRT_REG_WORD(®->mailbox1, mb[0]);
3938 WRT_REG_WORD(®->mailbox2, mb[1]);
3939 WRT_REG_WORD(®->mailbox3, mb[2]);
3940 WRT_REG_WORD(®->mailbox4, mb[3]);
3941
3942 WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT);
3943
3944 /* Poll for MBC interrupt */
3945 for (timer = 6000000; timer; timer--) {
3946 /* Check for pending interrupts. */
3947 stat = RD_REG_DWORD(®->host_status);
3948 if (stat & HSRX_RISC_INT) {
3949 stat &= 0xff;
3950
3951 if (stat == 0x1 || stat == 0x2 ||
3952 stat == 0x10 || stat == 0x11) {
3953 set_bit(MBX_INTERRUPT,
3954 &ha->mbx_cmd_flags);
3955 mb0 = RD_REG_WORD(®->mailbox0);
3956 WRT_REG_DWORD(®->hccr,
3957 HCCRX_CLR_RISC_INT);
3958 RD_REG_DWORD(®->hccr);
3959 break;
3960 }
3961 }
3962 udelay(5);
3963 }
3964
3965 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
3966 rval = mb0 & MBS_MASK;
3967 else
3968 rval = QLA_FUNCTION_FAILED;
3969
3970 if (rval != QLA_SUCCESS) {
3971 ql_dbg(ql_dbg_mbx, vha, 0x1104,
3972 "Failed=%x mb[0]=%x.\n", rval, mb[0]);
3973 } else {
3974 ql_dbg(ql_dbg_mbx, vha, 0x1105, "Done %s.\n", __func__);
3975 }
3976
3977 return rval;
3978 }
3979 int
qla2x00_get_data_rate(scsi_qla_host_t * vha)3980 qla2x00_get_data_rate(scsi_qla_host_t *vha)
3981 {
3982 int rval;
3983 mbx_cmd_t mc;
3984 mbx_cmd_t *mcp = &mc;
3985 struct qla_hw_data *ha = vha->hw;
3986
3987 ql_dbg(ql_dbg_mbx, vha, 0x1106, "Entered %s.\n", __func__);
3988
3989 if (!IS_FWI2_CAPABLE(ha))
3990 return QLA_FUNCTION_FAILED;
3991
3992 mcp->mb[0] = MBC_DATA_RATE;
3993 mcp->mb[1] = 0;
3994 mcp->out_mb = MBX_1|MBX_0;
3995 mcp->in_mb = MBX_2|MBX_1|MBX_0;
3996 mcp->tov = MBX_TOV_SECONDS;
3997 mcp->flags = 0;
3998 rval = qla2x00_mailbox_command(vha, mcp);
3999 if (rval != QLA_SUCCESS) {
4000 ql_dbg(ql_dbg_mbx, vha, 0x1107,
4001 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4002 } else {
4003 ql_dbg(ql_dbg_mbx, vha, 0x1108, "Done %s.\n", __func__);
4004 if (mcp->mb[1] != 0x7)
4005 ha->link_data_rate = mcp->mb[1];
4006 }
4007
4008 return rval;
4009 }
4010
4011 int
qla81xx_get_port_config(scsi_qla_host_t * vha,uint16_t * mb)4012 qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4013 {
4014 int rval;
4015 mbx_cmd_t mc;
4016 mbx_cmd_t *mcp = &mc;
4017 struct qla_hw_data *ha = vha->hw;
4018
4019 ql_dbg(ql_dbg_mbx, vha, 0x1109, "Entered %s.\n", __func__);
4020
4021 if (!IS_QLA81XX(ha))
4022 return QLA_FUNCTION_FAILED;
4023 mcp->mb[0] = MBC_GET_PORT_CONFIG;
4024 mcp->out_mb = MBX_0;
4025 mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4026 mcp->tov = MBX_TOV_SECONDS;
4027 mcp->flags = 0;
4028
4029 rval = qla2x00_mailbox_command(vha, mcp);
4030
4031 if (rval != QLA_SUCCESS) {
4032 ql_dbg(ql_dbg_mbx, vha, 0x110a,
4033 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4034 } else {
4035 /* Copy all bits to preserve original value */
4036 memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
4037
4038 ql_dbg(ql_dbg_mbx, vha, 0x110b, "Done %s.\n", __func__);
4039 }
4040 return rval;
4041 }
4042
4043 int
qla81xx_set_port_config(scsi_qla_host_t * vha,uint16_t * mb)4044 qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
4045 {
4046 int rval;
4047 mbx_cmd_t mc;
4048 mbx_cmd_t *mcp = &mc;
4049
4050 ql_dbg(ql_dbg_mbx, vha, 0x110c, "Entered %s.\n", __func__);
4051
4052 mcp->mb[0] = MBC_SET_PORT_CONFIG;
4053 /* Copy all bits to preserve original setting */
4054 memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
4055 mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4056 mcp->in_mb = MBX_0;
4057 mcp->tov = MBX_TOV_SECONDS;
4058 mcp->flags = 0;
4059 rval = qla2x00_mailbox_command(vha, mcp);
4060
4061 if (rval != QLA_SUCCESS) {
4062 ql_dbg(ql_dbg_mbx, vha, 0x110d,
4063 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4064 } else
4065 ql_dbg(ql_dbg_mbx, vha, 0x110e, "Done %s.\n", __func__);
4066
4067 return rval;
4068 }
4069
4070
4071 int
qla24xx_set_fcp_prio(scsi_qla_host_t * vha,uint16_t loop_id,uint16_t priority,uint16_t * mb)4072 qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
4073 uint16_t *mb)
4074 {
4075 int rval;
4076 mbx_cmd_t mc;
4077 mbx_cmd_t *mcp = &mc;
4078 struct qla_hw_data *ha = vha->hw;
4079
4080 ql_dbg(ql_dbg_mbx, vha, 0x110f, "Entered %s.\n", __func__);
4081
4082 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
4083 return QLA_FUNCTION_FAILED;
4084
4085 mcp->mb[0] = MBC_PORT_PARAMS;
4086 mcp->mb[1] = loop_id;
4087 if (ha->flags.fcp_prio_enabled)
4088 mcp->mb[2] = BIT_1;
4089 else
4090 mcp->mb[2] = BIT_2;
4091 mcp->mb[4] = priority & 0xf;
4092 mcp->mb[9] = vha->vp_idx;
4093 mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4094 mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
4095 mcp->tov = 30;
4096 mcp->flags = 0;
4097 rval = qla2x00_mailbox_command(vha, mcp);
4098 if (mb != NULL) {
4099 mb[0] = mcp->mb[0];
4100 mb[1] = mcp->mb[1];
4101 mb[3] = mcp->mb[3];
4102 mb[4] = mcp->mb[4];
4103 }
4104
4105 if (rval != QLA_SUCCESS) {
4106 ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
4107 } else {
4108 ql_dbg(ql_dbg_mbx, vha, 0x10cc, "Done %s.\n", __func__);
4109 }
4110
4111 return rval;
4112 }
4113
4114 int
qla2x00_get_thermal_temp(scsi_qla_host_t * vha,uint16_t * temp,uint16_t * frac)4115 qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp, uint16_t *frac)
4116 {
4117 int rval;
4118 uint8_t byte;
4119 struct qla_hw_data *ha = vha->hw;
4120
4121 ql_dbg(ql_dbg_mbx, vha, 0x10ca, "Entered %s.\n", __func__);
4122
4123 /* Integer part */
4124 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x01, 1, BIT_13|BIT_0);
4125 if (rval != QLA_SUCCESS) {
4126 ql_dbg(ql_dbg_mbx, vha, 0x10c9, "Failed=%x.\n", rval);
4127 ha->flags.thermal_supported = 0;
4128 goto fail;
4129 }
4130 *temp = byte;
4131
4132 /* Fraction part */
4133 rval = qla2x00_read_sfp(vha, 0, &byte, 0x98, 0x10, 1, BIT_13|BIT_0);
4134 if (rval != QLA_SUCCESS) {
4135 ql_dbg(ql_dbg_mbx, vha, 0x1019, "Failed=%x.\n", rval);
4136 ha->flags.thermal_supported = 0;
4137 goto fail;
4138 }
4139 *frac = (byte >> 6) * 25;
4140
4141 ql_dbg(ql_dbg_mbx, vha, 0x1018, "Done %s.\n", __func__);
4142 fail:
4143 return rval;
4144 }
4145
4146 int
qla82xx_mbx_intr_enable(scsi_qla_host_t * vha)4147 qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
4148 {
4149 int rval;
4150 struct qla_hw_data *ha = vha->hw;
4151 mbx_cmd_t mc;
4152 mbx_cmd_t *mcp = &mc;
4153
4154 ql_dbg(ql_dbg_mbx, vha, 0x1017, "Entered %s.\n", __func__);
4155
4156 if (!IS_FWI2_CAPABLE(ha))
4157 return QLA_FUNCTION_FAILED;
4158
4159 memset(mcp, 0, sizeof(mbx_cmd_t));
4160 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4161 mcp->mb[1] = 1;
4162
4163 mcp->out_mb = MBX_1|MBX_0;
4164 mcp->in_mb = MBX_0;
4165 mcp->tov = 30;
4166 mcp->flags = 0;
4167
4168 rval = qla2x00_mailbox_command(vha, mcp);
4169 if (rval != QLA_SUCCESS) {
4170 ql_dbg(ql_dbg_mbx, vha, 0x1016,
4171 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4172 } else {
4173 ql_dbg(ql_dbg_mbx, vha, 0x100e, "Done %s.\n", __func__);
4174 }
4175
4176 return rval;
4177 }
4178
4179 int
qla82xx_mbx_intr_disable(scsi_qla_host_t * vha)4180 qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
4181 {
4182 int rval;
4183 struct qla_hw_data *ha = vha->hw;
4184 mbx_cmd_t mc;
4185 mbx_cmd_t *mcp = &mc;
4186
4187 ql_dbg(ql_dbg_mbx, vha, 0x100d, "Entered %s.\n", __func__);
4188
4189 if (!IS_QLA82XX(ha))
4190 return QLA_FUNCTION_FAILED;
4191
4192 memset(mcp, 0, sizeof(mbx_cmd_t));
4193 mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
4194 mcp->mb[1] = 0;
4195
4196 mcp->out_mb = MBX_1|MBX_0;
4197 mcp->in_mb = MBX_0;
4198 mcp->tov = 30;
4199 mcp->flags = 0;
4200
4201 rval = qla2x00_mailbox_command(vha, mcp);
4202 if (rval != QLA_SUCCESS) {
4203 ql_dbg(ql_dbg_mbx, vha, 0x100c,
4204 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4205 } else {
4206 ql_dbg(ql_dbg_mbx, vha, 0x100b, "Done %s.\n", __func__);
4207 }
4208
4209 return rval;
4210 }
4211
4212 int
qla82xx_md_get_template_size(scsi_qla_host_t * vha)4213 qla82xx_md_get_template_size(scsi_qla_host_t *vha)
4214 {
4215 struct qla_hw_data *ha = vha->hw;
4216 mbx_cmd_t mc;
4217 mbx_cmd_t *mcp = &mc;
4218 int rval = QLA_FUNCTION_FAILED;
4219
4220 ql_dbg(ql_dbg_mbx, vha, 0x111f, "Entered %s.\n", __func__);
4221
4222 memset(mcp->mb, 0 , sizeof(mcp->mb));
4223 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4224 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4225 mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
4226 mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
4227
4228 mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4229 mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
4230 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4231
4232 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4233 mcp->tov = MBX_TOV_SECONDS;
4234 rval = qla2x00_mailbox_command(vha, mcp);
4235
4236 /* Always copy back return mailbox values. */
4237 if (rval != QLA_SUCCESS) {
4238 ql_dbg(ql_dbg_mbx, vha, 0x1120,
4239 "mailbox command FAILED=0x%x, subcode=%x.\n",
4240 (mcp->mb[1] << 16) | mcp->mb[0],
4241 (mcp->mb[3] << 16) | mcp->mb[2]);
4242 } else {
4243 ql_dbg(ql_dbg_mbx, vha, 0x1121, "Done %s.\n", __func__);
4244 ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
4245 if (!ha->md_template_size) {
4246 ql_dbg(ql_dbg_mbx, vha, 0x1122,
4247 "Null template size obtained.\n");
4248 rval = QLA_FUNCTION_FAILED;
4249 }
4250 }
4251 return rval;
4252 }
4253
4254 int
qla82xx_md_get_template(scsi_qla_host_t * vha)4255 qla82xx_md_get_template(scsi_qla_host_t *vha)
4256 {
4257 struct qla_hw_data *ha = vha->hw;
4258 mbx_cmd_t mc;
4259 mbx_cmd_t *mcp = &mc;
4260 int rval = QLA_FUNCTION_FAILED;
4261
4262 ql_dbg(ql_dbg_mbx, vha, 0x1123, "Entered %s.\n", __func__);
4263
4264 ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
4265 ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
4266 if (!ha->md_tmplt_hdr) {
4267 ql_log(ql_log_warn, vha, 0x1124,
4268 "Unable to allocate memory for Minidump template.\n");
4269 return rval;
4270 }
4271
4272 memset(mcp->mb, 0 , sizeof(mcp->mb));
4273 mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4274 mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
4275 mcp->mb[2] = LSW(RQST_TMPLT);
4276 mcp->mb[3] = MSW(RQST_TMPLT);
4277 mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
4278 mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
4279 mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
4280 mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
4281 mcp->mb[8] = LSW(ha->md_template_size);
4282 mcp->mb[9] = MSW(ha->md_template_size);
4283
4284 mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
4285 mcp->tov = MBX_TOV_SECONDS;
4286 mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
4287 MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
4288 mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
4289 rval = qla2x00_mailbox_command(vha, mcp);
4290
4291 if (rval != QLA_SUCCESS) {
4292 ql_dbg(ql_dbg_mbx, vha, 0x1125,
4293 "mailbox command FAILED=0x%x, subcode=%x.\n",
4294 ((mcp->mb[1] << 16) | mcp->mb[0]),
4295 ((mcp->mb[3] << 16) | mcp->mb[2]));
4296 } else
4297 ql_dbg(ql_dbg_mbx, vha, 0x1126, "Done %s.\n", __func__);
4298 return rval;
4299 }
4300
4301 int
qla82xx_mbx_beacon_ctl(scsi_qla_host_t * vha,int enable)4302 qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
4303 {
4304 int rval;
4305 struct qla_hw_data *ha = vha->hw;
4306 mbx_cmd_t mc;
4307 mbx_cmd_t *mcp = &mc;
4308
4309 if (!IS_QLA82XX(ha))
4310 return QLA_FUNCTION_FAILED;
4311
4312 ql_dbg(ql_dbg_mbx, vha, 0x1127,
4313 "Entered %s.\n", __func__);
4314
4315 memset(mcp, 0, sizeof(mbx_cmd_t));
4316 mcp->mb[0] = MBC_SET_LED_CONFIG;
4317 if (enable)
4318 mcp->mb[7] = 0xE;
4319 else
4320 mcp->mb[7] = 0xD;
4321
4322 mcp->out_mb = MBX_7|MBX_0;
4323 mcp->in_mb = MBX_0;
4324 mcp->tov = 30;
4325 mcp->flags = 0;
4326
4327 rval = qla2x00_mailbox_command(vha, mcp);
4328 if (rval != QLA_SUCCESS) {
4329 ql_dbg(ql_dbg_mbx, vha, 0x1128,
4330 "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
4331 } else {
4332 ql_dbg(ql_dbg_mbx, vha, 0x1129,
4333 "Done %s.\n", __func__);
4334 }
4335
4336 return rval;
4337 }
4338