1 /*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "qemu/osdep.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "cpu.h"
28 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "accel/tcg/cpu-ldst.h"
31 #include "exec/gdbstub.h"
32 #include "exec/translation-block.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "accel/tcg/cpu-ops.h"
35 #include "tcg/tcg.h"
36
37 static const struct {
38 const char *name;
39 uint8_t version_id;
40 } mb_cpu_lookup[] = {
41 /* These key value are as per MBV field in PVR0 */
42 {"5.00.a", 0x01},
43 {"5.00.b", 0x02},
44 {"5.00.c", 0x03},
45 {"6.00.a", 0x04},
46 {"6.00.b", 0x06},
47 {"7.00.a", 0x05},
48 {"7.00.b", 0x07},
49 {"7.10.a", 0x08},
50 {"7.10.b", 0x09},
51 {"7.10.c", 0x0a},
52 {"7.10.d", 0x0b},
53 {"7.20.a", 0x0c},
54 {"7.20.b", 0x0d},
55 {"7.20.c", 0x0e},
56 {"7.20.d", 0x0f},
57 {"7.30.a", 0x10},
58 {"7.30.b", 0x11},
59 {"8.00.a", 0x12},
60 {"8.00.b", 0x13},
61 {"8.10.a", 0x14},
62 {"8.20.a", 0x15},
63 {"8.20.b", 0x16},
64 {"8.30.a", 0x17},
65 {"8.40.a", 0x18},
66 {"8.40.b", 0x19},
67 {"8.50.a", 0x1A},
68 {"9.0", 0x1B},
69 {"9.1", 0x1D},
70 {"9.2", 0x1F},
71 {"9.3", 0x20},
72 {"9.4", 0x21},
73 {"9.5", 0x22},
74 {"9.6", 0x23},
75 {"10.0", 0x24},
76 {NULL, 0},
77 };
78
79 /* If no specific version gets selected, default to the following. */
80 #define DEFAULT_CPU_VERSION "10.0"
81
mb_cpu_set_pc(CPUState * cs,vaddr value)82 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
83 {
84 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
85
86 cpu->env.pc = value;
87 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
88 cpu->env.iflags = 0;
89 }
90
mb_cpu_get_pc(CPUState * cs)91 static vaddr mb_cpu_get_pc(CPUState *cs)
92 {
93 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
94
95 return cpu->env.pc;
96 }
97
mb_get_tb_cpu_state(CPUState * cs)98 static TCGTBCPUState mb_get_tb_cpu_state(CPUState *cs)
99 {
100 CPUMBState *env = cpu_env(cs);
101
102 return (TCGTBCPUState){
103 .pc = env->pc,
104 .flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK),
105 .cs_base = (env->iflags & IMM_FLAG ? env->imm : 0),
106 };
107 }
108
mb_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)109 static void mb_cpu_synchronize_from_tb(CPUState *cs,
110 const TranslationBlock *tb)
111 {
112 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
113
114 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
115 cpu->env.pc = tb->pc;
116 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
117 }
118
mb_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)119 static void mb_restore_state_to_opc(CPUState *cs,
120 const TranslationBlock *tb,
121 const uint64_t *data)
122 {
123 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
124
125 cpu->env.pc = data[0];
126 cpu->env.iflags = data[1];
127 }
128
129 #ifndef CONFIG_USER_ONLY
mb_cpu_has_work(CPUState * cs)130 static bool mb_cpu_has_work(CPUState *cs)
131 {
132 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
133 }
134 #endif /* !CONFIG_USER_ONLY */
135
mb_cpu_mmu_index(CPUState * cs,bool ifetch)136 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
137 {
138 CPUMBState *env = cpu_env(cs);
139 MicroBlazeCPU *cpu = env_archcpu(env);
140
141 /* Are we in nommu mode?. */
142 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
143 return MMU_NOMMU_IDX;
144 }
145
146 if (env->msr & MSR_UM) {
147 return MMU_USER_IDX;
148 }
149 return MMU_KERNEL_IDX;
150 }
151
152 #ifndef CONFIG_USER_ONLY
mb_cpu_ns_axi_dp(void * opaque,int irq,int level)153 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
154 {
155 MicroBlazeCPU *cpu = opaque;
156 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
157
158 cpu->ns_axi_dp = level & en;
159 }
160
mb_cpu_ns_axi_ip(void * opaque,int irq,int level)161 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
162 {
163 MicroBlazeCPU *cpu = opaque;
164 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
165
166 cpu->ns_axi_ip = level & en;
167 }
168
mb_cpu_ns_axi_dc(void * opaque,int irq,int level)169 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
170 {
171 MicroBlazeCPU *cpu = opaque;
172 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
173
174 cpu->ns_axi_dc = level & en;
175 }
176
mb_cpu_ns_axi_ic(void * opaque,int irq,int level)177 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
178 {
179 MicroBlazeCPU *cpu = opaque;
180 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
181
182 cpu->ns_axi_ic = level & en;
183 }
184
microblaze_cpu_set_irq(void * opaque,int irq,int level)185 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
186 {
187 MicroBlazeCPU *cpu = opaque;
188 CPUState *cs = CPU(cpu);
189 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
190
191 if (level) {
192 cpu_interrupt(cs, type);
193 } else {
194 cpu_reset_interrupt(cs, type);
195 }
196 }
197 #endif
198
mb_cpu_reset_hold(Object * obj,ResetType type)199 static void mb_cpu_reset_hold(Object *obj, ResetType type)
200 {
201 CPUState *cs = CPU(obj);
202 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
203 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj);
204 CPUMBState *env = &cpu->env;
205
206 if (mcc->parent_phases.hold) {
207 mcc->parent_phases.hold(obj, type);
208 }
209
210 memset(env, 0, offsetof(CPUMBState, end_reset_fields));
211 env->res_addr = RES_ADDR_NONE;
212
213 /* Disable stack protector. */
214 env->shr = ~0;
215
216 env->pc = cpu->cfg.base_vectors;
217
218 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
219 /*
220 * TODO: this is probably not the correct NaN propagation rule for
221 * this architecture.
222 */
223 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
224 /* Default NaN: sign bit set, most significant frac bit set */
225 set_float_default_nan_pattern(0b11000000, &env->fp_status);
226
227 #if defined(CONFIG_USER_ONLY)
228 /* start in user mode with interrupts enabled. */
229 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
230 #else
231 mb_cpu_write_msr(env, 0);
232 mmu_init(&env->mmu);
233 #endif
234 }
235
mb_disas_set_info(CPUState * cpu,disassemble_info * info)236 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
237 {
238 info->mach = bfd_arch_microblaze;
239 info->print_insn = print_insn_microblaze;
240 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
241 : BFD_ENDIAN_LITTLE;
242 }
243
mb_cpu_realizefn(DeviceState * dev,Error ** errp)244 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
245 {
246 CPUState *cs = CPU(dev);
247 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
248 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
249 uint8_t version_code = 0;
250 const char *version;
251 int i = 0;
252 Error *local_err = NULL;
253
254 cpu_exec_realizefn(cs, &local_err);
255 if (local_err != NULL) {
256 error_propagate(errp, local_err);
257 return;
258 }
259
260 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
261 error_setg(errp, "addr-size %d is out of range (32 - 64)",
262 cpu->cfg.addr_size);
263 return;
264 }
265
266 gdb_register_coprocessor(cs, mb_cpu_gdb_read_stack_protect,
267 mb_cpu_gdb_write_stack_protect,
268 gdb_find_static_feature("microblaze-stack-protect.xml"),
269 0);
270
271 qemu_init_vcpu(cs);
272
273 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
274 for (i = 0; mb_cpu_lookup[i].name && version; i++) {
275 if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
276 version_code = mb_cpu_lookup[i].version_id;
277 break;
278 }
279 }
280
281 if (!version_code) {
282 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
283 }
284
285 cpu->cfg.pvr_regs[0] =
286 (PVR0_USE_EXC_MASK |
287 PVR0_USE_ICACHE_MASK |
288 PVR0_USE_DCACHE_MASK |
289 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
290 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
291 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
292 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
293 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
294 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
295 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
296 (version_code << PVR0_VERSION_SHIFT) |
297 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
298 cpu->cfg.pvr_user1);
299
300 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
301
302 cpu->cfg.pvr_regs[2] =
303 (PVR2_D_OPB_MASK |
304 PVR2_D_LMB_MASK |
305 PVR2_I_OPB_MASK |
306 PVR2_I_LMB_MASK |
307 PVR2_FPU_EXC_MASK |
308 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
309 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
310 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
311 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
312 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
313 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
314 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
315 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
316 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
317 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
318 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
319 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
320 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
321 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
322
323 cpu->cfg.pvr_regs[5] |=
324 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
325
326 cpu->cfg.pvr_regs[10] =
327 (0x0c000000 | /* Default to spartan 3a dsp family. */
328 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
329
330 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
331 16 << 17);
332
333 cpu->cfg.mmu = 3;
334 cpu->cfg.mmu_tlb_access = 3;
335 cpu->cfg.mmu_zones = 16;
336 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
337
338 mcc->parent_realize(dev, errp);
339 }
340
mb_cpu_initfn(Object * obj)341 static void mb_cpu_initfn(Object *obj)
342 {
343 #ifndef CONFIG_USER_ONLY
344 /* Inbound IRQ and FIR lines */
345 qdev_init_gpio_in(DEVICE(obj), microblaze_cpu_set_irq, 2);
346 qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
347 qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
348 qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
349 qdev_init_gpio_in_named(DEVICE(obj), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
350 #endif
351
352 /* Restricted 'endianness' property is equivalent of 'little-endian' */
353 object_property_add_alias(obj, "little-endian", obj, "endianness");
354 }
355
356 static const Property mb_properties[] = {
357 /*
358 * Following properties are used by Xilinx DTS conversion tool
359 * do not rename them.
360 */
361 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
362 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
363 false),
364 /*
365 * This is the C_ADDR_SIZE synth-time configuration option of the
366 * MicroBlaze cores. Supported values range between 32 and 64.
367 *
368 * When set to > 32, 32bit MicroBlaze can emit load/stores
369 * with extended addressing.
370 */
371 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
372 /* If use-fpu > 0 - FPU is enabled
373 * If use-fpu = 2 - Floating point conversion and square root instructions
374 * are enabled
375 */
376 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
377 /* If use-hw-mul > 0 - Multiplier is enabled
378 * If use-hw-mul = 2 - 64-bit multiplier is enabled
379 */
380 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
381 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
382 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
383 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
384 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
385 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
386 /*
387 * use-non-secure enables/disables the use of the non_secure[3:0] signals.
388 * It is a bitfield where 1 = non-secure for the following bits and their
389 * corresponding interfaces:
390 * 0x1 - M_AXI_DP
391 * 0x2 - M_AXI_IP
392 * 0x4 - M_AXI_DC
393 * 0x8 - M_AXI_IC
394 */
395 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
396 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
397 false),
398 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
399 /* Enables bus exceptions on failed data accesses (load/stores). */
400 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
401 cfg.dopb_bus_exception, false),
402 /* Enables bus exceptions on failed instruction fetches. */
403 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
404 cfg.iopb_bus_exception, false),
405 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
406 cfg.illegal_opcode_exception, false),
407 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
408 cfg.div_zero_exception, false),
409 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
410 cfg.unaligned_exceptions, false),
411 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
412 cfg.opcode_0_illegal, false),
413 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
414 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
415 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
416 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
417 /*
418 * End of properties reserved by Xilinx DTS conversion tool.
419 */
420 };
421
mb_cpu_class_by_name(const char * cpu_model)422 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
423 {
424 return object_class_by_name(TYPE_MICROBLAZE_CPU);
425 }
426
427 #ifndef CONFIG_USER_ONLY
428 #include "hw/core/sysemu-cpu-ops.h"
429
430 static const struct SysemuCPUOps mb_sysemu_ops = {
431 .has_work = mb_cpu_has_work,
432 .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
433 };
434 #endif
435
436 static const TCGCPUOps mb_tcg_ops = {
437 /* MicroBlaze is always in-order. */
438 .guest_default_memory_order = TCG_MO_ALL,
439 .mttcg_supported = true,
440
441 .initialize = mb_tcg_init,
442 .translate_code = mb_translate_code,
443 .get_tb_cpu_state = mb_get_tb_cpu_state,
444 .synchronize_from_tb = mb_cpu_synchronize_from_tb,
445 .restore_state_to_opc = mb_restore_state_to_opc,
446 .mmu_index = mb_cpu_mmu_index,
447
448 #ifndef CONFIG_USER_ONLY
449 .tlb_fill = mb_cpu_tlb_fill,
450 .pointer_wrap = cpu_pointer_wrap_uint32,
451 .cpu_exec_interrupt = mb_cpu_exec_interrupt,
452 .cpu_exec_halt = mb_cpu_has_work,
453 .cpu_exec_reset = cpu_reset,
454 .do_interrupt = mb_cpu_do_interrupt,
455 .do_transaction_failed = mb_cpu_transaction_failed,
456 .do_unaligned_access = mb_cpu_do_unaligned_access,
457 #endif /* !CONFIG_USER_ONLY */
458 };
459
mb_cpu_class_init(ObjectClass * oc,const void * data)460 static void mb_cpu_class_init(ObjectClass *oc, const void *data)
461 {
462 DeviceClass *dc = DEVICE_CLASS(oc);
463 CPUClass *cc = CPU_CLASS(oc);
464 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
465 ResettableClass *rc = RESETTABLE_CLASS(oc);
466
467 device_class_set_parent_realize(dc, mb_cpu_realizefn,
468 &mcc->parent_realize);
469 resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
470 &mcc->parent_phases);
471
472 cc->class_by_name = mb_cpu_class_by_name;
473 cc->dump_state = mb_cpu_dump_state;
474 cc->set_pc = mb_cpu_set_pc;
475 cc->get_pc = mb_cpu_get_pc;
476 cc->gdb_read_register = mb_cpu_gdb_read_register;
477 cc->gdb_write_register = mb_cpu_gdb_write_register;
478
479 #ifndef CONFIG_USER_ONLY
480 dc->vmsd = &vmstate_mb_cpu;
481 cc->sysemu_ops = &mb_sysemu_ops;
482 #endif
483 device_class_set_props(dc, mb_properties);
484 cc->gdb_core_xml_file = "microblaze-core.xml";
485
486 cc->disas_set_info = mb_disas_set_info;
487 cc->tcg_ops = &mb_tcg_ops;
488 }
489
490 static const TypeInfo mb_cpu_type_info = {
491 .name = TYPE_MICROBLAZE_CPU,
492 .parent = TYPE_CPU,
493 .instance_size = sizeof(MicroBlazeCPU),
494 .instance_align = __alignof(MicroBlazeCPU),
495 .instance_init = mb_cpu_initfn,
496 .class_size = sizeof(MicroBlazeCPUClass),
497 .class_init = mb_cpu_class_init,
498 };
499
mb_cpu_register_types(void)500 static void mb_cpu_register_types(void)
501 {
502 type_register_static(&mb_cpu_type_info);
503 }
504
505 type_init(mb_cpu_register_types)
506