1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/etherdevice.h>
7 #include <linux/of.h>
8 #include <linux/hwmon.h>
9 #include <linux/hwmon-sysfs.h>
10 #include <linux/thermal.h>
11 #include "mt7996.h"
12 #include "mac.h"
13 #include "mcu.h"
14 #include "coredump.h"
15 #include "eeprom.h"
16 #if defined(__FreeBSD__)
17 #include <linux/delay.h>
18 #endif
19
20 static const struct ieee80211_iface_limit if_limits_global = {
21 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
22 .types = BIT(NL80211_IFTYPE_STATION)
23 | BIT(NL80211_IFTYPE_ADHOC)
24 | BIT(NL80211_IFTYPE_AP)
25 #ifdef CONFIG_MAC80211_MESH
26 | BIT(NL80211_IFTYPE_MESH_POINT)
27 #endif
28 };
29
30 static const struct ieee80211_iface_combination if_comb_global = {
31 .limits = &if_limits_global,
32 .n_limits = 1,
33 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS,
34 .num_different_channels = MT7996_MAX_RADIOS,
35 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
36 BIT(NL80211_CHAN_WIDTH_20) |
37 BIT(NL80211_CHAN_WIDTH_40) |
38 BIT(NL80211_CHAN_WIDTH_80) |
39 BIT(NL80211_CHAN_WIDTH_160),
40 };
41
42 static const struct ieee80211_iface_limit if_limits[] = {
43 {
44 .max = 16,
45 .types = BIT(NL80211_IFTYPE_AP)
46 #ifdef CONFIG_MAC80211_MESH
47 | BIT(NL80211_IFTYPE_MESH_POINT)
48 #endif
49 }, {
50 .max = MT7996_MAX_INTERFACES,
51 .types = BIT(NL80211_IFTYPE_STATION)
52 }
53 };
54
55 static const struct ieee80211_iface_combination if_comb = {
56 .limits = if_limits,
57 .n_limits = ARRAY_SIZE(if_limits),
58 .max_interfaces = MT7996_MAX_INTERFACES,
59 .num_different_channels = 1,
60 .beacon_int_infra_match = true,
61 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
62 BIT(NL80211_CHAN_WIDTH_20) |
63 BIT(NL80211_CHAN_WIDTH_40) |
64 BIT(NL80211_CHAN_WIDTH_80) |
65 BIT(NL80211_CHAN_WIDTH_160),
66 .beacon_int_min_gcd = 100,
67 };
68
69 static const u8 if_types_ext_capa_ap[] = {
70 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
71 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
72 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
73 };
74
75 static const struct wiphy_iftype_ext_capab iftypes_ext_capa[] = {
76 {
77 .iftype = NL80211_IFTYPE_AP,
78 .extended_capabilities = if_types_ext_capa_ap,
79 .extended_capabilities_mask = if_types_ext_capa_ap,
80 .extended_capabilities_len = sizeof(if_types_ext_capa_ap),
81 .eml_capabilities = IEEE80211_EML_CAP_EMLSR_SUPP,
82 .mld_capa_and_ops =
83 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS,
84 MT7996_MAX_RADIOS - 1),
85 }, {
86 .iftype = NL80211_IFTYPE_STATION,
87 .extended_capabilities = if_types_ext_capa_ap,
88 .extended_capabilities_mask = if_types_ext_capa_ap,
89 .extended_capabilities_len = sizeof(if_types_ext_capa_ap),
90 .mld_capa_and_ops =
91 FIELD_PREP_CONST(IEEE80211_MLD_CAP_OP_MAX_SIMUL_LINKS,
92 MT7996_MAX_RADIOS - 1),
93 },
94 };
95
96 #if defined(CONFIG_HWMON)
mt7996_thermal_temp_show(struct device * dev,struct device_attribute * attr,char * buf)97 static ssize_t mt7996_thermal_temp_show(struct device *dev,
98 struct device_attribute *attr,
99 char *buf)
100 {
101 struct mt7996_phy *phy = dev_get_drvdata(dev);
102 int i = to_sensor_dev_attr(attr)->index;
103 int temperature;
104
105 switch (i) {
106 case 0:
107 temperature = mt7996_mcu_get_temperature(phy);
108 if (temperature < 0)
109 return temperature;
110 /* display in millidegree celcius */
111 return sprintf(buf, "%u\n", temperature * 1000);
112 case 1:
113 case 2:
114 return sprintf(buf, "%u\n",
115 phy->throttle_temp[i - 1] * 1000);
116 case 3:
117 return sprintf(buf, "%hhu\n", phy->throttle_state);
118 default:
119 return -EINVAL;
120 }
121 }
122
mt7996_thermal_temp_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)123 static ssize_t mt7996_thermal_temp_store(struct device *dev,
124 struct device_attribute *attr,
125 const char *buf, size_t count)
126 {
127 struct mt7996_phy *phy = dev_get_drvdata(dev);
128 int ret, i = to_sensor_dev_attr(attr)->index;
129 long val;
130
131 ret = kstrtol(buf, 10, &val);
132 if (ret < 0)
133 return ret;
134
135 mutex_lock(&phy->dev->mt76.mutex);
136 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000);
137
138 /* add a safety margin ~10 */
139 if ((i - 1 == MT7996_CRIT_TEMP_IDX &&
140 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) ||
141 (i - 1 == MT7996_MAX_TEMP_IDX &&
142 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) {
143 dev_err(phy->dev->mt76.dev,
144 "temp1_max shall be 10 degrees higher than temp1_crit.");
145 mutex_unlock(&phy->dev->mt76.mutex);
146 return -EINVAL;
147 }
148
149 phy->throttle_temp[i - 1] = val;
150 mutex_unlock(&phy->dev->mt76.mutex);
151
152 ret = mt7996_mcu_set_thermal_protect(phy, true);
153 if (ret)
154 return ret;
155
156 return count;
157 }
158
159 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0);
160 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1);
161 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2);
162 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3);
163
164 static struct attribute *mt7996_hwmon_attrs[] = {
165 &sensor_dev_attr_temp1_input.dev_attr.attr,
166 &sensor_dev_attr_temp1_crit.dev_attr.attr,
167 &sensor_dev_attr_temp1_max.dev_attr.attr,
168 &sensor_dev_attr_throttle1.dev_attr.attr,
169 NULL,
170 };
171 ATTRIBUTE_GROUPS(mt7996_hwmon);
172
173 static int
mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)174 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev,
175 unsigned long *state)
176 {
177 *state = MT7996_CDEV_THROTTLE_MAX;
178
179 return 0;
180 }
181
182 static int
mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long * state)183 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev,
184 unsigned long *state)
185 {
186 struct mt7996_phy *phy = cdev->devdata;
187
188 *state = phy->cdev_state;
189
190 return 0;
191 }
192
193 static int
mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device * cdev,unsigned long state)194 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev,
195 unsigned long state)
196 {
197 struct mt7996_phy *phy = cdev->devdata;
198 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state;
199 int ret;
200
201 if (state > MT7996_CDEV_THROTTLE_MAX) {
202 dev_err(phy->dev->mt76.dev,
203 "please specify a valid throttling state\n");
204 return -EINVAL;
205 }
206
207 if (state == phy->cdev_state)
208 return 0;
209
210 /* cooling_device convention: 0 = no cooling, more = more cooling
211 * mcu convention: 1 = max cooling, more = less cooling
212 */
213 ret = mt7996_mcu_set_thermal_throttling(phy, throttling);
214 if (ret)
215 return ret;
216
217 phy->cdev_state = state;
218
219 return 0;
220 }
221
222 static const struct thermal_cooling_device_ops mt7996_thermal_ops = {
223 .get_max_state = mt7996_thermal_get_max_throttle_state,
224 .get_cur_state = mt7996_thermal_get_cur_throttle_state,
225 .set_cur_state = mt7996_thermal_set_cur_throttle_state,
226 };
227
mt7996_unregister_thermal(struct mt7996_phy * phy)228 static void mt7996_unregister_thermal(struct mt7996_phy *phy)
229 {
230 struct wiphy *wiphy = phy->mt76->hw->wiphy;
231 char name[sizeof("cooling_deviceXXX")];
232
233 if (!phy->cdev)
234 return;
235
236 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx);
237 sysfs_remove_link(&wiphy->dev.kobj, name);
238 thermal_cooling_device_unregister(phy->cdev);
239 }
240
mt7996_thermal_init(struct mt7996_phy * phy)241 static int mt7996_thermal_init(struct mt7996_phy *phy)
242 {
243 struct wiphy *wiphy = phy->mt76->hw->wiphy;
244 char cname[sizeof("cooling_deviceXXX")];
245 struct thermal_cooling_device *cdev;
246 struct device *hwmon;
247 const char *name;
248
249 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d",
250 wiphy_name(wiphy), phy->mt76->band_idx);
251 if (!name)
252 return -ENOMEM;
253
254 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx);
255
256 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops);
257 if (!IS_ERR(cdev)) {
258 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj,
259 cname) < 0)
260 thermal_cooling_device_unregister(cdev);
261 else
262 phy->cdev = cdev;
263 }
264
265 /* initialize critical/maximum high temperature */
266 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP;
267 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP;
268
269 if (!IS_REACHABLE(CONFIG_HWMON))
270 return 0;
271
272 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy,
273 mt7996_hwmon_groups);
274
275 if (IS_ERR(hwmon))
276 return PTR_ERR(hwmon);
277
278 return 0;
279 }
280 #endif
281
mt7996_led_set_config(struct led_classdev * led_cdev,u8 delay_on,u8 delay_off)282 static void mt7996_led_set_config(struct led_classdev *led_cdev,
283 u8 delay_on, u8 delay_off)
284 {
285 struct mt7996_dev *dev;
286 struct mt76_phy *mphy;
287 u32 val;
288
289 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev);
290 dev = container_of(mphy->dev, struct mt7996_dev, mt76);
291
292 /* select TX blink mode, 2: only data frames */
293 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2);
294
295 /* enable LED */
296 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1);
297
298 /* set LED Tx blink on/off time */
299 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) |
300 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off);
301 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val);
302
303 /* turn LED off */
304 if (delay_off == 0xff && delay_on == 0x0) {
305 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK;
306 } else {
307 /* control LED */
308 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK;
309 if (mphy->band_idx == MT_BAND1)
310 val |= MT_LED_CTRL_BLINK_BAND_SEL;
311 }
312
313 if (mphy->leds.al)
314 val |= MT_LED_CTRL_POLARITY;
315
316 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val);
317 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK);
318 }
319
mt7996_led_set_blink(struct led_classdev * led_cdev,unsigned long * delay_on,unsigned long * delay_off)320 static int mt7996_led_set_blink(struct led_classdev *led_cdev,
321 unsigned long *delay_on,
322 unsigned long *delay_off)
323 {
324 u16 delta_on = 0, delta_off = 0;
325
326 #define HW_TICK 10
327 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK)
328
329 if (*delay_on)
330 delta_on = TO_HW_TICK(*delay_on);
331 if (*delay_off)
332 delta_off = TO_HW_TICK(*delay_off);
333
334 mt7996_led_set_config(led_cdev, delta_on, delta_off);
335
336 return 0;
337 }
338
mt7996_led_set_brightness(struct led_classdev * led_cdev,enum led_brightness brightness)339 static void mt7996_led_set_brightness(struct led_classdev *led_cdev,
340 enum led_brightness brightness)
341 {
342 if (!brightness)
343 mt7996_led_set_config(led_cdev, 0, 0xff);
344 else
345 mt7996_led_set_config(led_cdev, 0xff, 0);
346 }
347
__mt7996_init_txpower(struct mt7996_phy * phy,struct ieee80211_supported_band * sband)348 static void __mt7996_init_txpower(struct mt7996_phy *phy,
349 struct ieee80211_supported_band *sband)
350 {
351 struct mt7996_dev *dev = phy->dev;
352 int i, n_chains = hweight16(phy->mt76->chainmask);
353 int path_delta = mt76_tx_power_path_delta(n_chains);
354 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band);
355 struct mt76_power_limits limits;
356
357 for (i = 0; i < sband->n_channels; i++) {
358 struct ieee80211_channel *chan = &sband->channels[i];
359 int target_power = mt7996_eeprom_get_target_power(dev, chan);
360
361 target_power += pwr_delta;
362 target_power = mt76_get_rate_power_limits(phy->mt76, chan,
363 &limits,
364 target_power);
365 target_power += path_delta;
366 target_power = DIV_ROUND_UP(target_power, 2);
367 chan->max_power = min_t(int, chan->max_reg_power,
368 target_power);
369 chan->orig_mpwr = target_power;
370 }
371 }
372
mt7996_init_txpower(struct mt7996_phy * phy)373 void mt7996_init_txpower(struct mt7996_phy *phy)
374 {
375 if (!phy)
376 return;
377
378 if (phy->mt76->cap.has_2ghz)
379 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband);
380 if (phy->mt76->cap.has_5ghz)
381 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband);
382 if (phy->mt76->cap.has_6ghz)
383 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband);
384 }
385
386 static void
mt7996_regd_notifier(struct wiphy * wiphy,struct regulatory_request * request)387 mt7996_regd_notifier(struct wiphy *wiphy,
388 struct regulatory_request *request)
389 {
390 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
391 struct mt7996_dev *dev = mt7996_hw_dev(hw);
392 struct mt7996_phy *phy;
393
394 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2));
395 dev->mt76.region = request->dfs_region;
396
397 mt7996_for_each_phy(dev, phy) {
398 if (dev->mt76.region == NL80211_DFS_UNSET)
399 mt7996_mcu_rdd_background_enable(phy, NULL);
400
401 mt7996_init_txpower(phy);
402 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN;
403 mt7996_dfs_init_radar_detector(phy);
404 }
405 }
406
407 static void
mt7996_init_wiphy_band(struct ieee80211_hw * hw,struct mt7996_phy * phy)408 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy)
409 {
410 struct mt7996_dev *dev = phy->dev;
411 struct wiphy *wiphy = hw->wiphy;
412 int n_radios = hw->wiphy->n_radio;
413 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios];
414 struct wiphy_radio *radio = &dev->radios[n_radios];
415
416 phy->slottime = 9;
417 phy->beacon_rate = -1;
418 phy->rxfilter = MT_WF_RFCR_DROP_OTHER_UC;
419
420 if (phy->mt76->cap.has_2ghz) {
421 phy->mt76->sband_2g.sband.ht_cap.cap |=
422 IEEE80211_HT_CAP_LDPC_CODING |
423 IEEE80211_HT_CAP_MAX_AMSDU;
424 phy->mt76->sband_2g.sband.ht_cap.ampdu_density =
425 IEEE80211_HT_MPDU_DENSITY_2;
426 freq->start_freq = 2400000;
427 freq->end_freq = 2500000;
428 } else if (phy->mt76->cap.has_5ghz) {
429 phy->mt76->sband_5g.sband.ht_cap.cap |=
430 IEEE80211_HT_CAP_LDPC_CODING |
431 IEEE80211_HT_CAP_MAX_AMSDU;
432
433 phy->mt76->sband_5g.sband.vht_cap.cap |=
434 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 |
435 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
436 IEEE80211_VHT_CAP_SHORT_GI_160 |
437 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
438 phy->mt76->sband_5g.sband.ht_cap.ampdu_density =
439 IEEE80211_HT_MPDU_DENSITY_1;
440
441 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
442 freq->start_freq = 5000000;
443 freq->end_freq = 5900000;
444 } else if (phy->mt76->cap.has_6ghz) {
445 freq->start_freq = 5900000;
446 freq->end_freq = 7200000;
447 } else {
448 return;
449 }
450
451 dev->radio_phy[n_radios] = phy;
452 radio->freq_range = freq;
453 radio->n_freq_range = 1;
454 radio->iface_combinations = &if_comb;
455 radio->n_iface_combinations = 1;
456 hw->wiphy->n_radio++;
457
458 wiphy->available_antennas_rx |= phy->mt76->chainmask;
459 wiphy->available_antennas_tx |= phy->mt76->chainmask;
460
461 mt76_set_stream_caps(phy->mt76, true);
462 mt7996_set_stream_vht_txbf_caps(phy);
463 mt7996_set_stream_he_eht_caps(phy);
464 mt7996_init_txpower(phy);
465 }
466
467 static void
mt7996_init_wiphy(struct ieee80211_hw * hw,struct mtk_wed_device * wed)468 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed)
469 {
470 struct mt7996_dev *dev = mt7996_hw_dev(hw);
471 struct mt76_dev *mdev = &dev->mt76;
472 struct wiphy *wiphy = hw->wiphy;
473 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT :
474 IEEE80211_MAX_AMPDU_BUF_HE;
475
476 hw->queues = 4;
477 hw->max_rx_aggregation_subframes = max_subframes;
478 hw->max_tx_aggregation_subframes = max_subframes;
479 if (is_mt7990(mdev) && dev->has_eht)
480 hw->max_tx_aggregation_subframes = 512;
481
482 hw->netdev_features = NETIF_F_RXCSUM;
483 if (mtk_wed_device_active(wed) || mt76_npu_device_active(mdev))
484 hw->netdev_features |= NETIF_F_HW_TC;
485
486 hw->radiotap_timestamp.units_pos =
487 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US;
488
489 hw->sta_data_size = sizeof(struct mt7996_sta);
490 hw->vif_data_size = sizeof(struct mt7996_vif);
491 hw->chanctx_data_size = sizeof(struct mt76_chanctx);
492
493 wiphy->iface_combinations = &if_comb_global;
494 wiphy->n_iface_combinations = 1;
495
496 wiphy->radio = dev->radios;
497
498 wiphy->reg_notifier = mt7996_regd_notifier;
499 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH |
500 WIPHY_FLAG_SUPPORTS_MLO;
501 wiphy->mbssid_max_interfaces = 16;
502 wiphy->iftype_ext_capab = iftypes_ext_capa;
503 wiphy->num_iftype_ext_capab = ARRAY_SIZE(iftypes_ext_capa);
504
505 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR);
506 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
507 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY);
508 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT);
509 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT);
510 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE);
511 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP);
512 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY);
513 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT);
514 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
515 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER);
516
517 if (mt7996_eeprom_has_background_radar(dev) &&
518 #if defined(CONFIG_OF)
519 (!mdev->dev->of_node ||
520 !of_property_read_bool(mdev->dev->of_node,
521 "mediatek,disable-radar-background")))
522 #else
523 1)
524 #endif
525 wiphy_ext_feature_set(wiphy,
526 NL80211_EXT_FEATURE_RADAR_BACKGROUND);
527
528 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
529 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD);
530 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD);
531 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR);
532 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
533
534 hw->max_tx_fragments = 4;
535
536 /* init led callbacks */
537 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
538 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness;
539 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink;
540 }
541
542 wiphy->max_scan_ssids = 4;
543 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
544
545 mt7996_init_wiphy_band(hw, &dev->phy);
546 }
547
548 static void
mt7996_mac_init_band(struct mt7996_dev * dev,u8 band)549 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band)
550 {
551 u32 mask, set;
552
553 /* clear estimated value of EIFS for Rx duration & OBSS time */
554 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR);
555
556 /* clear backoff time for Rx duration */
557 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band),
558 MT_WF_RMAC_MIB_NONQOSD_BACKOFF);
559 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band),
560 MT_WF_RMAC_MIB_QOS01_BACKOFF);
561 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band),
562 MT_WF_RMAC_MIB_QOS23_BACKOFF);
563
564 /* clear backoff time for Tx duration */
565 mt76_clear(dev, MT_WTBLOFF_ACR(band),
566 MT_WTBLOFF_ADM_BACKOFFTIME);
567
568 /* clear backoff time and set software compensation for OBSS time */
569 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET;
570 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) |
571 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4);
572 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set);
573
574 /* filter out non-resp frames and get instanstaeous signal reporting */
575 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM;
576 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) |
577 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3);
578 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set);
579
580 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than
581 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set.
582 */
583 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H);
584 }
585
mt7996_mac_init_basic_rates(struct mt7996_dev * dev)586 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev)
587 {
588 int i;
589
590 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) {
591 u16 rate = mt76_rates[i].hw_value;
592 /* odd index for driver, even index for firmware */
593 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i;
594
595 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) |
596 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0));
597 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false);
598 }
599 }
600
mt7996_mac_init(struct mt7996_dev * dev)601 void mt7996_mac_init(struct mt7996_dev *dev)
602 {
603 #define HIF_TXD_V2_1 0x21
604 int i;
605
606 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT);
607
608 for (i = 0; i < mt7996_wtbl_size(dev); i++)
609 mt7996_mac_wtbl_update(dev, i,
610 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
611
612 if (IS_ENABLED(CONFIG_MT76_LEDS)) {
613 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2;
614 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4);
615 }
616
617 /* rro module init */
618 if (dev->hif2)
619 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE,
620 is_mt7996(&dev->mt76) ? 2 : 7);
621 else
622 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 0);
623
624 if (mt7996_has_hwrro(dev)) {
625 u16 timeout;
626
627 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128;
628 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout);
629 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE,
630 is_mt7996(&dev->mt76) ? 1 : 2);
631 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH,
632 !is_mt7996(&dev->mt76));
633 } else {
634 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3);
635 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1);
636 }
637
638 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
639 MCU_WA_PARAM_HW_PATH_HIF_VER,
640 HIF_TXD_V2_1, 0);
641
642 for (i = MT_BAND0; i <= MT_BAND2; i++)
643 mt7996_mac_init_band(dev, i);
644
645 mt7996_mac_init_basic_rates(dev);
646 }
647
mt7996_txbf_init(struct mt7996_dev * dev)648 int mt7996_txbf_init(struct mt7996_dev *dev)
649 {
650 int ret;
651
652 if (mt7996_band_valid(dev, MT_BAND1) ||
653 mt7996_band_valid(dev, MT_BAND2)) {
654 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL);
655 if (ret)
656 return ret;
657 }
658
659 /* trigger sounding packets */
660 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON);
661 if (ret)
662 return ret;
663
664 /* enable eBF */
665 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE);
666 }
667
mt7996_register_phy(struct mt7996_dev * dev,enum mt76_band_id band)668 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band)
669 {
670 struct mt7996_phy *phy;
671 struct mt76_phy *mphy;
672 u32 mac_ofs, hif1_ofs = 0;
673 int ret;
674 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
675
676 if (!mt7996_band_valid(dev, band))
677 return 0;
678
679 if (dev->hif2 &&
680 ((is_mt7996(&dev->mt76) && band == MT_BAND2) ||
681 (is_mt7992(&dev->mt76) && band == MT_BAND1))) {
682 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);
683 wed = &dev->mt76.mmio.wed_hif2;
684 }
685
686 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band);
687 if (!mphy)
688 return -ENOMEM;
689
690 phy = mphy->priv;
691 phy->dev = dev;
692 phy->mt76 = mphy;
693 mphy->dev->phys[band] = mphy;
694
695 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work);
696
697 ret = mt7996_eeprom_parse_hw_cap(dev, phy);
698 if (ret)
699 goto error;
700
701 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2;
702 #if defined(__linux__)
703 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
704 #elif defined(__FreeBSD__)
705 memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + mac_ofs, ETH_ALEN);
706 #endif
707 /* Make the extra PHY MAC address local without overlapping with
708 * the usual MAC address allocation scheme on multiple virtual interfaces
709 */
710 if (!is_valid_ether_addr(mphy->macaddr)) {
711 #if defined(__linux__)
712 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
713 #elif defined(__FreeBSD__)
714 memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR,
715 #endif
716 ETH_ALEN);
717 mphy->macaddr[0] |= 2;
718 mphy->macaddr[0] ^= BIT(7);
719 if (band == MT_BAND2)
720 mphy->macaddr[0] ^= BIT(6);
721 }
722 ret = mt76_eeprom_override(mphy);
723 if (ret)
724 goto error;
725
726 /* init wiphy according to mphy and phy */
727 mt7996_init_wiphy_band(mphy->hw, phy);
728
729 if (is_mt7996(&dev->mt76) && !dev->hif2 && band == MT_BAND1) {
730 int i;
731
732 for (i = 0; i <= MT_TXQ_PSD; i++)
733 mphy->q_tx[i] = dev->mt76.phys[MT_BAND0]->q_tx[0];
734 } else {
735 ret = mt7996_init_tx_queues(mphy->priv, MT_TXQ_ID(band),
736 MT7996_TX_RING_SIZE,
737 MT_TXQ_RING_BASE(band) + hif1_ofs,
738 wed);
739 if (ret)
740 goto error;
741 }
742
743 ret = mt76_register_phy(mphy, true, mt76_rates,
744 ARRAY_SIZE(mt76_rates));
745 if (ret)
746 goto error;
747
748 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) {
749 mt76_wr(dev, MT_INT_PCIE1_MASK_CSR, MT_INT_TX_RX_DONE_EXT);
750 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2,
751 MT_INT_TX_RX_DONE_EXT);
752 }
753
754 return 0;
755
756 error:
757 mphy->dev->phys[band] = NULL;
758 return ret;
759 }
760
761 static void
mt7996_unregister_phy(struct mt7996_phy * phy)762 mt7996_unregister_phy(struct mt7996_phy *phy)
763 {
764 #if defined(CONFIG_HWMON)
765 if (phy)
766 mt7996_unregister_thermal(phy);
767 #endif
768 }
769
mt7996_init_work(struct work_struct * work)770 static void mt7996_init_work(struct work_struct *work)
771 {
772 struct mt7996_dev *dev = container_of(work, struct mt7996_dev,
773 init_work);
774
775 mt7996_mcu_set_eeprom(dev);
776 mt7996_mac_init(dev);
777 mt7996_txbf_init(dev);
778 }
779
mt7996_wfsys_reset(struct mt7996_dev * dev)780 void mt7996_wfsys_reset(struct mt7996_dev *dev)
781 {
782 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1);
783 msleep(20);
784
785 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1);
786 msleep(20);
787 }
788
mt7996_rro_hw_init_v3(struct mt7996_dev * dev)789 static void mt7996_rro_hw_init_v3(struct mt7996_dev *dev)
790 {
791 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
792 u32 session_id;
793
794 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1)
795 return;
796
797 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
798 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
799 wed->wlan.ind_cmd.win_size =
800 ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6;
801 if (is_mt7996(&dev->mt76))
802 wed->wlan.ind_cmd.particular_sid =
803 MT7996_RRO_MAX_SESSION;
804 else
805 wed->wlan.ind_cmd.particular_sid = 1;
806 wed->wlan.ind_cmd.particular_se_phys =
807 dev->wed_rro.session.phy_addr;
808 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN;
809 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL;
810 }
811 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
812
813 if (mtk_wed_device_active(wed) && mtk_wed_get_rx_capa(wed)) {
814 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00);
815 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1,
816 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN);
817 } else {
818 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0);
819 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 0);
820 }
821
822 /* particular session configure */
823 /* use max session idx + 1 as particular session id */
824 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr);
825
826 session_id = is_mt7996(&dev->mt76) ? MT7996_RRO_MAX_SESSION : 1;
827 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1,
828 MT_RRO_PARTICULAR_CONFG_EN |
829 FIELD_PREP(MT_RRO_PARTICULAR_SID, session_id));
830 }
831
mt7996_rro_hw_init(struct mt7996_dev * dev)832 void mt7996_rro_hw_init(struct mt7996_dev *dev)
833 {
834 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0;
835 int i;
836
837 if (!mt7996_has_hwrro(dev))
838 return;
839
840 INIT_LIST_HEAD(&dev->wed_rro.page_cache);
841 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.page_map); i++)
842 INIT_LIST_HEAD(&dev->wed_rro.page_map[i]);
843
844 if (!is_mt7996(&dev->mt76)) {
845 reg = MT_RRO_MSDU_PG_SEG_ADDR0;
846
847 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) {
848 mt76_clear(dev, MT_RRO_3_0_EMU_CONF,
849 MT_RRO_3_0_EMU_CONF_EN_MASK);
850 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG,
851 MT_RRO_3_1_GLOBAL_CONFIG_RXDMAD_SEL);
852 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) &&
853 !mt76_npu_device_active(&dev->mt76)) {
854 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG,
855 MT_RRO_3_1_GLOBAL_CONFIG_RX_DIDX_WR_EN |
856 MT_RRO_3_1_GLOBAL_CONFIG_RX_CIDX_RD_EN);
857 mt76_wr(dev, MT_RRO_RX_RING_AP_CIDX_ADDR,
858 dev->wed_rro.emi_rings_cpu.phy_addr >> 4);
859 mt76_wr(dev, MT_RRO_RX_RING_AP_DIDX_ADDR,
860 dev->wed_rro.emi_rings_dma.phy_addr >> 4);
861 }
862 } else {
863 /* set emul 3.0 function */
864 mt76_wr(dev, MT_RRO_3_0_EMU_CONF,
865 MT_RRO_3_0_EMU_CONF_EN_MASK);
866
867 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE0,
868 dev->wed_rro.addr_elem[0].phy_addr);
869 }
870
871 mt76_set(dev, MT_RRO_3_1_GLOBAL_CONFIG,
872 MT_RRO_3_1_GLOBAL_CONFIG_INTERLEAVE_EN);
873
874 /* setup Msdu page address */
875 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) {
876 mt76_wr(dev, reg,
877 dev->wed_rro.msdu_pg[i].phy_addr >> 4);
878 reg += 4;
879 }
880 } else {
881 /* TODO: remove line after WM has set */
882 mt76_clear(dev, WF_RRO_AXI_MST_CFG,
883 WF_RRO_AXI_MST_CFG_DIDX_OK);
884
885 /* setup BA bitmap cache address */
886 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0,
887 dev->wed_rro.ba_bitmap[0].phy_addr);
888 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0);
889 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0,
890 dev->wed_rro.ba_bitmap[1].phy_addr);
891 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0);
892
893 /* Setup Address element address */
894 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
895 mt76_wr(dev, reg,
896 dev->wed_rro.addr_elem[i].phy_addr >> 4);
897 reg += 4;
898 }
899
900 /* Setup Address element address - separate address segment
901 * mode.
902 */
903 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1,
904 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE);
905 }
906
907 mt7996_rro_hw_init_v3(dev);
908
909 /* interrupt enable */
910 mt76_wr(dev, MT_RRO_HOST_INT_ENA,
911 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA);
912 }
913
mt7996_wed_rro_init(struct mt7996_dev * dev)914 static int mt7996_wed_rro_init(struct mt7996_dev *dev)
915 {
916 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff);
917 struct mt7996_wed_rro_addr *addr;
918 void *ptr;
919 int i;
920
921 if (!mt7996_has_hwrro(dev))
922 return 0;
923
924 if (dev->mt76.hwrro_mode == MT76_HWRRO_V3) {
925 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
926 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
927 MT7996_RRO_BA_BITMAP_CR_SIZE,
928 &dev->wed_rro.ba_bitmap[i].phy_addr,
929 GFP_KERNEL);
930 if (!ptr)
931 return -ENOMEM;
932
933 dev->wed_rro.ba_bitmap[i].ptr = ptr;
934 }
935 }
936
937 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
938 int j;
939
940 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
941 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr),
942 &dev->wed_rro.addr_elem[i].phy_addr,
943 GFP_KERNEL);
944 if (!ptr)
945 return -ENOMEM;
946
947 dev->wed_rro.addr_elem[i].ptr = ptr;
948 memset(dev->wed_rro.addr_elem[i].ptr, 0,
949 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr));
950
951 addr = dev->wed_rro.addr_elem[i].ptr;
952 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) {
953 addr->data = cpu_to_le32(val);
954 addr++;
955 }
956
957 #ifdef CONFIG_NET_MEDIATEK_SOC_WED
958 if (mtk_wed_device_active(&dev->mt76.mmio.wed) &&
959 mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) {
960 struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
961
962 wed->wlan.ind_cmd.addr_elem_phys[i] =
963 dev->wed_rro.addr_elem[i].phy_addr;
964 }
965 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */
966 }
967
968 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) {
969 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
970 MT7996_RRO_MSDU_PG_SIZE_PER_CR,
971 &dev->wed_rro.msdu_pg[i].phy_addr,
972 GFP_KERNEL);
973 if (!ptr)
974 return -ENOMEM;
975
976 dev->wed_rro.msdu_pg[i].ptr = ptr;
977
978 memset(dev->wed_rro.msdu_pg[i].ptr, 0,
979 MT7996_RRO_MSDU_PG_SIZE_PER_CR);
980 }
981
982 if (!mtk_wed_device_active(&dev->mt76.mmio.wed) &&
983 dev->mt76.hwrro_mode == MT76_HWRRO_V3_1) {
984 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
985 sizeof(*dev->wed_rro.emi_rings_cpu.ptr),
986 &dev->wed_rro.emi_rings_cpu.phy_addr,
987 GFP_KERNEL);
988 if (!ptr)
989 return -ENOMEM;
990
991 dev->wed_rro.emi_rings_cpu.ptr = ptr;
992
993 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
994 sizeof(*dev->wed_rro.emi_rings_dma.ptr),
995 &dev->wed_rro.emi_rings_dma.phy_addr,
996 GFP_KERNEL);
997 if (!ptr)
998 return -ENOMEM;
999
1000 dev->wed_rro.emi_rings_dma.ptr = ptr;
1001 }
1002
1003 ptr = dmam_alloc_coherent(dev->mt76.dma_dev,
1004 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr),
1005 &dev->wed_rro.session.phy_addr,
1006 GFP_KERNEL);
1007 if (!ptr)
1008 return -ENOMEM;
1009
1010 dev->wed_rro.session.ptr = ptr;
1011 addr = dev->wed_rro.session.ptr;
1012 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
1013 addr->data = cpu_to_le32(val);
1014 addr++;
1015 }
1016
1017 mt7996_rro_hw_init(dev);
1018
1019 return mt7996_dma_rro_init(dev);
1020 }
1021
mt7996_wed_rro_free(struct mt7996_dev * dev)1022 static void mt7996_wed_rro_free(struct mt7996_dev *dev)
1023 {
1024 int i;
1025
1026 if (!mt7996_has_hwrro(dev))
1027 return;
1028
1029 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) {
1030 if (!dev->wed_rro.ba_bitmap[i].ptr)
1031 continue;
1032
1033 dmam_free_coherent(dev->mt76.dma_dev,
1034 MT7996_RRO_BA_BITMAP_CR_SIZE,
1035 dev->wed_rro.ba_bitmap[i].ptr,
1036 dev->wed_rro.ba_bitmap[i].phy_addr);
1037 }
1038
1039 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) {
1040 if (!dev->wed_rro.addr_elem[i].ptr)
1041 continue;
1042
1043 dmam_free_coherent(dev->mt76.dma_dev,
1044 MT7996_RRO_WINDOW_MAX_SIZE *
1045 sizeof(struct mt7996_wed_rro_addr),
1046 dev->wed_rro.addr_elem[i].ptr,
1047 dev->wed_rro.addr_elem[i].phy_addr);
1048 }
1049
1050 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.msdu_pg); i++) {
1051 if (!dev->wed_rro.msdu_pg[i].ptr)
1052 continue;
1053
1054 dmam_free_coherent(dev->mt76.dma_dev,
1055 MT7996_RRO_MSDU_PG_SIZE_PER_CR,
1056 dev->wed_rro.msdu_pg[i].ptr,
1057 dev->wed_rro.msdu_pg[i].phy_addr);
1058 }
1059
1060 if (dev->wed_rro.emi_rings_cpu.ptr)
1061 dmam_free_coherent(dev->mt76.dma_dev,
1062 sizeof(*dev->wed_rro.emi_rings_cpu.ptr),
1063 dev->wed_rro.emi_rings_cpu.ptr,
1064 dev->wed_rro.emi_rings_cpu.phy_addr);
1065
1066 if (dev->wed_rro.emi_rings_dma.ptr)
1067 dmam_free_coherent(dev->mt76.dma_dev,
1068 sizeof(*dev->wed_rro.emi_rings_dma.ptr),
1069 dev->wed_rro.emi_rings_dma.ptr,
1070 dev->wed_rro.emi_rings_dma.phy_addr);
1071
1072 if (!dev->wed_rro.session.ptr)
1073 return;
1074
1075 dmam_free_coherent(dev->mt76.dma_dev,
1076 MT7996_RRO_WINDOW_MAX_LEN *
1077 sizeof(struct mt7996_wed_rro_addr),
1078 dev->wed_rro.session.ptr,
1079 dev->wed_rro.session.phy_addr);
1080 }
1081
mt7996_wed_rro_work(struct work_struct * work)1082 static void mt7996_wed_rro_work(struct work_struct *work)
1083 {
1084 u32 val = FIELD_PREP(WED_RRO_ADDR_SIGNATURE_MASK, 0xff);
1085 struct mt7996_dev *dev;
1086 LIST_HEAD(list);
1087
1088 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev,
1089 wed_rro.work);
1090
1091 spin_lock_bh(&dev->wed_rro.lock);
1092 list_splice_init(&dev->wed_rro.poll_list, &list);
1093 spin_unlock_bh(&dev->wed_rro.lock);
1094
1095 while (!list_empty(&list)) {
1096 struct mt7996_wed_rro_session_id *e;
1097 int i;
1098
1099 e = list_first_entry(&list, struct mt7996_wed_rro_session_id,
1100 list);
1101 list_del_init(&e->list);
1102
1103 if (mt76_npu_device_active(&dev->mt76))
1104 goto reset_session;
1105
1106 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) {
1107 #if defined(__linux__)
1108 void *ptr = dev->wed_rro.session.ptr;
1109 #elif defined(__FreeBSD__)
1110 u8 *ptr = dev->wed_rro.session.ptr;
1111 #endif
1112 struct mt7996_wed_rro_addr *elem;
1113 u32 idx, elem_id = i;
1114
1115 if (e->id == MT7996_RRO_MAX_SESSION)
1116 goto reset;
1117
1118 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE;
1119 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem))
1120 goto out;
1121
1122 ptr = dev->wed_rro.addr_elem[idx].ptr;
1123 elem_id +=
1124 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) *
1125 MT7996_RRO_WINDOW_MAX_LEN;
1126 reset:
1127 #if defined(__linux__)
1128 elem = ptr + elem_id * sizeof(*elem);
1129 #elif defined(__FreeBSD__)
1130 elem = (void *)(ptr + elem_id * sizeof(*elem));
1131 #endif
1132 elem->data |= cpu_to_le32(val);
1133 }
1134 reset_session:
1135 mt7996_mcu_wed_rro_reset_sessions(dev, e->id);
1136 out:
1137 kfree(e);
1138 }
1139 }
1140
mt7996_variant_type_init(struct mt7996_dev * dev)1141 static int mt7996_variant_type_init(struct mt7996_dev *dev)
1142 {
1143 u32 val = mt76_rr(dev, MT_PAD_GPIO);
1144 u8 var_type;
1145
1146 switch (mt76_chip(&dev->mt76)) {
1147 case MT7996_DEVICE_ID:
1148 if (val & MT_PAD_GPIO_2ADIE_TBTC)
1149 var_type = MT7996_VAR_TYPE_233;
1150 else
1151 var_type = MT7996_VAR_TYPE_444;
1152 break;
1153 case MT7992_DEVICE_ID:
1154 if (val & MT_PAD_GPIO_ADIE_SINGLE)
1155 var_type = MT7992_VAR_TYPE_23;
1156 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992))
1157 var_type = MT7992_VAR_TYPE_44;
1158 else
1159 return -EINVAL;
1160 break;
1161 case MT7990_DEVICE_ID:
1162 var_type = MT7990_VAR_TYPE_23;
1163 break;
1164 default:
1165 return -EINVAL;
1166 }
1167
1168 dev->var.type = var_type;
1169 return 0;
1170 }
1171
mt7996_variant_fem_init(struct mt7996_dev * dev)1172 static int mt7996_variant_fem_init(struct mt7996_dev *dev)
1173 {
1174 #define MT7976C_EFUSE_OFFSET 0x470
1175 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb;
1176 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO);
1177 u16 adie_id, adie_ver;
1178 bool is_7976c;
1179 int ret;
1180
1181 if (is_mt7992(&dev->mt76)) {
1182 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1;
1183 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992);
1184 } else {
1185 adie_idx = 0;
1186 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB);
1187 }
1188
1189 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false);
1190 if (ret)
1191 return ret;
1192
1193 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf));
1194 if (ret && ret != -EINVAL)
1195 return ret;
1196
1197 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK);
1198 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE;
1199 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 ||
1200 adie_ver == 0x8c10 || buf[idx] == 0xc;
1201
1202 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK);
1203 if (adie_id == 0x7975 || adie_id == 0x7979 ||
1204 (adie_id == 0x7976 && is_7976c))
1205 dev->var.fem = MT7996_FEM_INT;
1206 else if (adie_id == 0x7977 && adie_comb == 1)
1207 dev->var.fem = MT7996_FEM_MIX;
1208 else
1209 dev->var.fem = MT7996_FEM_EXT;
1210
1211 return 0;
1212 }
1213
mt7996_init_hardware(struct mt7996_dev * dev)1214 static int mt7996_init_hardware(struct mt7996_dev *dev)
1215 {
1216 int ret, idx;
1217
1218 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);
1219 if (is_mt7992(&dev->mt76)) {
1220 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1221 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0);
1222 }
1223
1224 INIT_WORK(&dev->init_work, mt7996_init_work);
1225 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work);
1226 INIT_LIST_HEAD(&dev->wed_rro.poll_list);
1227 spin_lock_init(&dev->wed_rro.lock);
1228
1229 ret = mt7996_variant_type_init(dev);
1230 if (ret)
1231 return ret;
1232
1233 ret = mt7996_dma_init(dev);
1234 if (ret)
1235 return ret;
1236
1237 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
1238
1239 ret = mt7996_mcu_init(dev);
1240 if (ret)
1241 return ret;
1242
1243 ret = mt7996_wed_rro_init(dev);
1244 if (ret)
1245 return ret;
1246
1247 ret = mt7996_variant_fem_init(dev);
1248 if (ret)
1249 return ret;
1250
1251 ret = mt7996_eeprom_init(dev);
1252 if (ret < 0)
1253 return ret;
1254
1255 /* Beacon and mgmt frames should occupy wcid 0 */
1256 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA);
1257 if (idx)
1258 return -ENOSPC;
1259
1260 dev->mt76.global_wcid.idx = idx;
1261 dev->mt76.global_wcid.hw_key_idx = -1;
1262 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET;
1263 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid);
1264
1265 return 0;
1266 }
1267
mt7996_set_stream_vht_txbf_caps(struct mt7996_phy * phy)1268 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy)
1269 {
1270 int sts;
1271 u32 *cap;
1272
1273 if (!phy->mt76->cap.has_5ghz)
1274 return;
1275
1276 sts = hweight16(phy->mt76->chainmask);
1277 cap = &phy->mt76->sband_5g.sband.vht_cap.cap;
1278
1279 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
1280 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
1281
1282 if (is_mt7992(phy->mt76->dev))
1283 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4);
1284 else
1285 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3);
1286
1287 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK |
1288 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1289 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE);
1290
1291 if (sts < 2)
1292 return;
1293
1294 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE |
1295 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE |
1296 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1);
1297 }
1298
1299 static void
mt7996_set_stream_he_txbf_caps(struct mt7996_phy * phy,struct ieee80211_sta_he_cap * he_cap,int vif,enum nl80211_band band)1300 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy,
1301 struct ieee80211_sta_he_cap *he_cap, int vif,
1302 enum nl80211_band band)
1303 {
1304 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem;
1305 int sts = hweight16(phy->mt76->chainmask);
1306 bool non_2g = band != NL80211_BAND_2GHZ;
1307 u8 c;
1308
1309 #ifdef CONFIG_MAC80211_MESH
1310 if (vif == NL80211_IFTYPE_MESH_POINT)
1311 return;
1312 #endif
1313
1314 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1315 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1316
1317 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK |
1318 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK;
1319 elem->phy_cap_info[5] &= ~c;
1320
1321 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1322 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1323 elem->phy_cap_info[6] &= ~c;
1324
1325 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK;
1326
1327 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
1328 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1329 elem->phy_cap_info[2] |= c;
1330
1331 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE;
1332
1333 if (is_mt7992(phy->mt76->dev))
1334 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 |
1335 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g);
1336 else
1337 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 |
1338 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g);
1339
1340 elem->phy_cap_info[4] |= c;
1341
1342 /* do not support NG16 due to spec D4.0 changes subcarrier idx */
1343 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
1344 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU;
1345
1346 if (vif == NL80211_IFTYPE_STATION)
1347 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO;
1348
1349 elem->phy_cap_info[6] |= c;
1350
1351 if (sts < 2)
1352 return;
1353
1354 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */
1355 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3;
1356
1357 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION))
1358 return;
1359
1360 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER;
1361
1362 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
1363 sts - 1) |
1364 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK,
1365 sts - 1) * non_2g);
1366
1367 elem->phy_cap_info[5] |= c;
1368
1369 if (vif != NL80211_IFTYPE_AP)
1370 return;
1371
1372 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER;
1373
1374 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
1375 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB;
1376 elem->phy_cap_info[6] |= c;
1377
1378 c = 0;
1379 if (non_2g)
1380 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ |
1381 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1382 elem->phy_cap_info[7] |= c;
1383 }
1384
1385 static void
mt7996_init_he_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1386 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band,
1387 struct ieee80211_sband_iftype_data *data,
1388 enum nl80211_iftype iftype)
1389 {
1390 struct ieee80211_sta_he_cap *he_cap = &data->he_cap;
1391 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem;
1392 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp;
1393 int i, nss = hweight8(phy->mt76->antenna_mask);
1394 u16 mcs_map = 0;
1395
1396 for (i = 0; i < 8; i++) {
1397 if (i < nss)
1398 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2));
1399 else
1400 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2));
1401 }
1402
1403 he_cap->has_he = true;
1404
1405 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
1406 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
1407 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
1408 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
1409
1410 if (band == NL80211_BAND_2GHZ)
1411 he_cap_elem->phy_cap_info[0] =
1412 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
1413 else
1414 he_cap_elem->phy_cap_info[0] =
1415 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
1416 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1417
1418 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD;
1419 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
1420 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1421
1422 he_cap_elem->phy_cap_info[7] =
1423 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI;
1424
1425 switch (iftype) {
1426 case NL80211_IFTYPE_AP:
1427 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES;
1428 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR;
1429 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR;
1430 he_cap_elem->mac_cap_info[5] |=
1431 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX;
1432 he_cap_elem->phy_cap_info[3] |=
1433 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1434 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1435 he_cap_elem->phy_cap_info[6] |=
1436 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1437 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1438 he_cap_elem->phy_cap_info[9] |=
1439 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1440 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1441 break;
1442 case NL80211_IFTYPE_STATION:
1443 he_cap_elem->mac_cap_info[1] |=
1444 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
1445
1446 if (band == NL80211_BAND_2GHZ)
1447 he_cap_elem->phy_cap_info[0] |=
1448 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G;
1449 else
1450 he_cap_elem->phy_cap_info[0] |=
1451 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G;
1452
1453 he_cap_elem->phy_cap_info[1] |=
1454 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
1455 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
1456 he_cap_elem->phy_cap_info[3] |=
1457 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK |
1458 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK;
1459 he_cap_elem->phy_cap_info[6] |=
1460 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB |
1461 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE |
1462 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT;
1463 he_cap_elem->phy_cap_info[7] |=
1464 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP;
1465 he_cap_elem->phy_cap_info[8] |=
1466 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
1467 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
1468 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
1469 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484;
1470 he_cap_elem->phy_cap_info[9] |=
1471 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
1472 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK |
1473 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU |
1474 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
1475 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
1476 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB;
1477 break;
1478 default:
1479 break;
1480 }
1481
1482 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map);
1483 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map);
1484 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map);
1485 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map);
1486
1487 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band);
1488
1489 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres));
1490 if (he_cap_elem->phy_cap_info[6] &
1491 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) {
1492 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band);
1493 } else {
1494 he_cap_elem->phy_cap_info[9] |=
1495 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
1496 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
1497 }
1498
1499 if (band == NL80211_BAND_6GHZ) {
1500 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS |
1501 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
1502
1503 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5,
1504 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
1505 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
1506 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
1507 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
1508 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
1509
1510 data->he_6ghz_capa.capa = cpu_to_le16(cap);
1511 }
1512 }
1513
1514 static void
mt7996_init_eht_caps(struct mt7996_phy * phy,enum nl80211_band band,struct ieee80211_sband_iftype_data * data,enum nl80211_iftype iftype)1515 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
1516 struct ieee80211_sband_iftype_data *data,
1517 enum nl80211_iftype iftype)
1518 {
1519 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap;
1520 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem;
1521 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp;
1522 enum nl80211_chan_width width = phy->mt76->chandef.width;
1523 int nss = hweight8(phy->mt76->antenna_mask);
1524 int sts = hweight16(phy->mt76->chainmask);
1525 u8 val;
1526
1527 if (!phy->dev->has_eht)
1528 return;
1529
1530 eht_cap->has_eht = true;
1531
1532 eht_cap_elem->mac_cap_info[0] =
1533 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
1534 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
1535 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
1536
1537 eht_cap_elem->mac_cap_info[1] |=
1538 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK;
1539
1540 eht_cap_elem->phy_cap_info[0] =
1541 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
1542 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER |
1543 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
1544
1545 /* Set the maximum capability regardless of the antenna configuration. */
1546 val = is_mt7992(phy->mt76->dev) ? 4 : 3;
1547 eht_cap_elem->phy_cap_info[0] |=
1548 u8_encode_bits(u8_get_bits(val, BIT(0)),
1549 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
1550
1551 eht_cap_elem->phy_cap_info[1] =
1552 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)),
1553 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK);
1554
1555 eht_cap_elem->phy_cap_info[2] =
1556 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK);
1557
1558 if (band != NL80211_BAND_2GHZ) {
1559 eht_cap_elem->phy_cap_info[1] |=
1560 u8_encode_bits(val,
1561 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
1562
1563 eht_cap_elem->phy_cap_info[2] |=
1564 u8_encode_bits(sts - 1,
1565 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK);
1566 }
1567
1568 if (band == NL80211_BAND_6GHZ) {
1569 eht_cap_elem->phy_cap_info[0] |=
1570 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
1571
1572 eht_cap_elem->phy_cap_info[1] |=
1573 u8_encode_bits(val,
1574 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
1575
1576 eht_cap_elem->phy_cap_info[2] |=
1577 u8_encode_bits(sts - 1,
1578 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK);
1579 }
1580
1581 eht_cap_elem->phy_cap_info[3] =
1582 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1583 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1584 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1585 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
1586
1587 eht_cap_elem->phy_cap_info[4] =
1588 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI |
1589 u8_encode_bits(min_t(int, sts - 1, 2),
1590 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
1591
1592 eht_cap_elem->phy_cap_info[5] =
1593 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
1594 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
1595 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),
1596 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK);
1597
1598 val = width == NL80211_CHAN_WIDTH_320 ? 0xf :
1599 width == NL80211_CHAN_WIDTH_160 ? 0x7 :
1600 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1;
1601 eht_cap_elem->phy_cap_info[6] =
1602 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK);
1603
1604 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
1605 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX);
1606 #define SET_EHT_MAX_NSS(_bw, _val) do { \
1607 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \
1608 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \
1609 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \
1610 } while (0)
1611
1612 SET_EHT_MAX_NSS(80, val);
1613 SET_EHT_MAX_NSS(160, val);
1614 if (band == NL80211_BAND_6GHZ)
1615 SET_EHT_MAX_NSS(320, val);
1616 #undef SET_EHT_MAX_NSS
1617
1618 if (iftype != NL80211_IFTYPE_AP)
1619 return;
1620
1621 eht_cap_elem->phy_cap_info[3] |=
1622 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
1623 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
1624
1625 eht_cap_elem->phy_cap_info[7] =
1626 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ |
1627 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ;
1628
1629 if (band == NL80211_BAND_2GHZ)
1630 return;
1631
1632 eht_cap_elem->phy_cap_info[7] |=
1633 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ |
1634 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ;
1635
1636 if (band != NL80211_BAND_6GHZ)
1637 return;
1638
1639 eht_cap_elem->phy_cap_info[7] |=
1640 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ |
1641 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ;
1642 }
1643
1644 static void
__mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy,struct ieee80211_supported_band * sband,enum nl80211_band band)1645 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy,
1646 struct ieee80211_supported_band *sband,
1647 enum nl80211_band band)
1648 {
1649 struct ieee80211_sband_iftype_data *data = phy->iftype[band];
1650 int i, n = 0;
1651
1652 for (i = 0; i < NUM_NL80211_IFTYPES; i++) {
1653 switch (i) {
1654 case NL80211_IFTYPE_STATION:
1655 case NL80211_IFTYPE_AP:
1656 #ifdef CONFIG_MAC80211_MESH
1657 case NL80211_IFTYPE_MESH_POINT:
1658 #endif
1659 break;
1660 default:
1661 continue;
1662 }
1663
1664 data[n].types_mask = BIT(i);
1665 mt7996_init_he_caps(phy, band, &data[n], i);
1666 mt7996_init_eht_caps(phy, band, &data[n], i);
1667
1668 n++;
1669 }
1670
1671 _ieee80211_set_sband_iftype_data(sband, data, n);
1672 }
1673
mt7996_set_stream_he_eht_caps(struct mt7996_phy * phy)1674 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy)
1675 {
1676 if (phy->mt76->cap.has_2ghz)
1677 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband,
1678 NL80211_BAND_2GHZ);
1679
1680 if (phy->mt76->cap.has_5ghz)
1681 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband,
1682 NL80211_BAND_5GHZ);
1683
1684 if (phy->mt76->cap.has_6ghz)
1685 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband,
1686 NL80211_BAND_6GHZ);
1687 }
1688
mt7996_register_device(struct mt7996_dev * dev)1689 int mt7996_register_device(struct mt7996_dev *dev)
1690 {
1691 struct ieee80211_hw *hw = mt76_hw(dev);
1692 #if defined(CONFIG_HWMON)
1693 struct mt7996_phy *phy;
1694 #endif
1695 int ret;
1696
1697 dev->phy.dev = dev;
1698 dev->phy.mt76 = &dev->mt76.phy;
1699 dev->mt76.phy.priv = &dev->phy;
1700 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work);
1701 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work);
1702 INIT_LIST_HEAD(&dev->sta_rc_list);
1703 INIT_LIST_HEAD(&dev->twt_list);
1704
1705 init_waitqueue_head(&dev->reset_wait);
1706 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work);
1707 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work);
1708 mutex_init(&dev->dump_mutex);
1709
1710 ret = mt7996_init_hardware(dev);
1711 if (ret)
1712 return ret;
1713
1714 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed);
1715
1716 ret = mt7996_register_phy(dev, MT_BAND1);
1717 if (ret)
1718 return ret;
1719
1720 ret = mt7996_register_phy(dev, MT_BAND2);
1721 if (ret)
1722 return ret;
1723
1724 ret = mt7996_npu_hw_init(dev);
1725 if (ret)
1726 return ret;
1727
1728 ret = mt76_register_device(&dev->mt76, true, mt76_rates,
1729 ARRAY_SIZE(mt76_rates));
1730 if (ret)
1731 return ret;
1732
1733 #if defined(CONFIG_HWMON)
1734 mt7996_for_each_phy(dev, phy)
1735 mt7996_thermal_init(phy);
1736 #endif
1737
1738 ieee80211_queue_work(mt76_hw(dev), &dev->init_work);
1739
1740 dev->recovery.hw_init_done = true;
1741
1742 #if defined(CONFIG_MT7996_DEBUGFS)
1743 ret = mt7996_init_debugfs(dev);
1744 if (ret)
1745 goto error;
1746 #endif
1747
1748 ret = mt7996_coredump_register(dev);
1749 if (ret)
1750 goto error;
1751
1752 return 0;
1753
1754 error:
1755 cancel_work_sync(&dev->init_work);
1756
1757 return ret;
1758 }
1759
mt7996_unregister_device(struct mt7996_dev * dev)1760 void mt7996_unregister_device(struct mt7996_dev *dev)
1761 {
1762 cancel_work_sync(&dev->wed_rro.work);
1763 mt7996_unregister_phy(mt7996_phy3(dev));
1764 mt7996_unregister_phy(mt7996_phy2(dev));
1765 #if defined(CONFIG_HWMON)
1766 mt7996_unregister_thermal(&dev->phy);
1767 #endif
1768 mt7996_coredump_unregister(dev);
1769 mt76_unregister_device(&dev->mt76);
1770 mt7996_wed_rro_free(dev);
1771 mt7996_mcu_exit(dev);
1772 mt7996_tx_token_put(dev);
1773 mt7996_dma_cleanup(dev);
1774 if (mt7996_has_hwrro(dev) &&
1775 !mtk_wed_device_active(&dev->mt76.mmio.wed))
1776 mt7996_rro_msdu_page_map_free(dev);
1777 tasklet_disable(&dev->mt76.irq_tasklet);
1778
1779 mt76_free_device(&dev->mt76);
1780 }
1781