1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dcn401_clk_mgr_smu_msg.h"
6
7 #include "clk_mgr_internal.h"
8 #include "reg_helper.h"
9
10 #include "dalsmc.h"
11 #include "dcn401_smu14_driver_if.h"
12
13 #define mmDAL_MSG_REG 0x1628A
14 #define mmDAL_ARG_REG 0x16273
15 #define mmDAL_RESP_REG 0x16274
16
17 #define REG(reg_name) \
18 mm ## reg_name
19
20 #include "logger_types.h"
21
22 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); }
23
24 /* temporary define */
25 #ifndef DALSMC_MSG_SubvpUclkFclk
26 #define DALSMC_MSG_SubvpUclkFclk 0x1B
27 #endif
28 #ifndef DALSMC_MSG_GetNumUmcChannels
29 #define DALSMC_MSG_GetNumUmcChannels 0x1C
30 #endif
31
32 /*
33 * Function to be used instead of REG_WAIT macro because the wait ends when
34 * the register is NOT EQUAL to zero, and because the translation in msg_if.h
35 * won't work with REG_WAIT.
36 */
dcn401_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)37 static uint32_t dcn401_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
38 {
39 uint32_t reg = 0;
40
41 do {
42 reg = REG_READ(DAL_RESP_REG);
43 if (reg)
44 break;
45
46 if (delay_us >= 1000)
47 msleep(delay_us/1000);
48 else if (delay_us > 0)
49 udelay(delay_us);
50 } while (max_retries--);
51
52 return reg;
53 }
54
dcn401_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,uint32_t msg_id,uint32_t param_in,uint32_t * param_out)55 static bool dcn401_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out)
56 {
57 /* Wait for response register to be ready */
58 dcn401_smu_wait_for_response(clk_mgr, 10, 200000);
59
60 TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr->base.ctx);
61
62 /* Clear response register */
63 REG_WRITE(DAL_RESP_REG, 0);
64
65 /* Set the parameter register for the SMU message */
66 REG_WRITE(DAL_ARG_REG, param_in);
67
68 /* Trigger the message transaction by writing the message ID */
69 REG_WRITE(DAL_MSG_REG, msg_id);
70
71 /* Wait for response */
72 if (dcn401_smu_wait_for_response(clk_mgr, 10, 200000) == DALSMC_Result_OK) {
73 if (param_out)
74 *param_out = REG_READ(DAL_ARG_REG);
75
76 TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx);
77 return true;
78 }
79
80 TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx);
81 return false;
82 }
83
84 /*
85 * Use these functions to return back delay information so we can aggregate the total
86 * delay when requesting hardmin clk
87 *
88 * dcn401_smu_wait_for_response_delay
89 * dcn401_smu_send_msg_with_param_delay
90 *
91 */
dcn401_smu_wait_for_response_delay(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries,unsigned int * total_delay_us)92 static uint32_t dcn401_smu_wait_for_response_delay(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries, unsigned int *total_delay_us)
93 {
94 uint32_t reg = 0;
95 *total_delay_us = 0;
96
97 do {
98 reg = REG_READ(DAL_RESP_REG);
99 if (reg)
100 break;
101
102 if (delay_us >= 1000)
103 msleep(delay_us/1000);
104 else if (delay_us > 0)
105 udelay(delay_us);
106 *total_delay_us += delay_us;
107 } while (max_retries--);
108
109 return reg;
110 }
111
dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal * clk_mgr,uint32_t msg_id,uint32_t param_in,uint32_t * param_out,unsigned int * total_delay_us)112 static bool dcn401_smu_send_msg_with_param_delay(struct clk_mgr_internal *clk_mgr, uint32_t msg_id, uint32_t param_in, uint32_t *param_out, unsigned int *total_delay_us)
113 {
114 unsigned int delay1_us, delay2_us;
115 *total_delay_us = 0;
116
117 /* Wait for response register to be ready */
118 dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay1_us);
119
120 TRACE_SMU_MSG_ENTER(msg_id, param_in, clk_mgr->base.ctx);
121
122 /* Clear response register */
123 REG_WRITE(DAL_RESP_REG, 0);
124
125 /* Set the parameter register for the SMU message */
126 REG_WRITE(DAL_ARG_REG, param_in);
127
128 /* Trigger the message transaction by writing the message ID */
129 REG_WRITE(DAL_MSG_REG, msg_id);
130
131 /* Wait for response */
132 if (dcn401_smu_wait_for_response_delay(clk_mgr, 10, 200000, &delay2_us) == DALSMC_Result_OK) {
133 if (param_out)
134 *param_out = REG_READ(DAL_ARG_REG);
135
136 *total_delay_us = delay1_us + delay2_us;
137 TRACE_SMU_MSG_EXIT(true, param_out ? *param_out : 0, clk_mgr->base.ctx);
138 return true;
139 }
140
141 *total_delay_us = delay1_us + 2000000;
142 TRACE_SMU_MSG_EXIT(false, 0, clk_mgr->base.ctx);
143 return false;
144 }
145
dcn401_smu_get_smu_version(struct clk_mgr_internal * clk_mgr,unsigned int * version)146 bool dcn401_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version)
147 {
148 smu_print("SMU Get SMU version\n");
149
150 if (dcn401_smu_send_msg_with_param(clk_mgr,
151 DALSMC_MSG_GetSmuVersion, 0, version)) {
152
153 smu_print("SMU version: %d\n", *version);
154
155 return true;
156 }
157
158 return false;
159 }
160
161 /* Message output should match SMU11_DRIVER_IF_VERSION in smu11_driver_if.h */
dcn401_smu_check_driver_if_version(struct clk_mgr_internal * clk_mgr)162 bool dcn401_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr)
163 {
164 uint32_t response = 0;
165
166 smu_print("SMU Check driver if version\n");
167
168 if (dcn401_smu_send_msg_with_param(clk_mgr,
169 DALSMC_MSG_GetDriverIfVersion, 0, &response)) {
170
171 smu_print("SMU driver if version: %d\n", response);
172
173 if (response == SMU14_DRIVER_IF_VERSION)
174 return true;
175 }
176
177 return false;
178 }
179
180 /* Message output should match DALSMC_VERSION in dalsmc.h */
dcn401_smu_check_msg_header_version(struct clk_mgr_internal * clk_mgr)181 bool dcn401_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr)
182 {
183 uint32_t response = 0;
184
185 smu_print("SMU Check msg header version\n");
186
187 if (dcn401_smu_send_msg_with_param(clk_mgr,
188 DALSMC_MSG_GetMsgHeaderVersion, 0, &response)) {
189
190 smu_print("SMU msg header version: %d\n", response);
191
192 if (response == DALSMC_VERSION)
193 return true;
194 }
195
196 return false;
197 }
198
dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal * clk_mgr,bool support)199 void dcn401_smu_send_fclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
200 {
201 smu_print("FCLK P-state support value is : %d\n", support);
202
203 dcn401_smu_send_msg_with_param(clk_mgr,
204 DALSMC_MSG_SetFclkSwitchAllow, support, NULL);
205 }
206
dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal * clk_mgr,bool support)207 void dcn401_smu_send_uclk_pstate_message(struct clk_mgr_internal *clk_mgr, bool support)
208 {
209 smu_print("UCLK P-state support value is : %d\n", support);
210
211 dcn401_smu_send_msg_with_param(clk_mgr,
212 DALSMC_MSG_SetUclkPstateAllow, support, NULL);
213 }
214
dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal * clk_mgr,unsigned int num_ways)215 void dcn401_smu_send_cab_for_uclk_message(struct clk_mgr_internal *clk_mgr, unsigned int num_ways)
216 {
217 uint32_t param = (num_ways << 1) | (num_ways > 0);
218
219 dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetCabForUclkPstate, param, NULL);
220 smu_print("Numways for SubVP : %d\n", num_ways);
221 }
222
dcn401_smu_set_dram_addr_high(struct clk_mgr_internal * clk_mgr,uint32_t addr_high)223 void dcn401_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
224 {
225 smu_print("SMU Set DRAM addr high: %d\n", addr_high);
226
227 dcn401_smu_send_msg_with_param(clk_mgr,
228 DALSMC_MSG_SetDalDramAddrHigh, addr_high, NULL);
229 }
230
dcn401_smu_set_dram_addr_low(struct clk_mgr_internal * clk_mgr,uint32_t addr_low)231 void dcn401_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
232 {
233 smu_print("SMU Set DRAM addr low: %d\n", addr_low);
234
235 dcn401_smu_send_msg_with_param(clk_mgr,
236 DALSMC_MSG_SetDalDramAddrLow, addr_low, NULL);
237 }
238
dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal * clk_mgr)239 void dcn401_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
240 {
241 smu_print("SMU Transfer WM table DRAM 2 SMU\n");
242
243 dcn401_smu_send_msg_with_param(clk_mgr,
244 DALSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS, NULL);
245 }
246
dcn401_smu_set_pme_workaround(struct clk_mgr_internal * clk_mgr)247 void dcn401_smu_set_pme_workaround(struct clk_mgr_internal *clk_mgr)
248 {
249 smu_print("SMU Set PME workaround\n");
250
251 dcn401_smu_send_msg_with_param(clk_mgr,
252 DALSMC_MSG_BacoAudioD3PME, 0, NULL);
253 }
254
dcn401_smu_get_hard_min_status(struct clk_mgr_internal * clk_mgr,bool * no_timeout,unsigned int * total_delay_us)255 static unsigned int dcn401_smu_get_hard_min_status(struct clk_mgr_internal *clk_mgr, bool *no_timeout, unsigned int *total_delay_us)
256 {
257 uint32_t response = 0;
258
259 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
260 uint32_t param = 0;
261
262 *no_timeout = dcn401_smu_send_msg_with_param_delay(clk_mgr,
263 DALSMC_MSG_ReturnHardMinStatus, param, &response, total_delay_us);
264
265 smu_print("SMU Get hard min status: no_timeout %d delay %d us clk bits %x\n",
266 *no_timeout, *total_delay_us, response);
267
268 return response;
269 }
270
dcn401_smu_wait_hard_min_status(struct clk_mgr_internal * clk_mgr,uint32_t ppclk)271 static bool dcn401_smu_wait_hard_min_status(struct clk_mgr_internal *clk_mgr, uint32_t ppclk)
272 {
273 const unsigned int max_delay_us = 1000000;
274
275 unsigned int hardmin_status_mask = (1 << ppclk);
276 unsigned int total_delay_us = 0;
277 bool hardmin_done = false;
278
279 while (!hardmin_done && total_delay_us < max_delay_us) {
280 unsigned int hardmin_status;
281 unsigned int read_total_delay_us;
282 bool no_timeout;
283
284 if (!hardmin_done && total_delay_us > 0) {
285 /* hardmin not yet fulfilled, wait 500us and retry*/
286 udelay(500);
287 total_delay_us += 500;
288
289 smu_print("SMU Wait hard min status for %d us\n", total_delay_us);
290 }
291
292 hardmin_status = dcn401_smu_get_hard_min_status(clk_mgr, &no_timeout, &read_total_delay_us);
293 total_delay_us += read_total_delay_us;
294 hardmin_done = hardmin_status & hardmin_status_mask;
295 }
296
297 return hardmin_done;
298 }
299
300 /* Returns the actual frequency that was set in MHz, 0 on failure */
dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint16_t freq_mhz)301 unsigned int dcn401_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint16_t freq_mhz)
302 {
303 uint32_t response = 0;
304 bool hard_min_done = false;
305
306 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */
307 uint32_t param = (clk << 16) | freq_mhz;
308
309 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz);
310
311 dcn401_smu_send_msg_with_param(clk_mgr,
312 DALSMC_MSG_SetHardMinByFreq, param, &response);
313
314 /* wait until hardmin acknowledged */
315 hard_min_done = dcn401_smu_wait_hard_min_status(clk_mgr, clk);
316 smu_print("SMU Frequency set = %d KHz hard_min_done %d\n", response, hard_min_done);
317
318 return response;
319 }
320
dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal * clk_mgr,bool enable)321 void dcn401_smu_wait_for_dmub_ack_mclk(struct clk_mgr_internal *clk_mgr, bool enable)
322 {
323 smu_print("SMU to wait for DMCUB ack for MCLK : %d\n", enable);
324
325 dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_SetAlwaysWaitDmcubResp, enable ? 1 : 0, NULL);
326 }
327
dcn401_smu_indicate_drr_status(struct clk_mgr_internal * clk_mgr,bool mod_drr_for_pstate)328 void dcn401_smu_indicate_drr_status(struct clk_mgr_internal *clk_mgr, bool mod_drr_for_pstate)
329 {
330 smu_print("SMU Set indicate drr status = %d\n", mod_drr_for_pstate);
331
332 dcn401_smu_send_msg_with_param(clk_mgr,
333 DALSMC_MSG_IndicateDrrStatus, mod_drr_for_pstate ? 1 : 0, NULL);
334 }
335
dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal * clk_mgr,uint16_t uclk_freq_mhz,uint16_t fclk_freq_mhz)336 bool dcn401_smu_set_idle_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
337 uint16_t uclk_freq_mhz,
338 uint16_t fclk_freq_mhz)
339 {
340 uint32_t response = 0;
341 bool success;
342
343 /* 15:0 for uclk, 32:16 for fclk */
344 uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;
345
346 smu_print("SMU Set idle hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);
347
348 success = dcn401_smu_send_msg_with_param(clk_mgr,
349 DALSMC_MSG_IdleUclkFclk, param, &response);
350
351 /* wait until hardmin acknowledged */
352 success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);
353 smu_print("SMU hard_min_done %d\n", success);
354
355 return success;
356 }
357
dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal * clk_mgr,uint16_t uclk_freq_mhz,uint16_t fclk_freq_mhz)358 bool dcn401_smu_set_active_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
359 uint16_t uclk_freq_mhz,
360 uint16_t fclk_freq_mhz)
361 {
362 uint32_t response = 0;
363 bool success;
364
365 /* 15:0 for uclk, 32:16 for fclk */
366 uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;
367
368 smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);
369
370 success = dcn401_smu_send_msg_with_param(clk_mgr,
371 DALSMC_MSG_ActiveUclkFclk, param, &response);
372
373 /* wait until hardmin acknowledged */
374 success &= dcn401_smu_wait_hard_min_status(clk_mgr, PPCLK_UCLK);
375 smu_print("SMU hard_min_done %d\n", success);
376
377 return success;
378 }
379
dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal * clk_mgr,uint16_t uclk_freq_mhz,uint16_t fclk_freq_mhz)380 bool dcn401_smu_set_subvp_uclk_fclk_hardmin(struct clk_mgr_internal *clk_mgr,
381 uint16_t uclk_freq_mhz,
382 uint16_t fclk_freq_mhz)
383 {
384 uint32_t response = 0;
385 bool success;
386
387 /* 15:0 for uclk, 32:16 for fclk */
388 uint32_t param = (fclk_freq_mhz << 16) | uclk_freq_mhz;
389
390 smu_print("SMU Set active hardmin by freq: uclk_freq_mhz = %d MHz, fclk_freq_mhz = %d MHz\n", uclk_freq_mhz, fclk_freq_mhz);
391
392 success = dcn401_smu_send_msg_with_param(clk_mgr,
393 DALSMC_MSG_SubvpUclkFclk, param, &response);
394
395 return success;
396 }
397
dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal * clk_mgr,uint32_t freq_mhz)398 void dcn401_smu_set_min_deep_sleep_dcef_clk(struct clk_mgr_internal *clk_mgr, uint32_t freq_mhz)
399 {
400 smu_print("SMU Set min deep sleep dcef clk: freq_mhz = %d MHz\n", freq_mhz);
401
402 dcn401_smu_send_msg_with_param(clk_mgr,
403 DALSMC_MSG_SetMinDeepSleepDcfclk, freq_mhz, NULL);
404 }
405
dcn401_smu_set_num_of_displays(struct clk_mgr_internal * clk_mgr,uint32_t num_displays)406 void dcn401_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays)
407 {
408 smu_print("SMU Set num of displays: num_displays = %d\n", num_displays);
409
410 dcn401_smu_send_msg_with_param(clk_mgr,
411 DALSMC_MSG_NumOfDisplays, num_displays, NULL);
412 }
413
dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal * clk_mgr)414 unsigned int dcn401_smu_get_num_of_umc_channels(struct clk_mgr_internal *clk_mgr)
415 {
416 unsigned int response = 0;
417
418 dcn401_smu_send_msg_with_param(clk_mgr, DALSMC_MSG_GetNumUmcChannels, 0, &response);
419
420 smu_print("SMU Get Num UMC Channels: num_umc_channels = %d\n", response);
421
422 return response;
423 }
424
425 /*
426 * Frequency in MHz returned in lower 16 bits for valid DPM level
427 *
428 * Call with dpm_level = 0xFF to query features, return value will be:
429 * Bits 7:0 - number of DPM levels
430 * Bit 28 - 1 = auto DPM on
431 * Bit 29 - 1 = sweep DPM on
432 * Bit 30 - 1 = forced DPM on
433 * Bit 31 - 0 = discrete, 1 = fine-grained
434 *
435 * With fine-grained DPM, only min and max frequencies will be reported
436 *
437 * Returns 0 on failure
438 */
dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal * clk_mgr,uint32_t clk,uint8_t dpm_level)439 unsigned int dcn401_smu_get_dpm_freq_by_index(struct clk_mgr_internal *clk_mgr, uint32_t clk, uint8_t dpm_level)
440 {
441 uint32_t response = 0;
442
443 /* bits 23:16 for clock type, lower 8 bits for DPM level */
444 uint32_t param = (clk << 16) | dpm_level;
445
446 smu_print("SMU Get dpm freq by index: clk = %d, dpm_level = %d\n", clk, dpm_level);
447
448 dcn401_smu_send_msg_with_param(clk_mgr,
449 DALSMC_MSG_GetDpmFreqByIndex, param, &response);
450
451 smu_print("SMU dpm freq: %d MHz\n", response);
452
453 return response;
454 }
455
456 /* Returns the max DPM frequency in DC mode in MHz, 0 on failure */
dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal * clk_mgr,uint32_t clk)457 unsigned int dcn401_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, uint32_t clk)
458 {
459 uint32_t response = 0;
460
461 /* bits 23:16 for clock type */
462 uint32_t param = clk << 16;
463
464 smu_print("SMU Get DC mode max DPM freq: clk = %d\n", clk);
465
466 dcn401_smu_send_msg_with_param(clk_mgr,
467 DALSMC_MSG_GetDcModeMaxDpmFreq, param, &response);
468
469 smu_print("SMU DC mode max DMP freq: %d MHz\n", response);
470
471 return response;
472 }
473