1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/module.h>
34
35 #include "../iio.h"
36 #include "../sysfs.h"
37 #include "../events.h"
38 #include "../buffer.h"
39
40 #include "max1363.h"
41
42 #define MAX1363_MODE_SINGLE(_num, _mask) { \
43 .conf = MAX1363_CHANNEL_SEL(_num) \
44 | MAX1363_CONFIG_SCAN_SINGLE_1 \
45 | MAX1363_CONFIG_SE, \
46 .modemask[0] = _mask, \
47 }
48
49 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
50 .conf = MAX1363_CHANNEL_SEL(_num) \
51 | MAX1363_CONFIG_SCAN_TO_CS \
52 | MAX1363_CONFIG_SE, \
53 .modemask[0] = _mask, \
54 }
55
56 /* note not available for max1363 hence naming */
57 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
58 .conf = MAX1363_CHANNEL_SEL(_num) \
59 | MAX1236_SCAN_MID_TO_CHANNEL \
60 | MAX1363_CONFIG_SE, \
61 .modemask[0] = _mask \
62 }
63
64 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
65 .conf = MAX1363_CHANNEL_SEL(_nump) \
66 | MAX1363_CONFIG_SCAN_SINGLE_1 \
67 | MAX1363_CONFIG_DE, \
68 .modemask[0] = _mask \
69 }
70
71 /* Can't think how to automate naming so specify for now */
72 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
73 .conf = MAX1363_CHANNEL_SEL(_num) \
74 | MAX1363_CONFIG_SCAN_TO_CS \
75 | MAX1363_CONFIG_DE, \
76 .modemask[0] = _mask \
77 }
78
79 /* note only available for max1363 hence naming */
80 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
81 .conf = MAX1363_CHANNEL_SEL(_num) \
82 | MAX1236_SCAN_MID_TO_CHANNEL \
83 | MAX1363_CONFIG_SE, \
84 .modemask[0] = _mask \
85 }
86
87 static const struct max1363_mode max1363_mode_table[] = {
88 /* All of the single channel options first */
89 MAX1363_MODE_SINGLE(0, 1 << 0),
90 MAX1363_MODE_SINGLE(1, 1 << 1),
91 MAX1363_MODE_SINGLE(2, 1 << 2),
92 MAX1363_MODE_SINGLE(3, 1 << 3),
93 MAX1363_MODE_SINGLE(4, 1 << 4),
94 MAX1363_MODE_SINGLE(5, 1 << 5),
95 MAX1363_MODE_SINGLE(6, 1 << 6),
96 MAX1363_MODE_SINGLE(7, 1 << 7),
97 MAX1363_MODE_SINGLE(8, 1 << 8),
98 MAX1363_MODE_SINGLE(9, 1 << 9),
99 MAX1363_MODE_SINGLE(10, 1 << 10),
100 MAX1363_MODE_SINGLE(11, 1 << 11),
101
102 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
103 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
104 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
105 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
106 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
107 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
108 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
109 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
110 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
111 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
112 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
113 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
114
115 /* The multichannel scans next */
116 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
117 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
118 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
119 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
120 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
121 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
122 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
123 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
124 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
125 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
126 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
127 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
128 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
129 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
130 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
131 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
132 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
133
134 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
135 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
136 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
137 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
138 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
139 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
140 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
141 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
142 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
143 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
144 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
145 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
146 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
147 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
148 };
149
150 const struct max1363_mode
max1363_match_mode(const unsigned long * mask,const struct max1363_chip_info * ci)151 *max1363_match_mode(const unsigned long *mask,
152 const struct max1363_chip_info *ci)
153 {
154 int i;
155 if (mask)
156 for (i = 0; i < ci->num_modes; i++)
157 if (bitmap_subset(mask,
158 max1363_mode_table[ci->mode_list[i]].
159 modemask,
160 MAX1363_MAX_CHANNELS))
161 return &max1363_mode_table[ci->mode_list[i]];
162 return NULL;
163 }
164
max1363_write_basic_config(struct i2c_client * client,unsigned char d1,unsigned char d2)165 static int max1363_write_basic_config(struct i2c_client *client,
166 unsigned char d1,
167 unsigned char d2)
168 {
169 u8 tx_buf[2] = {d1, d2};
170
171 return i2c_master_send(client, tx_buf, 2);
172 }
173
max1363_set_scan_mode(struct max1363_state * st)174 int max1363_set_scan_mode(struct max1363_state *st)
175 {
176 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
177 | MAX1363_SCAN_MASK
178 | MAX1363_SE_DE_MASK);
179 st->configbyte |= st->current_mode->conf;
180
181 return max1363_write_basic_config(st->client,
182 st->setupbyte,
183 st->configbyte);
184 }
185
max1363_read_single_chan(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,long m)186 static int max1363_read_single_chan(struct iio_dev *indio_dev,
187 struct iio_chan_spec const *chan,
188 int *val,
189 long m)
190 {
191 int ret = 0;
192 s32 data;
193 char rxbuf[2];
194 struct max1363_state *st = iio_priv(indio_dev);
195 struct i2c_client *client = st->client;
196
197 mutex_lock(&indio_dev->mlock);
198 /*
199 * If monitor mode is enabled, the method for reading a single
200 * channel will have to be rather different and has not yet
201 * been implemented.
202 *
203 * Also, cannot read directly if buffered capture enabled.
204 */
205 if (st->monitor_on || iio_buffer_enabled(indio_dev)) {
206 ret = -EBUSY;
207 goto error_ret;
208 }
209
210 /* Check to see if current scan mode is correct */
211 if (st->current_mode != &max1363_mode_table[chan->address]) {
212 /* Update scan mode if needed */
213 st->current_mode = &max1363_mode_table[chan->address];
214 ret = max1363_set_scan_mode(st);
215 if (ret < 0)
216 goto error_ret;
217 }
218 if (st->chip_info->bits != 8) {
219 /* Get reading */
220 data = i2c_master_recv(client, rxbuf, 2);
221 if (data < 0) {
222 ret = data;
223 goto error_ret;
224 }
225 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
226 } else {
227 /* Get reading */
228 data = i2c_master_recv(client, rxbuf, 1);
229 if (data < 0) {
230 ret = data;
231 goto error_ret;
232 }
233 data = rxbuf[0];
234 }
235 *val = data;
236 error_ret:
237 mutex_unlock(&indio_dev->mlock);
238 return ret;
239
240 }
241
max1363_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)242 static int max1363_read_raw(struct iio_dev *indio_dev,
243 struct iio_chan_spec const *chan,
244 int *val,
245 int *val2,
246 long m)
247 {
248 struct max1363_state *st = iio_priv(indio_dev);
249 int ret;
250 switch (m) {
251 case 0:
252 ret = max1363_read_single_chan(indio_dev, chan, val, m);
253 if (ret < 0)
254 return ret;
255 return IIO_VAL_INT;
256 case IIO_CHAN_INFO_SCALE:
257 if ((1 << (st->chip_info->bits + 1)) >
258 st->chip_info->int_vref_mv) {
259 *val = 0;
260 *val2 = 500000;
261 return IIO_VAL_INT_PLUS_MICRO;
262 } else {
263 *val = (st->chip_info->int_vref_mv)
264 >> st->chip_info->bits;
265 return IIO_VAL_INT;
266 }
267 default:
268 return -EINVAL;
269 }
270 return 0;
271 }
272
273 /* Applies to max1363 */
274 static const enum max1363_modes max1363_mode_list[] = {
275 _s0, _s1, _s2, _s3,
276 s0to1, s0to2, s0to3,
277 d0m1, d2m3, d1m0, d3m2,
278 d0m1to2m3, d1m0to3m2,
279 };
280
281 #define MAX1363_EV_M \
282 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
283 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
284 #define MAX1363_INFO_MASK IIO_CHAN_INFO_SCALE_SHARED_BIT
285 #define MAX1363_CHAN_U(num, addr, si, bits, evmask) \
286 { \
287 .type = IIO_VOLTAGE, \
288 .indexed = 1, \
289 .channel = num, \
290 .address = addr, \
291 .info_mask = MAX1363_INFO_MASK, \
292 .datasheet_name = "AIN"#num, \
293 .scan_type = { \
294 .sign = 'u', \
295 .realbits = bits, \
296 .storagebits = (bits > 8) ? 16 : 8, \
297 .endianness = IIO_BE, \
298 }, \
299 .scan_index = si, \
300 .event_mask = evmask, \
301 }
302
303 /* bipolar channel */
304 #define MAX1363_CHAN_B(num, num2, addr, si, bits, evmask) \
305 { \
306 .type = IIO_VOLTAGE, \
307 .differential = 1, \
308 .indexed = 1, \
309 .channel = num, \
310 .channel2 = num2, \
311 .address = addr, \
312 .info_mask = MAX1363_INFO_MASK, \
313 .datasheet_name = "AIN"#num"-AIN"#num2, \
314 .scan_type = { \
315 .sign = 's', \
316 .realbits = bits, \
317 .storagebits = (bits > 8) ? 16 : 8, \
318 .endianness = IIO_BE, \
319 }, \
320 .scan_index = si, \
321 .event_mask = evmask, \
322 }
323
324 #define MAX1363_4X_CHANS(bits, em) { \
325 MAX1363_CHAN_U(0, _s0, 0, bits, em), \
326 MAX1363_CHAN_U(1, _s1, 1, bits, em), \
327 MAX1363_CHAN_U(2, _s2, 2, bits, em), \
328 MAX1363_CHAN_U(3, _s3, 3, bits, em), \
329 MAX1363_CHAN_B(0, 1, d0m1, 4, bits, em), \
330 MAX1363_CHAN_B(2, 3, d2m3, 5, bits, em), \
331 MAX1363_CHAN_B(1, 0, d1m0, 6, bits, em), \
332 MAX1363_CHAN_B(3, 2, d3m2, 7, bits, em), \
333 IIO_CHAN_SOFT_TIMESTAMP(8) \
334 }
335
336 static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8, 0);
337 static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10, 0);
338 static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12, 0);
339 static struct iio_chan_spec max1361_channels[] =
340 MAX1363_4X_CHANS(10, MAX1363_EV_M);
341 static struct iio_chan_spec max1363_channels[] =
342 MAX1363_4X_CHANS(12, MAX1363_EV_M);
343
344 /* Appies to max1236, max1237 */
345 static const enum max1363_modes max1236_mode_list[] = {
346 _s0, _s1, _s2, _s3,
347 s0to1, s0to2, s0to3,
348 d0m1, d2m3, d1m0, d3m2,
349 d0m1to2m3, d1m0to3m2,
350 s2to3,
351 };
352
353 /* Applies to max1238, max1239 */
354 static const enum max1363_modes max1238_mode_list[] = {
355 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
356 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
357 s0to7, s0to8, s0to9, s0to10, s0to11,
358 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
359 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
360 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
361 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
362 s6to7, s6to8, s6to9, s6to10, s6to11,
363 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
364 };
365
366 #define MAX1363_12X_CHANS(bits) { \
367 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
368 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
369 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
370 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
371 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
372 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
373 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
374 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
375 MAX1363_CHAN_U(8, _s8, 8, bits, 0), \
376 MAX1363_CHAN_U(9, _s9, 9, bits, 0), \
377 MAX1363_CHAN_U(10, _s10, 10, bits, 0), \
378 MAX1363_CHAN_U(11, _s11, 11, bits, 0), \
379 MAX1363_CHAN_B(0, 1, d0m1, 12, bits, 0), \
380 MAX1363_CHAN_B(2, 3, d2m3, 13, bits, 0), \
381 MAX1363_CHAN_B(4, 5, d4m5, 14, bits, 0), \
382 MAX1363_CHAN_B(6, 7, d6m7, 15, bits, 0), \
383 MAX1363_CHAN_B(8, 9, d8m9, 16, bits, 0), \
384 MAX1363_CHAN_B(10, 11, d10m11, 17, bits, 0), \
385 MAX1363_CHAN_B(1, 0, d1m0, 18, bits, 0), \
386 MAX1363_CHAN_B(3, 2, d3m2, 19, bits, 0), \
387 MAX1363_CHAN_B(5, 4, d5m4, 20, bits, 0), \
388 MAX1363_CHAN_B(7, 6, d7m6, 21, bits, 0), \
389 MAX1363_CHAN_B(9, 8, d9m8, 22, bits, 0), \
390 MAX1363_CHAN_B(11, 10, d11m10, 23, bits, 0), \
391 IIO_CHAN_SOFT_TIMESTAMP(24) \
392 }
393 static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
394 static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
395 static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
396
397 static const enum max1363_modes max11607_mode_list[] = {
398 _s0, _s1, _s2, _s3,
399 s0to1, s0to2, s0to3,
400 s2to3,
401 d0m1, d2m3, d1m0, d3m2,
402 d0m1to2m3, d1m0to3m2,
403 };
404
405 static const enum max1363_modes max11608_mode_list[] = {
406 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
407 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
408 s6to7,
409 d0m1, d2m3, d4m5, d6m7,
410 d1m0, d3m2, d5m4, d7m6,
411 d0m1to2m3, d0m1to4m5, d0m1to6m7,
412 d1m0to3m2, d1m0to5m4, d1m0to7m6,
413 };
414
415 #define MAX1363_8X_CHANS(bits) { \
416 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
417 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
418 MAX1363_CHAN_U(2, _s2, 2, bits, 0), \
419 MAX1363_CHAN_U(3, _s3, 3, bits, 0), \
420 MAX1363_CHAN_U(4, _s4, 4, bits, 0), \
421 MAX1363_CHAN_U(5, _s5, 5, bits, 0), \
422 MAX1363_CHAN_U(6, _s6, 6, bits, 0), \
423 MAX1363_CHAN_U(7, _s7, 7, bits, 0), \
424 MAX1363_CHAN_B(0, 1, d0m1, 8, bits, 0), \
425 MAX1363_CHAN_B(2, 3, d2m3, 9, bits, 0), \
426 MAX1363_CHAN_B(4, 5, d4m5, 10, bits, 0), \
427 MAX1363_CHAN_B(6, 7, d6m7, 11, bits, 0), \
428 MAX1363_CHAN_B(1, 0, d1m0, 12, bits, 0), \
429 MAX1363_CHAN_B(3, 2, d3m2, 13, bits, 0), \
430 MAX1363_CHAN_B(5, 4, d5m4, 14, bits, 0), \
431 MAX1363_CHAN_B(7, 6, d7m6, 15, bits, 0), \
432 IIO_CHAN_SOFT_TIMESTAMP(16) \
433 }
434 static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
435 static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
436 static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
437
438 static const enum max1363_modes max11644_mode_list[] = {
439 _s0, _s1, s0to1, d0m1, d1m0,
440 };
441
442 #define MAX1363_2X_CHANS(bits) { \
443 MAX1363_CHAN_U(0, _s0, 0, bits, 0), \
444 MAX1363_CHAN_U(1, _s1, 1, bits, 0), \
445 MAX1363_CHAN_B(0, 1, d0m1, 2, bits, 0), \
446 MAX1363_CHAN_B(1, 0, d1m0, 3, bits, 0), \
447 IIO_CHAN_SOFT_TIMESTAMP(4) \
448 }
449
450 static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
451 static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
452
453 enum { max1361,
454 max1362,
455 max1363,
456 max1364,
457 max1036,
458 max1037,
459 max1038,
460 max1039,
461 max1136,
462 max1137,
463 max1138,
464 max1139,
465 max1236,
466 max1237,
467 max1238,
468 max1239,
469 max11600,
470 max11601,
471 max11602,
472 max11603,
473 max11604,
474 max11605,
475 max11606,
476 max11607,
477 max11608,
478 max11609,
479 max11610,
480 max11611,
481 max11612,
482 max11613,
483 max11614,
484 max11615,
485 max11616,
486 max11617,
487 max11644,
488 max11645,
489 max11646,
490 max11647
491 };
492
493 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
494 8300, 4200, 2000, 1000 };
495
max1363_monitor_show_freq(struct device * dev,struct device_attribute * attr,char * buf)496 static ssize_t max1363_monitor_show_freq(struct device *dev,
497 struct device_attribute *attr,
498 char *buf)
499 {
500 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
501 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
502 }
503
max1363_monitor_store_freq(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)504 static ssize_t max1363_monitor_store_freq(struct device *dev,
505 struct device_attribute *attr,
506 const char *buf,
507 size_t len)
508 {
509 struct iio_dev *indio_dev = dev_get_drvdata(dev);
510 struct max1363_state *st = iio_priv(indio_dev);
511 int i, ret;
512 unsigned long val;
513 bool found = false;
514
515 ret = strict_strtoul(buf, 10, &val);
516 if (ret)
517 return -EINVAL;
518 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
519 if (val == max1363_monitor_speeds[i]) {
520 found = true;
521 break;
522 }
523 if (!found)
524 return -EINVAL;
525
526 mutex_lock(&indio_dev->mlock);
527 st->monitor_speed = i;
528 mutex_unlock(&indio_dev->mlock);
529
530 return 0;
531 }
532
533 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
534 max1363_monitor_show_freq,
535 max1363_monitor_store_freq);
536
537 static IIO_CONST_ATTR(sampling_frequency_available,
538 "133000 665000 33300 16600 8300 4200 2000 1000");
539
max1363_read_thresh(struct iio_dev * indio_dev,u64 event_code,int * val)540 static int max1363_read_thresh(struct iio_dev *indio_dev,
541 u64 event_code,
542 int *val)
543 {
544 struct max1363_state *st = iio_priv(indio_dev);
545 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
546 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
547 else
548 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
549 return 0;
550 }
551
max1363_write_thresh(struct iio_dev * indio_dev,u64 event_code,int val)552 static int max1363_write_thresh(struct iio_dev *indio_dev,
553 u64 event_code,
554 int val)
555 {
556 struct max1363_state *st = iio_priv(indio_dev);
557 /* make it handle signed correctly as well */
558 switch (st->chip_info->bits) {
559 case 10:
560 if (val > 0x3FF)
561 return -EINVAL;
562 break;
563 case 12:
564 if (val > 0xFFF)
565 return -EINVAL;
566 break;
567 }
568
569 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
570 case IIO_EV_DIR_FALLING:
571 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
572 break;
573 case IIO_EV_DIR_RISING:
574 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
575 break;
576 }
577
578 return 0;
579 }
580
581 static const u64 max1363_event_codes[] = {
582 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
583 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
584 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
585 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
586 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
587 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
588 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
589 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
590 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
591 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
592 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
593 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
594 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
595 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
596 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
597 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
598 };
599
max1363_event_handler(int irq,void * private)600 static irqreturn_t max1363_event_handler(int irq, void *private)
601 {
602 struct iio_dev *indio_dev = private;
603 struct max1363_state *st = iio_priv(indio_dev);
604 s64 timestamp = iio_get_time_ns();
605 unsigned long mask, loc;
606 u8 rx;
607 u8 tx[2] = { st->setupbyte,
608 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
609
610 i2c_master_recv(st->client, &rx, 1);
611 mask = rx;
612 for_each_set_bit(loc, &mask, 8)
613 iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
614 i2c_master_send(st->client, tx, 2);
615
616 return IRQ_HANDLED;
617 }
618
max1363_read_event_config(struct iio_dev * indio_dev,u64 event_code)619 static int max1363_read_event_config(struct iio_dev *indio_dev,
620 u64 event_code)
621 {
622 struct max1363_state *st = iio_priv(indio_dev);
623
624 int val;
625 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
626 mutex_lock(&indio_dev->mlock);
627 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
628 val = (1 << number) & st->mask_low;
629 else
630 val = (1 << number) & st->mask_high;
631 mutex_unlock(&indio_dev->mlock);
632
633 return val;
634 }
635
max1363_monitor_mode_update(struct max1363_state * st,int enabled)636 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
637 {
638 u8 *tx_buf;
639 int ret, i = 3, j;
640 unsigned long numelements;
641 int len;
642 const long *modemask;
643
644 if (!enabled) {
645 /* transition to ring capture is not currently supported */
646 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
647 st->configbyte &= ~MAX1363_SCAN_MASK;
648 st->monitor_on = false;
649 return max1363_write_basic_config(st->client,
650 st->setupbyte,
651 st->configbyte);
652 }
653
654 /* Ensure we are in the relevant mode */
655 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
656 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
657 | MAX1363_SCAN_MASK
658 | MAX1363_SE_DE_MASK);
659 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
660 if ((st->mask_low | st->mask_high) & 0x0F) {
661 st->configbyte |= max1363_mode_table[s0to3].conf;
662 modemask = max1363_mode_table[s0to3].modemask;
663 } else if ((st->mask_low | st->mask_high) & 0x30) {
664 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
665 modemask = max1363_mode_table[d0m1to2m3].modemask;
666 } else {
667 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
668 modemask = max1363_mode_table[d1m0to3m2].modemask;
669 }
670 numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
671 len = 3 * numelements + 3;
672 tx_buf = kmalloc(len, GFP_KERNEL);
673 if (!tx_buf) {
674 ret = -ENOMEM;
675 goto error_ret;
676 }
677 tx_buf[0] = st->configbyte;
678 tx_buf[1] = st->setupbyte;
679 tx_buf[2] = (st->monitor_speed << 1);
680
681 /*
682 * So we need to do yet another bit of nefarious scan mode
683 * setup to match what we need.
684 */
685 for (j = 0; j < 8; j++)
686 if (test_bit(j, modemask)) {
687 /* Establish the mode is in the scan */
688 if (st->mask_low & (1 << j)) {
689 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
690 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
691 } else if (j < 4) {
692 tx_buf[i] = 0;
693 tx_buf[i + 1] = 0;
694 } else {
695 tx_buf[i] = 0x80;
696 tx_buf[i + 1] = 0;
697 }
698 if (st->mask_high & (1 << j)) {
699 tx_buf[i + 1] |=
700 (st->thresh_high[j] >> 8) & 0x0F;
701 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
702 } else if (j < 4) {
703 tx_buf[i + 1] |= 0x0F;
704 tx_buf[i + 2] = 0xFF;
705 } else {
706 tx_buf[i + 1] |= 0x07;
707 tx_buf[i + 2] = 0xFF;
708 }
709 i += 3;
710 }
711
712
713 ret = i2c_master_send(st->client, tx_buf, len);
714 if (ret < 0)
715 goto error_ret;
716 if (ret != len) {
717 ret = -EIO;
718 goto error_ret;
719 }
720
721 /*
722 * Now that we hopefully have sensible thresholds in place it is
723 * time to turn the interrupts on.
724 * It is unclear from the data sheet if this should be necessary
725 * (i.e. whether monitor mode setup is atomic) but it appears to
726 * be in practice.
727 */
728 tx_buf[0] = st->setupbyte;
729 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
730 ret = i2c_master_send(st->client, tx_buf, 2);
731 if (ret < 0)
732 goto error_ret;
733 if (ret != 2) {
734 ret = -EIO;
735 goto error_ret;
736 }
737 ret = 0;
738 st->monitor_on = true;
739 error_ret:
740
741 kfree(tx_buf);
742
743 return ret;
744 }
745
746 /*
747 * To keep this manageable we always use one of 3 scan modes.
748 * Scan 0...3, 0-1,2-3 and 1-0,3-2
749 */
750
__max1363_check_event_mask(int thismask,int checkmask)751 static inline int __max1363_check_event_mask(int thismask, int checkmask)
752 {
753 int ret = 0;
754 /* Is it unipolar */
755 if (thismask < 4) {
756 if (checkmask & ~0x0F) {
757 ret = -EBUSY;
758 goto error_ret;
759 }
760 } else if (thismask < 6) {
761 if (checkmask & ~0x30) {
762 ret = -EBUSY;
763 goto error_ret;
764 }
765 } else if (checkmask & ~0xC0)
766 ret = -EBUSY;
767 error_ret:
768 return ret;
769 }
770
max1363_write_event_config(struct iio_dev * indio_dev,u64 event_code,int state)771 static int max1363_write_event_config(struct iio_dev *indio_dev,
772 u64 event_code,
773 int state)
774 {
775 int ret = 0;
776 struct max1363_state *st = iio_priv(indio_dev);
777 u16 unifiedmask;
778 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
779
780 mutex_lock(&indio_dev->mlock);
781 unifiedmask = st->mask_low | st->mask_high;
782 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
783
784 if (state == 0)
785 st->mask_low &= ~(1 << number);
786 else {
787 ret = __max1363_check_event_mask((1 << number),
788 unifiedmask);
789 if (ret)
790 goto error_ret;
791 st->mask_low |= (1 << number);
792 }
793 } else {
794 if (state == 0)
795 st->mask_high &= ~(1 << number);
796 else {
797 ret = __max1363_check_event_mask((1 << number),
798 unifiedmask);
799 if (ret)
800 goto error_ret;
801 st->mask_high |= (1 << number);
802 }
803 }
804
805 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
806 error_ret:
807 mutex_unlock(&indio_dev->mlock);
808
809 return ret;
810 }
811
812 /*
813 * As with scan_elements, only certain sets of these can
814 * be combined.
815 */
816 static struct attribute *max1363_event_attributes[] = {
817 &iio_dev_attr_sampling_frequency.dev_attr.attr,
818 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
819 NULL,
820 };
821
822 static struct attribute_group max1363_event_attribute_group = {
823 .attrs = max1363_event_attributes,
824 .name = "events",
825 };
826
827 #define MAX1363_EVENT_FUNCS \
828
829
830 static const struct iio_info max1238_info = {
831 .read_raw = &max1363_read_raw,
832 .driver_module = THIS_MODULE,
833 };
834
835 static const struct iio_info max1363_info = {
836 .read_event_value = &max1363_read_thresh,
837 .write_event_value = &max1363_write_thresh,
838 .read_event_config = &max1363_read_event_config,
839 .write_event_config = &max1363_write_event_config,
840 .read_raw = &max1363_read_raw,
841 .update_scan_mode = &max1363_update_scan_mode,
842 .driver_module = THIS_MODULE,
843 .event_attrs = &max1363_event_attribute_group,
844 };
845
846 /* max1363 and max1368 tested - rest from data sheet */
847 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
848 [max1361] = {
849 .bits = 10,
850 .int_vref_mv = 2048,
851 .mode_list = max1363_mode_list,
852 .num_modes = ARRAY_SIZE(max1363_mode_list),
853 .default_mode = s0to3,
854 .channels = max1361_channels,
855 .num_channels = ARRAY_SIZE(max1361_channels),
856 .info = &max1363_info,
857 },
858 [max1362] = {
859 .bits = 10,
860 .int_vref_mv = 4096,
861 .mode_list = max1363_mode_list,
862 .num_modes = ARRAY_SIZE(max1363_mode_list),
863 .default_mode = s0to3,
864 .channels = max1361_channels,
865 .num_channels = ARRAY_SIZE(max1361_channels),
866 .info = &max1363_info,
867 },
868 [max1363] = {
869 .bits = 12,
870 .int_vref_mv = 2048,
871 .mode_list = max1363_mode_list,
872 .num_modes = ARRAY_SIZE(max1363_mode_list),
873 .default_mode = s0to3,
874 .channels = max1363_channels,
875 .num_channels = ARRAY_SIZE(max1363_channels),
876 .info = &max1363_info,
877 },
878 [max1364] = {
879 .bits = 12,
880 .int_vref_mv = 4096,
881 .mode_list = max1363_mode_list,
882 .num_modes = ARRAY_SIZE(max1363_mode_list),
883 .default_mode = s0to3,
884 .channels = max1363_channels,
885 .num_channels = ARRAY_SIZE(max1363_channels),
886 .info = &max1363_info,
887 },
888 [max1036] = {
889 .bits = 8,
890 .int_vref_mv = 4096,
891 .mode_list = max1236_mode_list,
892 .num_modes = ARRAY_SIZE(max1236_mode_list),
893 .default_mode = s0to3,
894 .info = &max1238_info,
895 .channels = max1036_channels,
896 .num_channels = ARRAY_SIZE(max1036_channels),
897 },
898 [max1037] = {
899 .bits = 8,
900 .int_vref_mv = 2048,
901 .mode_list = max1236_mode_list,
902 .num_modes = ARRAY_SIZE(max1236_mode_list),
903 .default_mode = s0to3,
904 .info = &max1238_info,
905 .channels = max1036_channels,
906 .num_channels = ARRAY_SIZE(max1036_channels),
907 },
908 [max1038] = {
909 .bits = 8,
910 .int_vref_mv = 4096,
911 .mode_list = max1238_mode_list,
912 .num_modes = ARRAY_SIZE(max1238_mode_list),
913 .default_mode = s0to11,
914 .info = &max1238_info,
915 .channels = max1038_channels,
916 .num_channels = ARRAY_SIZE(max1038_channels),
917 },
918 [max1039] = {
919 .bits = 8,
920 .int_vref_mv = 2048,
921 .mode_list = max1238_mode_list,
922 .num_modes = ARRAY_SIZE(max1238_mode_list),
923 .default_mode = s0to11,
924 .info = &max1238_info,
925 .channels = max1038_channels,
926 .num_channels = ARRAY_SIZE(max1038_channels),
927 },
928 [max1136] = {
929 .bits = 10,
930 .int_vref_mv = 4096,
931 .mode_list = max1236_mode_list,
932 .num_modes = ARRAY_SIZE(max1236_mode_list),
933 .default_mode = s0to3,
934 .info = &max1238_info,
935 .channels = max1136_channels,
936 .num_channels = ARRAY_SIZE(max1136_channels),
937 },
938 [max1137] = {
939 .bits = 10,
940 .int_vref_mv = 2048,
941 .mode_list = max1236_mode_list,
942 .num_modes = ARRAY_SIZE(max1236_mode_list),
943 .default_mode = s0to3,
944 .info = &max1238_info,
945 .channels = max1136_channels,
946 .num_channels = ARRAY_SIZE(max1136_channels),
947 },
948 [max1138] = {
949 .bits = 10,
950 .int_vref_mv = 4096,
951 .mode_list = max1238_mode_list,
952 .num_modes = ARRAY_SIZE(max1238_mode_list),
953 .default_mode = s0to11,
954 .info = &max1238_info,
955 .channels = max1138_channels,
956 .num_channels = ARRAY_SIZE(max1138_channels),
957 },
958 [max1139] = {
959 .bits = 10,
960 .int_vref_mv = 2048,
961 .mode_list = max1238_mode_list,
962 .num_modes = ARRAY_SIZE(max1238_mode_list),
963 .default_mode = s0to11,
964 .info = &max1238_info,
965 .channels = max1138_channels,
966 .num_channels = ARRAY_SIZE(max1138_channels),
967 },
968 [max1236] = {
969 .bits = 12,
970 .int_vref_mv = 4096,
971 .mode_list = max1236_mode_list,
972 .num_modes = ARRAY_SIZE(max1236_mode_list),
973 .default_mode = s0to3,
974 .info = &max1238_info,
975 .channels = max1236_channels,
976 .num_channels = ARRAY_SIZE(max1236_channels),
977 },
978 [max1237] = {
979 .bits = 12,
980 .int_vref_mv = 2048,
981 .mode_list = max1236_mode_list,
982 .num_modes = ARRAY_SIZE(max1236_mode_list),
983 .default_mode = s0to3,
984 .info = &max1238_info,
985 .channels = max1236_channels,
986 .num_channels = ARRAY_SIZE(max1236_channels),
987 },
988 [max1238] = {
989 .bits = 12,
990 .int_vref_mv = 4096,
991 .mode_list = max1238_mode_list,
992 .num_modes = ARRAY_SIZE(max1238_mode_list),
993 .default_mode = s0to11,
994 .info = &max1238_info,
995 .channels = max1238_channels,
996 .num_channels = ARRAY_SIZE(max1238_channels),
997 },
998 [max1239] = {
999 .bits = 12,
1000 .int_vref_mv = 2048,
1001 .mode_list = max1238_mode_list,
1002 .num_modes = ARRAY_SIZE(max1238_mode_list),
1003 .default_mode = s0to11,
1004 .info = &max1238_info,
1005 .channels = max1238_channels,
1006 .num_channels = ARRAY_SIZE(max1238_channels),
1007 },
1008 [max11600] = {
1009 .bits = 8,
1010 .int_vref_mv = 4096,
1011 .mode_list = max11607_mode_list,
1012 .num_modes = ARRAY_SIZE(max11607_mode_list),
1013 .default_mode = s0to3,
1014 .info = &max1238_info,
1015 .channels = max1036_channels,
1016 .num_channels = ARRAY_SIZE(max1036_channels),
1017 },
1018 [max11601] = {
1019 .bits = 8,
1020 .int_vref_mv = 2048,
1021 .mode_list = max11607_mode_list,
1022 .num_modes = ARRAY_SIZE(max11607_mode_list),
1023 .default_mode = s0to3,
1024 .info = &max1238_info,
1025 .channels = max1036_channels,
1026 .num_channels = ARRAY_SIZE(max1036_channels),
1027 },
1028 [max11602] = {
1029 .bits = 8,
1030 .int_vref_mv = 4096,
1031 .mode_list = max11608_mode_list,
1032 .num_modes = ARRAY_SIZE(max11608_mode_list),
1033 .default_mode = s0to7,
1034 .info = &max1238_info,
1035 .channels = max11602_channels,
1036 .num_channels = ARRAY_SIZE(max11602_channels),
1037 },
1038 [max11603] = {
1039 .bits = 8,
1040 .int_vref_mv = 2048,
1041 .mode_list = max11608_mode_list,
1042 .num_modes = ARRAY_SIZE(max11608_mode_list),
1043 .default_mode = s0to7,
1044 .info = &max1238_info,
1045 .channels = max11602_channels,
1046 .num_channels = ARRAY_SIZE(max11602_channels),
1047 },
1048 [max11604] = {
1049 .bits = 8,
1050 .int_vref_mv = 4098,
1051 .mode_list = max1238_mode_list,
1052 .num_modes = ARRAY_SIZE(max1238_mode_list),
1053 .default_mode = s0to11,
1054 .info = &max1238_info,
1055 .channels = max1238_channels,
1056 .num_channels = ARRAY_SIZE(max1238_channels),
1057 },
1058 [max11605] = {
1059 .bits = 8,
1060 .int_vref_mv = 2048,
1061 .mode_list = max1238_mode_list,
1062 .num_modes = ARRAY_SIZE(max1238_mode_list),
1063 .default_mode = s0to11,
1064 .info = &max1238_info,
1065 .channels = max1238_channels,
1066 .num_channels = ARRAY_SIZE(max1238_channels),
1067 },
1068 [max11606] = {
1069 .bits = 10,
1070 .int_vref_mv = 4096,
1071 .mode_list = max11607_mode_list,
1072 .num_modes = ARRAY_SIZE(max11607_mode_list),
1073 .default_mode = s0to3,
1074 .info = &max1238_info,
1075 .channels = max1136_channels,
1076 .num_channels = ARRAY_SIZE(max1136_channels),
1077 },
1078 [max11607] = {
1079 .bits = 10,
1080 .int_vref_mv = 2048,
1081 .mode_list = max11607_mode_list,
1082 .num_modes = ARRAY_SIZE(max11607_mode_list),
1083 .default_mode = s0to3,
1084 .info = &max1238_info,
1085 .channels = max1136_channels,
1086 .num_channels = ARRAY_SIZE(max1136_channels),
1087 },
1088 [max11608] = {
1089 .bits = 10,
1090 .int_vref_mv = 4096,
1091 .mode_list = max11608_mode_list,
1092 .num_modes = ARRAY_SIZE(max11608_mode_list),
1093 .default_mode = s0to7,
1094 .info = &max1238_info,
1095 .channels = max11608_channels,
1096 .num_channels = ARRAY_SIZE(max11608_channels),
1097 },
1098 [max11609] = {
1099 .bits = 10,
1100 .int_vref_mv = 2048,
1101 .mode_list = max11608_mode_list,
1102 .num_modes = ARRAY_SIZE(max11608_mode_list),
1103 .default_mode = s0to7,
1104 .info = &max1238_info,
1105 .channels = max11608_channels,
1106 .num_channels = ARRAY_SIZE(max11608_channels),
1107 },
1108 [max11610] = {
1109 .bits = 10,
1110 .int_vref_mv = 4098,
1111 .mode_list = max1238_mode_list,
1112 .num_modes = ARRAY_SIZE(max1238_mode_list),
1113 .default_mode = s0to11,
1114 .info = &max1238_info,
1115 .channels = max1238_channels,
1116 .num_channels = ARRAY_SIZE(max1238_channels),
1117 },
1118 [max11611] = {
1119 .bits = 10,
1120 .int_vref_mv = 2048,
1121 .mode_list = max1238_mode_list,
1122 .num_modes = ARRAY_SIZE(max1238_mode_list),
1123 .default_mode = s0to11,
1124 .info = &max1238_info,
1125 .channels = max1238_channels,
1126 .num_channels = ARRAY_SIZE(max1238_channels),
1127 },
1128 [max11612] = {
1129 .bits = 12,
1130 .int_vref_mv = 4096,
1131 .mode_list = max11607_mode_list,
1132 .num_modes = ARRAY_SIZE(max11607_mode_list),
1133 .default_mode = s0to3,
1134 .info = &max1238_info,
1135 .channels = max1363_channels,
1136 .num_channels = ARRAY_SIZE(max1363_channels),
1137 },
1138 [max11613] = {
1139 .bits = 12,
1140 .int_vref_mv = 2048,
1141 .mode_list = max11607_mode_list,
1142 .num_modes = ARRAY_SIZE(max11607_mode_list),
1143 .default_mode = s0to3,
1144 .info = &max1238_info,
1145 .channels = max1363_channels,
1146 .num_channels = ARRAY_SIZE(max1363_channels),
1147 },
1148 [max11614] = {
1149 .bits = 12,
1150 .int_vref_mv = 4096,
1151 .mode_list = max11608_mode_list,
1152 .num_modes = ARRAY_SIZE(max11608_mode_list),
1153 .default_mode = s0to7,
1154 .info = &max1238_info,
1155 .channels = max11614_channels,
1156 .num_channels = ARRAY_SIZE(max11614_channels),
1157 },
1158 [max11615] = {
1159 .bits = 12,
1160 .int_vref_mv = 2048,
1161 .mode_list = max11608_mode_list,
1162 .num_modes = ARRAY_SIZE(max11608_mode_list),
1163 .default_mode = s0to7,
1164 .info = &max1238_info,
1165 .channels = max11614_channels,
1166 .num_channels = ARRAY_SIZE(max11614_channels),
1167 },
1168 [max11616] = {
1169 .bits = 12,
1170 .int_vref_mv = 4098,
1171 .mode_list = max1238_mode_list,
1172 .num_modes = ARRAY_SIZE(max1238_mode_list),
1173 .default_mode = s0to11,
1174 .info = &max1238_info,
1175 .channels = max1238_channels,
1176 .num_channels = ARRAY_SIZE(max1238_channels),
1177 },
1178 [max11617] = {
1179 .bits = 12,
1180 .int_vref_mv = 2048,
1181 .mode_list = max1238_mode_list,
1182 .num_modes = ARRAY_SIZE(max1238_mode_list),
1183 .default_mode = s0to11,
1184 .info = &max1238_info,
1185 .channels = max1238_channels,
1186 .num_channels = ARRAY_SIZE(max1238_channels),
1187 },
1188 [max11644] = {
1189 .bits = 12,
1190 .int_vref_mv = 2048,
1191 .mode_list = max11644_mode_list,
1192 .num_modes = ARRAY_SIZE(max11644_mode_list),
1193 .default_mode = s0to1,
1194 .info = &max1238_info,
1195 .channels = max11644_channels,
1196 .num_channels = ARRAY_SIZE(max11644_channels),
1197 },
1198 [max11645] = {
1199 .bits = 12,
1200 .int_vref_mv = 4096,
1201 .mode_list = max11644_mode_list,
1202 .num_modes = ARRAY_SIZE(max11644_mode_list),
1203 .default_mode = s0to1,
1204 .info = &max1238_info,
1205 .channels = max11644_channels,
1206 .num_channels = ARRAY_SIZE(max11644_channels),
1207 },
1208 [max11646] = {
1209 .bits = 10,
1210 .int_vref_mv = 2048,
1211 .mode_list = max11644_mode_list,
1212 .num_modes = ARRAY_SIZE(max11644_mode_list),
1213 .default_mode = s0to1,
1214 .info = &max1238_info,
1215 .channels = max11646_channels,
1216 .num_channels = ARRAY_SIZE(max11646_channels),
1217 },
1218 [max11647] = {
1219 .bits = 10,
1220 .int_vref_mv = 4096,
1221 .mode_list = max11644_mode_list,
1222 .num_modes = ARRAY_SIZE(max11644_mode_list),
1223 .default_mode = s0to1,
1224 .info = &max1238_info,
1225 .channels = max11646_channels,
1226 .num_channels = ARRAY_SIZE(max11646_channels),
1227 },
1228 };
1229
1230
1231
max1363_initial_setup(struct max1363_state * st)1232 static int max1363_initial_setup(struct max1363_state *st)
1233 {
1234 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1235 | MAX1363_SETUP_POWER_UP_INT_REF
1236 | MAX1363_SETUP_INT_CLOCK
1237 | MAX1363_SETUP_UNIPOLAR
1238 | MAX1363_SETUP_NORESET;
1239
1240 /* Set scan mode writes the config anyway so wait until then*/
1241 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1242 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1243 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1244
1245 return max1363_set_scan_mode(st);
1246 }
1247
max1363_probe(struct i2c_client * client,const struct i2c_device_id * id)1248 static int __devinit max1363_probe(struct i2c_client *client,
1249 const struct i2c_device_id *id)
1250 {
1251 int ret, i;
1252 struct max1363_state *st;
1253 struct iio_dev *indio_dev;
1254 struct regulator *reg;
1255
1256 reg = regulator_get(&client->dev, "vcc");
1257 if (IS_ERR(reg)) {
1258 ret = PTR_ERR(reg);
1259 goto error_out;
1260 }
1261
1262 ret = regulator_enable(reg);
1263 if (ret)
1264 goto error_put_reg;
1265
1266 indio_dev = iio_allocate_device(sizeof(struct max1363_state));
1267 if (indio_dev == NULL) {
1268 ret = -ENOMEM;
1269 goto error_disable_reg;
1270 }
1271 st = iio_priv(indio_dev);
1272 st->reg = reg;
1273 /* this is only used for device removal purposes */
1274 i2c_set_clientdata(client, indio_dev);
1275
1276 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1277 st->client = client;
1278
1279 indio_dev->available_scan_masks
1280 = kzalloc(BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*sizeof(long)*
1281 (st->chip_info->num_modes + 1), GFP_KERNEL);
1282 if (!indio_dev->available_scan_masks) {
1283 ret = -ENOMEM;
1284 goto error_free_device;
1285 }
1286
1287 for (i = 0; i < st->chip_info->num_modes; i++)
1288 bitmap_copy(indio_dev->available_scan_masks +
1289 BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1290 max1363_mode_table[st->chip_info->mode_list[i]]
1291 .modemask, MAX1363_MAX_CHANNELS);
1292 /* Estabilish that the iio_dev is a child of the i2c device */
1293 indio_dev->dev.parent = &client->dev;
1294 indio_dev->name = id->name;
1295 indio_dev->channels = st->chip_info->channels;
1296 indio_dev->num_channels = st->chip_info->num_channels;
1297 indio_dev->info = st->chip_info->info;
1298 indio_dev->modes = INDIO_DIRECT_MODE;
1299 indio_dev->channels = st->chip_info->channels;
1300 indio_dev->num_channels = st->chip_info->num_channels;
1301 ret = max1363_initial_setup(st);
1302 if (ret < 0)
1303 goto error_free_available_scan_masks;
1304
1305 ret = max1363_register_ring_funcs_and_init(indio_dev);
1306 if (ret)
1307 goto error_free_available_scan_masks;
1308
1309 ret = iio_buffer_register(indio_dev,
1310 st->chip_info->channels,
1311 st->chip_info->num_channels);
1312 if (ret)
1313 goto error_cleanup_ring;
1314
1315 if (client->irq) {
1316 ret = request_threaded_irq(st->client->irq,
1317 NULL,
1318 &max1363_event_handler,
1319 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1320 "max1363_event",
1321 indio_dev);
1322
1323 if (ret)
1324 goto error_uninit_ring;
1325 }
1326
1327 ret = iio_device_register(indio_dev);
1328 if (ret < 0)
1329 goto error_free_irq;
1330
1331 return 0;
1332 error_free_irq:
1333 free_irq(st->client->irq, indio_dev);
1334 error_uninit_ring:
1335 iio_buffer_unregister(indio_dev);
1336 error_cleanup_ring:
1337 max1363_ring_cleanup(indio_dev);
1338 error_free_available_scan_masks:
1339 kfree(indio_dev->available_scan_masks);
1340 error_free_device:
1341 iio_free_device(indio_dev);
1342 error_disable_reg:
1343 regulator_disable(reg);
1344 error_put_reg:
1345 regulator_put(reg);
1346 error_out:
1347 return ret;
1348 }
1349
max1363_remove(struct i2c_client * client)1350 static int max1363_remove(struct i2c_client *client)
1351 {
1352 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1353 struct max1363_state *st = iio_priv(indio_dev);
1354 struct regulator *reg = st->reg;
1355
1356 iio_device_unregister(indio_dev);
1357 if (client->irq)
1358 free_irq(st->client->irq, indio_dev);
1359 iio_buffer_unregister(indio_dev);
1360 max1363_ring_cleanup(indio_dev);
1361 kfree(indio_dev->available_scan_masks);
1362 if (!IS_ERR(reg)) {
1363 regulator_disable(reg);
1364 regulator_put(reg);
1365 }
1366 iio_free_device(indio_dev);
1367
1368 return 0;
1369 }
1370
1371 static const struct i2c_device_id max1363_id[] = {
1372 { "max1361", max1361 },
1373 { "max1362", max1362 },
1374 { "max1363", max1363 },
1375 { "max1364", max1364 },
1376 { "max1036", max1036 },
1377 { "max1037", max1037 },
1378 { "max1038", max1038 },
1379 { "max1039", max1039 },
1380 { "max1136", max1136 },
1381 { "max1137", max1137 },
1382 { "max1138", max1138 },
1383 { "max1139", max1139 },
1384 { "max1236", max1236 },
1385 { "max1237", max1237 },
1386 { "max1238", max1238 },
1387 { "max1239", max1239 },
1388 { "max11600", max11600 },
1389 { "max11601", max11601 },
1390 { "max11602", max11602 },
1391 { "max11603", max11603 },
1392 { "max11604", max11604 },
1393 { "max11605", max11605 },
1394 { "max11606", max11606 },
1395 { "max11607", max11607 },
1396 { "max11608", max11608 },
1397 { "max11609", max11609 },
1398 { "max11610", max11610 },
1399 { "max11611", max11611 },
1400 { "max11612", max11612 },
1401 { "max11613", max11613 },
1402 { "max11614", max11614 },
1403 { "max11615", max11615 },
1404 { "max11616", max11616 },
1405 { "max11617", max11617 },
1406 {}
1407 };
1408
1409 MODULE_DEVICE_TABLE(i2c, max1363_id);
1410
1411 static struct i2c_driver max1363_driver = {
1412 .driver = {
1413 .name = "max1363",
1414 },
1415 .probe = max1363_probe,
1416 .remove = max1363_remove,
1417 .id_table = max1363_id,
1418 };
1419 module_i2c_driver(max1363_driver);
1420
1421 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
1422 MODULE_DESCRIPTION("Maxim 1363 ADC");
1423 MODULE_LICENSE("GPL v2");
1424