| /linux/drivers/ras/amd/atl/ |
| H A D | system.c | 73 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df3p5_get_masks_shifts()
85 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df4_get_masks_shifts()
102 u32 mask0, mask1, mask2; in df4_get_fabric_id_mask_registers() local
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| /linux/tools/testing/selftests/bpf/progs/ |
| H A D | cpumask_success.c | 100 struct bpf_cpumask *mask1, *mask2, *mask3, *mask4; in create_cpumask_set() local
254 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
318 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
365 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
407 struct bpf_cpumask *mask1, *mask2, *dst1, *dst2; in BPF_PROG() local
754 struct bpf_cpumask *mask1, *mask2; in BPF_PROG() local
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_helper.c | 287 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2()
297 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3()
309 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4()
323 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5()
339 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6()
357 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get7()
377 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get8()
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| /linux/arch/mips/sgi-ip22/ |
| H A D | ip22-int.c | 114 u8 mask2; in indy_local0_irqdispatch() local
136 u8 mask2; in indy_local1_irqdispatch() local
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| H A D | irq_service_dcn21.c | 186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
| H A D | irq_service_dcn314.c | 183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| H A D | irq_service_dcn302.c | 178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| H A D | irq_service_dcn31.c | 181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| H A D | irq_service_dcn30.c | 193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/ |
| H A D | irq_service_dcn401.c | 172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
| H A D | irq_service_dcn32.c | 192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
| H A D | irq_service_dcn315.c | 188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/ |
| H A D | irq_service_dcn35.c | 180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/ |
| H A D | irq_service_dcn36.c | 158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/ |
| H A D | irq_service_dcn351.c | 159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
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| /linux/include/linux/ |
| H A D | cpumask.h | 409 #define for_each_cpu_and(cpu, mask1, mask2) \ argument
427 #define for_each_cpu_andnot(cpu, mask1, mask2) \ argument
444 #define for_each_cpu_or(cpu, mask1, mask2) \ argument
492 const struct cpumask *mask2, in cpumask_any_and_but()
519 const struct cpumask *mask2, in cpumask_any_andnot_but()
952 #define cpumask_any_and(mask1, mask2) cpumask_first_and((mask1), (mask2)) argument
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| /linux/drivers/net/hamradio/ |
| H A D | hdlcdrv.c | 159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
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| /linux/lib/tests/ |
| H A D | cpumask_kunit.c | 26 #define EXPECT_FOR_EACH_CPU_OP_EQ(test, op, mask1, mask2) \ argument
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| /linux/drivers/net/wireless/ath/ath9k/ |
| H A D | ar9002_mac.c | 36 u32 mask2 = 0; in ar9002_hw_get_isr() local
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| H A D | irq_service_dce120.c | 76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/fs/affs/ |
| H A D | bitmap.c | 122 u32 blk, bmap, bit, mask, mask2, tmp; in affs_alloc_block() local
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| H A D | irq_service_dcn303.c | 121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| H A D | irq_service_dcn10.c | 173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| H A D | irq_service_dcn20.c | 176 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| H A D | irq_service_dcn201.c | 125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
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