1 /*
2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
3 *
4 * Copyright (c) 2020 Western Digital
5 *
6 * Provides a board compatible with the OpenTitan FPGA platform:
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/cutils.h"
23 #include "hw/riscv/opentitan.h"
24 #include "qapi/error.h"
25 #include "qemu/error-report.h"
26 #include "hw/boards.h"
27 #include "hw/misc/unimp.h"
28 #include "hw/riscv/boot.h"
29 #include "qemu/units.h"
30 #include "system/system.h"
31 #include "system/address-spaces.h"
32
33 /*
34 * This version of the OpenTitan machine currently supports
35 * OpenTitan RTL version:
36 * <lowRISC/opentitan@565e4af39760a123c59a184aa2f5812a961fde47>
37 *
38 * MMIO mapping as per (specified commit):
39 * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h
40 */
41 static const MemMapEntry ibex_memmap[] = {
42 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
43 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
44 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
45 [IBEX_DEV_UART] = { 0x40000000, 0x40 },
46 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
47 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
48 [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
49 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
50 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
51 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
52 [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 },
53 [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 },
54 [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 },
55 [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 },
56 [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 },
57 [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 },
58 [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 },
59 [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 },
60 [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 },
61 [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 },
62 [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 },
63 [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 },
64 [IBEX_DEV_AES] = { 0x41100000, 0x100 },
65 [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 },
66 [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 },
67 [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 },
68 [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 },
69 [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 },
70 [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 },
71 [IBEX_DEV_EDNO] = { 0x41170000, 0x80 },
72 [IBEX_DEV_EDN1] = { 0x41180000, 0x80 },
73 [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 },
74 [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 },
75 [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 },
76 [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 },
77 };
78
opentitan_machine_init(MachineState * machine)79 static void opentitan_machine_init(MachineState *machine)
80 {
81 MachineClass *mc = MACHINE_GET_CLASS(machine);
82 OpenTitanState *s = OPENTITAN_MACHINE(machine);
83 const MemMapEntry *memmap = ibex_memmap;
84 MemoryRegion *sys_mem = get_system_memory();
85 RISCVBootInfo boot_info;
86
87 if (machine->ram_size != mc->default_ram_size) {
88 char *sz = size_to_str(mc->default_ram_size);
89 error_report("Invalid RAM size, should be %s", sz);
90 g_free(sz);
91 exit(EXIT_FAILURE);
92 }
93
94 /* Initialize SoC */
95 object_initialize_child(OBJECT(machine), "soc", &s->soc,
96 TYPE_RISCV_IBEX_SOC);
97 qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
98
99 memory_region_add_subregion(sys_mem,
100 memmap[IBEX_DEV_RAM].base, machine->ram);
101
102 if (machine->firmware) {
103 hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base;
104 riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL);
105 }
106
107 riscv_boot_info_init(&boot_info, &s->soc.cpus);
108 if (machine->kernel_filename) {
109 riscv_load_kernel(machine, &boot_info,
110 memmap[IBEX_DEV_RAM].base,
111 false, NULL);
112 }
113 }
114
opentitan_machine_class_init(ObjectClass * oc,const void * data)115 static void opentitan_machine_class_init(ObjectClass *oc, const void *data)
116 {
117 MachineClass *mc = MACHINE_CLASS(oc);
118
119 mc->desc = "RISC-V Board compatible with OpenTitan";
120 mc->init = opentitan_machine_init;
121 mc->max_cpus = 1;
122 mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
123 mc->default_ram_id = "riscv.lowrisc.ibex.ram";
124 mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size;
125 }
126
lowrisc_ibex_soc_init(Object * obj)127 static void lowrisc_ibex_soc_init(Object *obj)
128 {
129 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
130
131 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
132
133 object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);
134
135 object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
136
137 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
138
139 for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
140 object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
141 TYPE_IBEX_SPI_HOST);
142 }
143 }
144
lowrisc_ibex_soc_realize(DeviceState * dev_soc,Error ** errp)145 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
146 {
147 const MemMapEntry *memmap = ibex_memmap;
148 DeviceState *dev;
149 SysBusDevice *busdev;
150 MachineState *ms = MACHINE(qdev_get_machine());
151 LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
152 MemoryRegion *sys_mem = get_system_memory();
153 int i;
154
155 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
156 &error_abort);
157 object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
158 &error_abort);
159 object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
160 &error_abort);
161 sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
162
163 /* Boot ROM */
164 memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
165 memmap[IBEX_DEV_ROM].size, &error_fatal);
166 memory_region_add_subregion(sys_mem,
167 memmap[IBEX_DEV_ROM].base, &s->rom);
168
169 /* Flash memory */
170 memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
171 memmap[IBEX_DEV_FLASH].size, &error_fatal);
172 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
173 "riscv.lowrisc.ibex.flash_virtual", &s->flash_mem, 0,
174 memmap[IBEX_DEV_FLASH_VIRTUAL].size);
175 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
176 &s->flash_mem);
177 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH_VIRTUAL].base,
178 &s->flash_alias);
179
180 /* PLIC */
181 qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
182 qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
183 qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
184 qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
185 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
186 qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
187 qdev_prop_set_uint32(DEVICE(&s->plic), "context-base", 0x200000);
188 qdev_prop_set_uint32(DEVICE(&s->plic), "context-stride", 8);
189 qdev_prop_set_uint32(DEVICE(&s->plic), "aperture-size", memmap[IBEX_DEV_PLIC].size);
190
191 if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
192 return;
193 }
194 sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
195
196 for (i = 0; i < ms->smp.cpus; i++) {
197 CPUState *cpu = qemu_get_cpu(i);
198
199 qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
200 qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
201 }
202
203 /* UART */
204 qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
205 if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
206 return;
207 }
208 sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
209 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
210 0, qdev_get_gpio_in(DEVICE(&s->plic),
211 IBEX_UART0_TX_WATERMARK_IRQ));
212 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
213 1, qdev_get_gpio_in(DEVICE(&s->plic),
214 IBEX_UART0_RX_WATERMARK_IRQ));
215 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
216 2, qdev_get_gpio_in(DEVICE(&s->plic),
217 IBEX_UART0_TX_EMPTY_IRQ));
218 sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
219 3, qdev_get_gpio_in(DEVICE(&s->plic),
220 IBEX_UART0_RX_OVERFLOW_IRQ));
221
222 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer), errp)) {
223 return;
224 }
225 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, memmap[IBEX_DEV_TIMER].base);
226 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer),
227 0, qdev_get_gpio_in(DEVICE(&s->plic),
228 IBEX_TIMER_TIMEREXPIRED0_0));
229 qdev_connect_gpio_out(DEVICE(&s->timer), 0,
230 qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
231 IRQ_M_TIMER));
232
233 /* SPI-Hosts */
234 for (i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
235 dev = DEVICE(&(s->spi_host[i]));
236 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
237 return;
238 }
239 busdev = SYS_BUS_DEVICE(dev);
240 sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
241
242 switch (i) {
243 case OPENTITAN_SPI_HOST0:
244 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
245 IBEX_SPI_HOST0_ERR_IRQ));
246 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
247 IBEX_SPI_HOST0_SPI_EVENT_IRQ));
248 break;
249 case OPENTITAN_SPI_HOST1:
250 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
251 IBEX_SPI_HOST1_ERR_IRQ));
252 sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
253 IBEX_SPI_HOST1_SPI_EVENT_IRQ));
254 break;
255 }
256 }
257
258 create_unimplemented_device("riscv.lowrisc.ibex.gpio",
259 memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
260 create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
261 memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
262 create_unimplemented_device("riscv.lowrisc.ibex.i2c",
263 memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
264 create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
265 memmap[IBEX_DEV_PATTGEN].base, memmap[IBEX_DEV_PATTGEN].size);
266 create_unimplemented_device("riscv.lowrisc.ibex.sensor_ctrl",
267 memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
268 create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
269 memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
270 create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
271 memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
272 create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
273 memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
274 create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
275 memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
276 create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
277 memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
278 create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
279 memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
280 create_unimplemented_device("riscv.lowrisc.ibex.aon_timer",
281 memmap[IBEX_DEV_AON_TIMER].base, memmap[IBEX_DEV_AON_TIMER].size);
282 create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
283 memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
284 create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
285 memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
286 create_unimplemented_device("riscv.lowrisc.ibex.aes",
287 memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
288 create_unimplemented_device("riscv.lowrisc.ibex.hmac",
289 memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
290 create_unimplemented_device("riscv.lowrisc.ibex.kmac",
291 memmap[IBEX_DEV_KMAC].base, memmap[IBEX_DEV_KMAC].size);
292 create_unimplemented_device("riscv.lowrisc.ibex.keymgr",
293 memmap[IBEX_DEV_KEYMGR].base, memmap[IBEX_DEV_KEYMGR].size);
294 create_unimplemented_device("riscv.lowrisc.ibex.csrng",
295 memmap[IBEX_DEV_CSRNG].base, memmap[IBEX_DEV_CSRNG].size);
296 create_unimplemented_device("riscv.lowrisc.ibex.entropy",
297 memmap[IBEX_DEV_ENTROPY].base, memmap[IBEX_DEV_ENTROPY].size);
298 create_unimplemented_device("riscv.lowrisc.ibex.edn0",
299 memmap[IBEX_DEV_EDNO].base, memmap[IBEX_DEV_EDNO].size);
300 create_unimplemented_device("riscv.lowrisc.ibex.edn1",
301 memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size);
302 create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
303 memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
304 create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl",
305 memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size);
306 create_unimplemented_device("riscv.lowrisc.ibex.otbn",
307 memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size);
308 create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg",
309 memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size);
310 }
311
312 static const Property lowrisc_ibex_soc_props[] = {
313 DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
314 };
315
lowrisc_ibex_soc_class_init(ObjectClass * oc,const void * data)316 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, const void *data)
317 {
318 DeviceClass *dc = DEVICE_CLASS(oc);
319
320 device_class_set_props(dc, lowrisc_ibex_soc_props);
321 dc->realize = lowrisc_ibex_soc_realize;
322 /* Reason: Uses serial_hds in realize function, thus can't be used twice */
323 dc->user_creatable = false;
324 }
325
326 static const TypeInfo open_titan_types[] = {
327 {
328 .name = TYPE_RISCV_IBEX_SOC,
329 .parent = TYPE_DEVICE,
330 .instance_size = sizeof(LowRISCIbexSoCState),
331 .instance_init = lowrisc_ibex_soc_init,
332 .class_init = lowrisc_ibex_soc_class_init,
333 }, {
334 .name = TYPE_OPENTITAN_MACHINE,
335 .parent = TYPE_MACHINE,
336 .instance_size = sizeof(OpenTitanState),
337 .class_init = opentitan_machine_class_init,
338 }
339 };
340
341 DEFINE_TYPES(open_titan_types)
342