1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Loongson extioi interrupt controller emulation
4 * Copyright (C) 2024 Loongson Technology Corporation Limited
5 */
6 #include "qemu/osdep.h"
7 #include "qemu/error-report.h"
8 #include "qemu/module.h"
9 #include "qapi/error.h"
10 #include "hw/qdev-properties.h"
11 #include "hw/intc/loongarch_extioi_common.h"
12 #include "migration/vmstate.h"
13 #include "target/loongarch/cpu.h"
14
loongarch_extioi_get_cpu(LoongArchExtIOICommonState * s,DeviceState * dev)15 static ExtIOICore *loongarch_extioi_get_cpu(LoongArchExtIOICommonState *s,
16 DeviceState *dev)
17 {
18 CPUClass *k = CPU_GET_CLASS(dev);
19 uint64_t arch_id = k->get_arch_id(CPU(dev));
20 int i;
21
22 for (i = 0; i < s->num_cpu; i++) {
23 if (s->cpu[i].arch_id == arch_id) {
24 return &s->cpu[i];
25 }
26 }
27
28 return NULL;
29 }
30
loongarch_extioi_cpu_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)31 static void loongarch_extioi_cpu_plug(HotplugHandler *hotplug_dev,
32 DeviceState *dev, Error **errp)
33 {
34 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(hotplug_dev);
35 Object *obj = OBJECT(dev);
36 ExtIOICore *core;
37 int pin, index;
38
39 if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) {
40 warn_report("LoongArch extioi: Invalid %s device type",
41 object_get_typename(obj));
42 return;
43 }
44
45 core = loongarch_extioi_get_cpu(s, dev);
46 if (!core) {
47 return;
48 }
49
50 core->cpu = CPU(dev);
51 index = core - s->cpu;
52
53 /*
54 * connect extioi irq to the cpu irq
55 * cpu_pin[LS3A_INTC_IP + 2 : 2] <= intc_pin[LS3A_INTC_IP : 0]
56 */
57 for (pin = 0; pin < LS3A_INTC_IP; pin++) {
58 qdev_connect_gpio_out(DEVICE(s), index * LS3A_INTC_IP + pin,
59 qdev_get_gpio_in(dev, pin + 2));
60 }
61 }
62
loongarch_extioi_cpu_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)63 static void loongarch_extioi_cpu_unplug(HotplugHandler *hotplug_dev,
64 DeviceState *dev, Error **errp)
65 {
66 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(hotplug_dev);
67 Object *obj = OBJECT(dev);
68 ExtIOICore *core;
69
70 if (!object_dynamic_cast(obj, TYPE_LOONGARCH_CPU)) {
71 warn_report("LoongArch extioi: Invalid %s device type",
72 object_get_typename(obj));
73 return;
74 }
75
76 core = loongarch_extioi_get_cpu(s, dev);
77 if (!core) {
78 return;
79 }
80
81 core->cpu = NULL;
82 }
83
loongarch_extioi_common_realize(DeviceState * dev,Error ** errp)84 static void loongarch_extioi_common_realize(DeviceState *dev, Error **errp)
85 {
86 LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)dev;
87 MachineState *machine = MACHINE(qdev_get_machine());
88 MachineClass *mc = MACHINE_GET_CLASS(machine);
89 const CPUArchIdList *id_list;
90 int i, pin;
91
92 assert(mc->possible_cpu_arch_ids);
93 id_list = mc->possible_cpu_arch_ids(machine);
94 s->num_cpu = id_list->len;
95 s->cpu = g_new0(ExtIOICore, s->num_cpu);
96 if (s->cpu == NULL) {
97 error_setg(errp, "Memory allocation for ExtIOICore faile");
98 return;
99 }
100
101 for (i = 0; i < s->num_cpu; i++) {
102 s->cpu[i].arch_id = id_list->cpus[i].arch_id;
103 s->cpu[i].cpu = CPU(id_list->cpus[i].cpu);
104
105 for (pin = 0; pin < LS3A_INTC_IP; pin++) {
106 qdev_init_gpio_out(dev, &s->cpu[i].parent_irq[pin], 1);
107 }
108 }
109 }
110
loongarch_extioi_common_reset_hold(Object * obj,ResetType type)111 static void loongarch_extioi_common_reset_hold(Object *obj, ResetType type)
112 {
113 LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_GET_CLASS(obj);
114 LoongArchExtIOICommonState *s = LOONGARCH_EXTIOI_COMMON(obj);
115 ExtIOICore *core;
116 int i;
117
118 if (lecc->parent_phases.hold) {
119 lecc->parent_phases.hold(obj, type);
120 }
121
122 /* Clear HW registers for the board */
123 memset(s->nodetype, 0, sizeof(s->nodetype));
124 memset(s->bounce, 0, sizeof(s->bounce));
125 memset(s->isr, 0, sizeof(s->isr));
126 memset(s->enable, 0, sizeof(s->enable));
127 memset(s->ipmap, 0, sizeof(s->ipmap));
128 memset(s->coremap, 0, sizeof(s->coremap));
129 memset(s->sw_pending, 0, sizeof(s->sw_pending));
130 memset(s->sw_ipmap, 0, sizeof(s->sw_ipmap));
131 memset(s->sw_coremap, 0, sizeof(s->sw_coremap));
132
133 for (i = 0; i < s->num_cpu; i++) {
134 core = s->cpu + i;
135 /* EXTIOI with targeted CPU available however not present */
136 if (!core->cpu) {
137 continue;
138 }
139
140 /* Clear HW registers for CPUs */
141 memset(core->coreisr, 0, sizeof(core->coreisr));
142 memset(core->sw_isr, 0, sizeof(core->sw_isr));
143 }
144
145 s->status = 0;
146 }
147
loongarch_extioi_common_pre_save(void * opaque)148 static int loongarch_extioi_common_pre_save(void *opaque)
149 {
150 LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)opaque;
151 LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_GET_CLASS(s);
152
153 if (lecc->pre_save) {
154 return lecc->pre_save(s);
155 }
156
157 return 0;
158 }
159
loongarch_extioi_common_post_load(void * opaque,int version_id)160 static int loongarch_extioi_common_post_load(void *opaque, int version_id)
161 {
162 LoongArchExtIOICommonState *s = (LoongArchExtIOICommonState *)opaque;
163 LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_GET_CLASS(s);
164
165 if (lecc->post_load) {
166 return lecc->post_load(s, version_id);
167 }
168
169 return 0;
170 }
171
172 static const VMStateDescription vmstate_extioi_core = {
173 .name = "extioi-core",
174 .version_id = 1,
175 .minimum_version_id = 1,
176 .fields = (const VMStateField[]) {
177 VMSTATE_UINT32_ARRAY(coreisr, ExtIOICore, EXTIOI_IRQS_GROUP_COUNT),
178 VMSTATE_END_OF_LIST()
179 }
180 };
181
182 static const VMStateDescription vmstate_loongarch_extioi = {
183 .name = "loongarch.extioi",
184 .version_id = 3,
185 .minimum_version_id = 3,
186 .pre_save = loongarch_extioi_common_pre_save,
187 .post_load = loongarch_extioi_common_post_load,
188 .fields = (const VMStateField[]) {
189 VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOICommonState,
190 EXTIOI_IRQS_GROUP_COUNT),
191 VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOICommonState,
192 EXTIOI_IRQS_NODETYPE_COUNT / 2),
193 VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOICommonState,
194 EXTIOI_IRQS / 32),
195 VMSTATE_UINT32_ARRAY(isr, LoongArchExtIOICommonState,
196 EXTIOI_IRQS / 32),
197 VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOICommonState,
198 EXTIOI_IRQS_IPMAP_SIZE / 4),
199 VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOICommonState,
200 EXTIOI_IRQS / 4),
201 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, LoongArchExtIOICommonState,
202 num_cpu, vmstate_extioi_core, ExtIOICore),
203 VMSTATE_UINT32(features, LoongArchExtIOICommonState),
204 VMSTATE_UINT32(status, LoongArchExtIOICommonState),
205 VMSTATE_END_OF_LIST()
206 }
207 };
208
209 static const Property extioi_properties[] = {
210 DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState,
211 features, EXTIOI_HAS_VIRT_EXTENSION, 0),
212 };
213
loongarch_extioi_common_class_init(ObjectClass * klass,const void * data)214 static void loongarch_extioi_common_class_init(ObjectClass *klass,
215 const void *data)
216 {
217 DeviceClass *dc = DEVICE_CLASS(klass);
218 LoongArchExtIOICommonClass *lecc = LOONGARCH_EXTIOI_COMMON_CLASS(klass);
219 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
220 ResettableClass *rc = RESETTABLE_CLASS(klass);
221
222 device_class_set_parent_realize(dc, loongarch_extioi_common_realize,
223 &lecc->parent_realize);
224 resettable_class_set_parent_phases(rc, NULL,
225 loongarch_extioi_common_reset_hold,
226 NULL, &lecc->parent_phases);
227 device_class_set_props(dc, extioi_properties);
228 dc->vmsd = &vmstate_loongarch_extioi;
229 hc->plug = loongarch_extioi_cpu_plug;
230 hc->unplug = loongarch_extioi_cpu_unplug;
231 }
232
233 static const TypeInfo loongarch_extioi_common_types[] = {
234 {
235 .name = TYPE_LOONGARCH_EXTIOI_COMMON,
236 .parent = TYPE_SYS_BUS_DEVICE,
237 .instance_size = sizeof(LoongArchExtIOICommonState),
238 .class_size = sizeof(LoongArchExtIOICommonClass),
239 .class_init = loongarch_extioi_common_class_init,
240 .interfaces = (const InterfaceInfo[]) {
241 { TYPE_HOTPLUG_HANDLER },
242 { }
243 },
244 .abstract = true,
245 }
246 };
247
248 DEFINE_TYPES(loongarch_extioi_common_types)
249