xref: /linux/include/linux/dpll.h (revision 15ed91aa84ea7bacef3c24286d5136055b4335a8) !
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  Copyright (c) 2023 Meta Platforms, Inc. and affiliates
4  *  Copyright (c) 2023 Intel and affiliates
5  */
6 
7 #ifndef __DPLL_H__
8 #define __DPLL_H__
9 
10 #include <uapi/linux/dpll.h>
11 #include <linux/device.h>
12 #include <linux/netlink.h>
13 #include <linux/netdevice.h>
14 #include <linux/notifier.h>
15 #include <linux/rtnetlink.h>
16 
17 struct dpll_device;
18 struct dpll_pin;
19 struct dpll_pin_esync;
20 struct fwnode_handle;
21 struct ref_tracker;
22 
23 struct dpll_device_ops {
24 	int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,
25 			enum dpll_mode *mode, struct netlink_ext_ack *extack);
26 	int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,
27 			enum dpll_mode mode, struct netlink_ext_ack *extack);
28 	int (*supported_modes_get)(const struct dpll_device *dpll,
29 				   void *dpll_priv, unsigned long *modes,
30 				   struct netlink_ext_ack *extack);
31 	int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,
32 			       enum dpll_lock_status *status,
33 			       enum dpll_lock_status_error *status_error,
34 			       struct netlink_ext_ack *extack);
35 	int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,
36 			s32 *temp, struct netlink_ext_ack *extack);
37 	int (*clock_quality_level_get)(const struct dpll_device *dpll,
38 				       void *dpll_priv,
39 				       unsigned long *qls,
40 				       struct netlink_ext_ack *extack);
41 	int (*phase_offset_monitor_set)(const struct dpll_device *dpll,
42 					void *dpll_priv,
43 					enum dpll_feature_state state,
44 					struct netlink_ext_ack *extack);
45 	int (*phase_offset_monitor_get)(const struct dpll_device *dpll,
46 					void *dpll_priv,
47 					enum dpll_feature_state *state,
48 					struct netlink_ext_ack *extack);
49 	int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,
50 					   void *dpll_priv, u32 factor,
51 					   struct netlink_ext_ack *extack);
52 	int (*phase_offset_avg_factor_get)(const struct dpll_device *dpll,
53 					   void *dpll_priv, u32 *factor,
54 					   struct netlink_ext_ack *extack);
55 	int (*freq_monitor_set)(const struct dpll_device *dpll, void *dpll_priv,
56 				enum dpll_feature_state state,
57 				struct netlink_ext_ack *extack);
58 	int (*freq_monitor_get)(const struct dpll_device *dpll, void *dpll_priv,
59 				enum dpll_feature_state *state,
60 				struct netlink_ext_ack *extack);
61 };
62 
63 struct dpll_pin_ops {
64 	int (*frequency_set)(const struct dpll_pin *pin, void *pin_priv,
65 			     const struct dpll_device *dpll, void *dpll_priv,
66 			     const u64 frequency,
67 			     struct netlink_ext_ack *extack);
68 	int (*frequency_get)(const struct dpll_pin *pin, void *pin_priv,
69 			     const struct dpll_device *dpll, void *dpll_priv,
70 			     u64 *frequency, struct netlink_ext_ack *extack);
71 	int (*direction_set)(const struct dpll_pin *pin, void *pin_priv,
72 			     const struct dpll_device *dpll, void *dpll_priv,
73 			     const enum dpll_pin_direction direction,
74 			     struct netlink_ext_ack *extack);
75 	int (*direction_get)(const struct dpll_pin *pin, void *pin_priv,
76 			     const struct dpll_device *dpll, void *dpll_priv,
77 			     enum dpll_pin_direction *direction,
78 			     struct netlink_ext_ack *extack);
79 	int (*state_on_pin_get)(const struct dpll_pin *pin, void *pin_priv,
80 				const struct dpll_pin *parent_pin,
81 				void *parent_pin_priv,
82 				enum dpll_pin_state *state,
83 				struct netlink_ext_ack *extack);
84 	int (*state_on_dpll_get)(const struct dpll_pin *pin, void *pin_priv,
85 				 const struct dpll_device *dpll,
86 				 void *dpll_priv, enum dpll_pin_state *state,
87 				 struct netlink_ext_ack *extack);
88 	int (*state_on_pin_set)(const struct dpll_pin *pin, void *pin_priv,
89 				const struct dpll_pin *parent_pin,
90 				void *parent_pin_priv,
91 				const enum dpll_pin_state state,
92 				struct netlink_ext_ack *extack);
93 	int (*state_on_dpll_set)(const struct dpll_pin *pin, void *pin_priv,
94 				 const struct dpll_device *dpll,
95 				 void *dpll_priv,
96 				 const enum dpll_pin_state state,
97 				 struct netlink_ext_ack *extack);
98 	int (*prio_get)(const struct dpll_pin *pin,  void *pin_priv,
99 			const struct dpll_device *dpll,  void *dpll_priv,
100 			u32 *prio, struct netlink_ext_ack *extack);
101 	int (*prio_set)(const struct dpll_pin *pin, void *pin_priv,
102 			const struct dpll_device *dpll, void *dpll_priv,
103 			const u32 prio, struct netlink_ext_ack *extack);
104 	int (*phase_offset_get)(const struct dpll_pin *pin, void *pin_priv,
105 				const struct dpll_device *dpll, void *dpll_priv,
106 				s64 *phase_offset,
107 				struct netlink_ext_ack *extack);
108 	int (*phase_adjust_get)(const struct dpll_pin *pin, void *pin_priv,
109 				const struct dpll_device *dpll, void *dpll_priv,
110 				s32 *phase_adjust,
111 				struct netlink_ext_ack *extack);
112 	int (*phase_adjust_set)(const struct dpll_pin *pin, void *pin_priv,
113 				const struct dpll_device *dpll, void *dpll_priv,
114 				const s32 phase_adjust,
115 				struct netlink_ext_ack *extack);
116 	int (*ffo_get)(const struct dpll_pin *pin, void *pin_priv,
117 		       const struct dpll_device *dpll, void *dpll_priv,
118 		       s64 *ffo, struct netlink_ext_ack *extack);
119 	int (*measured_freq_get)(const struct dpll_pin *pin, void *pin_priv,
120 				 const struct dpll_device *dpll,
121 				 void *dpll_priv, u64 *measured_freq,
122 				 struct netlink_ext_ack *extack);
123 	int (*esync_set)(const struct dpll_pin *pin, void *pin_priv,
124 			 const struct dpll_device *dpll, void *dpll_priv,
125 			 u64 freq, struct netlink_ext_ack *extack);
126 	int (*esync_get)(const struct dpll_pin *pin, void *pin_priv,
127 			 const struct dpll_device *dpll, void *dpll_priv,
128 			 struct dpll_pin_esync *esync,
129 			 struct netlink_ext_ack *extack);
130 	int (*ref_sync_set)(const struct dpll_pin *pin, void *pin_priv,
131 			    const struct dpll_pin *ref_sync_pin,
132 			    void *ref_sync_pin_priv,
133 			    const enum dpll_pin_state state,
134 			    struct netlink_ext_ack *extack);
135 	int (*ref_sync_get)(const struct dpll_pin *pin, void *pin_priv,
136 			    const struct dpll_pin *ref_sync_pin,
137 			    void *ref_sync_pin_priv,
138 			    enum dpll_pin_state *state,
139 			    struct netlink_ext_ack *extack);
140 };
141 
142 struct dpll_pin_frequency {
143 	u64 min;
144 	u64 max;
145 };
146 
147 #define DPLL_PIN_FREQUENCY_RANGE(_min, _max)	\
148 	{					\
149 		.min = _min,			\
150 		.max = _max,			\
151 	}
152 
153 #define DPLL_PIN_FREQUENCY(_val) DPLL_PIN_FREQUENCY_RANGE(_val, _val)
154 #define DPLL_PIN_FREQUENCY_1PPS \
155 	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_1_HZ)
156 #define DPLL_PIN_FREQUENCY_10MHZ \
157 	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_MHZ)
158 #define DPLL_PIN_FREQUENCY_IRIG_B \
159 	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_10_KHZ)
160 #define DPLL_PIN_FREQUENCY_DCF77 \
161 	DPLL_PIN_FREQUENCY(DPLL_PIN_FREQUENCY_77_5_KHZ)
162 
163 struct dpll_pin_phase_adjust_range {
164 	s32 min;
165 	s32 max;
166 };
167 
168 struct dpll_pin_esync {
169 	u64 freq;
170 	const struct dpll_pin_frequency *range;
171 	u8 range_num;
172 	u8 pulse;
173 };
174 
175 struct dpll_pin_properties {
176 	const char *board_label;
177 	const char *panel_label;
178 	const char *package_label;
179 	enum dpll_pin_type type;
180 	unsigned long capabilities;
181 	u32 freq_supported_num;
182 	struct dpll_pin_frequency *freq_supported;
183 	struct dpll_pin_phase_adjust_range phase_range;
184 	u32 phase_gran;
185 };
186 
187 #ifdef CONFIG_DPLL_REFCNT_TRACKER
188 typedef struct ref_tracker *dpll_tracker;
189 #else
190 typedef struct {} dpll_tracker;
191 #endif
192 
193 #define DPLL_DEVICE_CREATED	1
194 #define DPLL_DEVICE_DELETED	2
195 #define DPLL_DEVICE_CHANGED	3
196 #define DPLL_PIN_CREATED	4
197 #define DPLL_PIN_DELETED	5
198 #define DPLL_PIN_CHANGED	6
199 
200 struct dpll_device_notifier_info {
201 	struct dpll_device *dpll;
202 	u32 id;
203 	u32 idx;
204 	u64 clock_id;
205 	enum dpll_type type;
206 };
207 
208 struct dpll_pin_notifier_info {
209 	struct dpll_pin *pin;
210 	u32 id;
211 	u32 idx;
212 	u64 clock_id;
213 	const struct fwnode_handle *fwnode;
214 	const struct dpll_pin_properties *prop;
215 };
216 
217 #if IS_ENABLED(CONFIG_DPLL)
218 void dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin);
219 void dpll_netdev_pin_clear(struct net_device *dev);
220 
221 size_t dpll_netdev_pin_handle_size(const struct net_device *dev);
222 int dpll_netdev_add_pin_handle(struct sk_buff *msg,
223 			       const struct net_device *dev);
224 
225 struct dpll_pin *fwnode_dpll_pin_find(struct fwnode_handle *fwnode,
226 				      dpll_tracker *tracker);
227 #else
228 static inline void
229 dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin) { }
230 static inline void dpll_netdev_pin_clear(struct net_device *dev) { }
231 
232 static inline size_t dpll_netdev_pin_handle_size(const struct net_device *dev)
233 {
234 	return 0;
235 }
236 
237 static inline int
238 dpll_netdev_add_pin_handle(struct sk_buff *msg, const struct net_device *dev)
239 {
240 	return 0;
241 }
242 
243 static inline struct dpll_pin *
244 fwnode_dpll_pin_find(struct fwnode_handle *fwnode, dpll_tracker *tracker)
245 {
246 	return NULL;
247 }
248 #endif
249 
250 struct dpll_device *
251 dpll_device_get(u64 clock_id, u32 dev_driver_id, struct module *module,
252 		dpll_tracker *tracker);
253 
254 void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker);
255 
256 int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,
257 			 const struct dpll_device_ops *ops, void *priv);
258 
259 void dpll_device_unregister(struct dpll_device *dpll,
260 			    const struct dpll_device_ops *ops, void *priv);
261 
262 #define DPLL_PIN_IDX_UNSPEC	U32_MAX
263 
264 struct dpll_pin *
265 dpll_pin_get(u64 clock_id, u32 dev_driver_id, struct module *module,
266 	     const struct dpll_pin_properties *prop, dpll_tracker *tracker);
267 
268 int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,
269 		      const struct dpll_pin_ops *ops, void *priv);
270 
271 void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,
272 			 const struct dpll_pin_ops *ops, void *priv);
273 
274 void dpll_pin_put(struct dpll_pin *pin, dpll_tracker *tracker);
275 
276 void dpll_pin_fwnode_set(struct dpll_pin *pin, struct fwnode_handle *fwnode);
277 
278 int dpll_pin_on_pin_register(struct dpll_pin *parent, struct dpll_pin *pin,
279 			     const struct dpll_pin_ops *ops, void *priv);
280 
281 void dpll_pin_on_pin_unregister(struct dpll_pin *parent, struct dpll_pin *pin,
282 				const struct dpll_pin_ops *ops, void *priv);
283 
284 int dpll_pin_ref_sync_pair_add(struct dpll_pin *pin,
285 			       struct dpll_pin *ref_sync_pin);
286 
287 int dpll_device_change_ntf(struct dpll_device *dpll);
288 
289 int dpll_pin_change_ntf(struct dpll_pin *pin);
290 
291 int register_dpll_notifier(struct notifier_block *nb);
292 
293 int unregister_dpll_notifier(struct notifier_block *nb);
294 
295 #endif
296