1 /*
2 comedi/drivers/cb_pcidas64.c
3 This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
4 64xx, 60xx, and 4020 cards.
5
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2001, 2002 Frank Mori Hess
8
9 Thanks also go to the following people:
10
11 Steve Rosenbluth, for providing the source code for
12 his pci-das6402 driver, and source code for working QNX pci-6402
13 drivers by Greg Laird and Mariusz Bogacz. None of the code was
14 used directly here, but it was useful as an additional source of
15 documentation on how to program the boards.
16
17 John Sims, for much testing and feedback on pcidas-4020 support.
18
19 COMEDI - Linux Control and Measurement Device Interface
20 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
21
22 This program is free software; you can redistribute it and/or modify
23 it under the terms of the GNU General Public License as published by
24 the Free Software Foundation; either version 2 of the License, or
25 (at your option) any later version.
26
27 This program is distributed in the hope that it will be useful,
28 but WITHOUT ANY WARRANTY; without even the implied warranty of
29 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 GNU General Public License for more details.
31
32 You should have received a copy of the GNU General Public License
33 along with this program; if not, write to the Free Software
34 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35
36 ************************************************************************/
37
38 /*
39
40 Driver: cb_pcidas64
41 Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series with the PLX 9080 PCI controller
42 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
43 Status: works
44 Updated: 2002-10-09
45 Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
46 PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
47 PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
48 PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
49 PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
50 PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
51 PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
52 PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
53 PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
54
55 Configuration options:
56 [0] - PCI bus of device (optional)
57 [1] - PCI slot of device (optional)
58
59 These boards may be autocalibrated with the comedi_calibrate utility.
60
61 To select the bnc trigger input on the 4020 (instead of the dio input),
62 specify a nonzero channel in the chanspec. If you wish to use an external
63 master clock on the 4020, you may do so by setting the scan_begin_src
64 to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
65 to configure the divisor to use for the external clock.
66
67 Some devices are not identified because the PCI device IDs are not yet
68 known. If you have such a board, please file a bug report at
69 https://bugs.comedi.org.
70
71 */
72
73 /*
74
75 TODO:
76 make it return error if user attempts an ai command that uses the
77 external queue, and an ao command simultaneously
78 user counter subdevice
79 there are a number of boards this driver will support when they are
80 fully released, but does not yet since the pci device id numbers
81 are not yet available.
82 support prescaled 100khz clock for slow pacing (not available on 6000 series?)
83 make ao fifo size adjustable like ai fifo
84 */
85
86 #include "../comedidev.h"
87 #include <linux/delay.h>
88 #include <linux/interrupt.h>
89 #include <asm/system.h>
90
91 #include "comedi_pci.h"
92 #include "8253.h"
93 #include "8255.h"
94 #include "plx9080.h"
95 #include "comedi_fc.h"
96
97 #undef PCIDAS64_DEBUG /* disable debugging code */
98 /* #define PCIDAS64_DEBUG enable debugging code */
99
100 #ifdef PCIDAS64_DEBUG
101 #define DEBUG_PRINT(format, args...) printk(format , ## args)
102 #else
103 #define DEBUG_PRINT(format, args...)
104 #endif
105
106 #define TIMER_BASE 25 /* 40MHz master clock */
107 #define PRESCALED_TIMER_BASE 10000 /* 100kHz 'prescaled' clock for slow acquisition, maybe I'll support this someday */
108 #define DMA_BUFFER_SIZE 0x1000
109
110 #define PCI_VENDOR_ID_COMPUTERBOARDS 0x1307
111
112 /* maximum value that can be loaded into board's 24-bit counters*/
113 static const int max_counter_value = 0xffffff;
114
115 /* PCI-DAS64xxx base addresses */
116
117 /* indices of base address regions */
118 enum base_address_regions {
119 PLX9080_BADDRINDEX = 0,
120 MAIN_BADDRINDEX = 2,
121 DIO_COUNTER_BADDRINDEX = 3,
122 };
123
124 /* priv(dev)->main_iobase registers */
125 enum write_only_registers {
126 INTR_ENABLE_REG = 0x0, /* interrupt enable register */
127 HW_CONFIG_REG = 0x2, /* hardware config register */
128 DAQ_SYNC_REG = 0xc,
129 DAQ_ATRIG_LOW_4020_REG = 0xc,
130 ADC_CONTROL0_REG = 0x10, /* adc control register 0 */
131 ADC_CONTROL1_REG = 0x12, /* adc control register 1 */
132 CALIBRATION_REG = 0x14,
133 ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16, /* lower 16 bits of adc sample interval counter */
134 ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18, /* upper 8 bits of adc sample interval counter */
135 ADC_DELAY_INTERVAL_LOWER_REG = 0x1a, /* lower 16 bits of delay interval counter */
136 ADC_DELAY_INTERVAL_UPPER_REG = 0x1c, /* upper 8 bits of delay interval counter */
137 ADC_COUNT_LOWER_REG = 0x1e, /* lower 16 bits of hardware conversion/scan counter */
138 ADC_COUNT_UPPER_REG = 0x20, /* upper 8 bits of hardware conversion/scan counter */
139 ADC_START_REG = 0x22, /* software trigger to start acquisition */
140 ADC_CONVERT_REG = 0x24, /* initiates single conversion */
141 ADC_QUEUE_CLEAR_REG = 0x26, /* clears adc queue */
142 ADC_QUEUE_LOAD_REG = 0x28, /* loads adc queue */
143 ADC_BUFFER_CLEAR_REG = 0x2a,
144 ADC_QUEUE_HIGH_REG = 0x2c, /* high channel for internal queue, use adc_chan_bits() inline above */
145 DAC_CONTROL0_REG = 0x50, /* dac control register 0 */
146 DAC_CONTROL1_REG = 0x52, /* dac control register 0 */
147 DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54, /* lower 16 bits of dac sample interval counter */
148 DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56, /* upper 8 bits of dac sample interval counter */
149 DAC_SELECT_REG = 0x60,
150 DAC_START_REG = 0x64,
151 DAC_BUFFER_CLEAR_REG = 0x66, /* clear dac buffer */
152 };
dac_convert_reg(unsigned int channel)153 static inline unsigned int dac_convert_reg(unsigned int channel)
154 {
155 return 0x70 + (2 * (channel & 0x1));
156 }
157
dac_lsb_4020_reg(unsigned int channel)158 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
159 {
160 return 0x70 + (4 * (channel & 0x1));
161 }
162
dac_msb_4020_reg(unsigned int channel)163 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
164 {
165 return 0x72 + (4 * (channel & 0x1));
166 }
167
168 enum read_only_registers {
169 HW_STATUS_REG = 0x0, /* hardware status register, reading this apparently clears pending interrupts as well */
170 PIPE1_READ_REG = 0x4,
171 ADC_READ_PNTR_REG = 0x8,
172 LOWER_XFER_REG = 0x10,
173 ADC_WRITE_PNTR_REG = 0xc,
174 PREPOST_REG = 0x14,
175 };
176
177 enum read_write_registers {
178 I8255_4020_REG = 0x48, /* 8255 offset, for 4020 only */
179 ADC_QUEUE_FIFO_REG = 0x100, /* external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
180 ADC_FIFO_REG = 0x200, /* adc data fifo */
181 DAC_FIFO_REG = 0x300, /* dac data fifo, has weird interactions with external channel queue */
182 };
183
184 /* priv(dev)->dio_counter_iobase registers */
185 enum dio_counter_registers {
186 DIO_8255_OFFSET = 0x0,
187 DO_REG = 0x20,
188 DI_REG = 0x28,
189 DIO_DIRECTION_60XX_REG = 0x40,
190 DIO_DATA_60XX_REG = 0x48,
191 };
192
193 /* bit definitions for write-only registers */
194
195 enum intr_enable_contents {
196 ADC_INTR_SRC_MASK = 0x3, /* bits that set adc interrupt source */
197 ADC_INTR_QFULL_BITS = 0x0, /* interrupt fifo quater full */
198 ADC_INTR_EOC_BITS = 0x1, /* interrupt end of conversion */
199 ADC_INTR_EOSCAN_BITS = 0x2, /* interrupt end of scan */
200 ADC_INTR_EOSEQ_BITS = 0x3, /* interrupt end of sequence (probably wont use this it's pretty fancy) */
201 EN_ADC_INTR_SRC_BIT = 0x4, /* enable adc interrupt source */
202 EN_ADC_DONE_INTR_BIT = 0x8, /* enable adc acquisition done interrupt */
203 DAC_INTR_SRC_MASK = 0x30,
204 DAC_INTR_QEMPTY_BITS = 0x0,
205 DAC_INTR_HIGH_CHAN_BITS = 0x10,
206 EN_DAC_INTR_SRC_BIT = 0x40, /* enable dac interrupt source */
207 EN_DAC_DONE_INTR_BIT = 0x80,
208 EN_ADC_ACTIVE_INTR_BIT = 0x200, /* enable adc active interrupt */
209 EN_ADC_STOP_INTR_BIT = 0x400, /* enable adc stop trigger interrupt */
210 EN_DAC_ACTIVE_INTR_BIT = 0x800, /* enable dac active interrupt */
211 EN_DAC_UNDERRUN_BIT = 0x4000, /* enable dac underrun status bit */
212 EN_ADC_OVERRUN_BIT = 0x8000, /* enable adc overrun status bit */
213 };
214
215 enum hw_config_contents {
216 MASTER_CLOCK_4020_MASK = 0x3, /* bits that specify master clock source for 4020 */
217 INTERNAL_CLOCK_4020_BITS = 0x1, /* use 40 MHz internal master clock for 4020 */
218 BNC_CLOCK_4020_BITS = 0x2, /* use BNC input for master clock */
219 EXT_CLOCK_4020_BITS = 0x3, /* use dio input for master clock */
220 EXT_QUEUE_BIT = 0x200, /* use external channel/gain queue (more versatile than internal queue) */
221 SLOW_DAC_BIT = 0x400, /* use 225 nanosec strobe when loading dac instead of 50 nanosec */
222 HW_CONFIG_DUMMY_BITS = 0x2000, /* bit with unknown function yet given as default value in pci-das64 manual */
223 DMA_CH_SELECT_BIT = 0x8000, /* bit selects channels 1/0 for analog input/output, otherwise 0/1 */
224 FIFO_SIZE_REG = 0x4, /* allows adjustment of fifo sizes */
225 DAC_FIFO_SIZE_MASK = 0xff00, /* bits that set dac fifo size */
226 DAC_FIFO_BITS = 0xf800, /* 8k sample ao fifo */
227 };
228 #define DAC_FIFO_SIZE 0x2000
229
230 enum daq_atrig_low_4020_contents {
231 EXT_AGATE_BNC_BIT = 0x8000, /* use trig/ext clk bnc input for analog gate signal */
232 EXT_STOP_TRIG_BNC_BIT = 0x4000, /* use trig/ext clk bnc input for external stop trigger signal */
233 EXT_START_TRIG_BNC_BIT = 0x2000, /* use trig/ext clk bnc input for external start trigger signal */
234 };
analog_trig_low_threshold_bits(uint16_t threshold)235 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
236 {
237 return threshold & 0xfff;
238 }
239
240 enum adc_control0_contents {
241 ADC_GATE_SRC_MASK = 0x3, /* bits that select gate */
242 ADC_SOFT_GATE_BITS = 0x1, /* software gate */
243 ADC_EXT_GATE_BITS = 0x2, /* external digital gate */
244 ADC_ANALOG_GATE_BITS = 0x3, /* analog level gate */
245 ADC_GATE_LEVEL_BIT = 0x4, /* level-sensitive gate (for digital) */
246 ADC_GATE_POLARITY_BIT = 0x8, /* gate active low */
247 ADC_START_TRIG_SOFT_BITS = 0x10,
248 ADC_START_TRIG_EXT_BITS = 0x20,
249 ADC_START_TRIG_ANALOG_BITS = 0x30,
250 ADC_START_TRIG_MASK = 0x30,
251 ADC_START_TRIG_FALLING_BIT = 0x40, /* trig 1 uses falling edge */
252 ADC_EXT_CONV_FALLING_BIT = 0x800, /* external pacing uses falling edge */
253 ADC_SAMPLE_COUNTER_EN_BIT = 0x1000, /* enable hardware scan counter */
254 ADC_DMA_DISABLE_BIT = 0x4000, /* disables dma */
255 ADC_ENABLE_BIT = 0x8000, /* master adc enable */
256 };
257
258 enum adc_control1_contents {
259 ADC_QUEUE_CONFIG_BIT = 0x1, /* should be set for boards with > 16 channels */
260 CONVERT_POLARITY_BIT = 0x10,
261 EOC_POLARITY_BIT = 0x20,
262 ADC_SW_GATE_BIT = 0x40, /* software gate of adc */
263 ADC_DITHER_BIT = 0x200, /* turn on extra noise for dithering */
264 RETRIGGER_BIT = 0x800,
265 ADC_LO_CHANNEL_4020_MASK = 0x300,
266 ADC_HI_CHANNEL_4020_MASK = 0xc00,
267 TWO_CHANNEL_4020_BITS = 0x1000, /* two channel mode for 4020 */
268 FOUR_CHANNEL_4020_BITS = 0x2000, /* four channel mode for 4020 */
269 CHANNEL_MODE_4020_MASK = 0x3000,
270 ADC_MODE_MASK = 0xf000,
271 };
adc_lo_chan_4020_bits(unsigned int channel)272 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
273 {
274 return (channel & 0x3) << 8;
275 };
276
adc_hi_chan_4020_bits(unsigned int channel)277 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
278 {
279 return (channel & 0x3) << 10;
280 };
281
adc_mode_bits(unsigned int mode)282 static inline uint16_t adc_mode_bits(unsigned int mode)
283 {
284 return (mode & 0xf) << 12;
285 };
286
287 enum calibration_contents {
288 SELECT_8800_BIT = 0x1,
289 SELECT_8402_64XX_BIT = 0x2,
290 SELECT_1590_60XX_BIT = 0x2,
291 CAL_EN_64XX_BIT = 0x40, /* calibration enable for 64xx series */
292 SERIAL_DATA_IN_BIT = 0x80,
293 SERIAL_CLOCK_BIT = 0x100,
294 CAL_EN_60XX_BIT = 0x200, /* calibration enable for 60xx series */
295 CAL_GAIN_BIT = 0x800,
296 };
297 /* calibration sources for 6025 are:
298 * 0 : ground
299 * 1 : 10V
300 * 2 : 5V
301 * 3 : 0.5V
302 * 4 : 0.05V
303 * 5 : ground
304 * 6 : dac channel 0
305 * 7 : dac channel 1
306 */
adc_src_bits(unsigned int source)307 static inline uint16_t adc_src_bits(unsigned int source)
308 {
309 return (source & 0xf) << 3;
310 };
311
adc_convert_chan_4020_bits(unsigned int channel)312 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
313 {
314 return (channel & 0x3) << 8;
315 };
316
317 enum adc_queue_load_contents {
318 UNIP_BIT = 0x800, /* unipolar/bipolar bit */
319 ADC_SE_DIFF_BIT = 0x1000, /* single-ended/ differential bit */
320 ADC_COMMON_BIT = 0x2000, /* non-referenced single-ended (common-mode input) */
321 QUEUE_EOSEQ_BIT = 0x4000, /* queue end of sequence */
322 QUEUE_EOSCAN_BIT = 0x8000, /* queue end of scan */
323 };
adc_chan_bits(unsigned int channel)324 static inline uint16_t adc_chan_bits(unsigned int channel)
325 {
326 return channel & 0x3f;
327 };
328
329 enum dac_control0_contents {
330 DAC_ENABLE_BIT = 0x8000, /* dac controller enable bit */
331 DAC_CYCLIC_STOP_BIT = 0x4000,
332 DAC_WAVEFORM_MODE_BIT = 0x100,
333 DAC_EXT_UPDATE_FALLING_BIT = 0x80,
334 DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
335 WAVEFORM_TRIG_MASK = 0x30,
336 WAVEFORM_TRIG_DISABLED_BITS = 0x0,
337 WAVEFORM_TRIG_SOFT_BITS = 0x10,
338 WAVEFORM_TRIG_EXT_BITS = 0x20,
339 WAVEFORM_TRIG_ADC1_BITS = 0x30,
340 WAVEFORM_TRIG_FALLING_BIT = 0x8,
341 WAVEFORM_GATE_LEVEL_BIT = 0x4,
342 WAVEFORM_GATE_ENABLE_BIT = 0x2,
343 WAVEFORM_GATE_SELECT_BIT = 0x1,
344 };
345
346 enum dac_control1_contents {
347 DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
348 DAC1_EXT_REF_BIT = 0x200,
349 DAC0_EXT_REF_BIT = 0x100,
350 DAC_OUTPUT_ENABLE_BIT = 0x80, /* dac output enable bit */
351 DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
352 DAC_SW_GATE_BIT = 0x20,
353 DAC1_UNIPOLAR_BIT = 0x8,
354 DAC0_UNIPOLAR_BIT = 0x2,
355 };
356
357 /* bit definitions for read-only registers */
358 enum hw_status_contents {
359 DAC_UNDERRUN_BIT = 0x1,
360 ADC_OVERRUN_BIT = 0x2,
361 DAC_ACTIVE_BIT = 0x4,
362 ADC_ACTIVE_BIT = 0x8,
363 DAC_INTR_PENDING_BIT = 0x10,
364 ADC_INTR_PENDING_BIT = 0x20,
365 DAC_DONE_BIT = 0x40,
366 ADC_DONE_BIT = 0x80,
367 EXT_INTR_PENDING_BIT = 0x100,
368 ADC_STOP_BIT = 0x200,
369 };
pipe_full_bits(uint16_t hw_status_bits)370 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
371 {
372 return (hw_status_bits >> 10) & 0x3;
373 };
374
dma_chain_flag_bits(uint16_t prepost_bits)375 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
376 {
377 return (prepost_bits >> 6) & 0x3;
378 }
379
adc_upper_read_ptr_code(uint16_t prepost_bits)380 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
381 {
382 return (prepost_bits >> 12) & 0x3;
383 }
384
adc_upper_write_ptr_code(uint16_t prepost_bits)385 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
386 {
387 return (prepost_bits >> 14) & 0x3;
388 }
389
390 /* I2C addresses for 4020 */
391 enum i2c_addresses {
392 RANGE_CAL_I2C_ADDR = 0x20,
393 CALDAC0_I2C_ADDR = 0xc,
394 CALDAC1_I2C_ADDR = 0xd,
395 };
396
397 enum range_cal_i2c_contents {
398 ADC_SRC_4020_MASK = 0x70, /* bits that set what source the adc converter measures */
399 BNC_TRIG_THRESHOLD_0V_BIT = 0x80, /* make bnc trig/ext clock threshold 0V instead of 2.5V */
400 };
adc_src_4020_bits(unsigned int source)401 static inline uint8_t adc_src_4020_bits(unsigned int source)
402 {
403 return (source << 4) & ADC_SRC_4020_MASK;
404 };
405
attenuate_bit(unsigned int channel)406 static inline uint8_t attenuate_bit(unsigned int channel)
407 {
408 /* attenuate channel (+-5V input range) */
409 return 1 << (channel & 0x3);
410 };
411
412 /* analog input ranges for 64xx boards */
413 static const struct comedi_lrange ai_ranges_64xx = {
414 8,
415 {
416 BIP_RANGE(10),
417 BIP_RANGE(5),
418 BIP_RANGE(2.5),
419 BIP_RANGE(1.25),
420 UNI_RANGE(10),
421 UNI_RANGE(5),
422 UNI_RANGE(2.5),
423 UNI_RANGE(1.25)
424 }
425 };
426
427 /* analog input ranges for 60xx boards */
428 static const struct comedi_lrange ai_ranges_60xx = {
429 4,
430 {
431 BIP_RANGE(10),
432 BIP_RANGE(5),
433 BIP_RANGE(0.5),
434 BIP_RANGE(0.05),
435 }
436 };
437
438 /* analog input ranges for 6030, etc boards */
439 static const struct comedi_lrange ai_ranges_6030 = {
440 14,
441 {
442 BIP_RANGE(10),
443 BIP_RANGE(5),
444 BIP_RANGE(2),
445 BIP_RANGE(1),
446 BIP_RANGE(0.5),
447 BIP_RANGE(0.2),
448 BIP_RANGE(0.1),
449 UNI_RANGE(10),
450 UNI_RANGE(5),
451 UNI_RANGE(2),
452 UNI_RANGE(1),
453 UNI_RANGE(0.5),
454 UNI_RANGE(0.2),
455 UNI_RANGE(0.1),
456 }
457 };
458
459 /* analog input ranges for 6052, etc boards */
460 static const struct comedi_lrange ai_ranges_6052 = {
461 15,
462 {
463 BIP_RANGE(10),
464 BIP_RANGE(5),
465 BIP_RANGE(2.5),
466 BIP_RANGE(1),
467 BIP_RANGE(0.5),
468 BIP_RANGE(0.25),
469 BIP_RANGE(0.1),
470 BIP_RANGE(0.05),
471 UNI_RANGE(10),
472 UNI_RANGE(5),
473 UNI_RANGE(2),
474 UNI_RANGE(1),
475 UNI_RANGE(0.5),
476 UNI_RANGE(0.2),
477 UNI_RANGE(0.1),
478 }
479 };
480
481 /* analog input ranges for 4020 board */
482 static const struct comedi_lrange ai_ranges_4020 = {
483 2,
484 {
485 BIP_RANGE(5),
486 BIP_RANGE(1),
487 }
488 };
489
490 /* analog output ranges */
491 static const struct comedi_lrange ao_ranges_64xx = {
492 4,
493 {
494 BIP_RANGE(5),
495 BIP_RANGE(10),
496 UNI_RANGE(5),
497 UNI_RANGE(10),
498 }
499 };
500
501 static const int ao_range_code_64xx[] = {
502 0x0,
503 0x1,
504 0x2,
505 0x3,
506 };
507
508 static const struct comedi_lrange ao_ranges_60xx = {
509 1,
510 {
511 BIP_RANGE(10),
512 }
513 };
514
515 static const int ao_range_code_60xx[] = {
516 0x0,
517 };
518
519 static const struct comedi_lrange ao_ranges_6030 = {
520 2,
521 {
522 BIP_RANGE(10),
523 UNI_RANGE(10),
524 }
525 };
526
527 static const int ao_range_code_6030[] = {
528 0x0,
529 0x2,
530 };
531
532 static const struct comedi_lrange ao_ranges_4020 = {
533 2,
534 {
535 BIP_RANGE(5),
536 BIP_RANGE(10),
537 }
538 };
539
540 static const int ao_range_code_4020[] = {
541 0x1,
542 0x0,
543 };
544
545 enum register_layout {
546 LAYOUT_60XX,
547 LAYOUT_64XX,
548 LAYOUT_4020,
549 };
550
551 struct hw_fifo_info {
552 unsigned int num_segments;
553 unsigned int max_segment_length;
554 unsigned int sample_packing_ratio;
555 uint16_t fifo_size_reg_mask;
556 };
557
558 struct pcidas64_board {
559 const char *name;
560 int device_id; /* pci device id */
561 int ai_se_chans; /* number of ai inputs in single-ended mode */
562 int ai_bits; /* analog input resolution */
563 int ai_speed; /* fastest conversion period in ns */
564 const struct comedi_lrange *ai_range_table;
565 int ao_nchan; /* number of analog out channels */
566 int ao_bits; /* analog output resolution */
567 int ao_scan_speed; /* analog output speed (for a scan, not conversion) */
568 const struct comedi_lrange *ao_range_table;
569 const int *ao_range_code;
570 const struct hw_fifo_info *const ai_fifo;
571 enum register_layout layout; /* different board families have slightly different registers */
572 unsigned has_8255:1;
573 };
574
575 static const struct hw_fifo_info ai_fifo_4020 = {
576 .num_segments = 2,
577 .max_segment_length = 0x8000,
578 .sample_packing_ratio = 2,
579 .fifo_size_reg_mask = 0x7f,
580 };
581
582 static const struct hw_fifo_info ai_fifo_64xx = {
583 .num_segments = 4,
584 .max_segment_length = 0x800,
585 .sample_packing_ratio = 1,
586 .fifo_size_reg_mask = 0x3f,
587 };
588
589 static const struct hw_fifo_info ai_fifo_60xx = {
590 .num_segments = 4,
591 .max_segment_length = 0x800,
592 .sample_packing_ratio = 1,
593 .fifo_size_reg_mask = 0x7f,
594 };
595
596 /* maximum number of dma transfers we will chain together into a ring
597 * (and the maximum number of dma buffers we maintain) */
598 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
599 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
600 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
ai_dma_ring_count(struct pcidas64_board * board)601 static inline unsigned int ai_dma_ring_count(struct pcidas64_board *board)
602 {
603 if (board->layout == LAYOUT_4020)
604 return MAX_AI_DMA_RING_COUNT;
605 else
606 return MIN_AI_DMA_RING_COUNT;
607 }
608
609 static const int bytes_in_sample = 2;
610
611 static const struct pcidas64_board pcidas64_boards[] = {
612 {
613 .name = "pci-das6402/16",
614 .device_id = 0x1d,
615 .ai_se_chans = 64,
616 .ai_bits = 16,
617 .ai_speed = 5000,
618 .ao_nchan = 2,
619 .ao_bits = 16,
620 .ao_scan_speed = 10000,
621 .layout = LAYOUT_64XX,
622 .ai_range_table = &ai_ranges_64xx,
623 .ao_range_table = &ao_ranges_64xx,
624 .ao_range_code = ao_range_code_64xx,
625 .ai_fifo = &ai_fifo_64xx,
626 .has_8255 = 1,
627 },
628 {
629 .name = "pci-das6402/12", /* XXX check */
630 .device_id = 0x1e,
631 .ai_se_chans = 64,
632 .ai_bits = 12,
633 .ai_speed = 5000,
634 .ao_nchan = 2,
635 .ao_bits = 12,
636 .ao_scan_speed = 10000,
637 .layout = LAYOUT_64XX,
638 .ai_range_table = &ai_ranges_64xx,
639 .ao_range_table = &ao_ranges_64xx,
640 .ao_range_code = ao_range_code_64xx,
641 .ai_fifo = &ai_fifo_64xx,
642 .has_8255 = 1,
643 },
644 {
645 .name = "pci-das64/m1/16",
646 .device_id = 0x35,
647 .ai_se_chans = 64,
648 .ai_bits = 16,
649 .ai_speed = 1000,
650 .ao_nchan = 2,
651 .ao_bits = 16,
652 .ao_scan_speed = 10000,
653 .layout = LAYOUT_64XX,
654 .ai_range_table = &ai_ranges_64xx,
655 .ao_range_table = &ao_ranges_64xx,
656 .ao_range_code = ao_range_code_64xx,
657 .ai_fifo = &ai_fifo_64xx,
658 .has_8255 = 1,
659 },
660 {
661 .name = "pci-das64/m2/16",
662 .device_id = 0x36,
663 .ai_se_chans = 64,
664 .ai_bits = 16,
665 .ai_speed = 500,
666 .ao_nchan = 2,
667 .ao_bits = 16,
668 .ao_scan_speed = 10000,
669 .layout = LAYOUT_64XX,
670 .ai_range_table = &ai_ranges_64xx,
671 .ao_range_table = &ao_ranges_64xx,
672 .ao_range_code = ao_range_code_64xx,
673 .ai_fifo = &ai_fifo_64xx,
674 .has_8255 = 1,
675 },
676 {
677 .name = "pci-das64/m3/16",
678 .device_id = 0x37,
679 .ai_se_chans = 64,
680 .ai_bits = 16,
681 .ai_speed = 333,
682 .ao_nchan = 2,
683 .ao_bits = 16,
684 .ao_scan_speed = 10000,
685 .layout = LAYOUT_64XX,
686 .ai_range_table = &ai_ranges_64xx,
687 .ao_range_table = &ao_ranges_64xx,
688 .ao_range_code = ao_range_code_64xx,
689 .ai_fifo = &ai_fifo_64xx,
690 .has_8255 = 1,
691 },
692 {
693 .name = "pci-das6013",
694 .device_id = 0x78,
695 .ai_se_chans = 16,
696 .ai_bits = 16,
697 .ai_speed = 5000,
698 .ao_nchan = 0,
699 .ao_bits = 16,
700 .layout = LAYOUT_60XX,
701 .ai_range_table = &ai_ranges_60xx,
702 .ao_range_table = &ao_ranges_60xx,
703 .ao_range_code = ao_range_code_60xx,
704 .ai_fifo = &ai_fifo_60xx,
705 .has_8255 = 0,
706 },
707 {
708 .name = "pci-das6014",
709 .device_id = 0x79,
710 .ai_se_chans = 16,
711 .ai_bits = 16,
712 .ai_speed = 5000,
713 .ao_nchan = 2,
714 .ao_bits = 16,
715 .ao_scan_speed = 100000,
716 .layout = LAYOUT_60XX,
717 .ai_range_table = &ai_ranges_60xx,
718 .ao_range_table = &ao_ranges_60xx,
719 .ao_range_code = ao_range_code_60xx,
720 .ai_fifo = &ai_fifo_60xx,
721 .has_8255 = 0,
722 },
723 {
724 .name = "pci-das6023",
725 .device_id = 0x5d,
726 .ai_se_chans = 16,
727 .ai_bits = 12,
728 .ai_speed = 5000,
729 .ao_nchan = 0,
730 .ao_scan_speed = 100000,
731 .layout = LAYOUT_60XX,
732 .ai_range_table = &ai_ranges_60xx,
733 .ao_range_table = &ao_ranges_60xx,
734 .ao_range_code = ao_range_code_60xx,
735 .ai_fifo = &ai_fifo_60xx,
736 .has_8255 = 1,
737 },
738 {
739 .name = "pci-das6025",
740 .device_id = 0x5e,
741 .ai_se_chans = 16,
742 .ai_bits = 12,
743 .ai_speed = 5000,
744 .ao_nchan = 2,
745 .ao_bits = 12,
746 .ao_scan_speed = 100000,
747 .layout = LAYOUT_60XX,
748 .ai_range_table = &ai_ranges_60xx,
749 .ao_range_table = &ao_ranges_60xx,
750 .ao_range_code = ao_range_code_60xx,
751 .ai_fifo = &ai_fifo_60xx,
752 .has_8255 = 1,
753 },
754 {
755 .name = "pci-das6030",
756 .device_id = 0x5f,
757 .ai_se_chans = 16,
758 .ai_bits = 16,
759 .ai_speed = 10000,
760 .ao_nchan = 2,
761 .ao_bits = 16,
762 .ao_scan_speed = 10000,
763 .layout = LAYOUT_60XX,
764 .ai_range_table = &ai_ranges_6030,
765 .ao_range_table = &ao_ranges_6030,
766 .ao_range_code = ao_range_code_6030,
767 .ai_fifo = &ai_fifo_60xx,
768 .has_8255 = 0,
769 },
770 {
771 .name = "pci-das6031",
772 .device_id = 0x60,
773 .ai_se_chans = 64,
774 .ai_bits = 16,
775 .ai_speed = 10000,
776 .ao_nchan = 2,
777 .ao_bits = 16,
778 .ao_scan_speed = 10000,
779 .layout = LAYOUT_60XX,
780 .ai_range_table = &ai_ranges_6030,
781 .ao_range_table = &ao_ranges_6030,
782 .ao_range_code = ao_range_code_6030,
783 .ai_fifo = &ai_fifo_60xx,
784 .has_8255 = 0,
785 },
786 {
787 .name = "pci-das6032",
788 .device_id = 0x61,
789 .ai_se_chans = 16,
790 .ai_bits = 16,
791 .ai_speed = 10000,
792 .ao_nchan = 0,
793 .layout = LAYOUT_60XX,
794 .ai_range_table = &ai_ranges_6030,
795 .ai_fifo = &ai_fifo_60xx,
796 .has_8255 = 0,
797 },
798 {
799 .name = "pci-das6033",
800 .device_id = 0x62,
801 .ai_se_chans = 64,
802 .ai_bits = 16,
803 .ai_speed = 10000,
804 .ao_nchan = 0,
805 .layout = LAYOUT_60XX,
806 .ai_range_table = &ai_ranges_6030,
807 .ai_fifo = &ai_fifo_60xx,
808 .has_8255 = 0,
809 },
810 {
811 .name = "pci-das6034",
812 .device_id = 0x63,
813 .ai_se_chans = 16,
814 .ai_bits = 16,
815 .ai_speed = 5000,
816 .ao_nchan = 0,
817 .ao_scan_speed = 0,
818 .layout = LAYOUT_60XX,
819 .ai_range_table = &ai_ranges_60xx,
820 .ai_fifo = &ai_fifo_60xx,
821 .has_8255 = 0,
822 },
823 {
824 .name = "pci-das6035",
825 .device_id = 0x64,
826 .ai_se_chans = 16,
827 .ai_bits = 16,
828 .ai_speed = 5000,
829 .ao_nchan = 2,
830 .ao_bits = 12,
831 .ao_scan_speed = 100000,
832 .layout = LAYOUT_60XX,
833 .ai_range_table = &ai_ranges_60xx,
834 .ao_range_table = &ao_ranges_60xx,
835 .ao_range_code = ao_range_code_60xx,
836 .ai_fifo = &ai_fifo_60xx,
837 .has_8255 = 0,
838 },
839 {
840 .name = "pci-das6036",
841 .device_id = 0x6f,
842 .ai_se_chans = 16,
843 .ai_bits = 16,
844 .ai_speed = 5000,
845 .ao_nchan = 2,
846 .ao_bits = 16,
847 .ao_scan_speed = 100000,
848 .layout = LAYOUT_60XX,
849 .ai_range_table = &ai_ranges_60xx,
850 .ao_range_table = &ao_ranges_60xx,
851 .ao_range_code = ao_range_code_60xx,
852 .ai_fifo = &ai_fifo_60xx,
853 .has_8255 = 0,
854 },
855 {
856 .name = "pci-das6040",
857 .device_id = 0x65,
858 .ai_se_chans = 16,
859 .ai_bits = 12,
860 .ai_speed = 2000,
861 .ao_nchan = 2,
862 .ao_bits = 12,
863 .ao_scan_speed = 1000,
864 .layout = LAYOUT_60XX,
865 .ai_range_table = &ai_ranges_6052,
866 .ao_range_table = &ao_ranges_6030,
867 .ao_range_code = ao_range_code_6030,
868 .ai_fifo = &ai_fifo_60xx,
869 .has_8255 = 0,
870 },
871 {
872 .name = "pci-das6052",
873 .device_id = 0x66,
874 .ai_se_chans = 16,
875 .ai_bits = 16,
876 .ai_speed = 3333,
877 .ao_nchan = 2,
878 .ao_bits = 16,
879 .ao_scan_speed = 3333,
880 .layout = LAYOUT_60XX,
881 .ai_range_table = &ai_ranges_6052,
882 .ao_range_table = &ao_ranges_6030,
883 .ao_range_code = ao_range_code_6030,
884 .ai_fifo = &ai_fifo_60xx,
885 .has_8255 = 0,
886 },
887 {
888 .name = "pci-das6070",
889 .device_id = 0x67,
890 .ai_se_chans = 16,
891 .ai_bits = 12,
892 .ai_speed = 800,
893 .ao_nchan = 2,
894 .ao_bits = 12,
895 .ao_scan_speed = 1000,
896 .layout = LAYOUT_60XX,
897 .ai_range_table = &ai_ranges_6052,
898 .ao_range_table = &ao_ranges_6030,
899 .ao_range_code = ao_range_code_6030,
900 .ai_fifo = &ai_fifo_60xx,
901 .has_8255 = 0,
902 },
903 {
904 .name = "pci-das6071",
905 .device_id = 0x68,
906 .ai_se_chans = 64,
907 .ai_bits = 12,
908 .ai_speed = 800,
909 .ao_nchan = 2,
910 .ao_bits = 12,
911 .ao_scan_speed = 1000,
912 .layout = LAYOUT_60XX,
913 .ai_range_table = &ai_ranges_6052,
914 .ao_range_table = &ao_ranges_6030,
915 .ao_range_code = ao_range_code_6030,
916 .ai_fifo = &ai_fifo_60xx,
917 .has_8255 = 0,
918 },
919 {
920 .name = "pci-das4020/12",
921 .device_id = 0x52,
922 .ai_se_chans = 4,
923 .ai_bits = 12,
924 .ai_speed = 50,
925 .ao_bits = 12,
926 .ao_nchan = 2,
927 .ao_scan_speed = 0, /* no hardware pacing on ao */
928 .layout = LAYOUT_4020,
929 .ai_range_table = &ai_ranges_4020,
930 .ao_range_table = &ao_ranges_4020,
931 .ao_range_code = ao_range_code_4020,
932 .ai_fifo = &ai_fifo_4020,
933 .has_8255 = 1,
934 },
935 #if 0
936 {
937 .name = "pci-das6402/16/jr",
938 .device_id = 0 /* XXX, */
939 .ai_se_chans = 64,
940 .ai_bits = 16,
941 .ai_speed = 5000,
942 .ao_nchan = 0,
943 .ao_scan_speed = 10000,
944 .layout = LAYOUT_64XX,
945 .ai_range_table = &ai_ranges_64xx,
946 .ai_fifo = ai_fifo_64xx,
947 .has_8255 = 1,
948 },
949 {
950 .name = "pci-das64/m1/16/jr",
951 .device_id = 0 /* XXX, */
952 .ai_se_chans = 64,
953 .ai_bits = 16,
954 .ai_speed = 1000,
955 .ao_nchan = 0,
956 .ao_scan_speed = 10000,
957 .layout = LAYOUT_64XX,
958 .ai_range_table = &ai_ranges_64xx,
959 .ai_fifo = ai_fifo_64xx,
960 .has_8255 = 1,
961 },
962 {
963 .name = "pci-das64/m2/16/jr",
964 .device_id = 0 /* XXX, */
965 .ai_se_chans = 64,
966 .ai_bits = 16,
967 .ai_speed = 500,
968 .ao_nchan = 0,
969 .ao_scan_speed = 10000,
970 .layout = LAYOUT_64XX,
971 .ai_range_table = &ai_ranges_64xx,
972 .ai_fifo = ai_fifo_64xx,
973 .has_8255 = 1,
974 },
975 {
976 .name = "pci-das64/m3/16/jr",
977 .device_id = 0 /* XXX, */
978 .ai_se_chans = 64,
979 .ai_bits = 16,
980 .ai_speed = 333,
981 .ao_nchan = 0,
982 .ao_scan_speed = 10000,
983 .layout = LAYOUT_64XX,
984 .ai_range_table = &ai_ranges_64xx,
985 .ai_fifo = ai_fifo_64xx,
986 .has_8255 = 1,
987 },
988 {
989 .name = "pci-das64/m1/14",
990 .device_id = 0, /* XXX */
991 .ai_se_chans = 64,
992 .ai_bits = 14,
993 .ai_speed = 1000,
994 .ao_nchan = 2,
995 .ao_scan_speed = 10000,
996 .layout = LAYOUT_64XX,
997 .ai_range_table = &ai_ranges_64xx,
998 .ai_fifo = ai_fifo_64xx,
999 .has_8255 = 1,
1000 },
1001 {
1002 .name = "pci-das64/m2/14",
1003 .device_id = 0, /* XXX */
1004 .ai_se_chans = 64,
1005 .ai_bits = 14,
1006 .ai_speed = 500,
1007 .ao_nchan = 2,
1008 .ao_scan_speed = 10000,
1009 .layout = LAYOUT_64XX,
1010 .ai_range_table = &ai_ranges_64xx,
1011 .ai_fifo = ai_fifo_64xx,
1012 .has_8255 = 1,
1013 },
1014 {
1015 .name = "pci-das64/m3/14",
1016 .device_id = 0, /* XXX */
1017 .ai_se_chans = 64,
1018 .ai_bits = 14,
1019 .ai_speed = 333,
1020 .ao_nchan = 2,
1021 .ao_scan_speed = 10000,
1022 .layout = LAYOUT_64XX,
1023 .ai_range_table = &ai_ranges_64xx,
1024 .ai_fifo = ai_fifo_64xx,
1025 .has_8255 = 1,
1026 },
1027 #endif
1028 };
1029
1030 static DEFINE_PCI_DEVICE_TABLE(pcidas64_pci_table) = {
1031 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001d) },
1032 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x001e) },
1033 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0035) },
1034 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0036) },
1035 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0037) },
1036 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0052) },
1037 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005d) },
1038 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005e) },
1039 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x005f) },
1040 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0061) },
1041 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0062) },
1042 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0063) },
1043 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0064) },
1044 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0066) },
1045 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0067) },
1046 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0068) },
1047 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x006f) },
1048 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0078) },
1049 { PCI_DEVICE(PCI_VENDOR_ID_COMPUTERBOARDS, 0x0079) },
1050 { 0 }
1051 };
1052
1053 MODULE_DEVICE_TABLE(pci, pcidas64_pci_table);
1054
board(const struct comedi_device * dev)1055 static inline struct pcidas64_board *board(const struct comedi_device *dev)
1056 {
1057 return (struct pcidas64_board *)dev->board_ptr;
1058 }
1059
se_diff_bit_6xxx(struct comedi_device * dev,int use_differential)1060 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1061 int use_differential)
1062 {
1063 if ((board(dev)->layout == LAYOUT_64XX && !use_differential) ||
1064 (board(dev)->layout == LAYOUT_60XX && use_differential))
1065 return ADC_SE_DIFF_BIT;
1066 else
1067 return 0;
1068 };
1069
1070 struct ext_clock_info {
1071 unsigned int divisor; /* master clock divisor to use for scans with external master clock */
1072 unsigned int chanspec; /* chanspec for master clock input when used as scan begin src */
1073 };
1074
1075 /* this structure is for data unique to this hardware driver. */
1076 struct pcidas64_private {
1077
1078 struct pci_dev *hw_dev; /* pointer to board's pci_dev struct */
1079 /* base addresses (physical) */
1080 resource_size_t plx9080_phys_iobase;
1081 resource_size_t main_phys_iobase;
1082 resource_size_t dio_counter_phys_iobase;
1083 /* base addresses (ioremapped) */
1084 void __iomem *plx9080_iobase;
1085 void __iomem *main_iobase;
1086 void __iomem *dio_counter_iobase;
1087 /* local address (used by dma controller) */
1088 uint32_t local0_iobase;
1089 uint32_t local1_iobase;
1090 volatile unsigned int ai_count; /* number of analog input samples remaining */
1091 uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT]; /* dma buffers for analog input */
1092 dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT]; /* physical addresses of ai dma buffers */
1093 struct plx_dma_desc *ai_dma_desc; /* array of ai dma descriptors read by plx9080, allocated to get proper alignment */
1094 dma_addr_t ai_dma_desc_bus_addr; /* physical address of ai dma descriptor array */
1095 volatile unsigned int ai_dma_index; /* index of the ai dma descriptor/buffer that is currently being used */
1096 uint16_t *ao_buffer[AO_DMA_RING_COUNT]; /* dma buffers for analog output */
1097 dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT]; /* physical addresses of ao dma buffers */
1098 struct plx_dma_desc *ao_dma_desc;
1099 dma_addr_t ao_dma_desc_bus_addr;
1100 volatile unsigned int ao_dma_index; /* keeps track of buffer where the next ao sample should go */
1101 volatile unsigned long ao_count; /* number of analog output samples remaining */
1102 volatile unsigned int ao_value[2]; /* remember what the analog outputs are set to, to allow readback */
1103 unsigned int hw_revision; /* stc chip hardware revision number */
1104 volatile unsigned int intr_enable_bits; /* last bits sent to INTR_ENABLE_REG register */
1105 volatile uint16_t adc_control1_bits; /* last bits sent to ADC_CONTROL1_REG register */
1106 volatile uint16_t fifo_size_bits; /* last bits sent to FIFO_SIZE_REG register */
1107 volatile uint16_t hw_config_bits; /* last bits sent to HW_CONFIG_REG register */
1108 volatile uint16_t dac_control1_bits;
1109 volatile uint32_t plx_control_bits; /* last bits written to plx9080 control register */
1110 volatile uint32_t plx_intcsr_bits; /* last bits written to plx interrupt control and status register */
1111 volatile int calibration_source; /* index of calibration source readable through ai ch0 */
1112 volatile uint8_t i2c_cal_range_bits; /* bits written to i2c calibration/range register */
1113 volatile unsigned int ext_trig_falling; /* configure digital triggers to trigger on falling edge */
1114 /* states of various devices stored to enable read-back */
1115 unsigned int ad8402_state[2];
1116 unsigned int caldac_state[8];
1117 volatile short ai_cmd_running;
1118 unsigned int ai_fifo_segment_length;
1119 struct ext_clock_info ext_clock;
1120 short ao_bounce_buffer[DAC_FIFO_SIZE];
1121 };
1122
1123 /* inline function that makes it easier to
1124 * access the private structure.
1125 */
priv(struct comedi_device * dev)1126 static inline struct pcidas64_private *priv(struct comedi_device *dev)
1127 {
1128 return dev->private;
1129 }
1130
1131 /*
1132 * The comedi_driver structure tells the Comedi core module
1133 * which functions to call to configure/deconfigure (attach/detach)
1134 * the board, and also about the kernel module that contains
1135 * the device code.
1136 */
1137 static int attach(struct comedi_device *dev, struct comedi_devconfig *it);
1138 static int detach(struct comedi_device *dev);
1139 static struct comedi_driver driver_cb_pcidas = {
1140 .driver_name = "cb_pcidas64",
1141 .module = THIS_MODULE,
1142 .attach = attach,
1143 .detach = detach,
1144 };
1145
1146 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1147 struct comedi_insn *insn, unsigned int *data);
1148 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1149 struct comedi_insn *insn, unsigned int *data);
1150 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
1151 struct comedi_insn *insn, unsigned int *data);
1152 static int ao_readback_insn(struct comedi_device *dev,
1153 struct comedi_subdevice *s,
1154 struct comedi_insn *insn, unsigned int *data);
1155 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1156 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1157 struct comedi_cmd *cmd);
1158 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
1159 static int ao_inttrig(struct comedi_device *dev,
1160 struct comedi_subdevice *subdev, unsigned int trig_num);
1161 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
1162 struct comedi_cmd *cmd);
1163 static irqreturn_t handle_interrupt(int irq, void *d);
1164 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1165 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
1166 static int dio_callback(int dir, int port, int data, unsigned long arg);
1167 static int dio_callback_4020(int dir, int port, int data, unsigned long arg);
1168 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
1169 struct comedi_insn *insn, unsigned int *data);
1170 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1171 struct comedi_insn *insn, unsigned int *data);
1172 static int dio_60xx_config_insn(struct comedi_device *dev,
1173 struct comedi_subdevice *s,
1174 struct comedi_insn *insn, unsigned int *data);
1175 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
1176 struct comedi_insn *insn, unsigned int *data);
1177 static int calib_read_insn(struct comedi_device *dev,
1178 struct comedi_subdevice *s, struct comedi_insn *insn,
1179 unsigned int *data);
1180 static int calib_write_insn(struct comedi_device *dev,
1181 struct comedi_subdevice *s,
1182 struct comedi_insn *insn, unsigned int *data);
1183 static int ad8402_read_insn(struct comedi_device *dev,
1184 struct comedi_subdevice *s,
1185 struct comedi_insn *insn, unsigned int *data);
1186 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
1187 unsigned int value);
1188 static int ad8402_write_insn(struct comedi_device *dev,
1189 struct comedi_subdevice *s,
1190 struct comedi_insn *insn, unsigned int *data);
1191 static int eeprom_read_insn(struct comedi_device *dev,
1192 struct comedi_subdevice *s,
1193 struct comedi_insn *insn, unsigned int *data);
1194 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
1195 static unsigned int get_divisor(unsigned int ns, unsigned int flags);
1196 static void i2c_write(struct comedi_device *dev, unsigned int address,
1197 const uint8_t * data, unsigned int length);
1198 static void caldac_write(struct comedi_device *dev, unsigned int channel,
1199 unsigned int value);
1200 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
1201 uint8_t value);
1202 /* static int dac_1590_write(struct comedi_device *dev, unsigned int dac_a, unsigned int dac_b); */
1203 static int caldac_i2c_write(struct comedi_device *dev,
1204 unsigned int caldac_channel, unsigned int value);
1205 static void abort_dma(struct comedi_device *dev, unsigned int channel);
1206 static void disable_plx_interrupts(struct comedi_device *dev);
1207 static int set_ai_fifo_size(struct comedi_device *dev,
1208 unsigned int num_samples);
1209 static unsigned int ai_fifo_size(struct comedi_device *dev);
1210 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1211 unsigned int num_entries);
1212 static void disable_ai_pacing(struct comedi_device *dev);
1213 static void disable_ai_interrupts(struct comedi_device *dev);
1214 static void enable_ai_interrupts(struct comedi_device *dev,
1215 const struct comedi_cmd *cmd);
1216 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags);
1217 static void load_ao_dma(struct comedi_device *dev,
1218 const struct comedi_cmd *cmd);
1219
driver_cb_pcidas_pci_probe(struct pci_dev * dev,const struct pci_device_id * ent)1220 static int __devinit driver_cb_pcidas_pci_probe(struct pci_dev *dev,
1221 const struct pci_device_id *ent)
1222 {
1223 return comedi_pci_auto_config(dev, driver_cb_pcidas.driver_name);
1224 }
1225
driver_cb_pcidas_pci_remove(struct pci_dev * dev)1226 static void __devexit driver_cb_pcidas_pci_remove(struct pci_dev *dev)
1227 {
1228 comedi_pci_auto_unconfig(dev);
1229 }
1230
1231 static struct pci_driver driver_cb_pcidas_pci_driver = {
1232 .id_table = pcidas64_pci_table,
1233 .probe = &driver_cb_pcidas_pci_probe,
1234 .remove = __devexit_p(&driver_cb_pcidas_pci_remove)
1235 };
1236
driver_cb_pcidas_init_module(void)1237 static int __init driver_cb_pcidas_init_module(void)
1238 {
1239 int retval;
1240
1241 retval = comedi_driver_register(&driver_cb_pcidas);
1242 if (retval < 0)
1243 return retval;
1244
1245 driver_cb_pcidas_pci_driver.name = (char *)driver_cb_pcidas.driver_name;
1246 return pci_register_driver(&driver_cb_pcidas_pci_driver);
1247 }
1248
driver_cb_pcidas_cleanup_module(void)1249 static void __exit driver_cb_pcidas_cleanup_module(void)
1250 {
1251 pci_unregister_driver(&driver_cb_pcidas_pci_driver);
1252 comedi_driver_unregister(&driver_cb_pcidas);
1253 }
1254
1255 module_init(driver_cb_pcidas_init_module);
1256 module_exit(driver_cb_pcidas_cleanup_module);
1257
ai_range_bits_6xxx(const struct comedi_device * dev,unsigned int range_index)1258 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1259 unsigned int range_index)
1260 {
1261 const struct comedi_krange *range =
1262 &board(dev)->ai_range_table->range[range_index];
1263 unsigned int bits = 0;
1264
1265 switch (range->max) {
1266 case 10000000:
1267 bits = 0x000;
1268 break;
1269 case 5000000:
1270 bits = 0x100;
1271 break;
1272 case 2000000:
1273 case 2500000:
1274 bits = 0x200;
1275 break;
1276 case 1000000:
1277 case 1250000:
1278 bits = 0x300;
1279 break;
1280 case 500000:
1281 bits = 0x400;
1282 break;
1283 case 200000:
1284 case 250000:
1285 bits = 0x500;
1286 break;
1287 case 100000:
1288 bits = 0x600;
1289 break;
1290 case 50000:
1291 bits = 0x700;
1292 break;
1293 default:
1294 comedi_error(dev, "bug! in ai_range_bits_6xxx");
1295 break;
1296 }
1297 if (range->min == 0)
1298 bits += 0x900;
1299 return bits;
1300 }
1301
hw_revision(const struct comedi_device * dev,uint16_t hw_status_bits)1302 static unsigned int hw_revision(const struct comedi_device *dev,
1303 uint16_t hw_status_bits)
1304 {
1305 if (board(dev)->layout == LAYOUT_4020)
1306 return (hw_status_bits >> 13) & 0x7;
1307
1308 return (hw_status_bits >> 12) & 0xf;
1309 }
1310
set_dac_range_bits(struct comedi_device * dev,volatile uint16_t * bits,unsigned int channel,unsigned int range)1311 static void set_dac_range_bits(struct comedi_device *dev,
1312 volatile uint16_t * bits, unsigned int channel,
1313 unsigned int range)
1314 {
1315 unsigned int code = board(dev)->ao_range_code[range];
1316
1317 if (channel > 1)
1318 comedi_error(dev, "bug! bad channel?");
1319 if (code & ~0x3)
1320 comedi_error(dev, "bug! bad range code?");
1321
1322 *bits &= ~(0x3 << (2 * channel));
1323 *bits |= code << (2 * channel);
1324 };
1325
ao_cmd_is_supported(const struct pcidas64_board * board)1326 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1327 {
1328 return board->ao_nchan && board->layout != LAYOUT_4020;
1329 }
1330
1331 /* initialize plx9080 chip */
init_plx9080(struct comedi_device * dev)1332 static void init_plx9080(struct comedi_device *dev)
1333 {
1334 uint32_t bits;
1335 void __iomem *plx_iobase = priv(dev)->plx9080_iobase;
1336
1337 priv(dev)->plx_control_bits =
1338 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG);
1339
1340 /* plx9080 dump */
1341 DEBUG_PRINT(" plx interrupt status 0x%x\n",
1342 readl(plx_iobase + PLX_INTRCS_REG));
1343 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
1344 DEBUG_PRINT(" plx control reg 0x%x\n", priv(dev)->plx_control_bits);
1345 DEBUG_PRINT(" plx mode/arbitration reg 0x%x\n",
1346 readl(plx_iobase + PLX_MARB_REG));
1347 DEBUG_PRINT(" plx region0 reg 0x%x\n",
1348 readl(plx_iobase + PLX_REGION0_REG));
1349 DEBUG_PRINT(" plx region1 reg 0x%x\n",
1350 readl(plx_iobase + PLX_REGION1_REG));
1351
1352 DEBUG_PRINT(" plx revision 0x%x\n",
1353 readl(plx_iobase + PLX_REVISION_REG));
1354 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
1355 readl(plx_iobase + PLX_DMA0_MODE_REG));
1356 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
1357 readl(plx_iobase + PLX_DMA1_MODE_REG));
1358 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
1359 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
1360 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
1361 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
1362 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
1363 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
1364 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
1365 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
1366 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
1367 readb(plx_iobase + PLX_DMA0_CS_REG));
1368 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
1369 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
1370 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
1371
1372 #ifdef __BIG_ENDIAN
1373 bits = BIGEND_DMA0 | BIGEND_DMA1;
1374 #else
1375 bits = 0;
1376 #endif
1377 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
1378
1379 disable_plx_interrupts(dev);
1380
1381 abort_dma(dev, 0);
1382 abort_dma(dev, 1);
1383
1384 /* configure dma0 mode */
1385 bits = 0;
1386 /* enable ready input, not sure if this is necessary */
1387 bits |= PLX_DMA_EN_READYIN_BIT;
1388 /* enable bterm, not sure if this is necessary */
1389 bits |= PLX_EN_BTERM_BIT;
1390 /* enable dma chaining */
1391 bits |= PLX_EN_CHAIN_BIT;
1392 /* enable interrupt on dma done (probably don't need this, since chain never finishes) */
1393 bits |= PLX_EN_DMA_DONE_INTR_BIT;
1394 /* don't increment local address during transfers (we are transferring from a fixed fifo register) */
1395 bits |= PLX_LOCAL_ADDR_CONST_BIT;
1396 /* route dma interrupt to pci bus */
1397 bits |= PLX_DMA_INTR_PCI_BIT;
1398 /* enable demand mode */
1399 bits |= PLX_DEMAND_MODE_BIT;
1400 /* enable local burst mode */
1401 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1402 /* 4020 uses 32 bit dma */
1403 if (board(dev)->layout == LAYOUT_4020) {
1404 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1405 } else { /* localspace0 bus is 16 bits wide */
1406 bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1407 }
1408 writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1409 if (ao_cmd_is_supported(board(dev)))
1410 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1411
1412 /* enable interrupts on plx 9080 */
1413 priv(dev)->plx_intcsr_bits |=
1414 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1415 ICS_DMA0_E | ICS_DMA1_E;
1416 writel(priv(dev)->plx_intcsr_bits,
1417 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1418 }
1419
1420 /* Allocate and initialize the subdevice structures.
1421 */
setup_subdevices(struct comedi_device * dev)1422 static int setup_subdevices(struct comedi_device *dev)
1423 {
1424 struct comedi_subdevice *s;
1425 void __iomem *dio_8255_iobase;
1426 int i;
1427
1428 if (alloc_subdevices(dev, 10) < 0)
1429 return -ENOMEM;
1430
1431 s = dev->subdevices + 0;
1432 /* analog input subdevice */
1433 dev->read_subdev = s;
1434 s->type = COMEDI_SUBD_AI;
1435 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
1436 if (board(dev)->layout == LAYOUT_60XX)
1437 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
1438 else if (board(dev)->layout == LAYOUT_64XX)
1439 s->subdev_flags |= SDF_DIFF;
1440 /* XXX Number of inputs in differential mode is ignored */
1441 s->n_chan = board(dev)->ai_se_chans;
1442 s->len_chanlist = 0x2000;
1443 s->maxdata = (1 << board(dev)->ai_bits) - 1;
1444 s->range_table = board(dev)->ai_range_table;
1445 s->insn_read = ai_rinsn;
1446 s->insn_config = ai_config_insn;
1447 s->do_cmd = ai_cmd;
1448 s->do_cmdtest = ai_cmdtest;
1449 s->cancel = ai_cancel;
1450 if (board(dev)->layout == LAYOUT_4020) {
1451 uint8_t data;
1452 /* set adc to read from inputs (not internal calibration sources) */
1453 priv(dev)->i2c_cal_range_bits = adc_src_4020_bits(4);
1454 /* set channels to +-5 volt input ranges */
1455 for (i = 0; i < s->n_chan; i++)
1456 priv(dev)->i2c_cal_range_bits |= attenuate_bit(i);
1457 data = priv(dev)->i2c_cal_range_bits;
1458 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
1459 }
1460
1461 /* analog output subdevice */
1462 s = dev->subdevices + 1;
1463 if (board(dev)->ao_nchan) {
1464 s->type = COMEDI_SUBD_AO;
1465 s->subdev_flags =
1466 SDF_READABLE | SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1467 s->n_chan = board(dev)->ao_nchan;
1468 s->maxdata = (1 << board(dev)->ao_bits) - 1;
1469 s->range_table = board(dev)->ao_range_table;
1470 s->insn_read = ao_readback_insn;
1471 s->insn_write = ao_winsn;
1472 if (ao_cmd_is_supported(board(dev))) {
1473 dev->write_subdev = s;
1474 s->do_cmdtest = ao_cmdtest;
1475 s->do_cmd = ao_cmd;
1476 s->len_chanlist = board(dev)->ao_nchan;
1477 s->cancel = ao_cancel;
1478 }
1479 } else {
1480 s->type = COMEDI_SUBD_UNUSED;
1481 }
1482
1483 /* digital input */
1484 s = dev->subdevices + 2;
1485 if (board(dev)->layout == LAYOUT_64XX) {
1486 s->type = COMEDI_SUBD_DI;
1487 s->subdev_flags = SDF_READABLE;
1488 s->n_chan = 4;
1489 s->maxdata = 1;
1490 s->range_table = &range_digital;
1491 s->insn_bits = di_rbits;
1492 } else
1493 s->type = COMEDI_SUBD_UNUSED;
1494
1495 /* digital output */
1496 if (board(dev)->layout == LAYOUT_64XX) {
1497 s = dev->subdevices + 3;
1498 s->type = COMEDI_SUBD_DO;
1499 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1500 s->n_chan = 4;
1501 s->maxdata = 1;
1502 s->range_table = &range_digital;
1503 s->insn_bits = do_wbits;
1504 } else
1505 s->type = COMEDI_SUBD_UNUSED;
1506
1507 /* 8255 */
1508 s = dev->subdevices + 4;
1509 if (board(dev)->has_8255) {
1510 if (board(dev)->layout == LAYOUT_4020) {
1511 dio_8255_iobase =
1512 priv(dev)->main_iobase + I8255_4020_REG;
1513 subdev_8255_init(dev, s, dio_callback_4020,
1514 (unsigned long)dio_8255_iobase);
1515 } else {
1516 dio_8255_iobase =
1517 priv(dev)->dio_counter_iobase + DIO_8255_OFFSET;
1518 subdev_8255_init(dev, s, dio_callback,
1519 (unsigned long)dio_8255_iobase);
1520 }
1521 } else
1522 s->type = COMEDI_SUBD_UNUSED;
1523
1524 /* 8 channel dio for 60xx */
1525 s = dev->subdevices + 5;
1526 if (board(dev)->layout == LAYOUT_60XX) {
1527 s->type = COMEDI_SUBD_DIO;
1528 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
1529 s->n_chan = 8;
1530 s->maxdata = 1;
1531 s->range_table = &range_digital;
1532 s->insn_config = dio_60xx_config_insn;
1533 s->insn_bits = dio_60xx_wbits;
1534 } else
1535 s->type = COMEDI_SUBD_UNUSED;
1536
1537 /* caldac */
1538 s = dev->subdevices + 6;
1539 s->type = COMEDI_SUBD_CALIB;
1540 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1541 s->n_chan = 8;
1542 if (board(dev)->layout == LAYOUT_4020)
1543 s->maxdata = 0xfff;
1544 else
1545 s->maxdata = 0xff;
1546 s->insn_read = calib_read_insn;
1547 s->insn_write = calib_write_insn;
1548 for (i = 0; i < s->n_chan; i++)
1549 caldac_write(dev, i, s->maxdata / 2);
1550
1551 /* 2 channel ad8402 potentiometer */
1552 s = dev->subdevices + 7;
1553 if (board(dev)->layout == LAYOUT_64XX) {
1554 s->type = COMEDI_SUBD_CALIB;
1555 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
1556 s->n_chan = 2;
1557 s->insn_read = ad8402_read_insn;
1558 s->insn_write = ad8402_write_insn;
1559 s->maxdata = 0xff;
1560 for (i = 0; i < s->n_chan; i++)
1561 ad8402_write(dev, i, s->maxdata / 2);
1562 } else
1563 s->type = COMEDI_SUBD_UNUSED;
1564
1565 /* serial EEPROM, if present */
1566 s = dev->subdevices + 8;
1567 if (readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
1568 s->type = COMEDI_SUBD_MEMORY;
1569 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
1570 s->n_chan = 128;
1571 s->maxdata = 0xffff;
1572 s->insn_read = eeprom_read_insn;
1573 } else
1574 s->type = COMEDI_SUBD_UNUSED;
1575
1576 /* user counter subd XXX */
1577 s = dev->subdevices + 9;
1578 s->type = COMEDI_SUBD_UNUSED;
1579
1580 return 0;
1581 }
1582
disable_plx_interrupts(struct comedi_device * dev)1583 static void disable_plx_interrupts(struct comedi_device *dev)
1584 {
1585 priv(dev)->plx_intcsr_bits = 0;
1586 writel(priv(dev)->plx_intcsr_bits,
1587 priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
1588 }
1589
init_stc_registers(struct comedi_device * dev)1590 static void init_stc_registers(struct comedi_device *dev)
1591 {
1592 uint16_t bits;
1593 unsigned long flags;
1594
1595 spin_lock_irqsave(&dev->spinlock, flags);
1596
1597 /* bit should be set for 6025, although docs say boards with <= 16 chans should be cleared XXX */
1598 if (1)
1599 priv(dev)->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1600 writew(priv(dev)->adc_control1_bits,
1601 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1602
1603 /* 6402/16 manual says this register must be initialized to 0xff? */
1604 writew(0xff, priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1605
1606 bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1607 if (board(dev)->layout == LAYOUT_4020)
1608 bits |= INTERNAL_CLOCK_4020_BITS;
1609 priv(dev)->hw_config_bits |= bits;
1610 writew(priv(dev)->hw_config_bits,
1611 priv(dev)->main_iobase + HW_CONFIG_REG);
1612
1613 writew(0, priv(dev)->main_iobase + DAQ_SYNC_REG);
1614 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1615
1616 spin_unlock_irqrestore(&dev->spinlock, flags);
1617
1618 /* set fifos to maximum size */
1619 priv(dev)->fifo_size_bits |= DAC_FIFO_BITS;
1620 set_ai_fifo_segment_length(dev,
1621 board(dev)->ai_fifo->max_segment_length);
1622
1623 priv(dev)->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1624 priv(dev)->intr_enable_bits = /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1625 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1626 writew(priv(dev)->intr_enable_bits,
1627 priv(dev)->main_iobase + INTR_ENABLE_REG);
1628
1629 disable_ai_pacing(dev);
1630 };
1631
alloc_and_init_dma_members(struct comedi_device * dev)1632 static int alloc_and_init_dma_members(struct comedi_device *dev)
1633 {
1634 int i;
1635
1636 /* alocate pci dma buffers */
1637 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1638 priv(dev)->ai_buffer[i] =
1639 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
1640 &priv(dev)->ai_buffer_bus_addr[i]);
1641 if (priv(dev)->ai_buffer[i] == NULL)
1642 return -ENOMEM;
1643
1644 }
1645 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1646 if (ao_cmd_is_supported(board(dev))) {
1647 priv(dev)->ao_buffer[i] =
1648 pci_alloc_consistent(priv(dev)->hw_dev,
1649 DMA_BUFFER_SIZE,
1650 &priv(dev)->
1651 ao_buffer_bus_addr[i]);
1652 if (priv(dev)->ao_buffer[i] == NULL)
1653 return -ENOMEM;
1654
1655 }
1656 }
1657 /* allocate dma descriptors */
1658 priv(dev)->ai_dma_desc =
1659 pci_alloc_consistent(priv(dev)->hw_dev,
1660 sizeof(struct plx_dma_desc) *
1661 ai_dma_ring_count(board(dev)),
1662 &priv(dev)->ai_dma_desc_bus_addr);
1663 if (priv(dev)->ai_dma_desc == NULL)
1664 return -ENOMEM;
1665
1666 DEBUG_PRINT("ai dma descriptors start at bus addr 0x%x\n",
1667 priv(dev)->ai_dma_desc_bus_addr);
1668 if (ao_cmd_is_supported(board(dev))) {
1669 priv(dev)->ao_dma_desc =
1670 pci_alloc_consistent(priv(dev)->hw_dev,
1671 sizeof(struct plx_dma_desc) *
1672 AO_DMA_RING_COUNT,
1673 &priv(dev)->ao_dma_desc_bus_addr);
1674 if (priv(dev)->ao_dma_desc == NULL)
1675 return -ENOMEM;
1676
1677 DEBUG_PRINT("ao dma descriptors start at bus addr 0x%x\n",
1678 priv(dev)->ao_dma_desc_bus_addr);
1679 }
1680 /* initialize dma descriptors */
1681 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1682 priv(dev)->ai_dma_desc[i].pci_start_addr =
1683 cpu_to_le32(priv(dev)->ai_buffer_bus_addr[i]);
1684 if (board(dev)->layout == LAYOUT_4020)
1685 priv(dev)->ai_dma_desc[i].local_start_addr =
1686 cpu_to_le32(priv(dev)->local1_iobase +
1687 ADC_FIFO_REG);
1688 else
1689 priv(dev)->ai_dma_desc[i].local_start_addr =
1690 cpu_to_le32(priv(dev)->local0_iobase +
1691 ADC_FIFO_REG);
1692 priv(dev)->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1693 priv(dev)->ai_dma_desc[i].next =
1694 cpu_to_le32((priv(dev)->ai_dma_desc_bus_addr + ((i +
1695 1) %
1696 ai_dma_ring_count
1697 (board
1698 (dev))) *
1699 sizeof(priv(dev)->ai_dma_desc[0])) |
1700 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1701 PLX_XFER_LOCAL_TO_PCI);
1702 }
1703 if (ao_cmd_is_supported(board(dev))) {
1704 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1705 priv(dev)->ao_dma_desc[i].pci_start_addr =
1706 cpu_to_le32(priv(dev)->ao_buffer_bus_addr[i]);
1707 priv(dev)->ao_dma_desc[i].local_start_addr =
1708 cpu_to_le32(priv(dev)->local0_iobase +
1709 DAC_FIFO_REG);
1710 priv(dev)->ao_dma_desc[i].transfer_size =
1711 cpu_to_le32(0);
1712 priv(dev)->ao_dma_desc[i].next =
1713 cpu_to_le32((priv(dev)->ao_dma_desc_bus_addr +
1714 ((i + 1) % (AO_DMA_RING_COUNT)) *
1715 sizeof(priv(dev)->ao_dma_desc[0])) |
1716 PLX_DESC_IN_PCI_BIT |
1717 PLX_INTR_TERM_COUNT);
1718 }
1719 }
1720 return 0;
1721 }
1722
warn_external_queue(struct comedi_device * dev)1723 static inline void warn_external_queue(struct comedi_device *dev)
1724 {
1725 comedi_error(dev,
1726 "AO command and AI external channel queue cannot be used simultaneously.");
1727 comedi_error(dev,
1728 "Use internal AI channel queue (channels must be consecutive and use same range/aref)");
1729 }
1730
1731 /*
1732 * Attach is called by the Comedi core to configure the driver
1733 * for a particular board.
1734 */
attach(struct comedi_device * dev,struct comedi_devconfig * it)1735 static int attach(struct comedi_device *dev, struct comedi_devconfig *it)
1736 {
1737 struct pci_dev *pcidev = NULL;
1738 int index;
1739 uint32_t local_range, local_decode;
1740 int retval;
1741
1742 /*
1743 * Allocate the private structure area.
1744 */
1745 if (alloc_private(dev, sizeof(struct pcidas64_private)) < 0)
1746 return -ENOMEM;
1747
1748 /*
1749 * Probe the device to determine what device in the series it is.
1750 */
1751
1752 for_each_pci_dev(pcidev) {
1753 /* is it not a computer boards card? */
1754 if (pcidev->vendor != PCI_VENDOR_ID_COMPUTERBOARDS)
1755 continue;
1756 /* loop through cards supported by this driver */
1757 for (index = 0; index < ARRAY_SIZE(pcidas64_boards); index++) {
1758 if (pcidas64_boards[index].device_id != pcidev->device)
1759 continue;
1760 /* was a particular bus/slot requested? */
1761 if (it->options[0] || it->options[1]) {
1762 /* are we on the wrong bus/slot? */
1763 if (pcidev->bus->number != it->options[0] ||
1764 PCI_SLOT(pcidev->devfn) != it->options[1]) {
1765 continue;
1766 }
1767 }
1768 priv(dev)->hw_dev = pcidev;
1769 dev->board_ptr = pcidas64_boards + index;
1770 break;
1771 }
1772 if (dev->board_ptr)
1773 break;
1774 }
1775
1776 if (dev->board_ptr == NULL) {
1777 printk
1778 ("No supported ComputerBoards/MeasurementComputing card found\n");
1779 return -EIO;
1780 }
1781
1782 dev_dbg(dev->hw_dev, "Found %s on bus %i, slot %i\n", board(dev)->name,
1783 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
1784
1785 if (comedi_pci_enable(pcidev, driver_cb_pcidas.driver_name)) {
1786 dev_warn(dev->hw_dev, "failed to enable PCI device and request regions\n");
1787 return -EIO;
1788 }
1789 pci_set_master(pcidev);
1790
1791 /* Initialize dev->board_name */
1792 dev->board_name = board(dev)->name;
1793
1794 priv(dev)->plx9080_phys_iobase =
1795 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
1796 priv(dev)->main_phys_iobase =
1797 pci_resource_start(pcidev, MAIN_BADDRINDEX);
1798 priv(dev)->dio_counter_phys_iobase =
1799 pci_resource_start(pcidev, DIO_COUNTER_BADDRINDEX);
1800
1801 /* remap, won't work with 2.0 kernels but who cares */
1802 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
1803 pci_resource_len(pcidev,
1804 PLX9080_BADDRINDEX));
1805 priv(dev)->main_iobase =
1806 ioremap(priv(dev)->main_phys_iobase,
1807 pci_resource_len(pcidev, MAIN_BADDRINDEX));
1808 priv(dev)->dio_counter_iobase =
1809 ioremap(priv(dev)->dio_counter_phys_iobase,
1810 pci_resource_len(pcidev, DIO_COUNTER_BADDRINDEX));
1811
1812 if (!priv(dev)->plx9080_iobase || !priv(dev)->main_iobase
1813 || !priv(dev)->dio_counter_iobase) {
1814 dev_warn(dev->hw_dev, "failed to remap io memory\n");
1815 return -ENOMEM;
1816 }
1817
1818 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
1819 DEBUG_PRINT(" main remapped to 0x%p\n", priv(dev)->main_iobase);
1820 DEBUG_PRINT(" diocounter remapped to 0x%p\n",
1821 priv(dev)->dio_counter_iobase);
1822
1823 /* figure out what local addresses are */
1824 local_range =
1825 readl(priv(dev)->plx9080_iobase + PLX_LAS0RNG_REG) & LRNG_MEM_MASK;
1826 local_decode =
1827 readl(priv(dev)->plx9080_iobase +
1828 PLX_LAS0MAP_REG) & local_range & LMAP_MEM_MASK;
1829 priv(dev)->local0_iobase =
1830 ((uint32_t) priv(dev)->main_phys_iobase & ~local_range) |
1831 local_decode;
1832 local_range =
1833 readl(priv(dev)->plx9080_iobase + PLX_LAS1RNG_REG) & LRNG_MEM_MASK;
1834 local_decode =
1835 readl(priv(dev)->plx9080_iobase +
1836 PLX_LAS1MAP_REG) & local_range & LMAP_MEM_MASK;
1837 priv(dev)->local1_iobase =
1838 ((uint32_t) priv(dev)->dio_counter_phys_iobase & ~local_range) |
1839 local_decode;
1840
1841 DEBUG_PRINT(" local 0 io addr 0x%x\n", priv(dev)->local0_iobase);
1842 DEBUG_PRINT(" local 1 io addr 0x%x\n", priv(dev)->local1_iobase);
1843
1844 retval = alloc_and_init_dma_members(dev);
1845 if (retval < 0)
1846 return retval;
1847
1848 priv(dev)->hw_revision =
1849 hw_revision(dev, readw(priv(dev)->main_iobase + HW_STATUS_REG));
1850 dev_dbg(dev->hw_dev, "stc hardware revision %i\n",
1851 priv(dev)->hw_revision);
1852 init_plx9080(dev);
1853 init_stc_registers(dev);
1854 /* get irq */
1855 if (request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
1856 "cb_pcidas64", dev)) {
1857 dev_dbg(dev->hw_dev, "unable to allocate irq %u\n",
1858 pcidev->irq);
1859 return -EINVAL;
1860 }
1861 dev->irq = pcidev->irq;
1862 dev_dbg(dev->hw_dev, "irq %u\n", dev->irq);
1863
1864 retval = setup_subdevices(dev);
1865 if (retval < 0)
1866 return retval;
1867
1868
1869 return 0;
1870 }
1871
1872 /*
1873 * _detach is called to deconfigure a device. It should deallocate
1874 * resources.
1875 * This function is also called when _attach() fails, so it should be
1876 * careful not to release resources that were not necessarily
1877 * allocated by _attach(). dev->private and dev->subdevices are
1878 * deallocated automatically by the core.
1879 */
detach(struct comedi_device * dev)1880 static int detach(struct comedi_device *dev)
1881 {
1882 unsigned int i;
1883
1884 if (dev->irq)
1885 free_irq(dev->irq, dev);
1886 if (priv(dev)) {
1887 if (priv(dev)->hw_dev) {
1888 if (priv(dev)->plx9080_iobase) {
1889 disable_plx_interrupts(dev);
1890 iounmap(priv(dev)->plx9080_iobase);
1891 }
1892 if (priv(dev)->main_iobase)
1893 iounmap(priv(dev)->main_iobase);
1894 if (priv(dev)->dio_counter_iobase)
1895 iounmap(priv(dev)->dio_counter_iobase);
1896 /* free pci dma buffers */
1897 for (i = 0; i < ai_dma_ring_count(board(dev)); i++) {
1898 if (priv(dev)->ai_buffer[i])
1899 pci_free_consistent(priv(dev)->hw_dev,
1900 DMA_BUFFER_SIZE,
1901 priv(dev)->
1902 ai_buffer[i],
1903 priv
1904 (dev)->ai_buffer_bus_addr
1905 [i]);
1906 }
1907 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1908 if (priv(dev)->ao_buffer[i])
1909 pci_free_consistent(priv(dev)->hw_dev,
1910 DMA_BUFFER_SIZE,
1911 priv(dev)->
1912 ao_buffer[i],
1913 priv
1914 (dev)->ao_buffer_bus_addr
1915 [i]);
1916 }
1917 /* free dma descriptors */
1918 if (priv(dev)->ai_dma_desc)
1919 pci_free_consistent(priv(dev)->hw_dev,
1920 sizeof(struct plx_dma_desc)
1921 *
1922 ai_dma_ring_count(board
1923 (dev)),
1924 priv(dev)->ai_dma_desc,
1925 priv(dev)->
1926 ai_dma_desc_bus_addr);
1927 if (priv(dev)->ao_dma_desc)
1928 pci_free_consistent(priv(dev)->hw_dev,
1929 sizeof(struct plx_dma_desc)
1930 * AO_DMA_RING_COUNT,
1931 priv(dev)->ao_dma_desc,
1932 priv(dev)->
1933 ao_dma_desc_bus_addr);
1934 if (priv(dev)->main_phys_iobase)
1935 comedi_pci_disable(priv(dev)->hw_dev);
1936
1937 pci_dev_put(priv(dev)->hw_dev);
1938 }
1939 }
1940 if (dev->subdevices)
1941 subdev_8255_cleanup(dev, dev->subdevices + 4);
1942
1943 return 0;
1944 }
1945
ai_rinsn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)1946 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1947 struct comedi_insn *insn, unsigned int *data)
1948 {
1949 unsigned int bits = 0, n, i;
1950 unsigned int channel, range, aref;
1951 unsigned long flags;
1952 static const int timeout = 100;
1953
1954 DEBUG_PRINT("chanspec 0x%x\n", insn->chanspec);
1955 channel = CR_CHAN(insn->chanspec);
1956 range = CR_RANGE(insn->chanspec);
1957 aref = CR_AREF(insn->chanspec);
1958
1959 /* disable card's analog input interrupt sources and pacing */
1960 /* 4020 generates dac done interrupts even though they are disabled */
1961 disable_ai_pacing(dev);
1962
1963 spin_lock_irqsave(&dev->spinlock, flags);
1964 if (insn->chanspec & CR_ALT_FILTER)
1965 priv(dev)->adc_control1_bits |= ADC_DITHER_BIT;
1966 else
1967 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
1968 writew(priv(dev)->adc_control1_bits,
1969 priv(dev)->main_iobase + ADC_CONTROL1_REG);
1970 spin_unlock_irqrestore(&dev->spinlock, flags);
1971
1972 if (board(dev)->layout != LAYOUT_4020) {
1973 /* use internal queue */
1974 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
1975 writew(priv(dev)->hw_config_bits,
1976 priv(dev)->main_iobase + HW_CONFIG_REG);
1977
1978 /* ALT_SOURCE is internal calibration reference */
1979 if (insn->chanspec & CR_ALT_SOURCE) {
1980 unsigned int cal_en_bit;
1981
1982 DEBUG_PRINT("reading calibration source\n");
1983 if (board(dev)->layout == LAYOUT_60XX)
1984 cal_en_bit = CAL_EN_60XX_BIT;
1985 else
1986 cal_en_bit = CAL_EN_64XX_BIT;
1987 /* select internal reference source to connect to channel 0 */
1988 writew(cal_en_bit |
1989 adc_src_bits(priv(dev)->calibration_source),
1990 priv(dev)->main_iobase + CALIBRATION_REG);
1991 } else {
1992 /* make sure internal calibration source is turned off */
1993 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
1994 }
1995 /* load internal queue */
1996 bits = 0;
1997 /* set gain */
1998 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1999 /* set single-ended / differential */
2000 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
2001 if (aref == AREF_COMMON)
2002 bits |= ADC_COMMON_BIT;
2003 bits |= adc_chan_bits(channel);
2004 /* set stop channel */
2005 writew(adc_chan_bits(channel),
2006 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2007 /* set start channel, and rest of settings */
2008 writew(bits, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2009 } else {
2010 uint8_t old_cal_range_bits = priv(dev)->i2c_cal_range_bits;
2011
2012 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2013 if (insn->chanspec & CR_ALT_SOURCE) {
2014 DEBUG_PRINT("reading calibration source\n");
2015 priv(dev)->i2c_cal_range_bits |=
2016 adc_src_4020_bits(priv(dev)->calibration_source);
2017 } else { /* select BNC inputs */
2018 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2019 }
2020 /* select range */
2021 if (range == 0)
2022 priv(dev)->i2c_cal_range_bits |= attenuate_bit(channel);
2023 else
2024 priv(dev)->i2c_cal_range_bits &=
2025 ~attenuate_bit(channel);
2026 /* update calibration/range i2c register only if necessary, as it is very slow */
2027 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2028 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2029 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2030 sizeof(i2c_data));
2031 }
2032
2033 /* 4020 manual asks that sample interval register to be set before writing to convert register.
2034 * Using somewhat arbitrary setting of 4 master clock ticks = 0.1 usec */
2035 writew(0,
2036 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2037 writew(2,
2038 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2039 }
2040
2041 for (n = 0; n < insn->n; n++) {
2042
2043 /* clear adc buffer (inside loop for 4020 sake) */
2044 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2045
2046 /* trigger conversion, bits sent only matter for 4020 */
2047 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
2048 priv(dev)->main_iobase + ADC_CONVERT_REG);
2049
2050 /* wait for data */
2051 for (i = 0; i < timeout; i++) {
2052 bits = readw(priv(dev)->main_iobase + HW_STATUS_REG);
2053 DEBUG_PRINT(" pipe bits 0x%x\n", pipe_full_bits(bits));
2054 if (board(dev)->layout == LAYOUT_4020) {
2055 if (readw(priv(dev)->main_iobase +
2056 ADC_WRITE_PNTR_REG))
2057 break;
2058 } else {
2059 if (pipe_full_bits(bits))
2060 break;
2061 }
2062 udelay(1);
2063 }
2064 DEBUG_PRINT(" looped %i times waiting for data\n", i);
2065 if (i == timeout) {
2066 comedi_error(dev, " analog input read insn timed out");
2067 printk(" status 0x%x\n", bits);
2068 return -ETIME;
2069 }
2070 if (board(dev)->layout == LAYOUT_4020)
2071 data[n] =
2072 readl(priv(dev)->dio_counter_iobase +
2073 ADC_FIFO_REG) & 0xffff;
2074 else
2075 data[n] =
2076 readw(priv(dev)->main_iobase + PIPE1_READ_REG);
2077 }
2078
2079 return n;
2080 }
2081
ai_config_calibration_source(struct comedi_device * dev,unsigned int * data)2082 static int ai_config_calibration_source(struct comedi_device *dev,
2083 unsigned int *data)
2084 {
2085 unsigned int source = data[1];
2086 int num_calibration_sources;
2087
2088 if (board(dev)->layout == LAYOUT_60XX)
2089 num_calibration_sources = 16;
2090 else
2091 num_calibration_sources = 8;
2092 if (source >= num_calibration_sources) {
2093 dev_dbg(dev->hw_dev, "invalid calibration source: %i\n",
2094 source);
2095 return -EINVAL;
2096 }
2097
2098 DEBUG_PRINT("setting calibration source to %i\n", source);
2099 priv(dev)->calibration_source = source;
2100
2101 return 2;
2102 }
2103
ai_config_block_size(struct comedi_device * dev,unsigned int * data)2104 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
2105 {
2106 int fifo_size;
2107 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
2108 unsigned int block_size, requested_block_size;
2109 int retval;
2110
2111 requested_block_size = data[1];
2112
2113 if (requested_block_size) {
2114 fifo_size =
2115 requested_block_size * fifo->num_segments / bytes_in_sample;
2116
2117 retval = set_ai_fifo_size(dev, fifo_size);
2118 if (retval < 0)
2119 return retval;
2120
2121 }
2122
2123 block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
2124
2125 data[1] = block_size;
2126
2127 return 2;
2128 }
2129
ai_config_master_clock_4020(struct comedi_device * dev,unsigned int * data)2130 static int ai_config_master_clock_4020(struct comedi_device *dev,
2131 unsigned int *data)
2132 {
2133 unsigned int divisor = data[4];
2134 int retval = 0;
2135
2136 if (divisor < 2) {
2137 divisor = 2;
2138 retval = -EAGAIN;
2139 }
2140
2141 switch (data[1]) {
2142 case COMEDI_EV_SCAN_BEGIN:
2143 priv(dev)->ext_clock.divisor = divisor;
2144 priv(dev)->ext_clock.chanspec = data[2];
2145 break;
2146 default:
2147 return -EINVAL;
2148 break;
2149 }
2150
2151 data[4] = divisor;
2152
2153 return retval ? retval : 5;
2154 }
2155
2156 /* XXX could add support for 60xx series */
ai_config_master_clock(struct comedi_device * dev,unsigned int * data)2157 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
2158 {
2159
2160 switch (board(dev)->layout) {
2161 case LAYOUT_4020:
2162 return ai_config_master_clock_4020(dev, data);
2163 break;
2164 default:
2165 return -EINVAL;
2166 break;
2167 }
2168
2169 return -EINVAL;
2170 }
2171
ai_config_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)2172 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
2173 struct comedi_insn *insn, unsigned int *data)
2174 {
2175 int id = data[0];
2176
2177 switch (id) {
2178 case INSN_CONFIG_ALT_SOURCE:
2179 return ai_config_calibration_source(dev, data);
2180 break;
2181 case INSN_CONFIG_BLOCK_SIZE:
2182 return ai_config_block_size(dev, data);
2183 break;
2184 case INSN_CONFIG_TIMER_1:
2185 return ai_config_master_clock(dev, data);
2186 break;
2187 default:
2188 return -EINVAL;
2189 break;
2190 }
2191 return -EINVAL;
2192 }
2193
ai_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)2194 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2195 struct comedi_cmd *cmd)
2196 {
2197 int err = 0;
2198 int tmp;
2199 unsigned int tmp_arg, tmp_arg2;
2200 int i;
2201 int aref;
2202 unsigned int triggers;
2203
2204 /* step 1: make sure trigger sources are trivially valid */
2205
2206 tmp = cmd->start_src;
2207 cmd->start_src &= TRIG_NOW | TRIG_EXT;
2208 if (!cmd->start_src || tmp != cmd->start_src)
2209 err++;
2210
2211 tmp = cmd->scan_begin_src;
2212 triggers = TRIG_TIMER;
2213 if (board(dev)->layout == LAYOUT_4020)
2214 triggers |= TRIG_OTHER;
2215 else
2216 triggers |= TRIG_FOLLOW;
2217 cmd->scan_begin_src &= triggers;
2218 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
2219 err++;
2220
2221 tmp = cmd->convert_src;
2222 triggers = TRIG_TIMER;
2223 if (board(dev)->layout == LAYOUT_4020)
2224 triggers |= TRIG_NOW;
2225 else
2226 triggers |= TRIG_EXT;
2227 cmd->convert_src &= triggers;
2228 if (!cmd->convert_src || tmp != cmd->convert_src)
2229 err++;
2230
2231 tmp = cmd->scan_end_src;
2232 cmd->scan_end_src &= TRIG_COUNT;
2233 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
2234 err++;
2235
2236 tmp = cmd->stop_src;
2237 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
2238 if (!cmd->stop_src || tmp != cmd->stop_src)
2239 err++;
2240
2241 if (err)
2242 return 1;
2243
2244 /* step 2: make sure trigger sources are unique and mutually compatible */
2245
2246 /* uniqueness check */
2247 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
2248 err++;
2249 if (cmd->scan_begin_src != TRIG_TIMER &&
2250 cmd->scan_begin_src != TRIG_OTHER &&
2251 cmd->scan_begin_src != TRIG_FOLLOW)
2252 err++;
2253 if (cmd->convert_src != TRIG_TIMER &&
2254 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
2255 err++;
2256 if (cmd->stop_src != TRIG_COUNT &&
2257 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2258 err++;
2259
2260 /* compatibility check */
2261 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2262 err++;
2263 if (cmd->stop_src != TRIG_COUNT &&
2264 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
2265 err++;
2266
2267 if (err)
2268 return 2;
2269
2270 /* step 3: make sure arguments are trivially compatible */
2271
2272 if (cmd->convert_src == TRIG_TIMER) {
2273 if (board(dev)->layout == LAYOUT_4020) {
2274 if (cmd->convert_arg) {
2275 cmd->convert_arg = 0;
2276 err++;
2277 }
2278 } else {
2279 if (cmd->convert_arg < board(dev)->ai_speed) {
2280 cmd->convert_arg = board(dev)->ai_speed;
2281 err++;
2282 }
2283 if (cmd->scan_begin_src == TRIG_TIMER) {
2284 /* if scans are timed faster than conversion rate allows */
2285 if (cmd->convert_arg * cmd->chanlist_len >
2286 cmd->scan_begin_arg) {
2287 cmd->scan_begin_arg =
2288 cmd->convert_arg *
2289 cmd->chanlist_len;
2290 err++;
2291 }
2292 }
2293 }
2294 }
2295
2296 if (!cmd->chanlist_len) {
2297 cmd->chanlist_len = 1;
2298 err++;
2299 }
2300 if (cmd->scan_end_arg != cmd->chanlist_len) {
2301 cmd->scan_end_arg = cmd->chanlist_len;
2302 err++;
2303 }
2304
2305 switch (cmd->stop_src) {
2306 case TRIG_EXT:
2307 break;
2308 case TRIG_COUNT:
2309 if (!cmd->stop_arg) {
2310 cmd->stop_arg = 1;
2311 err++;
2312 }
2313 break;
2314 case TRIG_NONE:
2315 if (cmd->stop_arg != 0) {
2316 cmd->stop_arg = 0;
2317 err++;
2318 }
2319 break;
2320 default:
2321 break;
2322 }
2323
2324 if (err)
2325 return 3;
2326
2327 /* step 4: fix up any arguments */
2328
2329 if (cmd->convert_src == TRIG_TIMER) {
2330 tmp_arg = cmd->convert_arg;
2331 tmp_arg2 = cmd->scan_begin_arg;
2332 check_adc_timing(dev, cmd);
2333 if (tmp_arg != cmd->convert_arg)
2334 err++;
2335 if (tmp_arg2 != cmd->scan_begin_arg)
2336 err++;
2337 }
2338
2339 if (err)
2340 return 4;
2341
2342 /* make sure user is doesn't change analog reference mid chanlist */
2343 if (cmd->chanlist) {
2344 aref = CR_AREF(cmd->chanlist[0]);
2345 for (i = 1; i < cmd->chanlist_len; i++) {
2346 if (aref != CR_AREF(cmd->chanlist[i])) {
2347 comedi_error(dev,
2348 "all elements in chanlist must use the same analog reference");
2349 err++;
2350 break;
2351 }
2352 }
2353 /* check 4020 chanlist */
2354 if (board(dev)->layout == LAYOUT_4020) {
2355 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
2356 for (i = 1; i < cmd->chanlist_len; i++) {
2357 if (CR_CHAN(cmd->chanlist[i]) !=
2358 first_channel + i) {
2359 comedi_error(dev,
2360 "chanlist must use consecutive channels");
2361 err++;
2362 break;
2363 }
2364 }
2365 if (cmd->chanlist_len == 3) {
2366 comedi_error(dev,
2367 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels");
2368 err++;
2369 }
2370 }
2371 }
2372
2373 if (err)
2374 return 5;
2375
2376 return 0;
2377 }
2378
use_hw_sample_counter(struct comedi_cmd * cmd)2379 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2380 {
2381 /* disable for now until I work out a race */
2382 return 0;
2383
2384 if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2385 return 1;
2386 else
2387 return 0;
2388 }
2389
setup_sample_counters(struct comedi_device * dev,struct comedi_cmd * cmd)2390 static void setup_sample_counters(struct comedi_device *dev,
2391 struct comedi_cmd *cmd)
2392 {
2393 if (cmd->stop_src == TRIG_COUNT) {
2394 /* set software count */
2395 priv(dev)->ai_count = cmd->stop_arg * cmd->chanlist_len;
2396 }
2397 /* load hardware conversion counter */
2398 if (use_hw_sample_counter(cmd)) {
2399 writew(cmd->stop_arg & 0xffff,
2400 priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2401 writew((cmd->stop_arg >> 16) & 0xff,
2402 priv(dev)->main_iobase + ADC_COUNT_UPPER_REG);
2403 } else {
2404 writew(1, priv(dev)->main_iobase + ADC_COUNT_LOWER_REG);
2405 }
2406 }
2407
dma_transfer_size(struct comedi_device * dev)2408 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2409 {
2410 unsigned int num_samples;
2411
2412 num_samples =
2413 priv(dev)->ai_fifo_segment_length *
2414 board(dev)->ai_fifo->sample_packing_ratio;
2415 if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2416 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2417
2418 return num_samples;
2419 }
2420
disable_ai_pacing(struct comedi_device * dev)2421 static void disable_ai_pacing(struct comedi_device *dev)
2422 {
2423 unsigned long flags;
2424
2425 disable_ai_interrupts(dev);
2426
2427 spin_lock_irqsave(&dev->spinlock, flags);
2428 priv(dev)->adc_control1_bits &= ~ADC_SW_GATE_BIT;
2429 writew(priv(dev)->adc_control1_bits,
2430 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2431 spin_unlock_irqrestore(&dev->spinlock, flags);
2432
2433 /* disable pacing, triggering, etc */
2434 writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
2435 priv(dev)->main_iobase + ADC_CONTROL0_REG);
2436 }
2437
disable_ai_interrupts(struct comedi_device * dev)2438 static void disable_ai_interrupts(struct comedi_device *dev)
2439 {
2440 unsigned long flags;
2441
2442 spin_lock_irqsave(&dev->spinlock, flags);
2443 priv(dev)->intr_enable_bits &=
2444 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
2445 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
2446 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
2447 writew(priv(dev)->intr_enable_bits,
2448 priv(dev)->main_iobase + INTR_ENABLE_REG);
2449 spin_unlock_irqrestore(&dev->spinlock, flags);
2450
2451 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2452 }
2453
enable_ai_interrupts(struct comedi_device * dev,const struct comedi_cmd * cmd)2454 static void enable_ai_interrupts(struct comedi_device *dev,
2455 const struct comedi_cmd *cmd)
2456 {
2457 uint32_t bits;
2458 unsigned long flags;
2459
2460 bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
2461 EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
2462 /* Use pio transfer and interrupt on end of conversion if TRIG_WAKE_EOS flag is set. */
2463 if (cmd->flags & TRIG_WAKE_EOS) {
2464 /* 4020 doesn't support pio transfers except for fifo dregs */
2465 if (board(dev)->layout != LAYOUT_4020)
2466 bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
2467 }
2468 spin_lock_irqsave(&dev->spinlock, flags);
2469 priv(dev)->intr_enable_bits |= bits;
2470 writew(priv(dev)->intr_enable_bits,
2471 priv(dev)->main_iobase + INTR_ENABLE_REG);
2472 DEBUG_PRINT("intr enable bits 0x%x\n", priv(dev)->intr_enable_bits);
2473 spin_unlock_irqrestore(&dev->spinlock, flags);
2474 }
2475
ai_convert_counter_6xxx(const struct comedi_device * dev,const struct comedi_cmd * cmd)2476 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2477 const struct comedi_cmd *cmd)
2478 {
2479 /* supposed to load counter with desired divisor minus 3 */
2480 return cmd->convert_arg / TIMER_BASE - 3;
2481 }
2482
ai_scan_counter_6xxx(struct comedi_device * dev,struct comedi_cmd * cmd)2483 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2484 struct comedi_cmd *cmd)
2485 {
2486 uint32_t count;
2487 /* figure out how long we need to delay at end of scan */
2488 switch (cmd->scan_begin_src) {
2489 case TRIG_TIMER:
2490 count = (cmd->scan_begin_arg -
2491 (cmd->convert_arg * (cmd->chanlist_len - 1)))
2492 / TIMER_BASE;
2493 break;
2494 case TRIG_FOLLOW:
2495 count = cmd->convert_arg / TIMER_BASE;
2496 break;
2497 default:
2498 return 0;
2499 break;
2500 }
2501 return count - 3;
2502 }
2503
ai_convert_counter_4020(struct comedi_device * dev,struct comedi_cmd * cmd)2504 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2505 struct comedi_cmd *cmd)
2506 {
2507 unsigned int divisor;
2508
2509 switch (cmd->scan_begin_src) {
2510 case TRIG_TIMER:
2511 divisor = cmd->scan_begin_arg / TIMER_BASE;
2512 break;
2513 case TRIG_OTHER:
2514 divisor = priv(dev)->ext_clock.divisor;
2515 break;
2516 default: /* should never happen */
2517 comedi_error(dev, "bug! failed to set ai pacing!");
2518 divisor = 1000;
2519 break;
2520 }
2521
2522 /* supposed to load counter with desired divisor minus 2 for 4020 */
2523 return divisor - 2;
2524 }
2525
select_master_clock_4020(struct comedi_device * dev,const struct comedi_cmd * cmd)2526 static void select_master_clock_4020(struct comedi_device *dev,
2527 const struct comedi_cmd *cmd)
2528 {
2529 /* select internal/external master clock */
2530 priv(dev)->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2531 if (cmd->scan_begin_src == TRIG_OTHER) {
2532 int chanspec = priv(dev)->ext_clock.chanspec;
2533
2534 if (CR_CHAN(chanspec))
2535 priv(dev)->hw_config_bits |= BNC_CLOCK_4020_BITS;
2536 else
2537 priv(dev)->hw_config_bits |= EXT_CLOCK_4020_BITS;
2538 } else {
2539 priv(dev)->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2540 }
2541 writew(priv(dev)->hw_config_bits,
2542 priv(dev)->main_iobase + HW_CONFIG_REG);
2543 }
2544
select_master_clock(struct comedi_device * dev,const struct comedi_cmd * cmd)2545 static void select_master_clock(struct comedi_device *dev,
2546 const struct comedi_cmd *cmd)
2547 {
2548 switch (board(dev)->layout) {
2549 case LAYOUT_4020:
2550 select_master_clock_4020(dev, cmd);
2551 break;
2552 default:
2553 break;
2554 }
2555 }
2556
dma_start_sync(struct comedi_device * dev,unsigned int channel)2557 static inline void dma_start_sync(struct comedi_device *dev,
2558 unsigned int channel)
2559 {
2560 unsigned long flags;
2561
2562 /* spinlock for plx dma control/status reg */
2563 spin_lock_irqsave(&dev->spinlock, flags);
2564 if (channel)
2565 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2566 PLX_CLEAR_DMA_INTR_BIT,
2567 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
2568 else
2569 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2570 PLX_CLEAR_DMA_INTR_BIT,
2571 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
2572 spin_unlock_irqrestore(&dev->spinlock, flags);
2573 }
2574
set_ai_pacing(struct comedi_device * dev,struct comedi_cmd * cmd)2575 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2576 {
2577 uint32_t convert_counter = 0, scan_counter = 0;
2578
2579 check_adc_timing(dev, cmd);
2580
2581 select_master_clock(dev, cmd);
2582
2583 if (board(dev)->layout == LAYOUT_4020) {
2584 convert_counter = ai_convert_counter_4020(dev, cmd);
2585 } else {
2586 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2587 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2588 }
2589
2590 /* load lower 16 bits of convert interval */
2591 writew(convert_counter & 0xffff,
2592 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2593 DEBUG_PRINT("convert counter 0x%x\n", convert_counter);
2594 /* load upper 8 bits of convert interval */
2595 writew((convert_counter >> 16) & 0xff,
2596 priv(dev)->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2597 /* load lower 16 bits of scan delay */
2598 writew(scan_counter & 0xffff,
2599 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2600 /* load upper 8 bits of scan delay */
2601 writew((scan_counter >> 16) & 0xff,
2602 priv(dev)->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2603 DEBUG_PRINT("scan counter 0x%x\n", scan_counter);
2604 }
2605
use_internal_queue_6xxx(const struct comedi_cmd * cmd)2606 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2607 {
2608 int i;
2609 for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2610 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2611 CR_CHAN(cmd->chanlist[i]) + 1)
2612 return 0;
2613 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2614 CR_RANGE(cmd->chanlist[i]))
2615 return 0;
2616 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2617 return 0;
2618 }
2619 return 1;
2620 }
2621
setup_channel_queue(struct comedi_device * dev,const struct comedi_cmd * cmd)2622 static int setup_channel_queue(struct comedi_device *dev,
2623 const struct comedi_cmd *cmd)
2624 {
2625 unsigned short bits;
2626 int i;
2627
2628 if (board(dev)->layout != LAYOUT_4020) {
2629 if (use_internal_queue_6xxx(cmd)) {
2630 priv(dev)->hw_config_bits &= ~EXT_QUEUE_BIT;
2631 writew(priv(dev)->hw_config_bits,
2632 priv(dev)->main_iobase + HW_CONFIG_REG);
2633 bits = 0;
2634 /* set channel */
2635 bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2636 /* set gain */
2637 bits |= ai_range_bits_6xxx(dev,
2638 CR_RANGE(cmd->chanlist[0]));
2639 /* set single-ended / differential */
2640 bits |= se_diff_bit_6xxx(dev,
2641 CR_AREF(cmd->chanlist[0]) ==
2642 AREF_DIFF);
2643 if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2644 bits |= ADC_COMMON_BIT;
2645 /* set stop channel */
2646 writew(adc_chan_bits
2647 (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2648 priv(dev)->main_iobase + ADC_QUEUE_HIGH_REG);
2649 /* set start channel, and rest of settings */
2650 writew(bits,
2651 priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2652 } else {
2653 /* use external queue */
2654 if (dev->write_subdev && dev->write_subdev->busy) {
2655 warn_external_queue(dev);
2656 return -EBUSY;
2657 }
2658 priv(dev)->hw_config_bits |= EXT_QUEUE_BIT;
2659 writew(priv(dev)->hw_config_bits,
2660 priv(dev)->main_iobase + HW_CONFIG_REG);
2661 /* clear DAC buffer to prevent weird interactions */
2662 writew(0,
2663 priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
2664 /* clear queue pointer */
2665 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2666 /* load external queue */
2667 for (i = 0; i < cmd->chanlist_len; i++) {
2668 bits = 0;
2669 /* set channel */
2670 bits |=
2671 adc_chan_bits(CR_CHAN(cmd->chanlist[i]));
2672 /* set gain */
2673 bits |= ai_range_bits_6xxx(dev,
2674 CR_RANGE(cmd->
2675 chanlist
2676 [i]));
2677 /* set single-ended / differential */
2678 bits |= se_diff_bit_6xxx(dev,
2679 CR_AREF(cmd->
2680 chanlist[i]) ==
2681 AREF_DIFF);
2682 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2683 bits |= ADC_COMMON_BIT;
2684 /* mark end of queue */
2685 if (i == cmd->chanlist_len - 1)
2686 bits |= QUEUE_EOSCAN_BIT |
2687 QUEUE_EOSEQ_BIT;
2688 writew(bits,
2689 priv(dev)->main_iobase +
2690 ADC_QUEUE_FIFO_REG);
2691 DEBUG_PRINT
2692 ("wrote 0x%x to external channel queue\n",
2693 bits);
2694 }
2695 /* doing a queue clear is not specified in board docs,
2696 * but required for reliable operation */
2697 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
2698 /* prime queue holding register */
2699 writew(0, priv(dev)->main_iobase + ADC_QUEUE_LOAD_REG);
2700 }
2701 } else {
2702 unsigned short old_cal_range_bits =
2703 priv(dev)->i2c_cal_range_bits;
2704
2705 priv(dev)->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2706 /* select BNC inputs */
2707 priv(dev)->i2c_cal_range_bits |= adc_src_4020_bits(4);
2708 /* select ranges */
2709 for (i = 0; i < cmd->chanlist_len; i++) {
2710 unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2711 unsigned int range = CR_RANGE(cmd->chanlist[i]);
2712
2713 if (range == 0)
2714 priv(dev)->i2c_cal_range_bits |=
2715 attenuate_bit(channel);
2716 else
2717 priv(dev)->i2c_cal_range_bits &=
2718 ~attenuate_bit(channel);
2719 }
2720 /* update calibration/range i2c register only if necessary, as it is very slow */
2721 if (old_cal_range_bits != priv(dev)->i2c_cal_range_bits) {
2722 uint8_t i2c_data = priv(dev)->i2c_cal_range_bits;
2723 i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2724 sizeof(i2c_data));
2725 }
2726 }
2727 return 0;
2728 }
2729
load_first_dma_descriptor(struct comedi_device * dev,unsigned int dma_channel,unsigned int descriptor_bits)2730 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2731 unsigned int dma_channel,
2732 unsigned int descriptor_bits)
2733 {
2734 /* The transfer size, pci address, and local address registers
2735 * are supposedly unused during chained dma,
2736 * but I have found that left over values from last operation
2737 * occasionally cause problems with transfer of first dma
2738 * block. Initializing them to zero seems to fix the problem. */
2739 if (dma_channel) {
2740 writel(0,
2741 priv(dev)->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2742 writel(0, priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2743 writel(0,
2744 priv(dev)->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2745 writel(descriptor_bits,
2746 priv(dev)->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2747 } else {
2748 writel(0,
2749 priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2750 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2751 writel(0,
2752 priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2753 writel(descriptor_bits,
2754 priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2755 }
2756 }
2757
ai_cmd(struct comedi_device * dev,struct comedi_subdevice * s)2758 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2759 {
2760 struct comedi_async *async = s->async;
2761 struct comedi_cmd *cmd = &async->cmd;
2762 uint32_t bits;
2763 unsigned int i;
2764 unsigned long flags;
2765 int retval;
2766
2767 disable_ai_pacing(dev);
2768 abort_dma(dev, 1);
2769
2770 retval = setup_channel_queue(dev, cmd);
2771 if (retval < 0)
2772 return retval;
2773
2774 /* make sure internal calibration source is turned off */
2775 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
2776
2777 set_ai_pacing(dev, cmd);
2778
2779 setup_sample_counters(dev, cmd);
2780
2781 enable_ai_interrupts(dev, cmd);
2782
2783 spin_lock_irqsave(&dev->spinlock, flags);
2784 /* set mode, allow conversions through software gate */
2785 priv(dev)->adc_control1_bits |= ADC_SW_GATE_BIT;
2786 priv(dev)->adc_control1_bits &= ~ADC_DITHER_BIT;
2787 if (board(dev)->layout != LAYOUT_4020) {
2788 priv(dev)->adc_control1_bits &= ~ADC_MODE_MASK;
2789 if (cmd->convert_src == TRIG_EXT)
2790 priv(dev)->adc_control1_bits |= adc_mode_bits(13); /* good old mode 13 */
2791 else
2792 priv(dev)->adc_control1_bits |= adc_mode_bits(8); /* mode 8. What else could you need? */
2793 } else {
2794 priv(dev)->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2795 if (cmd->chanlist_len == 4)
2796 priv(dev)->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2797 else if (cmd->chanlist_len == 2)
2798 priv(dev)->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2799 priv(dev)->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2800 priv(dev)->adc_control1_bits |=
2801 adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2802 priv(dev)->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2803 priv(dev)->adc_control1_bits |=
2804 adc_hi_chan_4020_bits(CR_CHAN
2805 (cmd->
2806 chanlist[cmd->chanlist_len - 1]));
2807 }
2808 writew(priv(dev)->adc_control1_bits,
2809 priv(dev)->main_iobase + ADC_CONTROL1_REG);
2810 DEBUG_PRINT("control1 bits 0x%x\n", priv(dev)->adc_control1_bits);
2811 spin_unlock_irqrestore(&dev->spinlock, flags);
2812
2813 /* clear adc buffer */
2814 writew(0, priv(dev)->main_iobase + ADC_BUFFER_CLEAR_REG);
2815
2816 if ((cmd->flags & TRIG_WAKE_EOS) == 0 ||
2817 board(dev)->layout == LAYOUT_4020) {
2818 priv(dev)->ai_dma_index = 0;
2819
2820 /* set dma transfer size */
2821 for (i = 0; i < ai_dma_ring_count(board(dev)); i++)
2822 priv(dev)->ai_dma_desc[i].transfer_size =
2823 cpu_to_le32(dma_transfer_size(dev) *
2824 sizeof(uint16_t));
2825
2826 /* give location of first dma descriptor */
2827 load_first_dma_descriptor(dev, 1,
2828 priv(dev)->ai_dma_desc_bus_addr |
2829 PLX_DESC_IN_PCI_BIT |
2830 PLX_INTR_TERM_COUNT |
2831 PLX_XFER_LOCAL_TO_PCI);
2832
2833 dma_start_sync(dev, 1);
2834 }
2835
2836 if (board(dev)->layout == LAYOUT_4020) {
2837 /* set source for external triggers */
2838 bits = 0;
2839 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2840 bits |= EXT_START_TRIG_BNC_BIT;
2841 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2842 bits |= EXT_STOP_TRIG_BNC_BIT;
2843 writew(bits, priv(dev)->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2844 }
2845
2846 spin_lock_irqsave(&dev->spinlock, flags);
2847
2848 /* enable pacing, triggering, etc */
2849 bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2850 if (cmd->flags & TRIG_WAKE_EOS)
2851 bits |= ADC_DMA_DISABLE_BIT;
2852 /* set start trigger */
2853 if (cmd->start_src == TRIG_EXT) {
2854 bits |= ADC_START_TRIG_EXT_BITS;
2855 if (cmd->start_arg & CR_INVERT)
2856 bits |= ADC_START_TRIG_FALLING_BIT;
2857 } else if (cmd->start_src == TRIG_NOW)
2858 bits |= ADC_START_TRIG_SOFT_BITS;
2859 if (use_hw_sample_counter(cmd))
2860 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2861 writew(bits, priv(dev)->main_iobase + ADC_CONTROL0_REG);
2862 DEBUG_PRINT("control0 bits 0x%x\n", bits);
2863
2864 priv(dev)->ai_cmd_running = 1;
2865
2866 spin_unlock_irqrestore(&dev->spinlock, flags);
2867
2868 /* start acquisition */
2869 if (cmd->start_src == TRIG_NOW) {
2870 writew(0, priv(dev)->main_iobase + ADC_START_REG);
2871 DEBUG_PRINT("soft trig\n");
2872 }
2873
2874 return 0;
2875 }
2876
2877 /* read num_samples from 16 bit wide ai fifo */
pio_drain_ai_fifo_16(struct comedi_device * dev)2878 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2879 {
2880 struct comedi_subdevice *s = dev->read_subdev;
2881 struct comedi_async *async = s->async;
2882 struct comedi_cmd *cmd = &async->cmd;
2883 unsigned int i;
2884 uint16_t prepost_bits;
2885 int read_segment, read_index, write_segment, write_index;
2886 int num_samples;
2887
2888 do {
2889 /* get least significant 15 bits */
2890 read_index =
2891 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2892 write_index =
2893 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2894 /* Get most significant bits (grey code). Different boards use different code
2895 * so use a scheme that doesn't depend on encoding. This read must
2896 * occur after reading least significant 15 bits to avoid race
2897 * with fifo switching to next segment. */
2898 prepost_bits = readw(priv(dev)->main_iobase + PREPOST_REG);
2899
2900 /* if read and write pointers are not on the same fifo segment, read to the
2901 * end of the read segment */
2902 read_segment = adc_upper_read_ptr_code(prepost_bits);
2903 write_segment = adc_upper_write_ptr_code(prepost_bits);
2904
2905 DEBUG_PRINT(" rd seg %i, wrt seg %i, rd idx %i, wrt idx %i\n",
2906 read_segment, write_segment, read_index,
2907 write_index);
2908
2909 if (read_segment != write_segment)
2910 num_samples =
2911 priv(dev)->ai_fifo_segment_length - read_index;
2912 else
2913 num_samples = write_index - read_index;
2914
2915 if (cmd->stop_src == TRIG_COUNT) {
2916 if (priv(dev)->ai_count == 0)
2917 break;
2918 if (num_samples > priv(dev)->ai_count)
2919 num_samples = priv(dev)->ai_count;
2920
2921 priv(dev)->ai_count -= num_samples;
2922 }
2923
2924 if (num_samples < 0) {
2925 dev_err(dev->hw_dev, "cb_pcidas64: bug! num_samples < 0\n");
2926 break;
2927 }
2928
2929 DEBUG_PRINT(" read %i samples from fifo\n", num_samples);
2930
2931 for (i = 0; i < num_samples; i++) {
2932 cfc_write_to_buffer(s,
2933 readw(priv(dev)->main_iobase +
2934 ADC_FIFO_REG));
2935 }
2936
2937 } while (read_segment != write_segment);
2938 }
2939
2940 /* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of pointers.
2941 * The pci-4020 hardware only supports
2942 * dma transfers (it only supports the use of pio for draining the last remaining
2943 * points from the fifo when a data acquisition operation has completed).
2944 */
pio_drain_ai_fifo_32(struct comedi_device * dev)2945 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2946 {
2947 struct comedi_subdevice *s = dev->read_subdev;
2948 struct comedi_async *async = s->async;
2949 struct comedi_cmd *cmd = &async->cmd;
2950 unsigned int i;
2951 unsigned int max_transfer = 100000;
2952 uint32_t fifo_data;
2953 int write_code =
2954 readw(priv(dev)->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2955 int read_code =
2956 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2957
2958 if (cmd->stop_src == TRIG_COUNT) {
2959 if (max_transfer > priv(dev)->ai_count)
2960 max_transfer = priv(dev)->ai_count;
2961
2962 }
2963 for (i = 0; read_code != write_code && i < max_transfer;) {
2964 fifo_data = readl(priv(dev)->dio_counter_iobase + ADC_FIFO_REG);
2965 cfc_write_to_buffer(s, fifo_data & 0xffff);
2966 i++;
2967 if (i < max_transfer) {
2968 cfc_write_to_buffer(s, (fifo_data >> 16) & 0xffff);
2969 i++;
2970 }
2971 read_code =
2972 readw(priv(dev)->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2973 }
2974 priv(dev)->ai_count -= i;
2975 }
2976
2977 /* empty fifo */
pio_drain_ai_fifo(struct comedi_device * dev)2978 static void pio_drain_ai_fifo(struct comedi_device *dev)
2979 {
2980 if (board(dev)->layout == LAYOUT_4020)
2981 pio_drain_ai_fifo_32(dev);
2982 else
2983 pio_drain_ai_fifo_16(dev);
2984 }
2985
drain_dma_buffers(struct comedi_device * dev,unsigned int channel)2986 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2987 {
2988 struct comedi_async *async = dev->read_subdev->async;
2989 uint32_t next_transfer_addr;
2990 int j;
2991 int num_samples = 0;
2992 void __iomem *pci_addr_reg;
2993
2994 if (channel)
2995 pci_addr_reg =
2996 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2997 else
2998 pci_addr_reg =
2999 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3000
3001 /* loop until we have read all the full buffers */
3002 for (j = 0, next_transfer_addr = readl(pci_addr_reg);
3003 (next_transfer_addr <
3004 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index]
3005 || next_transfer_addr >=
3006 priv(dev)->ai_buffer_bus_addr[priv(dev)->ai_dma_index] +
3007 DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board(dev)); j++) {
3008 /* transfer data from dma buffer to comedi buffer */
3009 num_samples = dma_transfer_size(dev);
3010 if (async->cmd.stop_src == TRIG_COUNT) {
3011 if (num_samples > priv(dev)->ai_count)
3012 num_samples = priv(dev)->ai_count;
3013 priv(dev)->ai_count -= num_samples;
3014 }
3015 cfc_write_array_to_buffer(dev->read_subdev,
3016 priv(dev)->ai_buffer[priv(dev)->
3017 ai_dma_index],
3018 num_samples * sizeof(uint16_t));
3019 priv(dev)->ai_dma_index =
3020 (priv(dev)->ai_dma_index +
3021 1) % ai_dma_ring_count(board(dev));
3022
3023 DEBUG_PRINT("next buffer addr 0x%lx\n",
3024 (unsigned long)priv(dev)->
3025 ai_buffer_bus_addr[priv(dev)->ai_dma_index]);
3026 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
3027 }
3028 /* XXX check for dma ring buffer overrun (use end-of-chain bit to mark last
3029 * unused buffer) */
3030 }
3031
handle_ai_interrupt(struct comedi_device * dev,unsigned short status,unsigned int plx_status)3032 static void handle_ai_interrupt(struct comedi_device *dev,
3033 unsigned short status,
3034 unsigned int plx_status)
3035 {
3036 struct comedi_subdevice *s = dev->read_subdev;
3037 struct comedi_async *async = s->async;
3038 struct comedi_cmd *cmd = &async->cmd;
3039 uint8_t dma1_status;
3040 unsigned long flags;
3041
3042 /* check for fifo overrun */
3043 if (status & ADC_OVERRUN_BIT) {
3044 comedi_error(dev, "fifo overrun");
3045 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
3046 }
3047 /* spin lock makes sure no one else changes plx dma control reg */
3048 spin_lock_irqsave(&dev->spinlock, flags);
3049 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
3050 if (plx_status & ICS_DMA1_A) { /* dma chan 1 interrupt */
3051 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
3052 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
3053 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
3054
3055 if (dma1_status & PLX_DMA_EN_BIT)
3056 drain_dma_buffers(dev, 1);
3057
3058 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
3059 }
3060 spin_unlock_irqrestore(&dev->spinlock, flags);
3061
3062 if (status & ADC_DONE_BIT)
3063 DEBUG_PRINT("adc done interrupt\n");
3064
3065 /* drain fifo with pio */
3066 if ((status & ADC_DONE_BIT) ||
3067 ((cmd->flags & TRIG_WAKE_EOS) &&
3068 (status & ADC_INTR_PENDING_BIT) &&
3069 (board(dev)->layout != LAYOUT_4020))) {
3070 DEBUG_PRINT("pio fifo drain\n");
3071 spin_lock_irqsave(&dev->spinlock, flags);
3072 if (priv(dev)->ai_cmd_running) {
3073 spin_unlock_irqrestore(&dev->spinlock, flags);
3074 pio_drain_ai_fifo(dev);
3075 } else
3076 spin_unlock_irqrestore(&dev->spinlock, flags);
3077 }
3078 /* if we are have all the data, then quit */
3079 if ((cmd->stop_src == TRIG_COUNT && (int)priv(dev)->ai_count <= 0) ||
3080 (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT))) {
3081 async->events |= COMEDI_CB_EOA;
3082 }
3083
3084 cfc_handle_events(dev, s);
3085 }
3086
prev_ao_dma_index(struct comedi_device * dev)3087 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
3088 {
3089 unsigned int buffer_index;
3090
3091 if (priv(dev)->ao_dma_index == 0)
3092 buffer_index = AO_DMA_RING_COUNT - 1;
3093 else
3094 buffer_index = priv(dev)->ao_dma_index - 1;
3095 return buffer_index;
3096 }
3097
last_ao_dma_load_completed(struct comedi_device * dev)3098 static int last_ao_dma_load_completed(struct comedi_device *dev)
3099 {
3100 unsigned int buffer_index;
3101 unsigned int transfer_address;
3102 unsigned short dma_status;
3103
3104 buffer_index = prev_ao_dma_index(dev);
3105 dma_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3106 if ((dma_status & PLX_DMA_DONE_BIT) == 0)
3107 return 0;
3108
3109 transfer_address =
3110 readl(priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
3111 if (transfer_address != priv(dev)->ao_buffer_bus_addr[buffer_index])
3112 return 0;
3113
3114 return 1;
3115 }
3116
ao_stopped_by_error(struct comedi_device * dev,const struct comedi_cmd * cmd)3117 static int ao_stopped_by_error(struct comedi_device *dev,
3118 const struct comedi_cmd *cmd)
3119 {
3120 if (cmd->stop_src == TRIG_NONE)
3121 return 1;
3122 if (cmd->stop_src == TRIG_COUNT) {
3123 if (priv(dev)->ao_count)
3124 return 1;
3125 if (last_ao_dma_load_completed(dev) == 0)
3126 return 1;
3127 }
3128 return 0;
3129 }
3130
ao_dma_needs_restart(struct comedi_device * dev,unsigned short dma_status)3131 static inline int ao_dma_needs_restart(struct comedi_device *dev,
3132 unsigned short dma_status)
3133 {
3134 if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
3135 (dma_status & PLX_DMA_EN_BIT) == 0)
3136 return 0;
3137 if (last_ao_dma_load_completed(dev))
3138 return 0;
3139
3140 return 1;
3141 }
3142
restart_ao_dma(struct comedi_device * dev)3143 static void restart_ao_dma(struct comedi_device *dev)
3144 {
3145 unsigned int dma_desc_bits;
3146
3147 dma_desc_bits =
3148 readl(priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
3149 dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
3150 DEBUG_PRINT("restarting ao dma, descriptor reg 0x%x\n", dma_desc_bits);
3151 load_first_dma_descriptor(dev, 0, dma_desc_bits);
3152
3153 dma_start_sync(dev, 0);
3154 }
3155
handle_ao_interrupt(struct comedi_device * dev,unsigned short status,unsigned int plx_status)3156 static void handle_ao_interrupt(struct comedi_device *dev,
3157 unsigned short status, unsigned int plx_status)
3158 {
3159 struct comedi_subdevice *s = dev->write_subdev;
3160 struct comedi_async *async;
3161 struct comedi_cmd *cmd;
3162 uint8_t dma0_status;
3163 unsigned long flags;
3164
3165 /* board might not support ao, in which case write_subdev is NULL */
3166 if (s == NULL)
3167 return;
3168 async = s->async;
3169 cmd = &async->cmd;
3170
3171 /* spin lock makes sure no one else changes plx dma control reg */
3172 spin_lock_irqsave(&dev->spinlock, flags);
3173 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3174 if (plx_status & ICS_DMA0_A) { /* dma chan 0 interrupt */
3175 if ((dma0_status & PLX_DMA_EN_BIT)
3176 && !(dma0_status & PLX_DMA_DONE_BIT))
3177 writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
3178 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3179 else
3180 writeb(PLX_CLEAR_DMA_INTR_BIT,
3181 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
3182 spin_unlock_irqrestore(&dev->spinlock, flags);
3183 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
3184 if (dma0_status & PLX_DMA_EN_BIT) {
3185 load_ao_dma(dev, cmd);
3186 /* try to recover from dma end-of-chain event */
3187 if (ao_dma_needs_restart(dev, dma0_status))
3188 restart_ao_dma(dev);
3189 }
3190 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
3191 } else
3192 spin_unlock_irqrestore(&dev->spinlock, flags);
3193
3194 if ((status & DAC_DONE_BIT)) {
3195 async->events |= COMEDI_CB_EOA;
3196 if (ao_stopped_by_error(dev, cmd))
3197 async->events |= COMEDI_CB_ERROR;
3198 DEBUG_PRINT("plx dma0 desc reg 0x%x\n",
3199 readl(priv(dev)->plx9080_iobase +
3200 PLX_DMA0_DESCRIPTOR_REG));
3201 DEBUG_PRINT("plx dma0 address reg 0x%x\n",
3202 readl(priv(dev)->plx9080_iobase +
3203 PLX_DMA0_PCI_ADDRESS_REG));
3204 }
3205 cfc_handle_events(dev, s);
3206 }
3207
handle_interrupt(int irq,void * d)3208 static irqreturn_t handle_interrupt(int irq, void *d)
3209 {
3210 struct comedi_device *dev = d;
3211 unsigned short status;
3212 uint32_t plx_status;
3213 uint32_t plx_bits;
3214
3215 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
3216 status = readw(priv(dev)->main_iobase + HW_STATUS_REG);
3217
3218 DEBUG_PRINT("cb_pcidas64: hw status 0x%x ", status);
3219 DEBUG_PRINT("plx status 0x%x\n", plx_status);
3220
3221 /* an interrupt before all the postconfig stuff gets done could
3222 * cause a NULL dereference if we continue through the
3223 * interrupt handler */
3224 if (dev->attached == 0) {
3225 DEBUG_PRINT("cb_pcidas64: premature interrupt, ignoring",
3226 status);
3227 return IRQ_HANDLED;
3228 }
3229 handle_ai_interrupt(dev, status, plx_status);
3230 handle_ao_interrupt(dev, status, plx_status);
3231
3232 /* clear possible plx9080 interrupt sources */
3233 if (plx_status & ICS_LDIA) { /* clear local doorbell interrupt */
3234 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3235 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
3236 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
3237 }
3238
3239 DEBUG_PRINT("exiting handler\n");
3240
3241 return IRQ_HANDLED;
3242 }
3243
abort_dma(struct comedi_device * dev,unsigned int channel)3244 static void abort_dma(struct comedi_device *dev, unsigned int channel)
3245 {
3246 unsigned long flags;
3247
3248 /* spinlock for plx dma control/status reg */
3249 spin_lock_irqsave(&dev->spinlock, flags);
3250
3251 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
3252
3253 spin_unlock_irqrestore(&dev->spinlock, flags);
3254 }
3255
ai_cancel(struct comedi_device * dev,struct comedi_subdevice * s)3256 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3257 {
3258 unsigned long flags;
3259
3260 spin_lock_irqsave(&dev->spinlock, flags);
3261 if (priv(dev)->ai_cmd_running == 0) {
3262 spin_unlock_irqrestore(&dev->spinlock, flags);
3263 return 0;
3264 }
3265 priv(dev)->ai_cmd_running = 0;
3266 spin_unlock_irqrestore(&dev->spinlock, flags);
3267
3268 disable_ai_pacing(dev);
3269
3270 abort_dma(dev, 1);
3271
3272 DEBUG_PRINT("ai canceled\n");
3273 return 0;
3274 }
3275
ao_winsn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3276 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3277 struct comedi_insn *insn, unsigned int *data)
3278 {
3279 int chan = CR_CHAN(insn->chanspec);
3280 int range = CR_RANGE(insn->chanspec);
3281
3282 /* do some initializing */
3283 writew(0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3284
3285 /* set range */
3286 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, chan, range);
3287 writew(priv(dev)->dac_control1_bits,
3288 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3289
3290 /* write to channel */
3291 if (board(dev)->layout == LAYOUT_4020) {
3292 writew(data[0] & 0xff,
3293 priv(dev)->main_iobase + dac_lsb_4020_reg(chan));
3294 writew((data[0] >> 8) & 0xf,
3295 priv(dev)->main_iobase + dac_msb_4020_reg(chan));
3296 } else {
3297 writew(data[0], priv(dev)->main_iobase + dac_convert_reg(chan));
3298 }
3299
3300 /* remember output value */
3301 priv(dev)->ao_value[chan] = data[0];
3302
3303 return 1;
3304 }
3305
ao_readback_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3306 static int ao_readback_insn(struct comedi_device *dev,
3307 struct comedi_subdevice *s,
3308 struct comedi_insn *insn, unsigned int *data)
3309 {
3310 data[0] = priv(dev)->ao_value[CR_CHAN(insn->chanspec)];
3311
3312 return 1;
3313 }
3314
set_dac_control0_reg(struct comedi_device * dev,const struct comedi_cmd * cmd)3315 static void set_dac_control0_reg(struct comedi_device *dev,
3316 const struct comedi_cmd *cmd)
3317 {
3318 unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3319 WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3320
3321 if (cmd->start_src == TRIG_EXT) {
3322 bits |= WAVEFORM_TRIG_EXT_BITS;
3323 if (cmd->start_arg & CR_INVERT)
3324 bits |= WAVEFORM_TRIG_FALLING_BIT;
3325 } else {
3326 bits |= WAVEFORM_TRIG_SOFT_BITS;
3327 }
3328 if (cmd->scan_begin_src == TRIG_EXT) {
3329 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3330 if (cmd->scan_begin_arg & CR_INVERT)
3331 bits |= DAC_EXT_UPDATE_FALLING_BIT;
3332 }
3333 writew(bits, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3334 }
3335
set_dac_control1_reg(struct comedi_device * dev,const struct comedi_cmd * cmd)3336 static void set_dac_control1_reg(struct comedi_device *dev,
3337 const struct comedi_cmd *cmd)
3338 {
3339 int i;
3340
3341 for (i = 0; i < cmd->chanlist_len; i++) {
3342 int channel, range;
3343
3344 channel = CR_CHAN(cmd->chanlist[i]);
3345 range = CR_RANGE(cmd->chanlist[i]);
3346 set_dac_range_bits(dev, &priv(dev)->dac_control1_bits, channel,
3347 range);
3348 }
3349 priv(dev)->dac_control1_bits |= DAC_SW_GATE_BIT;
3350 writew(priv(dev)->dac_control1_bits,
3351 priv(dev)->main_iobase + DAC_CONTROL1_REG);
3352 }
3353
set_dac_select_reg(struct comedi_device * dev,const struct comedi_cmd * cmd)3354 static void set_dac_select_reg(struct comedi_device *dev,
3355 const struct comedi_cmd *cmd)
3356 {
3357 uint16_t bits;
3358 unsigned int first_channel, last_channel;
3359
3360 first_channel = CR_CHAN(cmd->chanlist[0]);
3361 last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3362 if (last_channel < first_channel)
3363 comedi_error(dev, "bug! last ao channel < first ao channel");
3364
3365 bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3366
3367 writew(bits, priv(dev)->main_iobase + DAC_SELECT_REG);
3368 }
3369
set_dac_interval_regs(struct comedi_device * dev,const struct comedi_cmd * cmd)3370 static void set_dac_interval_regs(struct comedi_device *dev,
3371 const struct comedi_cmd *cmd)
3372 {
3373 unsigned int divisor;
3374
3375 if (cmd->scan_begin_src != TRIG_TIMER)
3376 return;
3377
3378 divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3379 if (divisor > max_counter_value) {
3380 comedi_error(dev, "bug! ao divisor too big");
3381 divisor = max_counter_value;
3382 }
3383 writew(divisor & 0xffff,
3384 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3385 writew((divisor >> 16) & 0xff,
3386 priv(dev)->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3387 }
3388
load_ao_dma_buffer(struct comedi_device * dev,const struct comedi_cmd * cmd)3389 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
3390 const struct comedi_cmd *cmd)
3391 {
3392 unsigned int num_bytes, buffer_index, prev_buffer_index;
3393 unsigned int next_bits;
3394
3395 buffer_index = priv(dev)->ao_dma_index;
3396 prev_buffer_index = prev_ao_dma_index(dev);
3397
3398 DEBUG_PRINT("attempting to load ao buffer %i (0x%x)\n", buffer_index,
3399 priv(dev)->ao_buffer_bus_addr[buffer_index]);
3400
3401 num_bytes = comedi_buf_read_n_available(dev->write_subdev->async);
3402 if (num_bytes > DMA_BUFFER_SIZE)
3403 num_bytes = DMA_BUFFER_SIZE;
3404 if (cmd->stop_src == TRIG_COUNT && num_bytes > priv(dev)->ao_count)
3405 num_bytes = priv(dev)->ao_count;
3406 num_bytes -= num_bytes % bytes_in_sample;
3407
3408 if (num_bytes == 0)
3409 return 0;
3410
3411 DEBUG_PRINT("loading %i bytes\n", num_bytes);
3412
3413 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3414 priv(dev)->
3415 ao_buffer[buffer_index],
3416 num_bytes);
3417 priv(dev)->ao_dma_desc[buffer_index].transfer_size =
3418 cpu_to_le32(num_bytes);
3419 /* set end of chain bit so we catch underruns */
3420 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[buffer_index].next);
3421 next_bits |= PLX_END_OF_CHAIN_BIT;
3422 priv(dev)->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
3423 /* clear end of chain bit on previous buffer now that we have set it
3424 * for the last buffer */
3425 next_bits = le32_to_cpu(priv(dev)->ao_dma_desc[prev_buffer_index].next);
3426 next_bits &= ~PLX_END_OF_CHAIN_BIT;
3427 priv(dev)->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
3428
3429 priv(dev)->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
3430 priv(dev)->ao_count -= num_bytes;
3431
3432 return num_bytes;
3433 }
3434
load_ao_dma(struct comedi_device * dev,const struct comedi_cmd * cmd)3435 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3436 {
3437 unsigned int num_bytes;
3438 unsigned int next_transfer_addr;
3439 void __iomem *pci_addr_reg =
3440 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
3441 unsigned int buffer_index;
3442
3443 do {
3444 buffer_index = priv(dev)->ao_dma_index;
3445 /* don't overwrite data that hasn't been transferred yet */
3446 next_transfer_addr = readl(pci_addr_reg);
3447 if (next_transfer_addr >=
3448 priv(dev)->ao_buffer_bus_addr[buffer_index]
3449 && next_transfer_addr <
3450 priv(dev)->ao_buffer_bus_addr[buffer_index] +
3451 DMA_BUFFER_SIZE)
3452 return;
3453 num_bytes = load_ao_dma_buffer(dev, cmd);
3454 } while (num_bytes >= DMA_BUFFER_SIZE);
3455 }
3456
prep_ao_dma(struct comedi_device * dev,const struct comedi_cmd * cmd)3457 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3458 {
3459 unsigned int num_bytes;
3460 int i;
3461
3462 /* clear queue pointer too, since external queue has
3463 * weird interactions with ao fifo */
3464 writew(0, priv(dev)->main_iobase + ADC_QUEUE_CLEAR_REG);
3465 writew(0, priv(dev)->main_iobase + DAC_BUFFER_CLEAR_REG);
3466
3467 num_bytes = (DAC_FIFO_SIZE / 2) * bytes_in_sample;
3468 if (cmd->stop_src == TRIG_COUNT &&
3469 num_bytes / bytes_in_sample > priv(dev)->ao_count)
3470 num_bytes = priv(dev)->ao_count * bytes_in_sample;
3471 num_bytes = cfc_read_array_from_buffer(dev->write_subdev,
3472 priv(dev)->ao_bounce_buffer,
3473 num_bytes);
3474 for (i = 0; i < num_bytes / bytes_in_sample; i++) {
3475 writew(priv(dev)->ao_bounce_buffer[i],
3476 priv(dev)->main_iobase + DAC_FIFO_REG);
3477 }
3478 priv(dev)->ao_count -= num_bytes / bytes_in_sample;
3479 if (cmd->stop_src == TRIG_COUNT && priv(dev)->ao_count == 0)
3480 return 0;
3481 num_bytes = load_ao_dma_buffer(dev, cmd);
3482 if (num_bytes == 0)
3483 return -1;
3484 if (num_bytes >= DMA_BUFFER_SIZE) ;
3485 load_ao_dma(dev, cmd);
3486
3487 dma_start_sync(dev, 0);
3488
3489 return 0;
3490 }
3491
external_ai_queue_in_use(struct comedi_device * dev)3492 static inline int external_ai_queue_in_use(struct comedi_device *dev)
3493 {
3494 if (dev->read_subdev->busy)
3495 return 0;
3496 if (board(dev)->layout == LAYOUT_4020)
3497 return 0;
3498 else if (use_internal_queue_6xxx(&dev->read_subdev->async->cmd))
3499 return 0;
3500 return 1;
3501 }
3502
ao_cmd(struct comedi_device * dev,struct comedi_subdevice * s)3503 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3504 {
3505 struct comedi_cmd *cmd = &s->async->cmd;
3506
3507 if (external_ai_queue_in_use(dev)) {
3508 warn_external_queue(dev);
3509 return -EBUSY;
3510 }
3511 /* disable analog output system during setup */
3512 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3513
3514 priv(dev)->ao_dma_index = 0;
3515 priv(dev)->ao_count = cmd->stop_arg * cmd->chanlist_len;
3516
3517 set_dac_select_reg(dev, cmd);
3518 set_dac_interval_regs(dev, cmd);
3519 load_first_dma_descriptor(dev, 0, priv(dev)->ao_dma_desc_bus_addr |
3520 PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3521
3522 set_dac_control1_reg(dev, cmd);
3523 s->async->inttrig = ao_inttrig;
3524
3525 return 0;
3526 }
3527
ao_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)3528 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3529 unsigned int trig_num)
3530 {
3531 struct comedi_cmd *cmd = &s->async->cmd;
3532 int retval;
3533
3534 if (trig_num != 0)
3535 return -EINVAL;
3536
3537 retval = prep_ao_dma(dev, cmd);
3538 if (retval < 0)
3539 return -EPIPE;
3540
3541 set_dac_control0_reg(dev, cmd);
3542
3543 if (cmd->start_src == TRIG_INT)
3544 writew(0, priv(dev)->main_iobase + DAC_START_REG);
3545
3546 s->async->inttrig = NULL;
3547
3548 return 0;
3549 }
3550
ao_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)3551 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3552 struct comedi_cmd *cmd)
3553 {
3554 int err = 0;
3555 int tmp;
3556 unsigned int tmp_arg;
3557 int i;
3558
3559 /* step 1: make sure trigger sources are trivially valid */
3560
3561 tmp = cmd->start_src;
3562 cmd->start_src &= TRIG_INT | TRIG_EXT;
3563 if (!cmd->start_src || tmp != cmd->start_src)
3564 err++;
3565
3566 tmp = cmd->scan_begin_src;
3567 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT;
3568 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
3569 err++;
3570
3571 tmp = cmd->convert_src;
3572 cmd->convert_src &= TRIG_NOW;
3573 if (!cmd->convert_src || tmp != cmd->convert_src)
3574 err++;
3575
3576 tmp = cmd->scan_end_src;
3577 cmd->scan_end_src &= TRIG_COUNT;
3578 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
3579 err++;
3580
3581 tmp = cmd->stop_src;
3582 cmd->stop_src &= TRIG_NONE;
3583 if (!cmd->stop_src || tmp != cmd->stop_src)
3584 err++;
3585
3586 if (err)
3587 return 1;
3588
3589 /* step 2: make sure trigger sources are unique and mutually compatible */
3590
3591 /* uniqueness check */
3592 if (cmd->start_src != TRIG_INT && cmd->start_src != TRIG_EXT)
3593 err++;
3594 if (cmd->scan_begin_src != TRIG_TIMER &&
3595 cmd->scan_begin_src != TRIG_EXT)
3596 err++;
3597
3598 /* compatibility check */
3599 if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3600 err++;
3601 if (cmd->stop_src != TRIG_COUNT &&
3602 cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3603 err++;
3604
3605 if (err)
3606 return 2;
3607
3608 /* step 3: make sure arguments are trivially compatible */
3609
3610 if (cmd->scan_begin_src == TRIG_TIMER) {
3611 if (cmd->scan_begin_arg < board(dev)->ao_scan_speed) {
3612 cmd->scan_begin_arg = board(dev)->ao_scan_speed;
3613 err++;
3614 }
3615 if (get_ao_divisor(cmd->scan_begin_arg,
3616 cmd->flags) > max_counter_value) {
3617 cmd->scan_begin_arg =
3618 (max_counter_value + 2) * TIMER_BASE;
3619 err++;
3620 }
3621 }
3622
3623 if (!cmd->chanlist_len) {
3624 cmd->chanlist_len = 1;
3625 err++;
3626 }
3627 if (cmd->scan_end_arg != cmd->chanlist_len) {
3628 cmd->scan_end_arg = cmd->chanlist_len;
3629 err++;
3630 }
3631
3632 if (err)
3633 return 3;
3634
3635 /* step 4: fix up any arguments */
3636
3637 if (cmd->scan_begin_src == TRIG_TIMER) {
3638 tmp_arg = cmd->scan_begin_arg;
3639 cmd->scan_begin_arg =
3640 get_divisor(cmd->scan_begin_arg, cmd->flags) * TIMER_BASE;
3641 if (tmp_arg != cmd->scan_begin_arg)
3642 err++;
3643 }
3644
3645 if (err)
3646 return 4;
3647
3648 if (cmd->chanlist) {
3649 unsigned int first_channel = CR_CHAN(cmd->chanlist[0]);
3650 for (i = 1; i < cmd->chanlist_len; i++) {
3651 if (CR_CHAN(cmd->chanlist[i]) != first_channel + i) {
3652 comedi_error(dev,
3653 "chanlist must use consecutive channels");
3654 err++;
3655 break;
3656 }
3657 }
3658 }
3659
3660 if (err)
3661 return 5;
3662
3663 return 0;
3664 }
3665
ao_cancel(struct comedi_device * dev,struct comedi_subdevice * s)3666 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3667 {
3668 writew(0x0, priv(dev)->main_iobase + DAC_CONTROL0_REG);
3669 abort_dma(dev, 0);
3670 return 0;
3671 }
3672
dio_callback(int dir,int port,int data,unsigned long arg)3673 static int dio_callback(int dir, int port, int data, unsigned long arg)
3674 {
3675 void __iomem *iobase = (void __iomem *)arg;
3676 if (dir) {
3677 writeb(data, iobase + port);
3678 DEBUG_PRINT("wrote 0x%x to port %i\n", data, port);
3679 return 0;
3680 } else {
3681 return readb(iobase + port);
3682 }
3683 }
3684
dio_callback_4020(int dir,int port,int data,unsigned long arg)3685 static int dio_callback_4020(int dir, int port, int data, unsigned long arg)
3686 {
3687 void __iomem *iobase = (void __iomem *)arg;
3688 if (dir) {
3689 writew(data, iobase + 2 * port);
3690 return 0;
3691 } else {
3692 return readw(iobase + 2 * port);
3693 }
3694 }
3695
di_rbits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3696 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3697 struct comedi_insn *insn, unsigned int *data)
3698 {
3699 unsigned int bits;
3700
3701 bits = readb(priv(dev)->dio_counter_iobase + DI_REG);
3702 bits &= 0xf;
3703 data[1] = bits;
3704 data[0] = 0;
3705
3706 return 2;
3707 }
3708
do_wbits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3709 static int do_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3710 struct comedi_insn *insn, unsigned int *data)
3711 {
3712 data[0] &= 0xf;
3713 /* zero bits we are going to change */
3714 s->state &= ~data[0];
3715 /* set new bits */
3716 s->state |= data[0] & data[1];
3717
3718 writeb(s->state, priv(dev)->dio_counter_iobase + DO_REG);
3719
3720 data[1] = s->state;
3721
3722 return 2;
3723 }
3724
dio_60xx_config_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3725 static int dio_60xx_config_insn(struct comedi_device *dev,
3726 struct comedi_subdevice *s,
3727 struct comedi_insn *insn, unsigned int *data)
3728 {
3729 unsigned int mask;
3730
3731 mask = 1 << CR_CHAN(insn->chanspec);
3732
3733 switch (data[0]) {
3734 case INSN_CONFIG_DIO_INPUT:
3735 s->io_bits &= ~mask;
3736 break;
3737 case INSN_CONFIG_DIO_OUTPUT:
3738 s->io_bits |= mask;
3739 break;
3740 case INSN_CONFIG_DIO_QUERY:
3741 data[1] = (s->io_bits & mask) ? COMEDI_OUTPUT : COMEDI_INPUT;
3742 return 2;
3743 default:
3744 return -EINVAL;
3745 }
3746
3747 writeb(s->io_bits,
3748 priv(dev)->dio_counter_iobase + DIO_DIRECTION_60XX_REG);
3749
3750 return 1;
3751 }
3752
dio_60xx_wbits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3753 static int dio_60xx_wbits(struct comedi_device *dev, struct comedi_subdevice *s,
3754 struct comedi_insn *insn, unsigned int *data)
3755 {
3756 if (data[0]) {
3757 s->state &= ~data[0];
3758 s->state |= (data[0] & data[1]);
3759 writeb(s->state,
3760 priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3761 }
3762
3763 data[1] = readb(priv(dev)->dio_counter_iobase + DIO_DATA_60XX_REG);
3764
3765 return 2;
3766 }
3767
caldac_write(struct comedi_device * dev,unsigned int channel,unsigned int value)3768 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3769 unsigned int value)
3770 {
3771 priv(dev)->caldac_state[channel] = value;
3772
3773 switch (board(dev)->layout) {
3774 case LAYOUT_60XX:
3775 case LAYOUT_64XX:
3776 caldac_8800_write(dev, channel, value);
3777 break;
3778 case LAYOUT_4020:
3779 caldac_i2c_write(dev, channel, value);
3780 break;
3781 default:
3782 break;
3783 }
3784 }
3785
calib_write_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3786 static int calib_write_insn(struct comedi_device *dev,
3787 struct comedi_subdevice *s,
3788 struct comedi_insn *insn, unsigned int *data)
3789 {
3790 int channel = CR_CHAN(insn->chanspec);
3791
3792 /* return immediately if setting hasn't changed, since
3793 * programming these things is slow */
3794 if (priv(dev)->caldac_state[channel] == data[0])
3795 return 1;
3796
3797 caldac_write(dev, channel, data[0]);
3798
3799 return 1;
3800 }
3801
calib_read_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3802 static int calib_read_insn(struct comedi_device *dev,
3803 struct comedi_subdevice *s, struct comedi_insn *insn,
3804 unsigned int *data)
3805 {
3806 unsigned int channel = CR_CHAN(insn->chanspec);
3807
3808 data[0] = priv(dev)->caldac_state[channel];
3809
3810 return 1;
3811 }
3812
ad8402_write(struct comedi_device * dev,unsigned int channel,unsigned int value)3813 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3814 unsigned int value)
3815 {
3816 static const int bitstream_length = 10;
3817 unsigned int bit, register_bits;
3818 unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3819 static const int ad8402_udelay = 1;
3820
3821 priv(dev)->ad8402_state[channel] = value;
3822
3823 register_bits = SELECT_8402_64XX_BIT;
3824 udelay(ad8402_udelay);
3825 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3826
3827 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3828 if (bitstream & bit)
3829 register_bits |= SERIAL_DATA_IN_BIT;
3830 else
3831 register_bits &= ~SERIAL_DATA_IN_BIT;
3832 udelay(ad8402_udelay);
3833 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
3834 udelay(ad8402_udelay);
3835 writew(register_bits | SERIAL_CLOCK_BIT,
3836 priv(dev)->main_iobase + CALIBRATION_REG);
3837 }
3838
3839 udelay(ad8402_udelay);
3840 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
3841 }
3842
3843 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
ad8402_write_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3844 static int ad8402_write_insn(struct comedi_device *dev,
3845 struct comedi_subdevice *s,
3846 struct comedi_insn *insn, unsigned int *data)
3847 {
3848 int channel = CR_CHAN(insn->chanspec);
3849
3850 /* return immediately if setting hasn't changed, since
3851 * programming these things is slow */
3852 if (priv(dev)->ad8402_state[channel] == data[0])
3853 return 1;
3854
3855 priv(dev)->ad8402_state[channel] = data[0];
3856
3857 ad8402_write(dev, channel, data[0]);
3858
3859 return 1;
3860 }
3861
ad8402_read_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3862 static int ad8402_read_insn(struct comedi_device *dev,
3863 struct comedi_subdevice *s,
3864 struct comedi_insn *insn, unsigned int *data)
3865 {
3866 unsigned int channel = CR_CHAN(insn->chanspec);
3867
3868 data[0] = priv(dev)->ad8402_state[channel];
3869
3870 return 1;
3871 }
3872
read_eeprom(struct comedi_device * dev,uint8_t address)3873 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3874 {
3875 static const int bitstream_length = 11;
3876 static const int read_command = 0x6;
3877 unsigned int bitstream = (read_command << 8) | address;
3878 unsigned int bit;
3879 void __iomem * const plx_control_addr =
3880 priv(dev)->plx9080_iobase + PLX_CONTROL_REG;
3881 uint16_t value;
3882 static const int value_length = 16;
3883 static const int eeprom_udelay = 1;
3884
3885 udelay(eeprom_udelay);
3886 priv(dev)->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3887 /* make sure we don't send anything to the i2c bus on 4020 */
3888 priv(dev)->plx_control_bits |= CTL_USERO;
3889 writel(priv(dev)->plx_control_bits, plx_control_addr);
3890 /* activate serial eeprom */
3891 udelay(eeprom_udelay);
3892 priv(dev)->plx_control_bits |= CTL_EE_CS;
3893 writel(priv(dev)->plx_control_bits, plx_control_addr);
3894
3895 /* write read command and desired memory address */
3896 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3897 /* set bit to be written */
3898 udelay(eeprom_udelay);
3899 if (bitstream & bit)
3900 priv(dev)->plx_control_bits |= CTL_EE_W;
3901 else
3902 priv(dev)->plx_control_bits &= ~CTL_EE_W;
3903 writel(priv(dev)->plx_control_bits, plx_control_addr);
3904 /* clock in bit */
3905 udelay(eeprom_udelay);
3906 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3907 writel(priv(dev)->plx_control_bits, plx_control_addr);
3908 udelay(eeprom_udelay);
3909 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3910 writel(priv(dev)->plx_control_bits, plx_control_addr);
3911 }
3912 /* read back value from eeprom memory location */
3913 value = 0;
3914 for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3915 /* clock out bit */
3916 udelay(eeprom_udelay);
3917 priv(dev)->plx_control_bits |= CTL_EE_CLK;
3918 writel(priv(dev)->plx_control_bits, plx_control_addr);
3919 udelay(eeprom_udelay);
3920 priv(dev)->plx_control_bits &= ~CTL_EE_CLK;
3921 writel(priv(dev)->plx_control_bits, plx_control_addr);
3922 udelay(eeprom_udelay);
3923 if (readl(plx_control_addr) & CTL_EE_R)
3924 value |= bit;
3925 }
3926
3927 /* deactivate eeprom serial input */
3928 udelay(eeprom_udelay);
3929 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
3930 writel(priv(dev)->plx_control_bits, plx_control_addr);
3931
3932 return value;
3933 }
3934
eeprom_read_insn(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)3935 static int eeprom_read_insn(struct comedi_device *dev,
3936 struct comedi_subdevice *s,
3937 struct comedi_insn *insn, unsigned int *data)
3938 {
3939 data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3940
3941 return 1;
3942 }
3943
3944 /* utility function that rounds desired timing to an achievable time, and
3945 * sets cmd members appropriately.
3946 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
3947 */
check_adc_timing(struct comedi_device * dev,struct comedi_cmd * cmd)3948 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
3949 {
3950 unsigned int convert_divisor = 0, scan_divisor;
3951 static const int min_convert_divisor = 3;
3952 static const int max_convert_divisor =
3953 max_counter_value + min_convert_divisor;
3954 static const int min_scan_divisor_4020 = 2;
3955 unsigned long long max_scan_divisor, min_scan_divisor;
3956
3957 if (cmd->convert_src == TRIG_TIMER) {
3958 if (board(dev)->layout == LAYOUT_4020) {
3959 cmd->convert_arg = 0;
3960 } else {
3961 convert_divisor =
3962 get_divisor(cmd->convert_arg, cmd->flags);
3963 if (convert_divisor > max_convert_divisor)
3964 convert_divisor = max_convert_divisor;
3965 if (convert_divisor < min_convert_divisor)
3966 convert_divisor = min_convert_divisor;
3967 cmd->convert_arg = convert_divisor * TIMER_BASE;
3968 }
3969 } else if (cmd->convert_src == TRIG_NOW)
3970 cmd->convert_arg = 0;
3971
3972 if (cmd->scan_begin_src == TRIG_TIMER) {
3973 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
3974 if (cmd->convert_src == TRIG_TIMER) {
3975 /* XXX check for integer overflows */
3976 min_scan_divisor = convert_divisor * cmd->chanlist_len;
3977 max_scan_divisor =
3978 (convert_divisor * cmd->chanlist_len - 1) +
3979 max_counter_value;
3980 } else {
3981 min_scan_divisor = min_scan_divisor_4020;
3982 max_scan_divisor = max_counter_value + min_scan_divisor;
3983 }
3984 if (scan_divisor > max_scan_divisor)
3985 scan_divisor = max_scan_divisor;
3986 if (scan_divisor < min_scan_divisor)
3987 scan_divisor = min_scan_divisor;
3988 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
3989 }
3990
3991 return;
3992 }
3993
3994 /* Gets nearest achievable timing given master clock speed, does not
3995 * take into account possible minimum/maximum divisor values. Used
3996 * by other timing checking functions. */
get_divisor(unsigned int ns,unsigned int flags)3997 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
3998 {
3999 unsigned int divisor;
4000
4001 switch (flags & TRIG_ROUND_MASK) {
4002 case TRIG_ROUND_UP:
4003 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
4004 break;
4005 case TRIG_ROUND_DOWN:
4006 divisor = ns / TIMER_BASE;
4007 break;
4008 case TRIG_ROUND_NEAREST:
4009 default:
4010 divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
4011 break;
4012 }
4013 return divisor;
4014 }
4015
get_ao_divisor(unsigned int ns,unsigned int flags)4016 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
4017 {
4018 return get_divisor(ns, flags) - 2;
4019 }
4020
4021 /* adjusts the size of hardware fifo (which determines block size for dma xfers) */
set_ai_fifo_size(struct comedi_device * dev,unsigned int num_samples)4022 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
4023 {
4024 unsigned int num_fifo_entries;
4025 int retval;
4026 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
4027
4028 num_fifo_entries = num_samples / fifo->sample_packing_ratio;
4029
4030 retval = set_ai_fifo_segment_length(dev,
4031 num_fifo_entries /
4032 fifo->num_segments);
4033 if (retval < 0)
4034 return retval;
4035
4036 num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
4037
4038 DEBUG_PRINT("set hardware fifo size to %i\n", num_samples);
4039
4040 return num_samples;
4041 }
4042
4043 /* query length of fifo */
ai_fifo_size(struct comedi_device * dev)4044 static unsigned int ai_fifo_size(struct comedi_device *dev)
4045 {
4046 return priv(dev)->ai_fifo_segment_length *
4047 board(dev)->ai_fifo->num_segments *
4048 board(dev)->ai_fifo->sample_packing_ratio;
4049 }
4050
set_ai_fifo_segment_length(struct comedi_device * dev,unsigned int num_entries)4051 static int set_ai_fifo_segment_length(struct comedi_device *dev,
4052 unsigned int num_entries)
4053 {
4054 static const int increment_size = 0x100;
4055 const struct hw_fifo_info *const fifo = board(dev)->ai_fifo;
4056 unsigned int num_increments;
4057 uint16_t bits;
4058
4059 if (num_entries < increment_size)
4060 num_entries = increment_size;
4061 if (num_entries > fifo->max_segment_length)
4062 num_entries = fifo->max_segment_length;
4063
4064 /* 1 == 256 entries, 2 == 512 entries, etc */
4065 num_increments = (num_entries + increment_size / 2) / increment_size;
4066
4067 bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
4068 priv(dev)->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
4069 priv(dev)->fifo_size_bits |= bits;
4070 writew(priv(dev)->fifo_size_bits,
4071 priv(dev)->main_iobase + FIFO_SIZE_REG);
4072
4073 priv(dev)->ai_fifo_segment_length = num_increments * increment_size;
4074
4075 DEBUG_PRINT("set hardware fifo segment length to %i\n",
4076 priv(dev)->ai_fifo_segment_length);
4077
4078 return priv(dev)->ai_fifo_segment_length;
4079 }
4080
4081 /* pci-6025 8800 caldac:
4082 * address 0 == dac channel 0 offset
4083 * address 1 == dac channel 0 gain
4084 * address 2 == dac channel 1 offset
4085 * address 3 == dac channel 1 gain
4086 * address 4 == fine adc offset
4087 * address 5 == coarse adc offset
4088 * address 6 == coarse adc gain
4089 * address 7 == fine adc gain
4090 */
4091 /* pci-6402/16 uses all 8 channels for dac:
4092 * address 0 == dac channel 0 fine gain
4093 * address 1 == dac channel 0 coarse gain
4094 * address 2 == dac channel 0 coarse offset
4095 * address 3 == dac channel 1 coarse offset
4096 * address 4 == dac channel 1 fine gain
4097 * address 5 == dac channel 1 coarse gain
4098 * address 6 == dac channel 0 fine offset
4099 * address 7 == dac channel 1 fine offset
4100 */
4101
caldac_8800_write(struct comedi_device * dev,unsigned int address,uint8_t value)4102 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
4103 uint8_t value)
4104 {
4105 static const int num_caldac_channels = 8;
4106 static const int bitstream_length = 11;
4107 unsigned int bitstream = ((address & 0x7) << 8) | value;
4108 unsigned int bit, register_bits;
4109 static const int caldac_8800_udelay = 1;
4110
4111 if (address >= num_caldac_channels) {
4112 comedi_error(dev, "illegal caldac channel");
4113 return -1;
4114 }
4115 for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
4116 register_bits = 0;
4117 if (bitstream & bit)
4118 register_bits |= SERIAL_DATA_IN_BIT;
4119 udelay(caldac_8800_udelay);
4120 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4121 register_bits |= SERIAL_CLOCK_BIT;
4122 udelay(caldac_8800_udelay);
4123 writew(register_bits, priv(dev)->main_iobase + CALIBRATION_REG);
4124 }
4125 udelay(caldac_8800_udelay);
4126 writew(SELECT_8800_BIT, priv(dev)->main_iobase + CALIBRATION_REG);
4127 udelay(caldac_8800_udelay);
4128 writew(0, priv(dev)->main_iobase + CALIBRATION_REG);
4129 udelay(caldac_8800_udelay);
4130 return 0;
4131 }
4132
4133 /* 4020 caldacs */
caldac_i2c_write(struct comedi_device * dev,unsigned int caldac_channel,unsigned int value)4134 static int caldac_i2c_write(struct comedi_device *dev,
4135 unsigned int caldac_channel, unsigned int value)
4136 {
4137 uint8_t serial_bytes[3];
4138 uint8_t i2c_addr;
4139 enum pointer_bits {
4140 /* manual has gain and offset bits switched */
4141 OFFSET_0_2 = 0x1,
4142 GAIN_0_2 = 0x2,
4143 OFFSET_1_3 = 0x4,
4144 GAIN_1_3 = 0x8,
4145 };
4146 enum data_bits {
4147 NOT_CLEAR_REGISTERS = 0x20,
4148 };
4149
4150 switch (caldac_channel) {
4151 case 0: /* chan 0 offset */
4152 i2c_addr = CALDAC0_I2C_ADDR;
4153 serial_bytes[0] = OFFSET_0_2;
4154 break;
4155 case 1: /* chan 1 offset */
4156 i2c_addr = CALDAC0_I2C_ADDR;
4157 serial_bytes[0] = OFFSET_1_3;
4158 break;
4159 case 2: /* chan 2 offset */
4160 i2c_addr = CALDAC1_I2C_ADDR;
4161 serial_bytes[0] = OFFSET_0_2;
4162 break;
4163 case 3: /* chan 3 offset */
4164 i2c_addr = CALDAC1_I2C_ADDR;
4165 serial_bytes[0] = OFFSET_1_3;
4166 break;
4167 case 4: /* chan 0 gain */
4168 i2c_addr = CALDAC0_I2C_ADDR;
4169 serial_bytes[0] = GAIN_0_2;
4170 break;
4171 case 5: /* chan 1 gain */
4172 i2c_addr = CALDAC0_I2C_ADDR;
4173 serial_bytes[0] = GAIN_1_3;
4174 break;
4175 case 6: /* chan 2 gain */
4176 i2c_addr = CALDAC1_I2C_ADDR;
4177 serial_bytes[0] = GAIN_0_2;
4178 break;
4179 case 7: /* chan 3 gain */
4180 i2c_addr = CALDAC1_I2C_ADDR;
4181 serial_bytes[0] = GAIN_1_3;
4182 break;
4183 default:
4184 comedi_error(dev, "invalid caldac channel\n");
4185 return -1;
4186 break;
4187 }
4188 serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
4189 serial_bytes[2] = value & 0xff;
4190 i2c_write(dev, i2c_addr, serial_bytes, 3);
4191 return 0;
4192 }
4193
4194 /* Their i2c requires a huge delay on setting clock or data high for some reason */
4195 static const int i2c_high_udelay = 1000;
4196 static const int i2c_low_udelay = 10;
4197
4198 /* set i2c data line high or low */
i2c_set_sda(struct comedi_device * dev,int state)4199 static void i2c_set_sda(struct comedi_device *dev, int state)
4200 {
4201 static const int data_bit = CTL_EE_W;
4202 void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4203 PLX_CONTROL_REG;
4204
4205 if (state) {
4206 /* set data line high */
4207 priv(dev)->plx_control_bits &= ~data_bit;
4208 writel(priv(dev)->plx_control_bits, plx_control_addr);
4209 udelay(i2c_high_udelay);
4210 } else { /* set data line low */
4211
4212 priv(dev)->plx_control_bits |= data_bit;
4213 writel(priv(dev)->plx_control_bits, plx_control_addr);
4214 udelay(i2c_low_udelay);
4215 }
4216 }
4217
4218 /* set i2c clock line high or low */
i2c_set_scl(struct comedi_device * dev,int state)4219 static void i2c_set_scl(struct comedi_device *dev, int state)
4220 {
4221 static const int clock_bit = CTL_USERO;
4222 void __iomem *plx_control_addr = priv(dev)->plx9080_iobase +
4223 PLX_CONTROL_REG;
4224
4225 if (state) {
4226 /* set clock line high */
4227 priv(dev)->plx_control_bits &= ~clock_bit;
4228 writel(priv(dev)->plx_control_bits, plx_control_addr);
4229 udelay(i2c_high_udelay);
4230 } else { /* set clock line low */
4231
4232 priv(dev)->plx_control_bits |= clock_bit;
4233 writel(priv(dev)->plx_control_bits, plx_control_addr);
4234 udelay(i2c_low_udelay);
4235 }
4236 }
4237
i2c_write_byte(struct comedi_device * dev,uint8_t byte)4238 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
4239 {
4240 uint8_t bit;
4241 unsigned int num_bits = 8;
4242
4243 DEBUG_PRINT("writing to i2c byte 0x%x\n", byte);
4244
4245 for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
4246 i2c_set_scl(dev, 0);
4247 if ((byte & bit))
4248 i2c_set_sda(dev, 1);
4249 else
4250 i2c_set_sda(dev, 0);
4251 i2c_set_scl(dev, 1);
4252 }
4253 }
4254
4255 /* we can't really read the lines, so fake it */
i2c_read_ack(struct comedi_device * dev)4256 static int i2c_read_ack(struct comedi_device *dev)
4257 {
4258 i2c_set_scl(dev, 0);
4259 i2c_set_sda(dev, 1);
4260 i2c_set_scl(dev, 1);
4261
4262 return 0; /* return fake acknowledge bit */
4263 }
4264
4265 /* send start bit */
i2c_start(struct comedi_device * dev)4266 static void i2c_start(struct comedi_device *dev)
4267 {
4268 i2c_set_scl(dev, 1);
4269 i2c_set_sda(dev, 1);
4270 i2c_set_sda(dev, 0);
4271 }
4272
4273 /* send stop bit */
i2c_stop(struct comedi_device * dev)4274 static void i2c_stop(struct comedi_device *dev)
4275 {
4276 i2c_set_scl(dev, 0);
4277 i2c_set_sda(dev, 0);
4278 i2c_set_scl(dev, 1);
4279 i2c_set_sda(dev, 1);
4280 }
4281
i2c_write(struct comedi_device * dev,unsigned int address,const uint8_t * data,unsigned int length)4282 static void i2c_write(struct comedi_device *dev, unsigned int address,
4283 const uint8_t * data, unsigned int length)
4284 {
4285 unsigned int i;
4286 uint8_t bitstream;
4287 static const int read_bit = 0x1;
4288
4289 /* XXX need mutex to prevent simultaneous attempts to access eeprom and i2c bus */
4290
4291 /* make sure we dont send anything to eeprom */
4292 priv(dev)->plx_control_bits &= ~CTL_EE_CS;
4293
4294 i2c_stop(dev);
4295 i2c_start(dev);
4296
4297 /* send address and write bit */
4298 bitstream = (address << 1) & ~read_bit;
4299 i2c_write_byte(dev, bitstream);
4300
4301 /* get acknowledge */
4302 if (i2c_read_ack(dev) != 0) {
4303 comedi_error(dev, "i2c write failed: no acknowledge");
4304 i2c_stop(dev);
4305 return;
4306 }
4307 /* write data bytes */
4308 for (i = 0; i < length; i++) {
4309 i2c_write_byte(dev, data[i]);
4310 if (i2c_read_ack(dev) != 0) {
4311 comedi_error(dev, "i2c write failed: no acknowledge");
4312 i2c_stop(dev);
4313 return;
4314 }
4315 }
4316 i2c_stop(dev);
4317 }
4318
4319 MODULE_AUTHOR("Comedi http://www.comedi.org");
4320 MODULE_DESCRIPTION("Comedi low-level driver");
4321 MODULE_LICENSE("GPL");
4322