1
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26 /*********************************************************************/
27 // USB4 DPIA BANDWIDTH ALLOCATION LOGIC
28 /*********************************************************************/
29 #include "link_dp_dpia_bw.h"
30 #include "link_dpcd.h"
31 #include "dc_dmub_srv.h"
32
33 #define DC_LOGGER \
34 link->ctx->logger
35
36 #define Kbps_TO_Gbps (1000 * 1000)
37
38 #define MST_TIME_SLOT_COUNT 64
39
40 // ------------------------------------------------------------------
41 // PRIVATE FUNCTIONS
42 // ------------------------------------------------------------------
43 /*
44 * Always Check the following:
45 * - Is it USB4 link?
46 * - Is HPD HIGH?
47 * - Is BW Allocation Support Mode enabled on DP-Tx?
48 */
link_dp_is_bw_alloc_available(struct dc_link * link)49 static bool link_dp_is_bw_alloc_available(struct dc_link *link)
50 {
51 return (link && link->hpd_status
52 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
53 && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dpia_bw_alloc
54 && link->dpcd_caps.usb4_dp_tun_info.driver_bw_cap.bits.driver_bw_alloc_support);
55 }
56
reset_bw_alloc_struct(struct dc_link * link)57 static void reset_bw_alloc_struct(struct dc_link *link)
58 {
59 link->dpia_bw_alloc_config.bw_alloc_enabled = false;
60 link->dpia_bw_alloc_config.link_verified_bw = 0;
61 link->dpia_bw_alloc_config.link_max_bw = 0;
62 link->dpia_bw_alloc_config.allocated_bw = 0;
63 link->dpia_bw_alloc_config.estimated_bw = 0;
64 link->dpia_bw_alloc_config.bw_granularity = 0;
65 link->dpia_bw_alloc_config.dp_overhead = 0;
66 link->dpia_bw_alloc_config.nrd_max_lane_count = 0;
67 link->dpia_bw_alloc_config.nrd_max_link_rate = 0;
68 for (int i = 0; i < MAX_SINKS_PER_LINK; i++)
69 link->dpia_bw_alloc_config.remote_sink_req_bw[i] = 0;
70 DC_LOG_DEBUG("reset usb4 bw alloc of link(%d)\n", link->link_index);
71 }
72
73 #define BW_GRANULARITY_0 4 // 0.25 Gbps
74 #define BW_GRANULARITY_1 2 // 0.5 Gbps
75 #define BW_GRANULARITY_2 1 // 1 Gbps
76
get_bw_granularity(struct dc_link * link)77 static uint8_t get_bw_granularity(struct dc_link *link)
78 {
79 uint8_t bw_granularity = 0;
80
81 core_link_read_dpcd(
82 link,
83 DP_BW_GRANULALITY,
84 &bw_granularity,
85 sizeof(uint8_t));
86
87 switch (bw_granularity & 0x3) {
88 case 0:
89 bw_granularity = BW_GRANULARITY_0;
90 break;
91 case 1:
92 bw_granularity = BW_GRANULARITY_1;
93 break;
94 case 2:
95 default:
96 bw_granularity = BW_GRANULARITY_2;
97 break;
98 }
99
100 return bw_granularity;
101 }
102
get_estimated_bw(struct dc_link * link)103 static int get_estimated_bw(struct dc_link *link)
104 {
105 uint8_t bw_estimated_bw = 0;
106
107 core_link_read_dpcd(
108 link,
109 ESTIMATED_BW,
110 &bw_estimated_bw,
111 sizeof(uint8_t));
112
113 return bw_estimated_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity);
114 }
115
get_non_reduced_max_link_rate(struct dc_link * link)116 static int get_non_reduced_max_link_rate(struct dc_link *link)
117 {
118 uint8_t nrd_max_link_rate = 0;
119
120 core_link_read_dpcd(
121 link,
122 DP_TUNNELING_MAX_LINK_RATE,
123 &nrd_max_link_rate,
124 sizeof(uint8_t));
125
126 return nrd_max_link_rate;
127 }
128
get_non_reduced_max_lane_count(struct dc_link * link)129 static int get_non_reduced_max_lane_count(struct dc_link *link)
130 {
131 uint8_t nrd_max_lane_count = 0;
132
133 core_link_read_dpcd(
134 link,
135 DP_TUNNELING_MAX_LANE_COUNT,
136 &nrd_max_lane_count,
137 sizeof(uint8_t));
138
139 return nrd_max_lane_count;
140 }
141
142 /*
143 * Read all New BW alloc configuration ex: estimated_bw, allocated_bw,
144 * granuality, Driver_ID, CM_Group, & populate the BW allocation structs
145 * for host router and dpia
146 */
retrieve_usb4_dp_bw_allocation_info(struct dc_link * link)147 static void retrieve_usb4_dp_bw_allocation_info(struct dc_link *link)
148 {
149 reset_bw_alloc_struct(link);
150
151 /* init the known values */
152 link->dpia_bw_alloc_config.bw_granularity = get_bw_granularity(link);
153 link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);
154 link->dpia_bw_alloc_config.nrd_max_link_rate = get_non_reduced_max_link_rate(link);
155 link->dpia_bw_alloc_config.nrd_max_lane_count = get_non_reduced_max_lane_count(link);
156
157 DC_LOG_DEBUG("%s: bw_granularity(%d), estimated_bw(%d)\n",
158 __func__, link->dpia_bw_alloc_config.bw_granularity,
159 link->dpia_bw_alloc_config.estimated_bw);
160 DC_LOG_DEBUG("%s: nrd_max_link_rate(%d), nrd_max_lane_count(%d)\n",
161 __func__, link->dpia_bw_alloc_config.nrd_max_link_rate,
162 link->dpia_bw_alloc_config.nrd_max_lane_count);
163 }
164
165 /*
166 * Cleanup function for when the dpia is unplugged to reset struct
167 * and perform any required clean up
168 *
169 * @link: pointer to the dc_link struct instance
170 *
171 * return: none
172 */
dpia_bw_alloc_unplug(struct dc_link * link)173 static void dpia_bw_alloc_unplug(struct dc_link *link)
174 {
175 if (link) {
176 DC_LOG_DEBUG("%s: resetting BW alloc config for link(%d)\n",
177 __func__, link->link_index);
178 reset_bw_alloc_struct(link);
179 }
180 }
181
link_dpia_send_bw_alloc_request(struct dc_link * link,int req_bw)182 static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw)
183 {
184 uint8_t request_reg_val;
185 uint32_t temp, request_bw;
186
187 if (link->dpia_bw_alloc_config.bw_granularity == 0) {
188 DC_LOG_ERROR("%s: Link[%d]: bw_granularity is zero!", __func__, link->link_index);
189 return;
190 }
191
192 temp = req_bw * link->dpia_bw_alloc_config.bw_granularity;
193 request_reg_val = temp / Kbps_TO_Gbps;
194
195 /* Always make sure to add more to account for floating points */
196 if (temp % Kbps_TO_Gbps)
197 ++request_reg_val;
198
199 request_bw = request_reg_val * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity);
200
201 if (request_bw > link->dpia_bw_alloc_config.estimated_bw) {
202 DC_LOG_ERROR("%s: Link[%d]: Request BW (%d --> %d) > Estimated BW (%d)... Set to Estimated BW!",
203 __func__, link->link_index,
204 req_bw, request_bw, link->dpia_bw_alloc_config.estimated_bw);
205 req_bw = link->dpia_bw_alloc_config.estimated_bw;
206
207 temp = req_bw * link->dpia_bw_alloc_config.bw_granularity;
208 request_reg_val = temp / Kbps_TO_Gbps;
209 if (temp % Kbps_TO_Gbps)
210 ++request_reg_val;
211 }
212
213 link->dpia_bw_alloc_config.allocated_bw = request_bw;
214 DC_LOG_DC("%s: Link[%d]: Request BW: %d", __func__, link->link_index, request_bw);
215
216 core_link_write_dpcd(link, REQUESTED_BW,
217 &request_reg_val,
218 sizeof(uint8_t));
219 }
220
221 // ------------------------------------------------------------------
222 // PUBLIC FUNCTIONS
223 // ------------------------------------------------------------------
link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link * link)224 bool link_dpia_enable_usb4_dp_bw_alloc_mode(struct dc_link *link)
225 {
226 bool ret = false;
227 uint8_t val;
228
229 if (link->hpd_status) {
230 val = DPTX_BW_ALLOC_MODE_ENABLE | DPTX_BW_ALLOC_UNMASK_IRQ;
231
232 if (core_link_write_dpcd(link, DPTX_BW_ALLOCATION_MODE_CONTROL, &val, sizeof(uint8_t)) == DC_OK) {
233 DC_LOG_DEBUG("%s: link[%d] DPTX BW allocation mode enabled", __func__, link->link_index);
234
235 retrieve_usb4_dp_bw_allocation_info(link);
236
237 if (link->dpia_bw_alloc_config.nrd_max_link_rate && link->dpia_bw_alloc_config.nrd_max_lane_count) {
238 link->reported_link_cap.link_rate = link->dpia_bw_alloc_config.nrd_max_link_rate;
239 link->reported_link_cap.lane_count = link->dpia_bw_alloc_config.nrd_max_lane_count;
240 }
241
242 link->dpia_bw_alloc_config.bw_alloc_enabled = true;
243 ret = true;
244
245 if (link->dc->debug.dpia_debug.bits.enable_usb4_bw_zero_alloc_patch) {
246 /*
247 * During DP tunnel creation, the CM preallocates BW
248 * and reduces the estimated BW of other DPIAs.
249 * The CM releases the preallocation only when the allocation is complete.
250 * Perform a zero allocation to make the CM release the preallocation
251 * and correctly update the estimated BW for all DPIAs per host router.
252 */
253 link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0);
254 }
255 } else
256 DC_LOG_DEBUG("%s: link[%d] failed to enable DPTX BW allocation mode", __func__, link->link_index);
257 }
258
259 return ret;
260 }
261
262 /*
263 * Handle DP BW allocation status register
264 *
265 * @link: pointer to the dc_link struct instance
266 * @status: content of DP tunneling status DPCD register
267 *
268 * return: none
269 */
link_dp_dpia_handle_bw_alloc_status(struct dc_link * link,uint8_t status)270 void link_dp_dpia_handle_bw_alloc_status(struct dc_link *link, uint8_t status)
271 {
272 link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);
273
274 if (status & DP_TUNNELING_BW_REQUEST_SUCCEEDED) {
275 DC_LOG_DEBUG("%s: BW Allocation request succeeded on link(%d)",
276 __func__, link->link_index);
277 } else if (status & DP_TUNNELING_BW_REQUEST_FAILED) {
278 DC_LOG_DEBUG("%s: BW Allocation request failed on link(%d) allocated/estimated BW=%d",
279 __func__, link->link_index, link->dpia_bw_alloc_config.estimated_bw);
280
281 link_dpia_send_bw_alloc_request(link, link->dpia_bw_alloc_config.estimated_bw);
282 } else if (status & DP_TUNNELING_ESTIMATED_BW_CHANGED) {
283 DC_LOG_DEBUG("%s: Estimated BW changed on link(%d) new estimated BW=%d",
284 __func__, link->link_index, link->dpia_bw_alloc_config.estimated_bw);
285 }
286
287 core_link_write_dpcd(
288 link, DP_TUNNELING_STATUS,
289 &status, sizeof(status));
290 }
291
292 /*
293 * Handle the DP Bandwidth allocation for DPIA
294 *
295 */
dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link * link,int peak_bw)296 void dpia_handle_usb4_bandwidth_allocation_for_link(struct dc_link *link, int peak_bw)
297 {
298 if (link && link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling
299 && link->dpia_bw_alloc_config.bw_alloc_enabled) {
300 //1. Hot Plug
301 if (link->hpd_status && peak_bw > 0) {
302 // If DP over USB4 then we need to check BW allocation
303 link->dpia_bw_alloc_config.link_max_bw = peak_bw;
304
305 link_dpia_send_bw_alloc_request(link, peak_bw);
306 }
307 //2. Cold Unplug
308 else if (!link->hpd_status)
309 dpia_bw_alloc_unplug(link);
310 }
311 }
312
link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link * link,int req_bw)313 void link_dp_dpia_allocate_usb4_bandwidth_for_stream(struct dc_link *link, int req_bw)
314 {
315 link->dpia_bw_alloc_config.estimated_bw = get_estimated_bw(link);
316
317 DC_LOG_DEBUG("%s: ENTER: link[%d] hpd(%d) Allocated_BW: %d Estimated_BW: %d Req_BW: %d",
318 __func__, link->link_index, link->hpd_status,
319 link->dpia_bw_alloc_config.allocated_bw,
320 link->dpia_bw_alloc_config.estimated_bw,
321 req_bw);
322
323 if (link_dp_is_bw_alloc_available(link))
324 link_dpia_send_bw_alloc_request(link, req_bw);
325 else
326 DC_LOG_DEBUG("%s: BW Allocation mode not available", __func__);
327 }
328
link_dpia_get_dp_overhead(const struct dc_link * link)329 uint32_t link_dpia_get_dp_overhead(const struct dc_link *link)
330 {
331 uint32_t link_dp_overhead = 0;
332
333 if ((link->type == dc_connection_mst_branch) &&
334 !link->dpcd_caps.channel_coding_cap.bits.DP_128b_132b_SUPPORTED) {
335 /* For 8b/10b encoding: MTP is 64 time slots long, slot 0 is used for MTPH
336 * MST overhead is 1/64 of link bandwidth (excluding any overhead)
337 */
338 const struct dc_link_settings *link_cap = dc_link_get_link_cap(link);
339
340 if (link_cap) {
341 uint32_t link_bw_in_kbps = (uint32_t)link_cap->link_rate *
342 (uint32_t)link_cap->lane_count *
343 LINK_RATE_REF_FREQ_IN_KHZ * 8;
344 link_dp_overhead = (link_bw_in_kbps / MST_TIME_SLOT_COUNT)
345 + ((link_bw_in_kbps % MST_TIME_SLOT_COUNT) ? 1 : 0);
346 }
347 }
348
349 return link_dp_overhead;
350 }
351
352 /*
353 * Aggregates the DPIA bandwidth usage for the respective USB4 Router.
354 * And then validate if the required bandwidth is within the router's capacity.
355 *
356 * @dc_validation_dpia_set: pointer to the dc_validation_dpia_set
357 * @count: number of DPIA validation sets
358 *
359 * return: true if validation is succeeded
360 */
link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set * dpia_link_sets,uint8_t count)361 bool link_dpia_validate_dp_tunnel_bandwidth(const struct dc_validation_dpia_set *dpia_link_sets, uint8_t count)
362 {
363 uint32_t granularity_Gbps;
364 const struct dc_link *link;
365 uint32_t link_bw_granularity;
366 uint32_t link_required_bw;
367 struct usb4_router_validation_set router_sets[MAX_HOST_ROUTERS_NUM] = { 0 };
368 uint8_t i;
369 bool is_success = true;
370 uint8_t router_count = 0;
371
372 if ((dpia_link_sets == NULL) || (count == 0))
373 return is_success;
374
375 // Iterate through each DP tunneling link (DPIA).
376 // Aggregate its bandwidth requirements onto the respective USB4 router.
377 for (i = 0; i < count; i++) {
378 link = dpia_link_sets[i].link;
379 link_required_bw = dpia_link_sets[i].required_bw;
380 const struct dc_tunnel_settings *dp_tunnel_settings = dpia_link_sets[i].tunnel_settings;
381
382 if ((link == NULL) || (dp_tunnel_settings == NULL) || dp_tunnel_settings->bw_granularity == 0)
383 break;
384
385 if (link->type == dc_connection_mst_branch)
386 link_required_bw += link_dpia_get_dp_overhead(link);
387
388 granularity_Gbps = (Kbps_TO_Gbps / dp_tunnel_settings->bw_granularity);
389 link_bw_granularity = (link_required_bw / granularity_Gbps) * granularity_Gbps +
390 ((link_required_bw % granularity_Gbps) ? granularity_Gbps : 0);
391
392 // Find or add the USB4 router associated with the current DPIA link
393 for (uint8_t j = 0; j < MAX_HOST_ROUTERS_NUM; j++) {
394 if (router_sets[j].is_valid == false) {
395 router_sets[j].is_valid = true;
396 router_sets[j].cm_id = dp_tunnel_settings->cm_id;
397 router_count++;
398 }
399
400 if (router_sets[j].cm_id == dp_tunnel_settings->cm_id) {
401 uint32_t remaining_bw =
402 dp_tunnel_settings->estimated_bw - dp_tunnel_settings->allocated_bw;
403
404 router_sets[j].allocated_bw += dp_tunnel_settings->allocated_bw;
405
406 if (remaining_bw > router_sets[j].remaining_bw)
407 router_sets[j].remaining_bw = remaining_bw;
408
409 // Get the max estimated BW within the same CM_ID
410 if (dp_tunnel_settings->estimated_bw > router_sets[j].estimated_bw)
411 router_sets[j].estimated_bw = dp_tunnel_settings->estimated_bw;
412
413 router_sets[j].required_bw += link_bw_granularity;
414 router_sets[j].dpia_count++;
415 break;
416 }
417 }
418 }
419
420 // Validate bandwidth for each unique router found.
421 for (i = 0; i < router_count; i++) {
422 uint32_t total_bw = 0;
423
424 if (router_sets[i].is_valid == false)
425 break;
426
427 // Determine the total available bandwidth for the current router based on aggregated data
428 if ((router_sets[i].dpia_count == 1) || (router_sets[i].allocated_bw == 0))
429 total_bw = router_sets[i].estimated_bw;
430 else
431 total_bw = router_sets[i].allocated_bw + router_sets[i].remaining_bw;
432
433 if (router_sets[i].required_bw > total_bw) {
434 is_success = false;
435 break;
436 }
437 }
438
439 return is_success;
440 }
441
442