1 /*
2 * QEMU MCH/ICH9 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009, 2010, 2011
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9 *
10 * This is based on piix.c, but heavily modified.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/log.h"
33 #include "hw/i386/pc.h"
34 #include "hw/pci-host/q35.h"
35 #include "hw/qdev-properties.h"
36 #include "migration/vmstate.h"
37 #include "qapi/error.h"
38 #include "qapi/visitor.h"
39 #include "qemu/module.h"
40
41 /****************************************************************************
42 * Q35 host
43 */
44
45 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35)
46
q35_host_realize(DeviceState * dev,Error ** errp)47 static void q35_host_realize(DeviceState *dev, Error **errp)
48 {
49 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
50 Q35PCIHost *s = Q35_HOST_DEVICE(dev);
51 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
52
53 memory_region_add_subregion(s->mch.address_space_io,
54 MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
55 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
56
57 memory_region_add_subregion(s->mch.address_space_io,
58 MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
59 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
60
61 /* register q35 0xcf8 port as coalesced pio */
62 memory_region_set_flush_coalesced(&pci->data_mem);
63 memory_region_add_coalescing(&pci->conf_mem, 0, 4);
64
65 pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0",
66 s->mch.pci_address_space,
67 s->mch.address_space_io,
68 0, TYPE_PCIE_BUS);
69
70 qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal);
71 }
72
q35_host_root_bus_path(PCIHostState * host_bridge,PCIBus * rootbus)73 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
74 PCIBus *rootbus)
75 {
76 return "0000:00";
77 }
78
q35_host_get_pci_hole_start(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)79 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
80 const char *name, void *opaque,
81 Error **errp)
82 {
83 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
84 uint64_t val64;
85 uint32_t value;
86
87 val64 = range_is_empty(&s->mch.pci_hole)
88 ? 0 : range_lob(&s->mch.pci_hole);
89 value = val64;
90 assert(value == val64);
91 visit_type_uint32(v, name, &value, errp);
92 }
93
q35_host_get_pci_hole_end(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)94 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
95 const char *name, void *opaque,
96 Error **errp)
97 {
98 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
99 uint64_t val64;
100 uint32_t value;
101
102 val64 = range_is_empty(&s->mch.pci_hole)
103 ? 0 : range_upb(&s->mch.pci_hole) + 1;
104 value = val64;
105 assert(value == val64);
106 visit_type_uint32(v, name, &value, errp);
107 }
108
109 /*
110 * The 64bit PCI hole start is set by the Guest firmware
111 * as the address of the first 64bit PCI MEM resource.
112 * If no PCI device has resources on the 64bit area,
113 * the 64bit PCI hole will start after "over 4G RAM" and the
114 * reserved space for memory hotplug if any.
115 */
q35_host_get_pci_hole64_start_value(Object * obj)116 static uint64_t q35_host_get_pci_hole64_start_value(Object *obj)
117 {
118 PCIHostState *h = PCI_HOST_BRIDGE(obj);
119 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
120 Range w64;
121 uint64_t value;
122
123 pci_bus_get_w64_range(h->bus, &w64);
124 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
125 if (!value && s->pci_hole64_fix) {
126 value = pc_pci_hole64_start();
127 }
128 return value;
129 }
130
q35_host_get_pci_hole64_start(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)131 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
132 const char *name, void *opaque,
133 Error **errp)
134 {
135 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj);
136
137 visit_type_uint64(v, name, &hole64_start, errp);
138 }
139
140 /*
141 * The 64bit PCI hole end is set by the Guest firmware
142 * as the address of the last 64bit PCI MEM resource.
143 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
144 * that can be configured by the user.
145 */
q35_host_get_pci_hole64_end(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)146 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
147 const char *name, void *opaque,
148 Error **errp)
149 {
150 PCIHostState *h = PCI_HOST_BRIDGE(obj);
151 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
152 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj);
153 Range w64;
154 uint64_t value, hole64_end;
155
156 pci_bus_get_w64_range(h->bus, &w64);
157 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
158 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30);
159 if (s->pci_hole64_fix && value < hole64_end) {
160 value = hole64_end;
161 }
162 visit_type_uint64(v, name, &value, errp);
163 }
164
165 /*
166 * NOTE: setting defaults for the mch.* fields in this table
167 * doesn't work, because mch is a separate QOM object that is
168 * zeroed by the object_initialize(&s->mch, ...) call inside
169 * q35_host_initfn(). The default values for those
170 * properties need to be initialized manually by
171 * q35_host_initfn() after the object_initialize() call.
172 */
173 static const Property q35_host_props[] = {
174 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
175 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
176 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
177 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT),
178 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
179 mch.below_4g_mem_size, 0),
180 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
181 mch.above_4g_mem_size, 0),
182 DEFINE_PROP_BOOL(PCI_HOST_PROP_SMM_RANGES, Q35PCIHost,
183 mch.has_smm_ranges, true),
184 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true),
185 };
186
q35_host_class_init(ObjectClass * klass,const void * data)187 static void q35_host_class_init(ObjectClass *klass, const void *data)
188 {
189 DeviceClass *dc = DEVICE_CLASS(klass);
190 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
191
192 hc->root_bus_path = q35_host_root_bus_path;
193 dc->realize = q35_host_realize;
194 device_class_set_props(dc, q35_host_props);
195 /* Reason: needs to be wired up by pc_q35_init */
196 dc->user_creatable = false;
197 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
198 dc->fw_name = "pci";
199 }
200
q35_host_initfn(Object * obj)201 static void q35_host_initfn(Object *obj)
202 {
203 Q35PCIHost *s = Q35_HOST_DEVICE(obj);
204 PCIHostState *phb = PCI_HOST_BRIDGE(obj);
205 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj);
206
207 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
208 "pci-conf-idx", 4);
209 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
210 "pci-conf-data", 4);
211
212 object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE);
213 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
214 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
215 /* mch's object_initialize resets the default value, set it again */
216 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE,
217 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT);
218
219 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
220 q35_host_get_pci_hole_start,
221 NULL, NULL, NULL);
222
223 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
224 q35_host_get_pci_hole_end,
225 NULL, NULL, NULL);
226
227 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
228 q35_host_get_pci_hole64_start,
229 NULL, NULL, NULL);
230
231 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
232 q35_host_get_pci_hole64_end,
233 NULL, NULL, NULL);
234
235 object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE,
236 &pehb->size, OBJ_PROP_FLAG_READ);
237
238 object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
239 (Object **) &s->mch.ram_memory,
240 qdev_prop_allow_set_link_before_realize, 0);
241
242 object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
243 (Object **) &s->mch.pci_address_space,
244 qdev_prop_allow_set_link_before_realize, 0);
245
246 object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
247 (Object **) &s->mch.system_memory,
248 qdev_prop_allow_set_link_before_realize, 0);
249
250 object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
251 (Object **) &s->mch.address_space_io,
252 qdev_prop_allow_set_link_before_realize, 0);
253 }
254
255 static const TypeInfo q35_host_info = {
256 .name = TYPE_Q35_HOST_DEVICE,
257 .parent = TYPE_PCIE_HOST_BRIDGE,
258 .instance_size = sizeof(Q35PCIHost),
259 .instance_init = q35_host_initfn,
260 .class_init = q35_host_class_init,
261 };
262
263 /****************************************************************************
264 * MCH D0:F0
265 */
266
blackhole_read(void * ptr,hwaddr reg,unsigned size)267 static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size)
268 {
269 return 0xffffffff;
270 }
271
blackhole_write(void * opaque,hwaddr addr,uint64_t val,unsigned width)272 static void blackhole_write(void *opaque, hwaddr addr, uint64_t val,
273 unsigned width)
274 {
275 /* nothing */
276 }
277
278 static const MemoryRegionOps blackhole_ops = {
279 .read = blackhole_read,
280 .write = blackhole_write,
281 .valid.min_access_size = 1,
282 .valid.max_access_size = 4,
283 .impl.min_access_size = 4,
284 .impl.max_access_size = 4,
285 .endianness = DEVICE_LITTLE_ENDIAN,
286 };
287
288 /* PCIe MMCFG */
mch_update_pciexbar(MCHPCIState * mch)289 static void mch_update_pciexbar(MCHPCIState *mch)
290 {
291 PCIDevice *pci_dev = PCI_DEVICE(mch);
292 BusState *bus = qdev_get_parent_bus(DEVICE(mch));
293 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
294
295 uint64_t pciexbar;
296 int enable;
297 uint64_t addr;
298 uint64_t addr_mask;
299 uint32_t length;
300
301 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
302 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
303 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
304 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
305 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
306 length = 256 * 1024 * 1024;
307 break;
308 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
309 length = 128 * 1024 * 1024;
310 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
311 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
312 break;
313 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
314 length = 64 * 1024 * 1024;
315 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
316 break;
317 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
318 qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n");
319 return;
320 default:
321 abort();
322 }
323 addr = pciexbar & addr_mask;
324 pcie_host_mmcfg_update(pehb, enable, addr, length);
325 }
326
327 /* PAM */
mch_update_pam(MCHPCIState * mch)328 static void mch_update_pam(MCHPCIState *mch)
329 {
330 PCIDevice *pd = PCI_DEVICE(mch);
331 int i;
332
333 memory_region_transaction_begin();
334 for (i = 0; i < 13; i++) {
335 pam_update(&mch->pam_regions[i], i,
336 pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]);
337 }
338 memory_region_transaction_commit();
339 }
340
341 /* SMRAM */
mch_update_smram(MCHPCIState * mch)342 static void mch_update_smram(MCHPCIState *mch)
343 {
344 PCIDevice *pd = PCI_DEVICE(mch);
345 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
346 uint32_t tseg_size;
347
348 /* implement SMRAM.D_LCK */
349 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) {
350 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN;
351 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK;
352 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK;
353 }
354
355 memory_region_transaction_begin();
356
357 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
358 /* Hide (!) low SMRAM if H_SMRAME = 1 */
359 memory_region_set_enabled(&mch->smram_region, h_smrame);
360 /* Show high SMRAM if H_SMRAME = 1 */
361 memory_region_set_enabled(&mch->open_high_smram, h_smrame);
362 } else {
363 /* Hide high SMRAM and low SMRAM */
364 memory_region_set_enabled(&mch->smram_region, true);
365 memory_region_set_enabled(&mch->open_high_smram, false);
366 }
367
368 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) {
369 memory_region_set_enabled(&mch->low_smram, !h_smrame);
370 memory_region_set_enabled(&mch->high_smram, h_smrame);
371 } else {
372 memory_region_set_enabled(&mch->low_smram, false);
373 memory_region_set_enabled(&mch->high_smram, false);
374 }
375
376 if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) &&
377 (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) {
378 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] &
379 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
380 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB:
381 tseg_size = 1024 * 1024;
382 break;
383 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB:
384 tseg_size = 1024 * 1024 * 2;
385 break;
386 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB:
387 tseg_size = 1024 * 1024 * 8;
388 break;
389 default:
390 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes;
391 break;
392 }
393 } else {
394 tseg_size = 0;
395 }
396 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
397 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
398 memory_region_set_size(&mch->tseg_blackhole, tseg_size);
399 memory_region_add_subregion_overlap(mch->system_memory,
400 mch->below_4g_mem_size - tseg_size,
401 &mch->tseg_blackhole, 1);
402
403 memory_region_set_enabled(&mch->tseg_window, tseg_size);
404 memory_region_set_size(&mch->tseg_window, tseg_size);
405 memory_region_set_address(&mch->tseg_window,
406 mch->below_4g_mem_size - tseg_size);
407 memory_region_set_alias_offset(&mch->tseg_window,
408 mch->below_4g_mem_size - tseg_size);
409
410 memory_region_transaction_commit();
411 }
412
mch_update_ext_tseg_mbytes(MCHPCIState * mch)413 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch)
414 {
415 PCIDevice *pd = PCI_DEVICE(mch);
416 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES;
417
418 if (mch->ext_tseg_mbytes > 0 &&
419 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) {
420 pci_set_word(reg, mch->ext_tseg_mbytes);
421 }
422 }
423
mch_update_smbase_smram(MCHPCIState * mch)424 static void mch_update_smbase_smram(MCHPCIState *mch)
425 {
426 PCIDevice *pd = PCI_DEVICE(mch);
427 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE;
428 bool lck;
429
430 if (!mch->has_smram_at_smbase) {
431 return;
432 }
433
434 if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) {
435 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =
436 MCH_HOST_BRIDGE_F_SMBASE_LCK;
437 *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM;
438 return;
439 }
440
441 /*
442 * default/reset state, discard written value
443 * which will disable SMRAM balackhole at SMBASE
444 */
445 if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) {
446 *reg = 0x00;
447 }
448
449 memory_region_transaction_begin();
450 if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) {
451 /* disable all writes */
452 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &=
453 ~MCH_HOST_BRIDGE_F_SMBASE_LCK;
454 *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK;
455 lck = true;
456 } else {
457 lck = false;
458 }
459 memory_region_set_enabled(&mch->smbase_blackhole, lck);
460 memory_region_set_enabled(&mch->smbase_window, lck);
461 memory_region_transaction_commit();
462 }
463
mch_write_config(PCIDevice * d,uint32_t address,uint32_t val,int len)464 static void mch_write_config(PCIDevice *d,
465 uint32_t address, uint32_t val, int len)
466 {
467 MCHPCIState *mch = MCH_PCI_DEVICE(d);
468
469 pci_default_write_config(d, address, val, len);
470
471 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
472 MCH_HOST_BRIDGE_PAM_SIZE)) {
473 mch_update_pam(mch);
474 }
475
476 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
477 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
478 mch_update_pciexbar(mch);
479 }
480
481 if (!mch->has_smm_ranges) {
482 return;
483 }
484
485 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
486 MCH_HOST_BRIDGE_SMRAM_SIZE)) {
487 mch_update_smram(mch);
488 }
489
490 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
491 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) {
492 mch_update_ext_tseg_mbytes(mch);
493 }
494
495 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) {
496 mch_update_smbase_smram(mch);
497 }
498 }
499
mch_update(MCHPCIState * mch)500 static void mch_update(MCHPCIState *mch)
501 {
502 mch_update_pciexbar(mch);
503
504 mch_update_pam(mch);
505 if (mch->has_smm_ranges) {
506 mch_update_smram(mch);
507 mch_update_ext_tseg_mbytes(mch);
508 mch_update_smbase_smram(mch);
509 }
510
511 /*
512 * pci hole goes from end-of-low-ram to io-apic.
513 * mmconfig will be excluded by the dsdt builder.
514 */
515 range_set_bounds(&mch->pci_hole,
516 mch->below_4g_mem_size,
517 IO_APIC_DEFAULT_ADDRESS - 1);
518 }
519
mch_post_load(void * opaque,int version_id)520 static int mch_post_load(void *opaque, int version_id)
521 {
522 MCHPCIState *mch = opaque;
523 mch_update(mch);
524 return 0;
525 }
526
527 static const VMStateDescription vmstate_mch = {
528 .name = "mch",
529 .version_id = 1,
530 .minimum_version_id = 1,
531 .post_load = mch_post_load,
532 .fields = (const VMStateField[]) {
533 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
534 /* Used to be smm_enabled, which was basically always zero because
535 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
536 */
537 VMSTATE_UNUSED(1),
538 VMSTATE_END_OF_LIST()
539 }
540 };
541
mch_reset(DeviceState * qdev)542 static void mch_reset(DeviceState *qdev)
543 {
544 PCIDevice *d = PCI_DEVICE(qdev);
545 MCHPCIState *mch = MCH_PCI_DEVICE(d);
546
547 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
548 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
549
550 if (mch->has_smm_ranges) {
551 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
552 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT;
553 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK;
554 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK;
555
556 if (mch->ext_tseg_mbytes > 0) {
557 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES,
558 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY);
559 }
560
561 d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0;
562 d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff;
563 }
564
565 mch_update(mch);
566 }
567
mch_realize(PCIDevice * d,Error ** errp)568 static void mch_realize(PCIDevice *d, Error **errp)
569 {
570 int i;
571 MCHPCIState *mch = MCH_PCI_DEVICE(d);
572
573 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) {
574 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16,
575 mch->ext_tseg_mbytes);
576 return;
577 }
578
579 /* setup pci memory mapping */
580 pc_pci_as_mapping_init(mch->system_memory, mch->pci_address_space);
581
582 /* PAM */
583 init_pam(&mch->pam_regions[0], OBJECT(mch), mch->ram_memory,
584 mch->system_memory, mch->pci_address_space,
585 PAM_BIOS_BASE, PAM_BIOS_SIZE);
586 for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) {
587 init_pam(&mch->pam_regions[i + 1], OBJECT(mch), mch->ram_memory,
588 mch->system_memory, mch->pci_address_space,
589 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
590 }
591
592 if (!mch->has_smm_ranges) {
593 return;
594 }
595
596 /* if *disabled* show SMRAM to all CPUs */
597 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
598 mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE,
599 MCH_HOST_BRIDGE_SMRAM_C_SIZE);
600 memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
601 &mch->smram_region, 1);
602 memory_region_set_enabled(&mch->smram_region, true);
603
604 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
605 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
606 MCH_HOST_BRIDGE_SMRAM_C_SIZE);
607 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
608 &mch->open_high_smram, 1);
609 memory_region_set_enabled(&mch->open_high_smram, false);
610
611 /* smram, as seen by SMM CPUs */
612 memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB);
613 memory_region_set_enabled(&mch->smram, true);
614 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
615 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
616 MCH_HOST_BRIDGE_SMRAM_C_SIZE);
617 memory_region_set_enabled(&mch->low_smram, true);
618 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE,
619 &mch->low_smram);
620 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
621 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE,
622 MCH_HOST_BRIDGE_SMRAM_C_SIZE);
623 memory_region_set_enabled(&mch->high_smram, true);
624 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
625
626 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
627 &blackhole_ops, NULL,
628 "tseg-blackhole", 0);
629 memory_region_set_enabled(&mch->tseg_blackhole, false);
630 memory_region_add_subregion_overlap(mch->system_memory,
631 mch->below_4g_mem_size,
632 &mch->tseg_blackhole, 1);
633
634 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
635 mch->ram_memory, mch->below_4g_mem_size, 0);
636 memory_region_set_enabled(&mch->tseg_window, false);
637 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size,
638 &mch->tseg_window);
639
640 /*
641 * This is not what hardware does, so it's QEMU specific hack.
642 * See commit message for details.
643 */
644 memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops,
645 NULL, "smbase-blackhole",
646 MCH_HOST_BRIDGE_SMBASE_SIZE);
647 memory_region_set_enabled(&mch->smbase_blackhole, false);
648 memory_region_add_subregion_overlap(mch->system_memory,
649 MCH_HOST_BRIDGE_SMBASE_ADDR,
650 &mch->smbase_blackhole, 1);
651
652 memory_region_init_alias(&mch->smbase_window, OBJECT(mch),
653 "smbase-window", mch->ram_memory,
654 MCH_HOST_BRIDGE_SMBASE_ADDR,
655 MCH_HOST_BRIDGE_SMBASE_SIZE);
656 memory_region_set_enabled(&mch->smbase_window, false);
657 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR,
658 &mch->smbase_window);
659
660 object_property_add_const_link(qdev_get_machine(), "smram",
661 OBJECT(&mch->smram));
662 }
663
664 static const Property mch_props[] = {
665 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes,
666 16),
667 DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true),
668 };
669
mch_class_init(ObjectClass * klass,const void * data)670 static void mch_class_init(ObjectClass *klass, const void *data)
671 {
672 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
673 DeviceClass *dc = DEVICE_CLASS(klass);
674
675 k->realize = mch_realize;
676 k->config_write = mch_write_config;
677 device_class_set_legacy_reset(dc, mch_reset);
678 device_class_set_props(dc, mch_props);
679 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
680 dc->desc = "Host bridge";
681 dc->vmsd = &vmstate_mch;
682 k->vendor_id = PCI_VENDOR_ID_INTEL;
683 /*
684 * The 'q35' machine type implements an Intel Series 3 chipset,
685 * of which there are several variants. The key difference between
686 * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that
687 * the latter has an integrated graphics adapter. QEMU does not
688 * implement integrated graphics, so uses the PCI ID for the 82P35
689 * chipset.
690 */
691 k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH;
692 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
693 k->class_id = PCI_CLASS_BRIDGE_HOST;
694 /*
695 * PCI-facing part of the host bridge, not usable without the
696 * host-facing part, which can't be device_add'ed, yet.
697 */
698 dc->user_creatable = false;
699 }
700
701 static const TypeInfo mch_info = {
702 .name = TYPE_MCH_PCI_DEVICE,
703 .parent = TYPE_PCI_DEVICE,
704 .instance_size = sizeof(MCHPCIState),
705 .class_init = mch_class_init,
706 .interfaces = (const InterfaceInfo[]) {
707 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
708 { },
709 },
710 };
711
q35_register(void)712 static void q35_register(void)
713 {
714 type_register_static(&mch_info);
715 type_register_static(&q35_host_info);
716 }
717
718 type_init(q35_register);
719