1 /* 2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_CPU_H 19 #define HEXAGON_CPU_H 20 21 #include "fpu/softfloat-types.h" 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-common.h" 25 #include "exec/cpu-defs.h" 26 #include "hex_regs.h" 27 #include "mmvec/mmvec.h" 28 #include "hw/registerfields.h" 29 30 #ifndef CONFIG_USER_ONLY 31 #error "Hexagon does not support system emulation" 32 #endif 33 34 #define NUM_PREGS 4 35 #define TOTAL_PER_THREAD_REGS 64 36 37 #define SLOTS_MAX 4 38 #define STORES_MAX 2 39 #define REG_WRITES_MAX 32 40 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ 41 #define VSTORES_MAX 2 42 43 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU 44 45 #define MMU_USER_IDX 0 46 47 typedef struct { 48 target_ulong va; 49 uint8_t width; 50 uint32_t data32; 51 uint64_t data64; 52 } MemLog; 53 54 typedef struct { 55 target_ulong va; 56 int size; 57 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); 58 MMVector data QEMU_ALIGNED(16); 59 } VStoreLog; 60 61 #define EXEC_STATUS_OK 0x0000 62 #define EXEC_STATUS_STOP 0x0002 63 #define EXEC_STATUS_REPLAY 0x0010 64 #define EXEC_STATUS_LOCKED 0x0020 65 #define EXEC_STATUS_EXCEPTION 0x0100 66 67 68 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) 69 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) 70 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) 71 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) 72 73 /* Maximum number of vector temps in a packet */ 74 #define VECTOR_TEMPS_MAX 4 75 76 typedef struct CPUArchState { 77 target_ulong gpr[TOTAL_PER_THREAD_REGS]; 78 target_ulong pred[NUM_PREGS]; 79 80 /* For comparing with LLDB on target - see adjust_stack_ptrs function */ 81 target_ulong last_pc_dumped; 82 target_ulong stack_start; 83 84 uint8_t slot_cancelled; 85 target_ulong new_value_usr; 86 87 MemLog mem_log_stores[STORES_MAX]; 88 89 float_status fp_status; 90 91 target_ulong llsc_addr; 92 target_ulong llsc_val; 93 uint64_t llsc_val_i64; 94 95 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); 96 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 97 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 98 99 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); 100 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); 101 102 /* Temporaries used within instructions */ 103 MMVectorPair VuuV QEMU_ALIGNED(16); 104 MMVectorPair VvvV QEMU_ALIGNED(16); 105 MMVectorPair VxxV QEMU_ALIGNED(16); 106 MMVector vtmp QEMU_ALIGNED(16); 107 MMQReg qtmp QEMU_ALIGNED(16); 108 109 VStoreLog vstore[VSTORES_MAX]; 110 target_ulong vstore_pending[VSTORES_MAX]; 111 bool vtcm_pending; 112 VTCMStoreLog vtcm_log; 113 } CPUHexagonState; 114 115 typedef struct HexagonCPUClass { 116 CPUClass parent_class; 117 118 DeviceRealize parent_realize; 119 ResettablePhases parent_phases; 120 } HexagonCPUClass; 121 122 struct ArchCPU { 123 CPUState parent_obj; 124 125 CPUHexagonState env; 126 127 bool lldb_compat; 128 target_ulong lldb_stack_adjust; 129 bool short_circuit; 130 }; 131 132 #include "cpu_bits.h" 133 134 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) 135 136 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, 137 uint32_t exception, 138 uintptr_t pc); 139 140 typedef HexagonCPU ArchCPU; 141 142 void hexagon_translate_init(void); 143 void hexagon_translate_code(CPUState *cs, TranslationBlock *tb, 144 int *max_insns, vaddr pc, void *host_pc); 145 146 #endif /* HEXAGON_CPU_H */ 147