1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_LAPIC_H
3 #define __KVM_X86_LAPIC_H
4
5 #include <kvm/iodev.h>
6
7 #include <asm/apic.h>
8
9 #include <linux/kvm_host.h>
10
11 #include "hyperv.h"
12 #include "smm.h"
13
14 #define KVM_APIC_INIT 0
15 #define KVM_APIC_SIPI 1
16
17 #define APIC_SHORT_MASK 0xc0000
18 #define APIC_DEST_NOSHORT 0x0
19 #define APIC_DEST_MASK 0x800
20
21 #define APIC_BUS_CYCLE_NS_DEFAULT 1
22
23 #define APIC_BROADCAST 0xFF
24 #define X2APIC_BROADCAST 0xFFFFFFFFul
25
26 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
27
28 enum lapic_mode {
29 LAPIC_MODE_DISABLED = 0,
30 LAPIC_MODE_INVALID = X2APIC_ENABLE,
31 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
32 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
33 };
34
35 enum lapic_lvt_entry {
36 LVT_TIMER,
37 LVT_THERMAL_MONITOR,
38 LVT_PERFORMANCE_COUNTER,
39 LVT_LINT0,
40 LVT_LINT1,
41 LVT_ERROR,
42 LVT_CMCI,
43
44 KVM_APIC_MAX_NR_LVT_ENTRIES,
45 };
46
47 #define APIC_LVTx(x) ((x) == LVT_CMCI ? APIC_LVTCMCI : APIC_LVTT + 0x10 * (x))
48
49 struct kvm_timer {
50 struct hrtimer timer;
51 s64 period; /* unit: ns */
52 ktime_t target_expiration;
53 u32 timer_mode;
54 u32 timer_mode_mask;
55 u64 tscdeadline;
56 u64 expired_tscdeadline;
57 u32 timer_advance_ns;
58 atomic_t pending; /* accumulated triggered timers */
59 bool hv_timer_in_use;
60 };
61
62 struct kvm_lapic {
63 unsigned long base_address;
64 struct kvm_io_device dev;
65 struct kvm_timer lapic_timer;
66 u32 divide_count;
67 struct kvm_vcpu *vcpu;
68 bool apicv_active;
69 bool sw_enabled;
70 bool irr_pending;
71 bool lvt0_in_nmi_mode;
72 /* Select registers in the vAPIC cannot be read/written. */
73 bool guest_apic_protected;
74 /* Number of bits set in ISR. */
75 s16 isr_count;
76 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
77 int highest_isr_cache;
78 /**
79 * APIC register page. The layout matches the register layout seen by
80 * the guest 1:1, because it is accessed by the vmx microcode.
81 * Note: Only one register, the TPR, is used by the microcode.
82 */
83 void *regs;
84 gpa_t vapic_addr;
85 struct gfn_to_hva_cache vapic_cache;
86 unsigned long pending_events;
87 unsigned int sipi_vector;
88 int nr_lvt_entries;
89 };
90
91 struct rtc_status;
92
93 int kvm_create_lapic(struct kvm_vcpu *vcpu);
94 void kvm_free_lapic(struct kvm_vcpu *vcpu);
95
96 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
97 void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector);
98 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
99 int kvm_apic_accept_events(struct kvm_vcpu *vcpu);
100 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
101 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
102 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
103 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
104 void kvm_apic_set_version(struct kvm_vcpu *vcpu);
105 void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu);
106 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
107 int shorthand, unsigned int dest, int dest_mode);
108 void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
109 bool __kvm_apic_update_irr(unsigned long *pir, void *regs, int *max_irr);
110 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, unsigned long *pir, int *max_irr);
111 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
112 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
113 struct rtc_status *rtc_status);
114 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
115 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
116 int kvm_alloc_apic_access_page(struct kvm *kvm);
117 void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu);
118
119 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
120 struct kvm_lapic_irq *irq, int *r);
121 int __kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
122 struct kvm_lapic_irq *irq,
123 struct rtc_status *rtc_status);
124
kvm_irq_delivery_to_apic(struct kvm * kvm,struct kvm_lapic * src,struct kvm_lapic_irq * irq)125 static inline int kvm_irq_delivery_to_apic(struct kvm *kvm,
126 struct kvm_lapic *src,
127 struct kvm_lapic_irq *irq)
128 {
129 return __kvm_irq_delivery_to_apic(kvm, src, irq, NULL);
130 }
131
132 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
133
134 int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated);
135 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
136 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
137 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
138
139 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
140 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
141
142 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
143 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
144
145 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
146 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
147 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
148
149 int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data);
150 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
151 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
152
153 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
154 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
155
156 int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
157 void kvm_lapic_exit(void);
158
159 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
160
kvm_lapic_set_irr(int vec,struct kvm_lapic * apic)161 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
162 {
163 apic_set_vector(vec, apic->regs + APIC_IRR);
164 /*
165 * irr_pending must be true if any interrupt is pending; set it after
166 * APIC_IRR to avoid race with apic_clear_irr
167 */
168 apic->irr_pending = true;
169 }
170
kvm_lapic_get_reg(struct kvm_lapic * apic,int reg_off)171 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
172 {
173 return apic_get_reg(apic->regs, reg_off);
174 }
175
176 DECLARE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
177
lapic_in_kernel(struct kvm_vcpu * vcpu)178 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
179 {
180 if (static_branch_unlikely(&kvm_has_noapic_vcpu))
181 return vcpu->arch.apic;
182 return true;
183 }
184
185 extern struct static_key_false_deferred apic_hw_disabled;
186
kvm_apic_hw_enabled(struct kvm_lapic * apic)187 static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)
188 {
189 if (static_branch_unlikely(&apic_hw_disabled.key))
190 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
191 return true;
192 }
193
194 extern struct static_key_false_deferred apic_sw_disabled;
195
kvm_apic_sw_enabled(struct kvm_lapic * apic)196 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
197 {
198 if (static_branch_unlikely(&apic_sw_disabled.key))
199 return apic->sw_enabled;
200 return true;
201 }
202
kvm_apic_present(struct kvm_vcpu * vcpu)203 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
204 {
205 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
206 }
207
kvm_lapic_enabled(struct kvm_vcpu * vcpu)208 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
209 {
210 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
211 }
212
apic_x2apic_mode(struct kvm_lapic * apic)213 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
214 {
215 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
216 }
217
kvm_vcpu_apicv_active(struct kvm_vcpu * vcpu)218 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
219 {
220 return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;
221 }
222
kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu * vcpu)223 static inline bool kvm_apic_has_pending_init_or_sipi(struct kvm_vcpu *vcpu)
224 {
225 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
226 }
227
kvm_apic_init_sipi_allowed(struct kvm_vcpu * vcpu)228 static inline bool kvm_apic_init_sipi_allowed(struct kvm_vcpu *vcpu)
229 {
230 return !is_smm(vcpu) &&
231 !kvm_x86_call(apic_init_signal_blocked)(vcpu);
232 }
233
kvm_lapic_latched_init(struct kvm_vcpu * vcpu)234 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
235 {
236 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
237 }
238
239 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
240
241 bool kvm_lapic_suppress_eoi_broadcast(struct kvm_lapic *apic);
242
243 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
244
245 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
246 unsigned long *vcpu_bitmap);
247
248 bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
249 struct kvm_vcpu **dest_vcpu);
250 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
251 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
252 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
253 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
254 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
255
kvm_apic_mode(u64 apic_base)256 static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
257 {
258 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
259 }
260
kvm_get_apic_mode(struct kvm_vcpu * vcpu)261 static inline enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
262 {
263 return kvm_apic_mode(vcpu->arch.apic_base);
264 }
265
kvm_xapic_id(struct kvm_lapic * apic)266 static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
267 {
268 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
269 }
270
271 #endif
272