1 /*
2 * VPIF header file
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #ifndef VPIF_H
17 #define VPIF_H
18
19 #include <linux/io.h>
20 #include <linux/videodev2.h>
21 #include <mach/hardware.h>
22 #include <mach/dm646x.h>
23 #include <media/davinci/vpif_types.h>
24
25 /* Maximum channel allowed */
26 #define VPIF_NUM_CHANNELS (4)
27 #define VPIF_CAPTURE_NUM_CHANNELS (2)
28 #define VPIF_DISPLAY_NUM_CHANNELS (2)
29
30 /* Macros to read/write registers */
31 extern void __iomem *vpif_base;
32 extern spinlock_t vpif_lock;
33
34 #define regr(reg) readl((reg) + vpif_base)
35 #define regw(value, reg) writel(value, (reg + vpif_base))
36
37 /* Register Address Offsets */
38 #define VPIF_PID (0x0000)
39 #define VPIF_CH0_CTRL (0x0004)
40 #define VPIF_CH1_CTRL (0x0008)
41 #define VPIF_CH2_CTRL (0x000C)
42 #define VPIF_CH3_CTRL (0x0010)
43
44 #define VPIF_INTEN (0x0020)
45 #define VPIF_INTEN_SET (0x0024)
46 #define VPIF_INTEN_CLR (0x0028)
47 #define VPIF_STATUS (0x002C)
48 #define VPIF_STATUS_CLR (0x0030)
49 #define VPIF_EMULATION_CTRL (0x0034)
50 #define VPIF_REQ_SIZE (0x0038)
51
52 #define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040)
53 #define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044)
54 #define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048)
55 #define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c)
56 #define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050)
57 #define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054)
58 #define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058)
59 #define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c)
60 #define VPIF_CH0_SP_CFG (0x0060)
61 #define VPIF_CH0_IMG_ADD_OFST (0x0064)
62 #define VPIF_CH0_HANC_ADD_OFST (0x0068)
63 #define VPIF_CH0_H_CFG (0x006c)
64 #define VPIF_CH0_V_CFG_00 (0x0070)
65 #define VPIF_CH0_V_CFG_01 (0x0074)
66 #define VPIF_CH0_V_CFG_02 (0x0078)
67 #define VPIF_CH0_V_CFG_03 (0x007c)
68
69 #define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080)
70 #define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084)
71 #define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088)
72 #define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c)
73 #define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090)
74 #define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094)
75 #define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098)
76 #define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c)
77 #define VPIF_CH1_SP_CFG (0x00a0)
78 #define VPIF_CH1_IMG_ADD_OFST (0x00a4)
79 #define VPIF_CH1_HANC_ADD_OFST (0x00a8)
80 #define VPIF_CH1_H_CFG (0x00ac)
81 #define VPIF_CH1_V_CFG_00 (0x00b0)
82 #define VPIF_CH1_V_CFG_01 (0x00b4)
83 #define VPIF_CH1_V_CFG_02 (0x00b8)
84 #define VPIF_CH1_V_CFG_03 (0x00bc)
85
86 #define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0)
87 #define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4)
88 #define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8)
89 #define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc)
90 #define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0)
91 #define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4)
92 #define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8)
93 #define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc)
94 #define VPIF_CH2_SP_CFG (0x00e0)
95 #define VPIF_CH2_IMG_ADD_OFST (0x00e4)
96 #define VPIF_CH2_HANC_ADD_OFST (0x00e8)
97 #define VPIF_CH2_H_CFG (0x00ec)
98 #define VPIF_CH2_V_CFG_00 (0x00f0)
99 #define VPIF_CH2_V_CFG_01 (0x00f4)
100 #define VPIF_CH2_V_CFG_02 (0x00f8)
101 #define VPIF_CH2_V_CFG_03 (0x00fc)
102 #define VPIF_CH2_HANC0_STRT (0x0100)
103 #define VPIF_CH2_HANC0_SIZE (0x0104)
104 #define VPIF_CH2_HANC1_STRT (0x0108)
105 #define VPIF_CH2_HANC1_SIZE (0x010c)
106 #define VPIF_CH2_VANC0_STRT (0x0110)
107 #define VPIF_CH2_VANC0_SIZE (0x0114)
108 #define VPIF_CH2_VANC1_STRT (0x0118)
109 #define VPIF_CH2_VANC1_SIZE (0x011c)
110
111 #define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140)
112 #define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144)
113 #define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148)
114 #define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c)
115 #define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150)
116 #define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154)
117 #define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158)
118 #define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c)
119 #define VPIF_CH3_SP_CFG (0x0160)
120 #define VPIF_CH3_IMG_ADD_OFST (0x0164)
121 #define VPIF_CH3_HANC_ADD_OFST (0x0168)
122 #define VPIF_CH3_H_CFG (0x016c)
123 #define VPIF_CH3_V_CFG_00 (0x0170)
124 #define VPIF_CH3_V_CFG_01 (0x0174)
125 #define VPIF_CH3_V_CFG_02 (0x0178)
126 #define VPIF_CH3_V_CFG_03 (0x017c)
127 #define VPIF_CH3_HANC0_STRT (0x0180)
128 #define VPIF_CH3_HANC0_SIZE (0x0184)
129 #define VPIF_CH3_HANC1_STRT (0x0188)
130 #define VPIF_CH3_HANC1_SIZE (0x018c)
131 #define VPIF_CH3_VANC0_STRT (0x0190)
132 #define VPIF_CH3_VANC0_SIZE (0x0194)
133 #define VPIF_CH3_VANC1_STRT (0x0198)
134 #define VPIF_CH3_VANC1_SIZE (0x019c)
135
136 #define VPIF_IODFT_CTRL (0x01c0)
137
138 /* Functions for bit Manipulation */
vpif_set_bit(u32 reg,u32 bit)139 static inline void vpif_set_bit(u32 reg, u32 bit)
140 {
141 regw((regr(reg)) | (0x01 << bit), reg);
142 }
143
vpif_clr_bit(u32 reg,u32 bit)144 static inline void vpif_clr_bit(u32 reg, u32 bit)
145 {
146 regw(((regr(reg)) & ~(0x01 << bit)), reg);
147 }
148
149 /* Macro for Generating mask */
150 #ifdef GENERATE_MASK
151 #undef GENERATE_MASK
152 #endif
153
154 #define GENERATE_MASK(bits, pos) \
155 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
156
157 /* Bit positions in the channel control registers */
158 #define VPIF_CH_DATA_MODE_BIT (2)
159 #define VPIF_CH_YC_MUX_BIT (3)
160 #define VPIF_CH_SDR_FMT_BIT (4)
161 #define VPIF_CH_HANC_EN_BIT (8)
162 #define VPIF_CH_VANC_EN_BIT (9)
163
164 #define VPIF_CAPTURE_CH_NIP (10)
165 #define VPIF_DISPLAY_CH_NIP (11)
166
167 #define VPIF_DISPLAY_PIX_EN_BIT (10)
168
169 #define VPIF_CH_INPUT_FIELD_FRAME_BIT (12)
170
171 #define VPIF_CH_FID_POLARITY_BIT (15)
172 #define VPIF_CH_V_VALID_POLARITY_BIT (14)
173 #define VPIF_CH_H_VALID_POLARITY_BIT (13)
174 #define VPIF_CH_DATA_WIDTH_BIT (28)
175
176 #define VPIF_CH_CLK_EDGE_CTRL_BIT (31)
177
178 /* Mask various length */
179 #define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0)
180 #define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0)
181 #define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0)
182 #define VPIF_CH_LEN_SHIFT (16)
183
184 /* VPIF masks for registers */
185 #define VPIF_REQ_SIZE_MASK (0x1ff)
186
187 /* bit posotion of interrupt vpif_ch_intr register */
188 #define VPIF_INTEN_FRAME_CH0 (0x00000001)
189 #define VPIF_INTEN_FRAME_CH1 (0x00000002)
190 #define VPIF_INTEN_FRAME_CH2 (0x00000004)
191 #define VPIF_INTEN_FRAME_CH3 (0x00000008)
192
193 /* bit position of clock and channel enable in vpif_chn_ctrl register */
194
195 #define VPIF_CH0_CLK_EN (0x00000002)
196 #define VPIF_CH0_EN (0x00000001)
197 #define VPIF_CH1_CLK_EN (0x00000002)
198 #define VPIF_CH1_EN (0x00000001)
199 #define VPIF_CH2_CLK_EN (0x00000002)
200 #define VPIF_CH2_EN (0x00000001)
201 #define VPIF_CH3_CLK_EN (0x00000002)
202 #define VPIF_CH3_EN (0x00000001)
203 #define VPIF_CH_CLK_EN (0x00000002)
204 #define VPIF_CH_EN (0x00000001)
205
206 #define VPIF_INT_TOP (0x00)
207 #define VPIF_INT_BOTTOM (0x01)
208 #define VPIF_INT_BOTH (0x02)
209
210 #define VPIF_CH0_INT_CTRL_SHIFT (6)
211 #define VPIF_CH1_INT_CTRL_SHIFT (6)
212 #define VPIF_CH2_INT_CTRL_SHIFT (6)
213 #define VPIF_CH3_INT_CTRL_SHIFT (6)
214 #define VPIF_CH_INT_CTRL_SHIFT (6)
215
216 /* enabled interrupt on both the fields on vpid_ch0_ctrl register */
217 #define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
218 (VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL))
219
220 /* enabled interrupt on both the fields on vpid_ch1_ctrl register */
221 #define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
222 (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL))
223
224 /* enabled interrupt on both the fields on vpid_ch0_ctrl register */
225 #define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
226 (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL))
227
228 /* enabled interrupt on both the fields on vpid_ch1_ctrl register */
229 #define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
230 (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL))
231
232 #define VPIF_CH_FID_MASK (0x20)
233 #define VPIF_CH_FID_SHIFT (5)
234
235 #define VPIF_NTSC_VBI_START_FIELD0 (1)
236 #define VPIF_NTSC_VBI_START_FIELD1 (263)
237 #define VPIF_PAL_VBI_START_FIELD0 (624)
238 #define VPIF_PAL_VBI_START_FIELD1 (311)
239
240 #define VPIF_NTSC_HBI_START_FIELD0 (1)
241 #define VPIF_NTSC_HBI_START_FIELD1 (263)
242 #define VPIF_PAL_HBI_START_FIELD0 (624)
243 #define VPIF_PAL_HBI_START_FIELD1 (311)
244
245 #define VPIF_NTSC_VBI_COUNT_FIELD0 (20)
246 #define VPIF_NTSC_VBI_COUNT_FIELD1 (19)
247 #define VPIF_PAL_VBI_COUNT_FIELD0 (24)
248 #define VPIF_PAL_VBI_COUNT_FIELD1 (25)
249
250 #define VPIF_NTSC_HBI_COUNT_FIELD0 (263)
251 #define VPIF_NTSC_HBI_COUNT_FIELD1 (262)
252 #define VPIF_PAL_HBI_COUNT_FIELD0 (312)
253 #define VPIF_PAL_HBI_COUNT_FIELD1 (313)
254
255 #define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720)
256 #define VPIF_PAL_VBI_SAMPLES_PER_LINE (720)
257 #define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268)
258 #define VPIF_PAL_HBI_SAMPLES_PER_LINE (280)
259
260 #define VPIF_CH_VANC_EN (0x20)
261 #define VPIF_DMA_REQ_SIZE (0x080)
262 #define VPIF_EMULATION_DISABLE (0x01)
263
264 extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS];
265
266 /* inline function to enable/disable channel0 */
enable_channel0(int enable)267 static inline void enable_channel0(int enable)
268 {
269 if (enable)
270 regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);
271 else
272 regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);
273 }
274
275 /* inline function to enable/disable channel1 */
enable_channel1(int enable)276 static inline void enable_channel1(int enable)
277 {
278 if (enable)
279 regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);
280 else
281 regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);
282 }
283
284 /* inline function to enable interrupt for channel0 */
channel0_intr_enable(int enable)285 static inline void channel0_intr_enable(int enable)
286 {
287 unsigned long flags;
288
289 spin_lock_irqsave(&vpif_lock, flags);
290
291 if (enable) {
292 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
293 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
294
295 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);
296 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
297 VPIF_INTEN_SET);
298 } else {
299 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);
300 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
301 VPIF_INTEN_SET);
302 }
303 spin_unlock_irqrestore(&vpif_lock, flags);
304 }
305
306 /* inline function to enable interrupt for channel1 */
channel1_intr_enable(int enable)307 static inline void channel1_intr_enable(int enable)
308 {
309 unsigned long flags;
310
311 spin_lock_irqsave(&vpif_lock, flags);
312
313 if (enable) {
314 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
315 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
316
317 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);
318 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
319 VPIF_INTEN_SET);
320 } else {
321 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);
322 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
323 VPIF_INTEN_SET);
324 }
325 spin_unlock_irqrestore(&vpif_lock, flags);
326 }
327
328 /* inline function to set buffer addresses in case of Y/C non mux mode */
ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)329 static inline void ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,
330 unsigned long btm_strt_luma,
331 unsigned long top_strt_chroma,
332 unsigned long btm_strt_chroma)
333 {
334 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
335 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
336 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
337 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
338 }
339
340 /* inline function to set buffer addresses in VPIF registers for video data */
ch0_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)341 static inline void ch0_set_videobuf_addr(unsigned long top_strt_luma,
342 unsigned long btm_strt_luma,
343 unsigned long top_strt_chroma,
344 unsigned long btm_strt_chroma)
345 {
346 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
347 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
348 regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA);
349 regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA);
350 }
351
ch1_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)352 static inline void ch1_set_videobuf_addr(unsigned long top_strt_luma,
353 unsigned long btm_strt_luma,
354 unsigned long top_strt_chroma,
355 unsigned long btm_strt_chroma)
356 {
357
358 regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA);
359 regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA);
360 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
361 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
362 }
363
ch0_set_vbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)364 static inline void ch0_set_vbi_addr(unsigned long top_vbi,
365 unsigned long btm_vbi, unsigned long a, unsigned long b)
366 {
367 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC);
368 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC);
369 }
370
ch0_set_hbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)371 static inline void ch0_set_hbi_addr(unsigned long top_vbi,
372 unsigned long btm_vbi, unsigned long a, unsigned long b)
373 {
374 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC);
375 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC);
376 }
377
ch1_set_vbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)378 static inline void ch1_set_vbi_addr(unsigned long top_vbi,
379 unsigned long btm_vbi, unsigned long a, unsigned long b)
380 {
381 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC);
382 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC);
383 }
384
ch1_set_hbi_addr(unsigned long top_vbi,unsigned long btm_vbi,unsigned long a,unsigned long b)385 static inline void ch1_set_hbi_addr(unsigned long top_vbi,
386 unsigned long btm_vbi, unsigned long a, unsigned long b)
387 {
388 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC);
389 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC);
390 }
391
392 /* Inline function to enable raw vbi in the given channel */
disable_raw_feature(u8 channel_id,u8 index)393 static inline void disable_raw_feature(u8 channel_id, u8 index)
394 {
395 u32 ctrl_reg;
396 if (0 == channel_id)
397 ctrl_reg = VPIF_CH0_CTRL;
398 else
399 ctrl_reg = VPIF_CH1_CTRL;
400
401 if (1 == index)
402 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
403 else
404 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
405 }
406
enable_raw_feature(u8 channel_id,u8 index)407 static inline void enable_raw_feature(u8 channel_id, u8 index)
408 {
409 u32 ctrl_reg;
410 if (0 == channel_id)
411 ctrl_reg = VPIF_CH0_CTRL;
412 else
413 ctrl_reg = VPIF_CH1_CTRL;
414
415 if (1 == index)
416 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
417 else
418 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
419 }
420
421 /* inline function to enable/disable channel2 */
enable_channel2(int enable)422 static inline void enable_channel2(int enable)
423 {
424 if (enable) {
425 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
426 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);
427 } else {
428 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
429 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);
430 }
431 }
432
433 /* inline function to enable/disable channel3 */
enable_channel3(int enable)434 static inline void enable_channel3(int enable)
435 {
436 if (enable) {
437 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
438 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);
439 } else {
440 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
441 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);
442 }
443 }
444
445 /* inline function to enable interrupt for channel2 */
channel2_intr_enable(int enable)446 static inline void channel2_intr_enable(int enable)
447 {
448 unsigned long flags;
449
450 spin_lock_irqsave(&vpif_lock, flags);
451
452 if (enable) {
453 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
454 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
455 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);
456 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
457 VPIF_INTEN_SET);
458 } else {
459 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);
460 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
461 VPIF_INTEN_SET);
462 }
463 spin_unlock_irqrestore(&vpif_lock, flags);
464 }
465
466 /* inline function to enable interrupt for channel3 */
channel3_intr_enable(int enable)467 static inline void channel3_intr_enable(int enable)
468 {
469 unsigned long flags;
470
471 spin_lock_irqsave(&vpif_lock, flags);
472
473 if (enable) {
474 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
475 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
476
477 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);
478 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
479 VPIF_INTEN_SET);
480 } else {
481 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);
482 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
483 VPIF_INTEN_SET);
484 }
485 spin_unlock_irqrestore(&vpif_lock, flags);
486 }
487
488 /* inline function to enable raw vbi data for channel2 */
channel2_raw_enable(int enable,u8 index)489 static inline void channel2_raw_enable(int enable, u8 index)
490 {
491 u32 mask;
492
493 if (1 == index)
494 mask = VPIF_CH_VANC_EN_BIT;
495 else
496 mask = VPIF_CH_HANC_EN_BIT;
497
498 if (enable)
499 vpif_set_bit(VPIF_CH2_CTRL, mask);
500 else
501 vpif_clr_bit(VPIF_CH2_CTRL, mask);
502 }
503
504 /* inline function to enable raw vbi data for channel3*/
channel3_raw_enable(int enable,u8 index)505 static inline void channel3_raw_enable(int enable, u8 index)
506 {
507 u32 mask;
508
509 if (1 == index)
510 mask = VPIF_CH_VANC_EN_BIT;
511 else
512 mask = VPIF_CH_HANC_EN_BIT;
513
514 if (enable)
515 vpif_set_bit(VPIF_CH3_CTRL, mask);
516 else
517 vpif_clr_bit(VPIF_CH3_CTRL, mask);
518 }
519
520 /* inline function to set buffer addresses in case of Y/C non mux mode */
ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)521 static inline void ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,
522 unsigned long btm_strt_luma,
523 unsigned long top_strt_chroma,
524 unsigned long btm_strt_chroma)
525 {
526 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
527 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
528 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
529 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
530 }
531
532 /* inline function to set buffer addresses in VPIF registers for video data */
ch2_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)533 static inline void ch2_set_videobuf_addr(unsigned long top_strt_luma,
534 unsigned long btm_strt_luma,
535 unsigned long top_strt_chroma,
536 unsigned long btm_strt_chroma)
537 {
538 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
539 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
540 regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA);
541 regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA);
542 }
543
ch3_set_videobuf_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)544 static inline void ch3_set_videobuf_addr(unsigned long top_strt_luma,
545 unsigned long btm_strt_luma,
546 unsigned long top_strt_chroma,
547 unsigned long btm_strt_chroma)
548 {
549 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA);
550 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA);
551 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
552 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
553 }
554
555 /* inline function to set buffer addresses in VPIF registers for vbi data */
ch2_set_vbi_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)556 static inline void ch2_set_vbi_addr(unsigned long top_strt_luma,
557 unsigned long btm_strt_luma,
558 unsigned long top_strt_chroma,
559 unsigned long btm_strt_chroma)
560 {
561 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC);
562 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC);
563 }
564
ch3_set_vbi_addr(unsigned long top_strt_luma,unsigned long btm_strt_luma,unsigned long top_strt_chroma,unsigned long btm_strt_chroma)565 static inline void ch3_set_vbi_addr(unsigned long top_strt_luma,
566 unsigned long btm_strt_luma,
567 unsigned long top_strt_chroma,
568 unsigned long btm_strt_chroma)
569 {
570 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC);
571 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC);
572 }
573
574 #define VPIF_MAX_NAME (30)
575
576 /* This structure will store size parameters as per the mode selected by user */
577 struct vpif_channel_config_params {
578 char name[VPIF_MAX_NAME]; /* Name of the mode */
579 u16 width; /* Indicates width of the image */
580 u16 height; /* Indicates height of the image */
581 u8 frm_fmt; /* Interlaced (0) or progressive (1) */
582 u8 ycmux_mode; /* This mode requires one (0) or two (1)
583 channels */
584 u16 eav2sav; /* length of eav 2 sav */
585 u16 sav2eav; /* length of sav 2 eav */
586 u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */
587 u16 vsize; /* Vertical size of the image */
588 u8 capture_format; /* Indicates whether capture format
589 * is in BT or in CCD/CMOS */
590 u8 vbi_supported; /* Indicates whether this mode
591 * supports capturing vbi or not */
592 u8 hd_sd; /* HDTV (1) or SDTV (0) format */
593 v4l2_std_id stdid; /* SDTV format */
594 u32 dv_preset; /* HDTV format */
595 };
596
597 extern const unsigned int vpif_ch_params_count;
598 extern const struct vpif_channel_config_params ch_params[];
599
600 struct vpif_video_params;
601 struct vpif_params;
602 struct vpif_vbi_params;
603
604 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id);
605 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
606 u8 channel_id);
607 int vpif_channel_getfid(u8 channel_id);
608
609 enum data_size {
610 _8BITS = 0,
611 _10BITS,
612 _12BITS,
613 };
614
615 /* Structure for vpif parameters for raw vbi data */
616 struct vpif_vbi_params {
617 __u32 hstart0; /* Horizontal start of raw vbi data for first field */
618 __u32 vstart0; /* Vertical start of raw vbi data for first field */
619 __u32 hsize0; /* Horizontal size of raw vbi data for first field */
620 __u32 vsize0; /* Vertical size of raw vbi data for first field */
621 __u32 hstart1; /* Horizontal start of raw vbi data for second field */
622 __u32 vstart1; /* Vertical start of raw vbi data for second field */
623 __u32 hsize1; /* Horizontal size of raw vbi data for second field */
624 __u32 vsize1; /* Vertical size of raw vbi data for second field */
625 };
626
627 /* structure for vpif parameters */
628 struct vpif_video_params {
629 __u8 storage_mode; /* Indicates field or frame mode */
630 unsigned long hpitch;
631 v4l2_std_id stdid;
632 };
633
634 struct vpif_params {
635 struct vpif_interface iface;
636 struct vpif_video_params video_params;
637 struct vpif_channel_config_params std_info;
638 union param {
639 struct vpif_vbi_params vbi_params;
640 enum data_size data_sz;
641 } params;
642 };
643
644 #endif /* End of #ifndef VPIF_H */
645
646