1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * derived from drivers/kvm/kvm_main.c
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright (C) 2008 Qumranet, Inc.
9 * Copyright IBM Corporation, 2008
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 *
12 * Authors:
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Amit Shah <amit.shah@qumranet.com>
16 * Ben-Ami Yassour <benami@il.ibm.com>
17 */
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/kvm_host.h>
21 #include "irq.h"
22 #include "ioapic.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
28 #include "mmu/page_track.h"
29 #include "x86.h"
30 #include "cpuid.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33 #include "lapic.h"
34 #include "xen.h"
35 #include "smm.h"
36
37 #include <linux/clocksource.h>
38 #include <linux/interrupt.h>
39 #include <linux/kvm.h>
40 #include <linux/fs.h>
41 #include <linux/vmalloc.h>
42 #include <linux/export.h>
43 #include <linux/moduleparam.h>
44 #include <linux/mman.h>
45 #include <linux/highmem.h>
46 #include <linux/iommu.h>
47 #include <linux/cpufreq.h>
48 #include <linux/user-return-notifier.h>
49 #include <linux/srcu.h>
50 #include <linux/slab.h>
51 #include <linux/perf_event.h>
52 #include <linux/uaccess.h>
53 #include <linux/hash.h>
54 #include <linux/pci.h>
55 #include <linux/timekeeper_internal.h>
56 #include <linux/pvclock_gtod.h>
57 #include <linux/kvm_irqfd.h>
58 #include <linux/irqbypass.h>
59 #include <linux/sched/stat.h>
60 #include <linux/sched/isolation.h>
61 #include <linux/mem_encrypt.h>
62 #include <linux/entry-kvm.h>
63 #include <linux/suspend.h>
64 #include <linux/smp.h>
65
66 #include <trace/events/ipi.h>
67 #include <trace/events/kvm.h>
68
69 #include <asm/debugreg.h>
70 #include <asm/msr.h>
71 #include <asm/desc.h>
72 #include <asm/mce.h>
73 #include <asm/pkru.h>
74 #include <linux/kernel_stat.h>
75 #include <asm/fpu/api.h>
76 #include <asm/fpu/xcr.h>
77 #include <asm/fpu/xstate.h>
78 #include <asm/pvclock.h>
79 #include <asm/div64.h>
80 #include <asm/irq_remapping.h>
81 #include <asm/mshyperv.h>
82 #include <asm/hypervisor.h>
83 #include <asm/tlbflush.h>
84 #include <asm/intel_pt.h>
85 #include <asm/emulate_prefix.h>
86 #include <asm/sgx.h>
87 #include <clocksource/hyperv_timer.h>
88
89 #define CREATE_TRACE_POINTS
90 #include "trace.h"
91
92 #define MAX_IO_MSRS 256
93 #define KVM_MAX_MCE_BANKS 32
94
95 struct kvm_caps kvm_caps __read_mostly = {
96 .supported_mce_cap = MCG_CTL_P | MCG_SER_P,
97 };
98 EXPORT_SYMBOL_GPL(kvm_caps);
99
100 #define ERR_PTR_USR(e) ((void __user *)ERR_PTR(e))
101
102 #define emul_to_vcpu(ctxt) \
103 ((struct kvm_vcpu *)(ctxt)->vcpu)
104
105 /* EFER defaults:
106 * - enable syscall per default because its emulated by KVM
107 * - enable LME and LMA per default on 64 bit KVM
108 */
109 #ifdef CONFIG_X86_64
110 static
111 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
112 #else
113 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
114 #endif
115
116 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
117
118 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
119
120 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
121
122 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
123 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
124
125 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
126 static void process_nmi(struct kvm_vcpu *vcpu);
127 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
128 static void store_regs(struct kvm_vcpu *vcpu);
129 static int sync_regs(struct kvm_vcpu *vcpu);
130 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
131
132 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
133 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
134
135 static DEFINE_MUTEX(vendor_module_lock);
136 struct kvm_x86_ops kvm_x86_ops __read_mostly;
137
138 #define KVM_X86_OP(func) \
139 DEFINE_STATIC_CALL_NULL(kvm_x86_##func, \
140 *(((struct kvm_x86_ops *)0)->func));
141 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
142 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
143 #include <asm/kvm-x86-ops.h>
144 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
145 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
146
147 static bool __read_mostly ignore_msrs = 0;
148 module_param(ignore_msrs, bool, 0644);
149
150 bool __read_mostly report_ignored_msrs = true;
151 module_param(report_ignored_msrs, bool, 0644);
152 EXPORT_SYMBOL_GPL(report_ignored_msrs);
153
154 unsigned int min_timer_period_us = 200;
155 module_param(min_timer_period_us, uint, 0644);
156
157 static bool __read_mostly kvmclock_periodic_sync = true;
158 module_param(kvmclock_periodic_sync, bool, 0444);
159
160 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
161 static u32 __read_mostly tsc_tolerance_ppm = 250;
162 module_param(tsc_tolerance_ppm, uint, 0644);
163
164 /*
165 * lapic timer advance (tscdeadline mode only) in nanoseconds. '-1' enables
166 * adaptive tuning starting from default advancement of 1000ns. '0' disables
167 * advancement entirely. Any other value is used as-is and disables adaptive
168 * tuning, i.e. allows privileged userspace to set an exact advancement time.
169 */
170 static int __read_mostly lapic_timer_advance_ns = -1;
171 module_param(lapic_timer_advance_ns, int, 0644);
172
173 static bool __read_mostly vector_hashing = true;
174 module_param(vector_hashing, bool, 0444);
175
176 bool __read_mostly enable_vmware_backdoor = false;
177 module_param(enable_vmware_backdoor, bool, 0444);
178 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
179
180 /*
181 * Flags to manipulate forced emulation behavior (any non-zero value will
182 * enable forced emulation).
183 */
184 #define KVM_FEP_CLEAR_RFLAGS_RF BIT(1)
185 static int __read_mostly force_emulation_prefix;
186 module_param(force_emulation_prefix, int, 0644);
187
188 int __read_mostly pi_inject_timer = -1;
189 module_param(pi_inject_timer, bint, 0644);
190
191 /* Enable/disable PMU virtualization */
192 bool __read_mostly enable_pmu = true;
193 EXPORT_SYMBOL_GPL(enable_pmu);
194 module_param(enable_pmu, bool, 0444);
195
196 bool __read_mostly eager_page_split = true;
197 module_param(eager_page_split, bool, 0644);
198
199 /* Enable/disable SMT_RSB bug mitigation */
200 static bool __read_mostly mitigate_smt_rsb;
201 module_param(mitigate_smt_rsb, bool, 0444);
202
203 /*
204 * Restoring the host value for MSRs that are only consumed when running in
205 * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
206 * returns to userspace, i.e. the kernel can run with the guest's value.
207 */
208 #define KVM_MAX_NR_USER_RETURN_MSRS 16
209
210 struct kvm_user_return_msrs {
211 struct user_return_notifier urn;
212 bool registered;
213 struct kvm_user_return_msr_values {
214 u64 host;
215 u64 curr;
216 } values[KVM_MAX_NR_USER_RETURN_MSRS];
217 };
218
219 u32 __read_mostly kvm_nr_uret_msrs;
220 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
221 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
222 static struct kvm_user_return_msrs __percpu *user_return_msrs;
223
224 #define KVM_SUPPORTED_XCR0 (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
225 | XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
226 | XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
227 | XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
228
229 u64 __read_mostly host_efer;
230 EXPORT_SYMBOL_GPL(host_efer);
231
232 bool __read_mostly allow_smaller_maxphyaddr = 0;
233 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
234
235 bool __read_mostly enable_apicv = true;
236 EXPORT_SYMBOL_GPL(enable_apicv);
237
238 u64 __read_mostly host_xss;
239 EXPORT_SYMBOL_GPL(host_xss);
240
241 u64 __read_mostly host_arch_capabilities;
242 EXPORT_SYMBOL_GPL(host_arch_capabilities);
243
244 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
245 KVM_GENERIC_VM_STATS(),
246 STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
247 STATS_DESC_COUNTER(VM, mmu_pte_write),
248 STATS_DESC_COUNTER(VM, mmu_pde_zapped),
249 STATS_DESC_COUNTER(VM, mmu_flooded),
250 STATS_DESC_COUNTER(VM, mmu_recycled),
251 STATS_DESC_COUNTER(VM, mmu_cache_miss),
252 STATS_DESC_ICOUNTER(VM, mmu_unsync),
253 STATS_DESC_ICOUNTER(VM, pages_4k),
254 STATS_DESC_ICOUNTER(VM, pages_2m),
255 STATS_DESC_ICOUNTER(VM, pages_1g),
256 STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
257 STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
258 STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
259 };
260
261 const struct kvm_stats_header kvm_vm_stats_header = {
262 .name_size = KVM_STATS_NAME_SIZE,
263 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
264 .id_offset = sizeof(struct kvm_stats_header),
265 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
266 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
267 sizeof(kvm_vm_stats_desc),
268 };
269
270 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
271 KVM_GENERIC_VCPU_STATS(),
272 STATS_DESC_COUNTER(VCPU, pf_taken),
273 STATS_DESC_COUNTER(VCPU, pf_fixed),
274 STATS_DESC_COUNTER(VCPU, pf_emulate),
275 STATS_DESC_COUNTER(VCPU, pf_spurious),
276 STATS_DESC_COUNTER(VCPU, pf_fast),
277 STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
278 STATS_DESC_COUNTER(VCPU, pf_guest),
279 STATS_DESC_COUNTER(VCPU, tlb_flush),
280 STATS_DESC_COUNTER(VCPU, invlpg),
281 STATS_DESC_COUNTER(VCPU, exits),
282 STATS_DESC_COUNTER(VCPU, io_exits),
283 STATS_DESC_COUNTER(VCPU, mmio_exits),
284 STATS_DESC_COUNTER(VCPU, signal_exits),
285 STATS_DESC_COUNTER(VCPU, irq_window_exits),
286 STATS_DESC_COUNTER(VCPU, nmi_window_exits),
287 STATS_DESC_COUNTER(VCPU, l1d_flush),
288 STATS_DESC_COUNTER(VCPU, halt_exits),
289 STATS_DESC_COUNTER(VCPU, request_irq_exits),
290 STATS_DESC_COUNTER(VCPU, irq_exits),
291 STATS_DESC_COUNTER(VCPU, host_state_reload),
292 STATS_DESC_COUNTER(VCPU, fpu_reload),
293 STATS_DESC_COUNTER(VCPU, insn_emulation),
294 STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
295 STATS_DESC_COUNTER(VCPU, hypercalls),
296 STATS_DESC_COUNTER(VCPU, irq_injections),
297 STATS_DESC_COUNTER(VCPU, nmi_injections),
298 STATS_DESC_COUNTER(VCPU, req_event),
299 STATS_DESC_COUNTER(VCPU, nested_run),
300 STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
301 STATS_DESC_COUNTER(VCPU, directed_yield_successful),
302 STATS_DESC_COUNTER(VCPU, preemption_reported),
303 STATS_DESC_COUNTER(VCPU, preemption_other),
304 STATS_DESC_IBOOLEAN(VCPU, guest_mode),
305 STATS_DESC_COUNTER(VCPU, notify_window_exits),
306 };
307
308 const struct kvm_stats_header kvm_vcpu_stats_header = {
309 .name_size = KVM_STATS_NAME_SIZE,
310 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
311 .id_offset = sizeof(struct kvm_stats_header),
312 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
313 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
314 sizeof(kvm_vcpu_stats_desc),
315 };
316
317 u64 __read_mostly host_xcr0;
318
319 static struct kmem_cache *x86_emulator_cache;
320
321 /*
322 * When called, it means the previous get/set msr reached an invalid msr.
323 * Return true if we want to ignore/silent this failed msr access.
324 */
kvm_msr_ignored_check(u32 msr,u64 data,bool write)325 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
326 {
327 const char *op = write ? "wrmsr" : "rdmsr";
328
329 if (ignore_msrs) {
330 if (report_ignored_msrs)
331 kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
332 op, msr, data);
333 /* Mask the error */
334 return true;
335 } else {
336 kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
337 op, msr, data);
338 return false;
339 }
340 }
341
kvm_alloc_emulator_cache(void)342 static struct kmem_cache *kvm_alloc_emulator_cache(void)
343 {
344 unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
345 unsigned int size = sizeof(struct x86_emulate_ctxt);
346
347 return kmem_cache_create_usercopy("x86_emulator", size,
348 __alignof__(struct x86_emulate_ctxt),
349 SLAB_ACCOUNT, useroffset,
350 size - useroffset, NULL);
351 }
352
353 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
354
kvm_async_pf_hash_reset(struct kvm_vcpu * vcpu)355 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
356 {
357 int i;
358 for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
359 vcpu->arch.apf.gfns[i] = ~0;
360 }
361
kvm_on_user_return(struct user_return_notifier * urn)362 static void kvm_on_user_return(struct user_return_notifier *urn)
363 {
364 unsigned slot;
365 struct kvm_user_return_msrs *msrs
366 = container_of(urn, struct kvm_user_return_msrs, urn);
367 struct kvm_user_return_msr_values *values;
368 unsigned long flags;
369
370 /*
371 * Disabling irqs at this point since the following code could be
372 * interrupted and executed through kvm_arch_hardware_disable()
373 */
374 local_irq_save(flags);
375 if (msrs->registered) {
376 msrs->registered = false;
377 user_return_notifier_unregister(urn);
378 }
379 local_irq_restore(flags);
380 for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
381 values = &msrs->values[slot];
382 if (values->host != values->curr) {
383 wrmsrl(kvm_uret_msrs_list[slot], values->host);
384 values->curr = values->host;
385 }
386 }
387 }
388
kvm_probe_user_return_msr(u32 msr)389 static int kvm_probe_user_return_msr(u32 msr)
390 {
391 u64 val;
392 int ret;
393
394 preempt_disable();
395 ret = rdmsrl_safe(msr, &val);
396 if (ret)
397 goto out;
398 ret = wrmsrl_safe(msr, val);
399 out:
400 preempt_enable();
401 return ret;
402 }
403
kvm_add_user_return_msr(u32 msr)404 int kvm_add_user_return_msr(u32 msr)
405 {
406 BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
407
408 if (kvm_probe_user_return_msr(msr))
409 return -1;
410
411 kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
412 return kvm_nr_uret_msrs++;
413 }
414 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
415
kvm_find_user_return_msr(u32 msr)416 int kvm_find_user_return_msr(u32 msr)
417 {
418 int i;
419
420 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
421 if (kvm_uret_msrs_list[i] == msr)
422 return i;
423 }
424 return -1;
425 }
426 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
427
kvm_user_return_msr_cpu_online(void)428 static void kvm_user_return_msr_cpu_online(void)
429 {
430 unsigned int cpu = smp_processor_id();
431 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
432 u64 value;
433 int i;
434
435 for (i = 0; i < kvm_nr_uret_msrs; ++i) {
436 rdmsrl_safe(kvm_uret_msrs_list[i], &value);
437 msrs->values[i].host = value;
438 msrs->values[i].curr = value;
439 }
440 }
441
kvm_set_user_return_msr(unsigned slot,u64 value,u64 mask)442 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
443 {
444 unsigned int cpu = smp_processor_id();
445 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
446 int err;
447
448 value = (value & mask) | (msrs->values[slot].host & ~mask);
449 if (value == msrs->values[slot].curr)
450 return 0;
451 err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
452 if (err)
453 return 1;
454
455 msrs->values[slot].curr = value;
456 if (!msrs->registered) {
457 msrs->urn.on_user_return = kvm_on_user_return;
458 user_return_notifier_register(&msrs->urn);
459 msrs->registered = true;
460 }
461 return 0;
462 }
463 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
464
drop_user_return_notifiers(void)465 static void drop_user_return_notifiers(void)
466 {
467 unsigned int cpu = smp_processor_id();
468 struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
469
470 if (msrs->registered)
471 kvm_on_user_return(&msrs->urn);
472 }
473
kvm_get_apic_base(struct kvm_vcpu * vcpu)474 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
475 {
476 return vcpu->arch.apic_base;
477 }
478
kvm_get_apic_mode(struct kvm_vcpu * vcpu)479 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
480 {
481 return kvm_apic_mode(kvm_get_apic_base(vcpu));
482 }
483 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
484
kvm_set_apic_base(struct kvm_vcpu * vcpu,struct msr_data * msr_info)485 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
486 {
487 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
488 enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
489 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
490 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
491
492 if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
493 return 1;
494 if (!msr_info->host_initiated) {
495 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
496 return 1;
497 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
498 return 1;
499 }
500
501 kvm_lapic_set_base(vcpu, msr_info->data);
502 kvm_recalculate_apic_map(vcpu->kvm);
503 return 0;
504 }
505
506 /*
507 * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
508 *
509 * Hardware virtualization extension instructions may fault if a reboot turns
510 * off virtualization while processes are running. Usually after catching the
511 * fault we just panic; during reboot instead the instruction is ignored.
512 */
kvm_spurious_fault(void)513 noinstr void kvm_spurious_fault(void)
514 {
515 /* Fault while not rebooting. We want the trace. */
516 BUG_ON(!kvm_rebooting);
517 }
518 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
519
520 #define EXCPT_BENIGN 0
521 #define EXCPT_CONTRIBUTORY 1
522 #define EXCPT_PF 2
523
exception_class(int vector)524 static int exception_class(int vector)
525 {
526 switch (vector) {
527 case PF_VECTOR:
528 return EXCPT_PF;
529 case DE_VECTOR:
530 case TS_VECTOR:
531 case NP_VECTOR:
532 case SS_VECTOR:
533 case GP_VECTOR:
534 return EXCPT_CONTRIBUTORY;
535 default:
536 break;
537 }
538 return EXCPT_BENIGN;
539 }
540
541 #define EXCPT_FAULT 0
542 #define EXCPT_TRAP 1
543 #define EXCPT_ABORT 2
544 #define EXCPT_INTERRUPT 3
545 #define EXCPT_DB 4
546
exception_type(int vector)547 static int exception_type(int vector)
548 {
549 unsigned int mask;
550
551 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
552 return EXCPT_INTERRUPT;
553
554 mask = 1 << vector;
555
556 /*
557 * #DBs can be trap-like or fault-like, the caller must check other CPU
558 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
559 */
560 if (mask & (1 << DB_VECTOR))
561 return EXCPT_DB;
562
563 if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
564 return EXCPT_TRAP;
565
566 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
567 return EXCPT_ABORT;
568
569 /* Reserved exceptions will result in fault */
570 return EXCPT_FAULT;
571 }
572
kvm_deliver_exception_payload(struct kvm_vcpu * vcpu,struct kvm_queued_exception * ex)573 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
574 struct kvm_queued_exception *ex)
575 {
576 if (!ex->has_payload)
577 return;
578
579 switch (ex->vector) {
580 case DB_VECTOR:
581 /*
582 * "Certain debug exceptions may clear bit 0-3. The
583 * remaining contents of the DR6 register are never
584 * cleared by the processor".
585 */
586 vcpu->arch.dr6 &= ~DR_TRAP_BITS;
587 /*
588 * In order to reflect the #DB exception payload in guest
589 * dr6, three components need to be considered: active low
590 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
591 * DR6_BS and DR6_BT)
592 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
593 * In the target guest dr6:
594 * FIXED_1 bits should always be set.
595 * Active low bits should be cleared if 1-setting in payload.
596 * Active high bits should be set if 1-setting in payload.
597 *
598 * Note, the payload is compatible with the pending debug
599 * exceptions/exit qualification under VMX, that active_low bits
600 * are active high in payload.
601 * So they need to be flipped for DR6.
602 */
603 vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
604 vcpu->arch.dr6 |= ex->payload;
605 vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
606
607 /*
608 * The #DB payload is defined as compatible with the 'pending
609 * debug exceptions' field under VMX, not DR6. While bit 12 is
610 * defined in the 'pending debug exceptions' field (enabled
611 * breakpoint), it is reserved and must be zero in DR6.
612 */
613 vcpu->arch.dr6 &= ~BIT(12);
614 break;
615 case PF_VECTOR:
616 vcpu->arch.cr2 = ex->payload;
617 break;
618 }
619
620 ex->has_payload = false;
621 ex->payload = 0;
622 }
623 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
624
kvm_queue_exception_vmexit(struct kvm_vcpu * vcpu,unsigned int vector,bool has_error_code,u32 error_code,bool has_payload,unsigned long payload)625 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
626 bool has_error_code, u32 error_code,
627 bool has_payload, unsigned long payload)
628 {
629 struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
630
631 ex->vector = vector;
632 ex->injected = false;
633 ex->pending = true;
634 ex->has_error_code = has_error_code;
635 ex->error_code = error_code;
636 ex->has_payload = has_payload;
637 ex->payload = payload;
638 }
639
640 /* Forcibly leave the nested mode in cases like a vCPU reset */
kvm_leave_nested(struct kvm_vcpu * vcpu)641 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
642 {
643 kvm_x86_ops.nested_ops->leave_nested(vcpu);
644 }
645
kvm_multiple_exception(struct kvm_vcpu * vcpu,unsigned nr,bool has_error,u32 error_code,bool has_payload,unsigned long payload,bool reinject)646 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
647 unsigned nr, bool has_error, u32 error_code,
648 bool has_payload, unsigned long payload, bool reinject)
649 {
650 u32 prev_nr;
651 int class1, class2;
652
653 kvm_make_request(KVM_REQ_EVENT, vcpu);
654
655 /*
656 * If the exception is destined for L2 and isn't being reinjected,
657 * morph it to a VM-Exit if L1 wants to intercept the exception. A
658 * previously injected exception is not checked because it was checked
659 * when it was original queued, and re-checking is incorrect if _L1_
660 * injected the exception, in which case it's exempt from interception.
661 */
662 if (!reinject && is_guest_mode(vcpu) &&
663 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
664 kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
665 has_payload, payload);
666 return;
667 }
668
669 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
670 queue:
671 if (reinject) {
672 /*
673 * On VM-Entry, an exception can be pending if and only
674 * if event injection was blocked by nested_run_pending.
675 * In that case, however, vcpu_enter_guest() requests an
676 * immediate exit, and the guest shouldn't proceed far
677 * enough to need reinjection.
678 */
679 WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
680 vcpu->arch.exception.injected = true;
681 if (WARN_ON_ONCE(has_payload)) {
682 /*
683 * A reinjected event has already
684 * delivered its payload.
685 */
686 has_payload = false;
687 payload = 0;
688 }
689 } else {
690 vcpu->arch.exception.pending = true;
691 vcpu->arch.exception.injected = false;
692 }
693 vcpu->arch.exception.has_error_code = has_error;
694 vcpu->arch.exception.vector = nr;
695 vcpu->arch.exception.error_code = error_code;
696 vcpu->arch.exception.has_payload = has_payload;
697 vcpu->arch.exception.payload = payload;
698 if (!is_guest_mode(vcpu))
699 kvm_deliver_exception_payload(vcpu,
700 &vcpu->arch.exception);
701 return;
702 }
703
704 /* to check exception */
705 prev_nr = vcpu->arch.exception.vector;
706 if (prev_nr == DF_VECTOR) {
707 /* triple fault -> shutdown */
708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
709 return;
710 }
711 class1 = exception_class(prev_nr);
712 class2 = exception_class(nr);
713 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
714 (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
715 /*
716 * Synthesize #DF. Clear the previously injected or pending
717 * exception so as not to incorrectly trigger shutdown.
718 */
719 vcpu->arch.exception.injected = false;
720 vcpu->arch.exception.pending = false;
721
722 kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
723 } else {
724 /* replace previous exception with a new one in a hope
725 that instruction re-execution will regenerate lost
726 exception */
727 goto queue;
728 }
729 }
730
kvm_queue_exception(struct kvm_vcpu * vcpu,unsigned nr)731 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
732 {
733 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
734 }
735 EXPORT_SYMBOL_GPL(kvm_queue_exception);
736
kvm_requeue_exception(struct kvm_vcpu * vcpu,unsigned nr)737 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
738 {
739 kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
740 }
741 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
742
kvm_queue_exception_p(struct kvm_vcpu * vcpu,unsigned nr,unsigned long payload)743 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
744 unsigned long payload)
745 {
746 kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
747 }
748 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
749
kvm_queue_exception_e_p(struct kvm_vcpu * vcpu,unsigned nr,u32 error_code,unsigned long payload)750 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
751 u32 error_code, unsigned long payload)
752 {
753 kvm_multiple_exception(vcpu, nr, true, error_code,
754 true, payload, false);
755 }
756
kvm_complete_insn_gp(struct kvm_vcpu * vcpu,int err)757 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
758 {
759 if (err)
760 kvm_inject_gp(vcpu, 0);
761 else
762 return kvm_skip_emulated_instruction(vcpu);
763
764 return 1;
765 }
766 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
767
complete_emulated_insn_gp(struct kvm_vcpu * vcpu,int err)768 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
769 {
770 if (err) {
771 kvm_inject_gp(vcpu, 0);
772 return 1;
773 }
774
775 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
776 EMULTYPE_COMPLETE_USER_EXIT);
777 }
778
kvm_inject_page_fault(struct kvm_vcpu * vcpu,struct x86_exception * fault)779 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
780 {
781 ++vcpu->stat.pf_guest;
782
783 /*
784 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
785 * whether or not L1 wants to intercept "regular" #PF.
786 */
787 if (is_guest_mode(vcpu) && fault->async_page_fault)
788 kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
789 true, fault->error_code,
790 true, fault->address);
791 else
792 kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
793 fault->address);
794 }
795
kvm_inject_emulated_page_fault(struct kvm_vcpu * vcpu,struct x86_exception * fault)796 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
797 struct x86_exception *fault)
798 {
799 struct kvm_mmu *fault_mmu;
800 WARN_ON_ONCE(fault->vector != PF_VECTOR);
801
802 fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
803 vcpu->arch.walk_mmu;
804
805 /*
806 * Invalidate the TLB entry for the faulting address, if it exists,
807 * else the access will fault indefinitely (and to emulate hardware).
808 */
809 if ((fault->error_code & PFERR_PRESENT_MASK) &&
810 !(fault->error_code & PFERR_RSVD_MASK))
811 kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
812 KVM_MMU_ROOT_CURRENT);
813
814 fault_mmu->inject_page_fault(vcpu, fault);
815 }
816 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
817
kvm_inject_nmi(struct kvm_vcpu * vcpu)818 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
819 {
820 atomic_inc(&vcpu->arch.nmi_queued);
821 kvm_make_request(KVM_REQ_NMI, vcpu);
822 }
823
kvm_queue_exception_e(struct kvm_vcpu * vcpu,unsigned nr,u32 error_code)824 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
825 {
826 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
827 }
828 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
829
kvm_requeue_exception_e(struct kvm_vcpu * vcpu,unsigned nr,u32 error_code)830 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
831 {
832 kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
833 }
834 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
835
836 /*
837 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
838 * a #GP and return false.
839 */
kvm_require_cpl(struct kvm_vcpu * vcpu,int required_cpl)840 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
841 {
842 if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
843 return true;
844 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
845 return false;
846 }
847
kvm_require_dr(struct kvm_vcpu * vcpu,int dr)848 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
849 {
850 if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
851 return true;
852
853 kvm_queue_exception(vcpu, UD_VECTOR);
854 return false;
855 }
856 EXPORT_SYMBOL_GPL(kvm_require_dr);
857
pdptr_rsvd_bits(struct kvm_vcpu * vcpu)858 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
859 {
860 return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
861 }
862
863 /*
864 * Load the pae pdptrs. Return 1 if they are all valid, 0 otherwise.
865 */
load_pdptrs(struct kvm_vcpu * vcpu,unsigned long cr3)866 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
867 {
868 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
869 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
870 gpa_t real_gpa;
871 int i;
872 int ret;
873 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
874
875 /*
876 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
877 * to an L1 GPA.
878 */
879 real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
880 PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
881 if (real_gpa == INVALID_GPA)
882 return 0;
883
884 /* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
885 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
886 cr3 & GENMASK(11, 5), sizeof(pdpte));
887 if (ret < 0)
888 return 0;
889
890 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
891 if ((pdpte[i] & PT_PRESENT_MASK) &&
892 (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
893 return 0;
894 }
895 }
896
897 /*
898 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
899 * Shadow page roots need to be reconstructed instead.
900 */
901 if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
902 kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
903
904 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
905 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
906 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
907 vcpu->arch.pdptrs_from_userspace = false;
908
909 return 1;
910 }
911 EXPORT_SYMBOL_GPL(load_pdptrs);
912
kvm_is_valid_cr0(struct kvm_vcpu * vcpu,unsigned long cr0)913 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
914 {
915 #ifdef CONFIG_X86_64
916 if (cr0 & 0xffffffff00000000UL)
917 return false;
918 #endif
919
920 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
921 return false;
922
923 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
924 return false;
925
926 return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0);
927 }
928
kvm_post_set_cr0(struct kvm_vcpu * vcpu,unsigned long old_cr0,unsigned long cr0)929 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
930 {
931 /*
932 * CR0.WP is incorporated into the MMU role, but only for non-nested,
933 * indirect shadow MMUs. If paging is disabled, no updates are needed
934 * as there are no permission bits to emulate. If TDP is enabled, the
935 * MMU's metadata needs to be updated, e.g. so that emulating guest
936 * translations does the right thing, but there's no need to unload the
937 * root as CR0.WP doesn't affect SPTEs.
938 */
939 if ((cr0 ^ old_cr0) == X86_CR0_WP) {
940 if (!(cr0 & X86_CR0_PG))
941 return;
942
943 if (tdp_enabled) {
944 kvm_init_mmu(vcpu);
945 return;
946 }
947 }
948
949 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
950 kvm_clear_async_pf_completion_queue(vcpu);
951 kvm_async_pf_hash_reset(vcpu);
952
953 /*
954 * Clearing CR0.PG is defined to flush the TLB from the guest's
955 * perspective.
956 */
957 if (!(cr0 & X86_CR0_PG))
958 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
959 }
960
961 if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
962 kvm_mmu_reset_context(vcpu);
963
964 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
965 kvm_mmu_honors_guest_mtrrs(vcpu->kvm) &&
966 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
967 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
968 }
969 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
970
kvm_set_cr0(struct kvm_vcpu * vcpu,unsigned long cr0)971 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
972 {
973 unsigned long old_cr0 = kvm_read_cr0(vcpu);
974
975 if (!kvm_is_valid_cr0(vcpu, cr0))
976 return 1;
977
978 cr0 |= X86_CR0_ET;
979
980 /* Write to CR0 reserved bits are ignored, even on Intel. */
981 cr0 &= ~CR0_RESERVED_BITS;
982
983 #ifdef CONFIG_X86_64
984 if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
985 (cr0 & X86_CR0_PG)) {
986 int cs_db, cs_l;
987
988 if (!is_pae(vcpu))
989 return 1;
990 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
991 if (cs_l)
992 return 1;
993 }
994 #endif
995 if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
996 is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
997 !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
998 return 1;
999
1000 if (!(cr0 & X86_CR0_PG) &&
1001 (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
1002 return 1;
1003
1004 static_call(kvm_x86_set_cr0)(vcpu, cr0);
1005
1006 kvm_post_set_cr0(vcpu, old_cr0, cr0);
1007
1008 return 0;
1009 }
1010 EXPORT_SYMBOL_GPL(kvm_set_cr0);
1011
kvm_lmsw(struct kvm_vcpu * vcpu,unsigned long msw)1012 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
1013 {
1014 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1015 }
1016 EXPORT_SYMBOL_GPL(kvm_lmsw);
1017
kvm_load_guest_xsave_state(struct kvm_vcpu * vcpu)1018 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1019 {
1020 if (vcpu->arch.guest_state_protected)
1021 return;
1022
1023 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1024
1025 if (vcpu->arch.xcr0 != host_xcr0)
1026 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1027
1028 if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1029 vcpu->arch.ia32_xss != host_xss)
1030 wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1031 }
1032
1033 if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1034 vcpu->arch.pkru != vcpu->arch.host_pkru &&
1035 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1036 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1037 write_pkru(vcpu->arch.pkru);
1038 }
1039 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1040
kvm_load_host_xsave_state(struct kvm_vcpu * vcpu)1041 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1042 {
1043 if (vcpu->arch.guest_state_protected)
1044 return;
1045
1046 if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1047 ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1048 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1049 vcpu->arch.pkru = rdpkru();
1050 if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1051 write_pkru(vcpu->arch.host_pkru);
1052 }
1053
1054 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1055
1056 if (vcpu->arch.xcr0 != host_xcr0)
1057 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1058
1059 if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1060 vcpu->arch.ia32_xss != host_xss)
1061 wrmsrl(MSR_IA32_XSS, host_xss);
1062 }
1063
1064 }
1065 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1066
1067 #ifdef CONFIG_X86_64
kvm_guest_supported_xfd(struct kvm_vcpu * vcpu)1068 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1069 {
1070 return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1071 }
1072 #endif
1073
__kvm_set_xcr(struct kvm_vcpu * vcpu,u32 index,u64 xcr)1074 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1075 {
1076 u64 xcr0 = xcr;
1077 u64 old_xcr0 = vcpu->arch.xcr0;
1078 u64 valid_bits;
1079
1080 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
1081 if (index != XCR_XFEATURE_ENABLED_MASK)
1082 return 1;
1083 if (!(xcr0 & XFEATURE_MASK_FP))
1084 return 1;
1085 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1086 return 1;
1087
1088 /*
1089 * Do not allow the guest to set bits that we do not support
1090 * saving. However, xcr0 bit 0 is always set, even if the
1091 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1092 */
1093 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1094 if (xcr0 & ~valid_bits)
1095 return 1;
1096
1097 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1098 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1099 return 1;
1100
1101 if (xcr0 & XFEATURE_MASK_AVX512) {
1102 if (!(xcr0 & XFEATURE_MASK_YMM))
1103 return 1;
1104 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1105 return 1;
1106 }
1107
1108 if ((xcr0 & XFEATURE_MASK_XTILE) &&
1109 ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1110 return 1;
1111
1112 vcpu->arch.xcr0 = xcr0;
1113
1114 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1115 kvm_update_cpuid_runtime(vcpu);
1116 return 0;
1117 }
1118
kvm_emulate_xsetbv(struct kvm_vcpu * vcpu)1119 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1120 {
1121 /* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1122 if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1123 __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1124 kvm_inject_gp(vcpu, 0);
1125 return 1;
1126 }
1127
1128 return kvm_skip_emulated_instruction(vcpu);
1129 }
1130 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1131
__kvm_is_valid_cr4(struct kvm_vcpu * vcpu,unsigned long cr4)1132 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1133 {
1134 if (cr4 & cr4_reserved_bits)
1135 return false;
1136
1137 if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1138 return false;
1139
1140 return true;
1141 }
1142 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1143
kvm_is_valid_cr4(struct kvm_vcpu * vcpu,unsigned long cr4)1144 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1145 {
1146 return __kvm_is_valid_cr4(vcpu, cr4) &&
1147 static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1148 }
1149
kvm_post_set_cr4(struct kvm_vcpu * vcpu,unsigned long old_cr4,unsigned long cr4)1150 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1151 {
1152 if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1153 kvm_mmu_reset_context(vcpu);
1154
1155 /*
1156 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1157 * according to the SDM; however, stale prev_roots could be reused
1158 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1159 * free them all. This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1160 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1161 * so fall through.
1162 */
1163 if (!tdp_enabled &&
1164 (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1165 kvm_mmu_unload(vcpu);
1166
1167 /*
1168 * The TLB has to be flushed for all PCIDs if any of the following
1169 * (architecturally required) changes happen:
1170 * - CR4.PCIDE is changed from 1 to 0
1171 * - CR4.PGE is toggled
1172 *
1173 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1174 */
1175 if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1176 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1177 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1178
1179 /*
1180 * The TLB has to be flushed for the current PCID if any of the
1181 * following (architecturally required) changes happen:
1182 * - CR4.SMEP is changed from 0 to 1
1183 * - CR4.PAE is toggled
1184 */
1185 else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1186 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1187 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1188
1189 }
1190 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1191
kvm_set_cr4(struct kvm_vcpu * vcpu,unsigned long cr4)1192 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1193 {
1194 unsigned long old_cr4 = kvm_read_cr4(vcpu);
1195
1196 if (!kvm_is_valid_cr4(vcpu, cr4))
1197 return 1;
1198
1199 if (is_long_mode(vcpu)) {
1200 if (!(cr4 & X86_CR4_PAE))
1201 return 1;
1202 if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1203 return 1;
1204 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1205 && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1206 && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1207 return 1;
1208
1209 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1210 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1211 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1212 return 1;
1213 }
1214
1215 static_call(kvm_x86_set_cr4)(vcpu, cr4);
1216
1217 kvm_post_set_cr4(vcpu, old_cr4, cr4);
1218
1219 return 0;
1220 }
1221 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1222
kvm_invalidate_pcid(struct kvm_vcpu * vcpu,unsigned long pcid)1223 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1224 {
1225 struct kvm_mmu *mmu = vcpu->arch.mmu;
1226 unsigned long roots_to_free = 0;
1227 int i;
1228
1229 /*
1230 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1231 * this is reachable when running EPT=1 and unrestricted_guest=0, and
1232 * also via the emulator. KVM's TDP page tables are not in the scope of
1233 * the invalidation, but the guest's TLB entries need to be flushed as
1234 * the CPU may have cached entries in its TLB for the target PCID.
1235 */
1236 if (unlikely(tdp_enabled)) {
1237 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1238 return;
1239 }
1240
1241 /*
1242 * If neither the current CR3 nor any of the prev_roots use the given
1243 * PCID, then nothing needs to be done here because a resync will
1244 * happen anyway before switching to any other CR3.
1245 */
1246 if (kvm_get_active_pcid(vcpu) == pcid) {
1247 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1248 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1249 }
1250
1251 /*
1252 * If PCID is disabled, there is no need to free prev_roots even if the
1253 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1254 * with PCIDE=0.
1255 */
1256 if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1257 return;
1258
1259 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1260 if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1261 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1262
1263 kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1264 }
1265
kvm_set_cr3(struct kvm_vcpu * vcpu,unsigned long cr3)1266 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1267 {
1268 bool skip_tlb_flush = false;
1269 unsigned long pcid = 0;
1270 #ifdef CONFIG_X86_64
1271 if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1272 skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1273 cr3 &= ~X86_CR3_PCID_NOFLUSH;
1274 pcid = cr3 & X86_CR3_PCID_MASK;
1275 }
1276 #endif
1277
1278 /* PDPTRs are always reloaded for PAE paging. */
1279 if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1280 goto handle_tlb_flush;
1281
1282 /*
1283 * Do not condition the GPA check on long mode, this helper is used to
1284 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1285 * the current vCPU mode is accurate.
1286 */
1287 if (!kvm_vcpu_is_legal_cr3(vcpu, cr3))
1288 return 1;
1289
1290 if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1291 return 1;
1292
1293 if (cr3 != kvm_read_cr3(vcpu))
1294 kvm_mmu_new_pgd(vcpu, cr3);
1295
1296 vcpu->arch.cr3 = cr3;
1297 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1298 /* Do not call post_set_cr3, we do not get here for confidential guests. */
1299
1300 handle_tlb_flush:
1301 /*
1302 * A load of CR3 that flushes the TLB flushes only the current PCID,
1303 * even if PCID is disabled, in which case PCID=0 is flushed. It's a
1304 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1305 * and it's impossible to use a non-zero PCID when PCID is disabled,
1306 * i.e. only PCID=0 can be relevant.
1307 */
1308 if (!skip_tlb_flush)
1309 kvm_invalidate_pcid(vcpu, pcid);
1310
1311 return 0;
1312 }
1313 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1314
kvm_set_cr8(struct kvm_vcpu * vcpu,unsigned long cr8)1315 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1316 {
1317 if (cr8 & CR8_RESERVED_BITS)
1318 return 1;
1319 if (lapic_in_kernel(vcpu))
1320 kvm_lapic_set_tpr(vcpu, cr8);
1321 else
1322 vcpu->arch.cr8 = cr8;
1323 return 0;
1324 }
1325 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1326
kvm_get_cr8(struct kvm_vcpu * vcpu)1327 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1328 {
1329 if (lapic_in_kernel(vcpu))
1330 return kvm_lapic_get_cr8(vcpu);
1331 else
1332 return vcpu->arch.cr8;
1333 }
1334 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1335
kvm_update_dr0123(struct kvm_vcpu * vcpu)1336 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1337 {
1338 int i;
1339
1340 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1341 for (i = 0; i < KVM_NR_DB_REGS; i++)
1342 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1343 }
1344 }
1345
kvm_update_dr7(struct kvm_vcpu * vcpu)1346 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1347 {
1348 unsigned long dr7;
1349
1350 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1351 dr7 = vcpu->arch.guest_debug_dr7;
1352 else
1353 dr7 = vcpu->arch.dr7;
1354 static_call(kvm_x86_set_dr7)(vcpu, dr7);
1355 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1356 if (dr7 & DR7_BP_EN_MASK)
1357 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1358 }
1359 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1360
kvm_dr6_fixed(struct kvm_vcpu * vcpu)1361 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1362 {
1363 u64 fixed = DR6_FIXED_1;
1364
1365 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1366 fixed |= DR6_RTM;
1367
1368 if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1369 fixed |= DR6_BUS_LOCK;
1370 return fixed;
1371 }
1372
kvm_set_dr(struct kvm_vcpu * vcpu,int dr,unsigned long val)1373 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1374 {
1375 size_t size = ARRAY_SIZE(vcpu->arch.db);
1376
1377 switch (dr) {
1378 case 0 ... 3:
1379 vcpu->arch.db[array_index_nospec(dr, size)] = val;
1380 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1381 vcpu->arch.eff_db[dr] = val;
1382 break;
1383 case 4:
1384 case 6:
1385 if (!kvm_dr6_valid(val))
1386 return 1; /* #GP */
1387 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1388 break;
1389 case 5:
1390 default: /* 7 */
1391 if (!kvm_dr7_valid(val))
1392 return 1; /* #GP */
1393 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1394 kvm_update_dr7(vcpu);
1395 break;
1396 }
1397
1398 return 0;
1399 }
1400 EXPORT_SYMBOL_GPL(kvm_set_dr);
1401
kvm_get_dr(struct kvm_vcpu * vcpu,int dr,unsigned long * val)1402 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1403 {
1404 size_t size = ARRAY_SIZE(vcpu->arch.db);
1405
1406 switch (dr) {
1407 case 0 ... 3:
1408 *val = vcpu->arch.db[array_index_nospec(dr, size)];
1409 break;
1410 case 4:
1411 case 6:
1412 *val = vcpu->arch.dr6;
1413 break;
1414 case 5:
1415 default: /* 7 */
1416 *val = vcpu->arch.dr7;
1417 break;
1418 }
1419 }
1420 EXPORT_SYMBOL_GPL(kvm_get_dr);
1421
kvm_emulate_rdpmc(struct kvm_vcpu * vcpu)1422 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1423 {
1424 u32 ecx = kvm_rcx_read(vcpu);
1425 u64 data;
1426
1427 if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1428 kvm_inject_gp(vcpu, 0);
1429 return 1;
1430 }
1431
1432 kvm_rax_write(vcpu, (u32)data);
1433 kvm_rdx_write(vcpu, data >> 32);
1434 return kvm_skip_emulated_instruction(vcpu);
1435 }
1436 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1437
1438 /*
1439 * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track
1440 * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
1441 * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST. msrs_to_save holds MSRs that
1442 * require host support, i.e. should be probed via RDMSR. emulated_msrs holds
1443 * MSRs that KVM emulates without strictly requiring host support.
1444 * msr_based_features holds MSRs that enumerate features, i.e. are effectively
1445 * CPUID leafs. Note, msr_based_features isn't mutually exclusive with
1446 * msrs_to_save and emulated_msrs.
1447 */
1448
1449 static const u32 msrs_to_save_base[] = {
1450 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1451 MSR_STAR,
1452 #ifdef CONFIG_X86_64
1453 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1454 #endif
1455 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1456 MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1457 MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
1458 MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1459 MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1460 MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1461 MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1462 MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1463 MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1464 MSR_IA32_UMWAIT_CONTROL,
1465
1466 MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1467 };
1468
1469 static const u32 msrs_to_save_pmu[] = {
1470 MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1471 MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1472 MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1473 MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1474 MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1475
1476 /* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1477 MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1478 MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1479 MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1480 MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1481 MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1482 MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1483 MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1484 MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1485
1486 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1487 MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1488
1489 /* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1490 MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1491 MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1492 MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1493 MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1494
1495 MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
1496 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
1497 MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
1498 };
1499
1500 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1501 ARRAY_SIZE(msrs_to_save_pmu)];
1502 static unsigned num_msrs_to_save;
1503
1504 static const u32 emulated_msrs_all[] = {
1505 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1506 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1507
1508 #ifdef CONFIG_KVM_HYPERV
1509 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1510 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1511 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1512 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1513 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1514 HV_X64_MSR_RESET,
1515 HV_X64_MSR_VP_INDEX,
1516 HV_X64_MSR_VP_RUNTIME,
1517 HV_X64_MSR_SCONTROL,
1518 HV_X64_MSR_STIMER0_CONFIG,
1519 HV_X64_MSR_VP_ASSIST_PAGE,
1520 HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1521 HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1522 HV_X64_MSR_SYNDBG_OPTIONS,
1523 HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1524 HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1525 HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1526 #endif
1527
1528 MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1529 MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1530
1531 MSR_IA32_TSC_ADJUST,
1532 MSR_IA32_TSC_DEADLINE,
1533 MSR_IA32_ARCH_CAPABILITIES,
1534 MSR_IA32_PERF_CAPABILITIES,
1535 MSR_IA32_MISC_ENABLE,
1536 MSR_IA32_MCG_STATUS,
1537 MSR_IA32_MCG_CTL,
1538 MSR_IA32_MCG_EXT_CTL,
1539 MSR_IA32_SMBASE,
1540 MSR_SMI_COUNT,
1541 MSR_PLATFORM_INFO,
1542 MSR_MISC_FEATURES_ENABLES,
1543 MSR_AMD64_VIRT_SPEC_CTRL,
1544 MSR_AMD64_TSC_RATIO,
1545 MSR_IA32_POWER_CTL,
1546 MSR_IA32_UCODE_REV,
1547
1548 /*
1549 * KVM always supports the "true" VMX control MSRs, even if the host
1550 * does not. The VMX MSRs as a whole are considered "emulated" as KVM
1551 * doesn't strictly require them to exist in the host (ignoring that
1552 * KVM would refuse to load in the first place if the core set of MSRs
1553 * aren't supported).
1554 */
1555 MSR_IA32_VMX_BASIC,
1556 MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1557 MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1558 MSR_IA32_VMX_TRUE_EXIT_CTLS,
1559 MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1560 MSR_IA32_VMX_MISC,
1561 MSR_IA32_VMX_CR0_FIXED0,
1562 MSR_IA32_VMX_CR4_FIXED0,
1563 MSR_IA32_VMX_VMCS_ENUM,
1564 MSR_IA32_VMX_PROCBASED_CTLS2,
1565 MSR_IA32_VMX_EPT_VPID_CAP,
1566 MSR_IA32_VMX_VMFUNC,
1567
1568 MSR_K7_HWCR,
1569 MSR_KVM_POLL_CONTROL,
1570 };
1571
1572 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1573 static unsigned num_emulated_msrs;
1574
1575 /*
1576 * List of MSRs that control the existence of MSR-based features, i.e. MSRs
1577 * that are effectively CPUID leafs. VMX MSRs are also included in the set of
1578 * feature MSRs, but are handled separately to allow expedited lookups.
1579 */
1580 static const u32 msr_based_features_all_except_vmx[] = {
1581 MSR_AMD64_DE_CFG,
1582 MSR_IA32_UCODE_REV,
1583 MSR_IA32_ARCH_CAPABILITIES,
1584 MSR_IA32_PERF_CAPABILITIES,
1585 };
1586
1587 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) +
1588 (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)];
1589 static unsigned int num_msr_based_features;
1590
1591 /*
1592 * All feature MSRs except uCode revID, which tracks the currently loaded uCode
1593 * patch, are immutable once the vCPU model is defined.
1594 */
kvm_is_immutable_feature_msr(u32 msr)1595 static bool kvm_is_immutable_feature_msr(u32 msr)
1596 {
1597 int i;
1598
1599 if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR)
1600 return true;
1601
1602 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) {
1603 if (msr == msr_based_features_all_except_vmx[i])
1604 return msr != MSR_IA32_UCODE_REV;
1605 }
1606
1607 return false;
1608 }
1609
1610 /*
1611 * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1612 * does not yet virtualize. These include:
1613 * 10 - MISC_PACKAGE_CTRLS
1614 * 11 - ENERGY_FILTERING_CTL
1615 * 12 - DOITM
1616 * 18 - FB_CLEAR_CTRL
1617 * 21 - XAPIC_DISABLE_STATUS
1618 * 23 - OVERCLOCKING_STATUS
1619 */
1620
1621 #define KVM_SUPPORTED_ARCH_CAP \
1622 (ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1623 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1624 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1625 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1626 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO)
1627
kvm_get_arch_capabilities(void)1628 static u64 kvm_get_arch_capabilities(void)
1629 {
1630 u64 data = host_arch_capabilities & KVM_SUPPORTED_ARCH_CAP;
1631
1632 /*
1633 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1634 * the nested hypervisor runs with NX huge pages. If it is not,
1635 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1636 * L1 guests, so it need not worry about its own (L2) guests.
1637 */
1638 data |= ARCH_CAP_PSCHANGE_MC_NO;
1639
1640 /*
1641 * If we're doing cache flushes (either "always" or "cond")
1642 * we will do one whenever the guest does a vmlaunch/vmresume.
1643 * If an outer hypervisor is doing the cache flush for us
1644 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that
1645 * capability to the guest too, and if EPT is disabled we're not
1646 * vulnerable. Overall, only VMENTER_L1D_FLUSH_NEVER will
1647 * require a nested hypervisor to do a flush of its own.
1648 */
1649 if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1650 data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1651
1652 if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1653 data |= ARCH_CAP_RDCL_NO;
1654 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1655 data |= ARCH_CAP_SSB_NO;
1656 if (!boot_cpu_has_bug(X86_BUG_MDS))
1657 data |= ARCH_CAP_MDS_NO;
1658
1659 if (!boot_cpu_has(X86_FEATURE_RTM)) {
1660 /*
1661 * If RTM=0 because the kernel has disabled TSX, the host might
1662 * have TAA_NO or TSX_CTRL. Clear TAA_NO (the guest sees RTM=0
1663 * and therefore knows that there cannot be TAA) but keep
1664 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1665 * and we want to allow migrating those guests to tsx=off hosts.
1666 */
1667 data &= ~ARCH_CAP_TAA_NO;
1668 } else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1669 data |= ARCH_CAP_TAA_NO;
1670 } else {
1671 /*
1672 * Nothing to do here; we emulate TSX_CTRL if present on the
1673 * host so the guest can choose between disabling TSX or
1674 * using VERW to clear CPU buffers.
1675 */
1676 }
1677
1678 if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated())
1679 data |= ARCH_CAP_GDS_NO;
1680
1681 return data;
1682 }
1683
kvm_get_msr_feature(struct kvm_msr_entry * msr)1684 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1685 {
1686 switch (msr->index) {
1687 case MSR_IA32_ARCH_CAPABILITIES:
1688 msr->data = kvm_get_arch_capabilities();
1689 break;
1690 case MSR_IA32_PERF_CAPABILITIES:
1691 msr->data = kvm_caps.supported_perf_cap;
1692 break;
1693 case MSR_IA32_UCODE_REV:
1694 rdmsrl_safe(msr->index, &msr->data);
1695 break;
1696 default:
1697 return static_call(kvm_x86_get_msr_feature)(msr);
1698 }
1699 return 0;
1700 }
1701
do_get_msr_feature(struct kvm_vcpu * vcpu,unsigned index,u64 * data)1702 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1703 {
1704 struct kvm_msr_entry msr;
1705 int r;
1706
1707 /* Unconditionally clear the output for simplicity */
1708 msr.data = 0;
1709 msr.index = index;
1710 r = kvm_get_msr_feature(&msr);
1711
1712 if (r == KVM_MSR_RET_INVALID && kvm_msr_ignored_check(index, 0, false))
1713 r = 0;
1714
1715 *data = msr.data;
1716
1717 return r;
1718 }
1719
__kvm_valid_efer(struct kvm_vcpu * vcpu,u64 efer)1720 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1721 {
1722 if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1723 return false;
1724
1725 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1726 return false;
1727
1728 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1729 return false;
1730
1731 if (efer & (EFER_LME | EFER_LMA) &&
1732 !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1733 return false;
1734
1735 if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1736 return false;
1737
1738 return true;
1739
1740 }
kvm_valid_efer(struct kvm_vcpu * vcpu,u64 efer)1741 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1742 {
1743 if (efer & efer_reserved_bits)
1744 return false;
1745
1746 return __kvm_valid_efer(vcpu, efer);
1747 }
1748 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1749
set_efer(struct kvm_vcpu * vcpu,struct msr_data * msr_info)1750 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1751 {
1752 u64 old_efer = vcpu->arch.efer;
1753 u64 efer = msr_info->data;
1754 int r;
1755
1756 if (efer & efer_reserved_bits)
1757 return 1;
1758
1759 if (!msr_info->host_initiated) {
1760 if (!__kvm_valid_efer(vcpu, efer))
1761 return 1;
1762
1763 if (is_paging(vcpu) &&
1764 (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1765 return 1;
1766 }
1767
1768 efer &= ~EFER_LMA;
1769 efer |= vcpu->arch.efer & EFER_LMA;
1770
1771 r = static_call(kvm_x86_set_efer)(vcpu, efer);
1772 if (r) {
1773 WARN_ON(r > 0);
1774 return r;
1775 }
1776
1777 if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1778 kvm_mmu_reset_context(vcpu);
1779
1780 if (!static_cpu_has(X86_FEATURE_XSAVES) &&
1781 (efer & EFER_SVME))
1782 kvm_hv_xsaves_xsavec_maybe_warn(vcpu);
1783
1784 return 0;
1785 }
1786
kvm_enable_efer_bits(u64 mask)1787 void kvm_enable_efer_bits(u64 mask)
1788 {
1789 efer_reserved_bits &= ~mask;
1790 }
1791 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1792
kvm_msr_allowed(struct kvm_vcpu * vcpu,u32 index,u32 type)1793 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1794 {
1795 struct kvm_x86_msr_filter *msr_filter;
1796 struct msr_bitmap_range *ranges;
1797 struct kvm *kvm = vcpu->kvm;
1798 bool allowed;
1799 int idx;
1800 u32 i;
1801
1802 /* x2APIC MSRs do not support filtering. */
1803 if (index >= 0x800 && index <= 0x8ff)
1804 return true;
1805
1806 idx = srcu_read_lock(&kvm->srcu);
1807
1808 msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1809 if (!msr_filter) {
1810 allowed = true;
1811 goto out;
1812 }
1813
1814 allowed = msr_filter->default_allow;
1815 ranges = msr_filter->ranges;
1816
1817 for (i = 0; i < msr_filter->count; i++) {
1818 u32 start = ranges[i].base;
1819 u32 end = start + ranges[i].nmsrs;
1820 u32 flags = ranges[i].flags;
1821 unsigned long *bitmap = ranges[i].bitmap;
1822
1823 if ((index >= start) && (index < end) && (flags & type)) {
1824 allowed = test_bit(index - start, bitmap);
1825 break;
1826 }
1827 }
1828
1829 out:
1830 srcu_read_unlock(&kvm->srcu, idx);
1831
1832 return allowed;
1833 }
1834 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1835
1836 /*
1837 * Write @data into the MSR specified by @index. Select MSR specific fault
1838 * checks are bypassed if @host_initiated is %true.
1839 * Returns 0 on success, non-0 otherwise.
1840 * Assumes vcpu_load() was already called.
1841 */
__kvm_set_msr(struct kvm_vcpu * vcpu,u32 index,u64 data,bool host_initiated)1842 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1843 bool host_initiated)
1844 {
1845 struct msr_data msr;
1846
1847 switch (index) {
1848 case MSR_FS_BASE:
1849 case MSR_GS_BASE:
1850 case MSR_KERNEL_GS_BASE:
1851 case MSR_CSTAR:
1852 case MSR_LSTAR:
1853 if (is_noncanonical_address(data, vcpu))
1854 return 1;
1855 break;
1856 case MSR_IA32_SYSENTER_EIP:
1857 case MSR_IA32_SYSENTER_ESP:
1858 /*
1859 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1860 * non-canonical address is written on Intel but not on
1861 * AMD (which ignores the top 32-bits, because it does
1862 * not implement 64-bit SYSENTER).
1863 *
1864 * 64-bit code should hence be able to write a non-canonical
1865 * value on AMD. Making the address canonical ensures that
1866 * vmentry does not fail on Intel after writing a non-canonical
1867 * value, and that something deterministic happens if the guest
1868 * invokes 64-bit SYSENTER.
1869 */
1870 data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1871 break;
1872 case MSR_TSC_AUX:
1873 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1874 return 1;
1875
1876 if (!host_initiated &&
1877 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1878 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1879 return 1;
1880
1881 /*
1882 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1883 * incomplete and conflicting architectural behavior. Current
1884 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1885 * reserved and always read as zeros. Enforce Intel's reserved
1886 * bits check if and only if the guest CPU is Intel, and clear
1887 * the bits in all other cases. This ensures cross-vendor
1888 * migration will provide consistent behavior for the guest.
1889 */
1890 if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1891 return 1;
1892
1893 data = (u32)data;
1894 break;
1895 }
1896
1897 msr.data = data;
1898 msr.index = index;
1899 msr.host_initiated = host_initiated;
1900
1901 return static_call(kvm_x86_set_msr)(vcpu, &msr);
1902 }
1903
kvm_set_msr_ignored_check(struct kvm_vcpu * vcpu,u32 index,u64 data,bool host_initiated)1904 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1905 u32 index, u64 data, bool host_initiated)
1906 {
1907 int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1908
1909 if (ret == KVM_MSR_RET_INVALID)
1910 if (kvm_msr_ignored_check(index, data, true))
1911 ret = 0;
1912
1913 return ret;
1914 }
1915
1916 /*
1917 * Read the MSR specified by @index into @data. Select MSR specific fault
1918 * checks are bypassed if @host_initiated is %true.
1919 * Returns 0 on success, non-0 otherwise.
1920 * Assumes vcpu_load() was already called.
1921 */
__kvm_get_msr(struct kvm_vcpu * vcpu,u32 index,u64 * data,bool host_initiated)1922 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1923 bool host_initiated)
1924 {
1925 struct msr_data msr;
1926 int ret;
1927
1928 switch (index) {
1929 case MSR_TSC_AUX:
1930 if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1931 return 1;
1932
1933 if (!host_initiated &&
1934 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1935 !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1936 return 1;
1937 break;
1938 }
1939
1940 msr.index = index;
1941 msr.host_initiated = host_initiated;
1942
1943 ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1944 if (!ret)
1945 *data = msr.data;
1946 return ret;
1947 }
1948
kvm_get_msr_ignored_check(struct kvm_vcpu * vcpu,u32 index,u64 * data,bool host_initiated)1949 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1950 u32 index, u64 *data, bool host_initiated)
1951 {
1952 int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1953
1954 if (ret == KVM_MSR_RET_INVALID) {
1955 /* Unconditionally clear *data for simplicity */
1956 *data = 0;
1957 if (kvm_msr_ignored_check(index, 0, false))
1958 ret = 0;
1959 }
1960
1961 return ret;
1962 }
1963
kvm_get_msr_with_filter(struct kvm_vcpu * vcpu,u32 index,u64 * data)1964 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1965 {
1966 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1967 return KVM_MSR_RET_FILTERED;
1968 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1969 }
1970
kvm_set_msr_with_filter(struct kvm_vcpu * vcpu,u32 index,u64 data)1971 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1972 {
1973 if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1974 return KVM_MSR_RET_FILTERED;
1975 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1976 }
1977
kvm_get_msr(struct kvm_vcpu * vcpu,u32 index,u64 * data)1978 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1979 {
1980 return kvm_get_msr_ignored_check(vcpu, index, data, false);
1981 }
1982 EXPORT_SYMBOL_GPL(kvm_get_msr);
1983
kvm_set_msr(struct kvm_vcpu * vcpu,u32 index,u64 data)1984 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1985 {
1986 return kvm_set_msr_ignored_check(vcpu, index, data, false);
1987 }
1988 EXPORT_SYMBOL_GPL(kvm_set_msr);
1989
complete_userspace_rdmsr(struct kvm_vcpu * vcpu)1990 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1991 {
1992 if (!vcpu->run->msr.error) {
1993 kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1994 kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1995 }
1996 }
1997
complete_emulated_msr_access(struct kvm_vcpu * vcpu)1998 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
1999 {
2000 return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
2001 }
2002
complete_emulated_rdmsr(struct kvm_vcpu * vcpu)2003 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
2004 {
2005 complete_userspace_rdmsr(vcpu);
2006 return complete_emulated_msr_access(vcpu);
2007 }
2008
complete_fast_msr_access(struct kvm_vcpu * vcpu)2009 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
2010 {
2011 return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
2012 }
2013
complete_fast_rdmsr(struct kvm_vcpu * vcpu)2014 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2015 {
2016 complete_userspace_rdmsr(vcpu);
2017 return complete_fast_msr_access(vcpu);
2018 }
2019
kvm_msr_reason(int r)2020 static u64 kvm_msr_reason(int r)
2021 {
2022 switch (r) {
2023 case KVM_MSR_RET_INVALID:
2024 return KVM_MSR_EXIT_REASON_UNKNOWN;
2025 case KVM_MSR_RET_FILTERED:
2026 return KVM_MSR_EXIT_REASON_FILTER;
2027 default:
2028 return KVM_MSR_EXIT_REASON_INVAL;
2029 }
2030 }
2031
kvm_msr_user_space(struct kvm_vcpu * vcpu,u32 index,u32 exit_reason,u64 data,int (* completion)(struct kvm_vcpu * vcpu),int r)2032 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2033 u32 exit_reason, u64 data,
2034 int (*completion)(struct kvm_vcpu *vcpu),
2035 int r)
2036 {
2037 u64 msr_reason = kvm_msr_reason(r);
2038
2039 /* Check if the user wanted to know about this MSR fault */
2040 if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2041 return 0;
2042
2043 vcpu->run->exit_reason = exit_reason;
2044 vcpu->run->msr.error = 0;
2045 memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2046 vcpu->run->msr.reason = msr_reason;
2047 vcpu->run->msr.index = index;
2048 vcpu->run->msr.data = data;
2049 vcpu->arch.complete_userspace_io = completion;
2050
2051 return 1;
2052 }
2053
kvm_emulate_rdmsr(struct kvm_vcpu * vcpu)2054 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2055 {
2056 u32 ecx = kvm_rcx_read(vcpu);
2057 u64 data;
2058 int r;
2059
2060 r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2061
2062 if (!r) {
2063 trace_kvm_msr_read(ecx, data);
2064
2065 kvm_rax_write(vcpu, data & -1u);
2066 kvm_rdx_write(vcpu, (data >> 32) & -1u);
2067 } else {
2068 /* MSR read failed? See if we should ask user space */
2069 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2070 complete_fast_rdmsr, r))
2071 return 0;
2072 trace_kvm_msr_read_ex(ecx);
2073 }
2074
2075 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2076 }
2077 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2078
kvm_emulate_wrmsr(struct kvm_vcpu * vcpu)2079 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2080 {
2081 u32 ecx = kvm_rcx_read(vcpu);
2082 u64 data = kvm_read_edx_eax(vcpu);
2083 int r;
2084
2085 r = kvm_set_msr_with_filter(vcpu, ecx, data);
2086
2087 if (!r) {
2088 trace_kvm_msr_write(ecx, data);
2089 } else {
2090 /* MSR write failed? See if we should ask user space */
2091 if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2092 complete_fast_msr_access, r))
2093 return 0;
2094 /* Signal all other negative errors to userspace */
2095 if (r < 0)
2096 return r;
2097 trace_kvm_msr_write_ex(ecx, data);
2098 }
2099
2100 return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2101 }
2102 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2103
kvm_emulate_as_nop(struct kvm_vcpu * vcpu)2104 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2105 {
2106 return kvm_skip_emulated_instruction(vcpu);
2107 }
2108
kvm_emulate_invd(struct kvm_vcpu * vcpu)2109 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2110 {
2111 /* Treat an INVD instruction as a NOP and just skip it. */
2112 return kvm_emulate_as_nop(vcpu);
2113 }
2114 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2115
kvm_handle_invalid_op(struct kvm_vcpu * vcpu)2116 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2117 {
2118 kvm_queue_exception(vcpu, UD_VECTOR);
2119 return 1;
2120 }
2121 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2122
2123
kvm_emulate_monitor_mwait(struct kvm_vcpu * vcpu,const char * insn)2124 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2125 {
2126 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2127 !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2128 return kvm_handle_invalid_op(vcpu);
2129
2130 pr_warn_once("%s instruction emulated as NOP!\n", insn);
2131 return kvm_emulate_as_nop(vcpu);
2132 }
kvm_emulate_mwait(struct kvm_vcpu * vcpu)2133 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2134 {
2135 return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2136 }
2137 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2138
kvm_emulate_monitor(struct kvm_vcpu * vcpu)2139 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2140 {
2141 return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2142 }
2143 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2144
kvm_vcpu_exit_request(struct kvm_vcpu * vcpu)2145 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2146 {
2147 xfer_to_guest_mode_prepare();
2148 return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2149 xfer_to_guest_mode_work_pending();
2150 }
2151
2152 /*
2153 * The fast path for frequent and performance sensitive wrmsr emulation,
2154 * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2155 * the latency of virtual IPI by avoiding the expensive bits of transitioning
2156 * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2157 * other cases which must be called after interrupts are enabled on the host.
2158 */
handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu * vcpu,u64 data)2159 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2160 {
2161 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2162 return 1;
2163
2164 if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2165 ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2166 ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2167 ((u32)(data >> 32) != X2APIC_BROADCAST))
2168 return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2169
2170 return 1;
2171 }
2172
handle_fastpath_set_tscdeadline(struct kvm_vcpu * vcpu,u64 data)2173 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2174 {
2175 if (!kvm_can_use_hv_timer(vcpu))
2176 return 1;
2177
2178 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2179 return 0;
2180 }
2181
handle_fastpath_set_msr_irqoff(struct kvm_vcpu * vcpu)2182 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2183 {
2184 u32 msr = kvm_rcx_read(vcpu);
2185 u64 data;
2186 fastpath_t ret = EXIT_FASTPATH_NONE;
2187
2188 kvm_vcpu_srcu_read_lock(vcpu);
2189
2190 switch (msr) {
2191 case APIC_BASE_MSR + (APIC_ICR >> 4):
2192 data = kvm_read_edx_eax(vcpu);
2193 if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2194 kvm_skip_emulated_instruction(vcpu);
2195 ret = EXIT_FASTPATH_EXIT_HANDLED;
2196 }
2197 break;
2198 case MSR_IA32_TSC_DEADLINE:
2199 data = kvm_read_edx_eax(vcpu);
2200 if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2201 kvm_skip_emulated_instruction(vcpu);
2202 ret = EXIT_FASTPATH_REENTER_GUEST;
2203 }
2204 break;
2205 default:
2206 break;
2207 }
2208
2209 if (ret != EXIT_FASTPATH_NONE)
2210 trace_kvm_msr_write(msr, data);
2211
2212 kvm_vcpu_srcu_read_unlock(vcpu);
2213
2214 return ret;
2215 }
2216 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2217
2218 /*
2219 * Adapt set_msr() to msr_io()'s calling convention
2220 */
do_get_msr(struct kvm_vcpu * vcpu,unsigned index,u64 * data)2221 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2222 {
2223 return kvm_get_msr_ignored_check(vcpu, index, data, true);
2224 }
2225
do_set_msr(struct kvm_vcpu * vcpu,unsigned index,u64 * data)2226 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2227 {
2228 u64 val;
2229
2230 /*
2231 * Disallow writes to immutable feature MSRs after KVM_RUN. KVM does
2232 * not support modifying the guest vCPU model on the fly, e.g. changing
2233 * the nVMX capabilities while L2 is running is nonsensical. Ignore
2234 * writes of the same value, e.g. to allow userspace to blindly stuff
2235 * all MSRs when emulating RESET.
2236 */
2237 if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) {
2238 if (do_get_msr(vcpu, index, &val) || *data != val)
2239 return -EINVAL;
2240
2241 return 0;
2242 }
2243
2244 return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2245 }
2246
2247 #ifdef CONFIG_X86_64
2248 struct pvclock_clock {
2249 int vclock_mode;
2250 u64 cycle_last;
2251 u64 mask;
2252 u32 mult;
2253 u32 shift;
2254 u64 base_cycles;
2255 u64 offset;
2256 };
2257
2258 struct pvclock_gtod_data {
2259 seqcount_t seq;
2260
2261 struct pvclock_clock clock; /* extract of a clocksource struct */
2262 struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2263
2264 ktime_t offs_boot;
2265 u64 wall_time_sec;
2266 };
2267
2268 static struct pvclock_gtod_data pvclock_gtod_data;
2269
update_pvclock_gtod(struct timekeeper * tk)2270 static void update_pvclock_gtod(struct timekeeper *tk)
2271 {
2272 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2273
2274 write_seqcount_begin(&vdata->seq);
2275
2276 /* copy pvclock gtod data */
2277 vdata->clock.vclock_mode = tk->tkr_mono.clock->vdso_clock_mode;
2278 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
2279 vdata->clock.mask = tk->tkr_mono.mask;
2280 vdata->clock.mult = tk->tkr_mono.mult;
2281 vdata->clock.shift = tk->tkr_mono.shift;
2282 vdata->clock.base_cycles = tk->tkr_mono.xtime_nsec;
2283 vdata->clock.offset = tk->tkr_mono.base;
2284
2285 vdata->raw_clock.vclock_mode = tk->tkr_raw.clock->vdso_clock_mode;
2286 vdata->raw_clock.cycle_last = tk->tkr_raw.cycle_last;
2287 vdata->raw_clock.mask = tk->tkr_raw.mask;
2288 vdata->raw_clock.mult = tk->tkr_raw.mult;
2289 vdata->raw_clock.shift = tk->tkr_raw.shift;
2290 vdata->raw_clock.base_cycles = tk->tkr_raw.xtime_nsec;
2291 vdata->raw_clock.offset = tk->tkr_raw.base;
2292
2293 vdata->wall_time_sec = tk->xtime_sec;
2294
2295 vdata->offs_boot = tk->offs_boot;
2296
2297 write_seqcount_end(&vdata->seq);
2298 }
2299
get_kvmclock_base_ns(void)2300 static s64 get_kvmclock_base_ns(void)
2301 {
2302 /* Count up from boot time, but with the frequency of the raw clock. */
2303 return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2304 }
2305 #else
get_kvmclock_base_ns(void)2306 static s64 get_kvmclock_base_ns(void)
2307 {
2308 /* Master clock not used, so we can just use CLOCK_BOOTTIME. */
2309 return ktime_get_boottime_ns();
2310 }
2311 #endif
2312
kvm_write_wall_clock(struct kvm * kvm,gpa_t wall_clock,int sec_hi_ofs)2313 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2314 {
2315 int version;
2316 int r;
2317 struct pvclock_wall_clock wc;
2318 u32 wc_sec_hi;
2319 u64 wall_nsec;
2320
2321 if (!wall_clock)
2322 return;
2323
2324 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2325 if (r)
2326 return;
2327
2328 if (version & 1)
2329 ++version; /* first time write, random junk */
2330
2331 ++version;
2332
2333 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2334 return;
2335
2336 wall_nsec = kvm_get_wall_clock_epoch(kvm);
2337
2338 wc.nsec = do_div(wall_nsec, NSEC_PER_SEC);
2339 wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2340 wc.version = version;
2341
2342 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2343
2344 if (sec_hi_ofs) {
2345 wc_sec_hi = wall_nsec >> 32;
2346 kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2347 &wc_sec_hi, sizeof(wc_sec_hi));
2348 }
2349
2350 version++;
2351 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2352 }
2353
kvm_write_system_time(struct kvm_vcpu * vcpu,gpa_t system_time,bool old_msr,bool host_initiated)2354 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2355 bool old_msr, bool host_initiated)
2356 {
2357 struct kvm_arch *ka = &vcpu->kvm->arch;
2358
2359 if (vcpu->vcpu_id == 0 && !host_initiated) {
2360 if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2361 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2362
2363 ka->boot_vcpu_runs_old_kvmclock = old_msr;
2364 }
2365
2366 vcpu->arch.time = system_time;
2367 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2368
2369 /* we verify if the enable bit is set... */
2370 if (system_time & 1)
2371 kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2372 sizeof(struct pvclock_vcpu_time_info));
2373 else
2374 kvm_gpc_deactivate(&vcpu->arch.pv_time);
2375
2376 return;
2377 }
2378
div_frac(uint32_t dividend,uint32_t divisor)2379 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2380 {
2381 do_shl32_div32(dividend, divisor);
2382 return dividend;
2383 }
2384
kvm_get_time_scale(uint64_t scaled_hz,uint64_t base_hz,s8 * pshift,u32 * pmultiplier)2385 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2386 s8 *pshift, u32 *pmultiplier)
2387 {
2388 uint64_t scaled64;
2389 int32_t shift = 0;
2390 uint64_t tps64;
2391 uint32_t tps32;
2392
2393 tps64 = base_hz;
2394 scaled64 = scaled_hz;
2395 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2396 tps64 >>= 1;
2397 shift--;
2398 }
2399
2400 tps32 = (uint32_t)tps64;
2401 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2402 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2403 scaled64 >>= 1;
2404 else
2405 tps32 <<= 1;
2406 shift++;
2407 }
2408
2409 *pshift = shift;
2410 *pmultiplier = div_frac(scaled64, tps32);
2411 }
2412
2413 #ifdef CONFIG_X86_64
2414 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2415 #endif
2416
2417 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2418 static unsigned long max_tsc_khz;
2419
adjust_tsc_khz(u32 khz,s32 ppm)2420 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2421 {
2422 u64 v = (u64)khz * (1000000 + ppm);
2423 do_div(v, 1000000);
2424 return v;
2425 }
2426
2427 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2428
set_tsc_khz(struct kvm_vcpu * vcpu,u32 user_tsc_khz,bool scale)2429 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2430 {
2431 u64 ratio;
2432
2433 /* Guest TSC same frequency as host TSC? */
2434 if (!scale) {
2435 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2436 return 0;
2437 }
2438
2439 /* TSC scaling supported? */
2440 if (!kvm_caps.has_tsc_control) {
2441 if (user_tsc_khz > tsc_khz) {
2442 vcpu->arch.tsc_catchup = 1;
2443 vcpu->arch.tsc_always_catchup = 1;
2444 return 0;
2445 } else {
2446 pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2447 return -1;
2448 }
2449 }
2450
2451 /* TSC scaling required - calculate ratio */
2452 ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2453 user_tsc_khz, tsc_khz);
2454
2455 if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2456 pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2457 user_tsc_khz);
2458 return -1;
2459 }
2460
2461 kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2462 return 0;
2463 }
2464
kvm_set_tsc_khz(struct kvm_vcpu * vcpu,u32 user_tsc_khz)2465 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2466 {
2467 u32 thresh_lo, thresh_hi;
2468 int use_scaling = 0;
2469
2470 /* tsc_khz can be zero if TSC calibration fails */
2471 if (user_tsc_khz == 0) {
2472 /* set tsc_scaling_ratio to a safe value */
2473 kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2474 return -1;
2475 }
2476
2477 /* Compute a scale to convert nanoseconds in TSC cycles */
2478 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2479 &vcpu->arch.virtual_tsc_shift,
2480 &vcpu->arch.virtual_tsc_mult);
2481 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2482
2483 /*
2484 * Compute the variation in TSC rate which is acceptable
2485 * within the range of tolerance and decide if the
2486 * rate being applied is within that bounds of the hardware
2487 * rate. If so, no scaling or compensation need be done.
2488 */
2489 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2490 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2491 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2492 pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2493 user_tsc_khz, thresh_lo, thresh_hi);
2494 use_scaling = 1;
2495 }
2496 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2497 }
2498
compute_guest_tsc(struct kvm_vcpu * vcpu,s64 kernel_ns)2499 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2500 {
2501 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2502 vcpu->arch.virtual_tsc_mult,
2503 vcpu->arch.virtual_tsc_shift);
2504 tsc += vcpu->arch.this_tsc_write;
2505 return tsc;
2506 }
2507
2508 #ifdef CONFIG_X86_64
gtod_is_based_on_tsc(int mode)2509 static inline bool gtod_is_based_on_tsc(int mode)
2510 {
2511 return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2512 }
2513 #endif
2514
kvm_track_tsc_matching(struct kvm_vcpu * vcpu,bool new_generation)2515 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu, bool new_generation)
2516 {
2517 #ifdef CONFIG_X86_64
2518 struct kvm_arch *ka = &vcpu->kvm->arch;
2519 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2520
2521 /*
2522 * To use the masterclock, the host clocksource must be based on TSC
2523 * and all vCPUs must have matching TSCs. Note, the count for matching
2524 * vCPUs doesn't include the reference vCPU, hence "+1".
2525 */
2526 bool use_master_clock = (ka->nr_vcpus_matched_tsc + 1 ==
2527 atomic_read(&vcpu->kvm->online_vcpus)) &&
2528 gtod_is_based_on_tsc(gtod->clock.vclock_mode);
2529
2530 /*
2531 * Request a masterclock update if the masterclock needs to be toggled
2532 * on/off, or when starting a new generation and the masterclock is
2533 * enabled (compute_guest_tsc() requires the masterclock snapshot to be
2534 * taken _after_ the new generation is created).
2535 */
2536 if ((ka->use_master_clock && new_generation) ||
2537 (ka->use_master_clock != use_master_clock))
2538 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2539
2540 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2541 atomic_read(&vcpu->kvm->online_vcpus),
2542 ka->use_master_clock, gtod->clock.vclock_mode);
2543 #endif
2544 }
2545
2546 /*
2547 * Multiply tsc by a fixed point number represented by ratio.
2548 *
2549 * The most significant 64-N bits (mult) of ratio represent the
2550 * integral part of the fixed point number; the remaining N bits
2551 * (frac) represent the fractional part, ie. ratio represents a fixed
2552 * point number (mult + frac * 2^(-N)).
2553 *
2554 * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2555 */
__scale_tsc(u64 ratio,u64 tsc)2556 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2557 {
2558 return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2559 }
2560
kvm_scale_tsc(u64 tsc,u64 ratio)2561 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2562 {
2563 u64 _tsc = tsc;
2564
2565 if (ratio != kvm_caps.default_tsc_scaling_ratio)
2566 _tsc = __scale_tsc(ratio, tsc);
2567
2568 return _tsc;
2569 }
2570
kvm_compute_l1_tsc_offset(struct kvm_vcpu * vcpu,u64 target_tsc)2571 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2572 {
2573 u64 tsc;
2574
2575 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2576
2577 return target_tsc - tsc;
2578 }
2579
kvm_read_l1_tsc(struct kvm_vcpu * vcpu,u64 host_tsc)2580 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2581 {
2582 return vcpu->arch.l1_tsc_offset +
2583 kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2584 }
2585 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2586
kvm_calc_nested_tsc_offset(u64 l1_offset,u64 l2_offset,u64 l2_multiplier)2587 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2588 {
2589 u64 nested_offset;
2590
2591 if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2592 nested_offset = l1_offset;
2593 else
2594 nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2595 kvm_caps.tsc_scaling_ratio_frac_bits);
2596
2597 nested_offset += l2_offset;
2598 return nested_offset;
2599 }
2600 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2601
kvm_calc_nested_tsc_multiplier(u64 l1_multiplier,u64 l2_multiplier)2602 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2603 {
2604 if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2605 return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2606 kvm_caps.tsc_scaling_ratio_frac_bits);
2607
2608 return l1_multiplier;
2609 }
2610 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2611
kvm_vcpu_write_tsc_offset(struct kvm_vcpu * vcpu,u64 l1_offset)2612 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2613 {
2614 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2615 vcpu->arch.l1_tsc_offset,
2616 l1_offset);
2617
2618 vcpu->arch.l1_tsc_offset = l1_offset;
2619
2620 /*
2621 * If we are here because L1 chose not to trap WRMSR to TSC then
2622 * according to the spec this should set L1's TSC (as opposed to
2623 * setting L1's offset for L2).
2624 */
2625 if (is_guest_mode(vcpu))
2626 vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2627 l1_offset,
2628 static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2629 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2630 else
2631 vcpu->arch.tsc_offset = l1_offset;
2632
2633 static_call(kvm_x86_write_tsc_offset)(vcpu);
2634 }
2635
kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu * vcpu,u64 l1_multiplier)2636 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2637 {
2638 vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2639
2640 /* Userspace is changing the multiplier while L2 is active */
2641 if (is_guest_mode(vcpu))
2642 vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2643 l1_multiplier,
2644 static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2645 else
2646 vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2647
2648 if (kvm_caps.has_tsc_control)
2649 static_call(kvm_x86_write_tsc_multiplier)(vcpu);
2650 }
2651
kvm_check_tsc_unstable(void)2652 static inline bool kvm_check_tsc_unstable(void)
2653 {
2654 #ifdef CONFIG_X86_64
2655 /*
2656 * TSC is marked unstable when we're running on Hyper-V,
2657 * 'TSC page' clocksource is good.
2658 */
2659 if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2660 return false;
2661 #endif
2662 return check_tsc_unstable();
2663 }
2664
2665 /*
2666 * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2667 * offset for the vcpu and tracks the TSC matching generation that the vcpu
2668 * participates in.
2669 */
__kvm_synchronize_tsc(struct kvm_vcpu * vcpu,u64 offset,u64 tsc,u64 ns,bool matched)2670 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2671 u64 ns, bool matched)
2672 {
2673 struct kvm *kvm = vcpu->kvm;
2674
2675 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2676
2677 /*
2678 * We also track th most recent recorded KHZ, write and time to
2679 * allow the matching interval to be extended at each write.
2680 */
2681 kvm->arch.last_tsc_nsec = ns;
2682 kvm->arch.last_tsc_write = tsc;
2683 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2684 kvm->arch.last_tsc_offset = offset;
2685
2686 vcpu->arch.last_guest_tsc = tsc;
2687
2688 kvm_vcpu_write_tsc_offset(vcpu, offset);
2689
2690 if (!matched) {
2691 /*
2692 * We split periods of matched TSC writes into generations.
2693 * For each generation, we track the original measured
2694 * nanosecond time, offset, and write, so if TSCs are in
2695 * sync, we can match exact offset, and if not, we can match
2696 * exact software computation in compute_guest_tsc()
2697 *
2698 * These values are tracked in kvm->arch.cur_xxx variables.
2699 */
2700 kvm->arch.cur_tsc_generation++;
2701 kvm->arch.cur_tsc_nsec = ns;
2702 kvm->arch.cur_tsc_write = tsc;
2703 kvm->arch.cur_tsc_offset = offset;
2704 kvm->arch.nr_vcpus_matched_tsc = 0;
2705 } else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2706 kvm->arch.nr_vcpus_matched_tsc++;
2707 }
2708
2709 /* Keep track of which generation this VCPU has synchronized to */
2710 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2711 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2712 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2713
2714 kvm_track_tsc_matching(vcpu, !matched);
2715 }
2716
kvm_synchronize_tsc(struct kvm_vcpu * vcpu,u64 * user_value)2717 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 *user_value)
2718 {
2719 u64 data = user_value ? *user_value : 0;
2720 struct kvm *kvm = vcpu->kvm;
2721 u64 offset, ns, elapsed;
2722 unsigned long flags;
2723 bool matched = false;
2724 bool synchronizing = false;
2725
2726 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2727 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2728 ns = get_kvmclock_base_ns();
2729 elapsed = ns - kvm->arch.last_tsc_nsec;
2730
2731 if (vcpu->arch.virtual_tsc_khz) {
2732 if (data == 0) {
2733 /*
2734 * Force synchronization when creating a vCPU, or when
2735 * userspace explicitly writes a zero value.
2736 */
2737 synchronizing = true;
2738 } else if (kvm->arch.user_set_tsc) {
2739 u64 tsc_exp = kvm->arch.last_tsc_write +
2740 nsec_to_cycles(vcpu, elapsed);
2741 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2742 /*
2743 * Here lies UAPI baggage: when a user-initiated TSC write has
2744 * a small delta (1 second) of virtual cycle time against the
2745 * previously set vCPU, we assume that they were intended to be
2746 * in sync and the delta was only due to the racy nature of the
2747 * legacy API.
2748 *
2749 * This trick falls down when restoring a guest which genuinely
2750 * has been running for less time than the 1 second of imprecision
2751 * which we allow for in the legacy API. In this case, the first
2752 * value written by userspace (on any vCPU) should not be subject
2753 * to this 'correction' to make it sync up with values that only
2754 * come from the kernel's default vCPU creation. Make the 1-second
2755 * slop hack only trigger if the user_set_tsc flag is already set.
2756 */
2757 synchronizing = data < tsc_exp + tsc_hz &&
2758 data + tsc_hz > tsc_exp;
2759 }
2760 }
2761
2762 if (user_value)
2763 kvm->arch.user_set_tsc = true;
2764
2765 /*
2766 * For a reliable TSC, we can match TSC offsets, and for an unstable
2767 * TSC, we add elapsed time in this computation. We could let the
2768 * compensation code attempt to catch up if we fall behind, but
2769 * it's better to try to match offsets from the beginning.
2770 */
2771 if (synchronizing &&
2772 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2773 if (!kvm_check_tsc_unstable()) {
2774 offset = kvm->arch.cur_tsc_offset;
2775 } else {
2776 u64 delta = nsec_to_cycles(vcpu, elapsed);
2777 data += delta;
2778 offset = kvm_compute_l1_tsc_offset(vcpu, data);
2779 }
2780 matched = true;
2781 }
2782
2783 __kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2784 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2785 }
2786
adjust_tsc_offset_guest(struct kvm_vcpu * vcpu,s64 adjustment)2787 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2788 s64 adjustment)
2789 {
2790 u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2791 kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2792 }
2793
adjust_tsc_offset_host(struct kvm_vcpu * vcpu,s64 adjustment)2794 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2795 {
2796 if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2797 WARN_ON(adjustment < 0);
2798 adjustment = kvm_scale_tsc((u64) adjustment,
2799 vcpu->arch.l1_tsc_scaling_ratio);
2800 adjust_tsc_offset_guest(vcpu, adjustment);
2801 }
2802
2803 #ifdef CONFIG_X86_64
2804
read_tsc(void)2805 static u64 read_tsc(void)
2806 {
2807 u64 ret = (u64)rdtsc_ordered();
2808 u64 last = pvclock_gtod_data.clock.cycle_last;
2809
2810 if (likely(ret >= last))
2811 return ret;
2812
2813 /*
2814 * GCC likes to generate cmov here, but this branch is extremely
2815 * predictable (it's just a function of time and the likely is
2816 * very likely) and there's a data dependence, so force GCC
2817 * to generate a branch instead. I don't barrier() because
2818 * we don't actually need a barrier, and if this function
2819 * ever gets inlined it will generate worse code.
2820 */
2821 asm volatile ("");
2822 return last;
2823 }
2824
vgettsc(struct pvclock_clock * clock,u64 * tsc_timestamp,int * mode)2825 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2826 int *mode)
2827 {
2828 u64 tsc_pg_val;
2829 long v;
2830
2831 switch (clock->vclock_mode) {
2832 case VDSO_CLOCKMODE_HVCLOCK:
2833 if (hv_read_tsc_page_tsc(hv_get_tsc_page(),
2834 tsc_timestamp, &tsc_pg_val)) {
2835 /* TSC page valid */
2836 *mode = VDSO_CLOCKMODE_HVCLOCK;
2837 v = (tsc_pg_val - clock->cycle_last) &
2838 clock->mask;
2839 } else {
2840 /* TSC page invalid */
2841 *mode = VDSO_CLOCKMODE_NONE;
2842 }
2843 break;
2844 case VDSO_CLOCKMODE_TSC:
2845 *mode = VDSO_CLOCKMODE_TSC;
2846 *tsc_timestamp = read_tsc();
2847 v = (*tsc_timestamp - clock->cycle_last) &
2848 clock->mask;
2849 break;
2850 default:
2851 *mode = VDSO_CLOCKMODE_NONE;
2852 }
2853
2854 if (*mode == VDSO_CLOCKMODE_NONE)
2855 *tsc_timestamp = v = 0;
2856
2857 return v * clock->mult;
2858 }
2859
do_monotonic_raw(s64 * t,u64 * tsc_timestamp)2860 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2861 {
2862 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2863 unsigned long seq;
2864 int mode;
2865 u64 ns;
2866
2867 do {
2868 seq = read_seqcount_begin(>od->seq);
2869 ns = gtod->raw_clock.base_cycles;
2870 ns += vgettsc(>od->raw_clock, tsc_timestamp, &mode);
2871 ns >>= gtod->raw_clock.shift;
2872 ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2873 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2874 *t = ns;
2875
2876 return mode;
2877 }
2878
do_realtime(struct timespec64 * ts,u64 * tsc_timestamp)2879 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2880 {
2881 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2882 unsigned long seq;
2883 int mode;
2884 u64 ns;
2885
2886 do {
2887 seq = read_seqcount_begin(>od->seq);
2888 ts->tv_sec = gtod->wall_time_sec;
2889 ns = gtod->clock.base_cycles;
2890 ns += vgettsc(>od->clock, tsc_timestamp, &mode);
2891 ns >>= gtod->clock.shift;
2892 } while (unlikely(read_seqcount_retry(>od->seq, seq)));
2893
2894 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2895 ts->tv_nsec = ns;
2896
2897 return mode;
2898 }
2899
2900 /* returns true if host is using TSC based clocksource */
kvm_get_time_and_clockread(s64 * kernel_ns,u64 * tsc_timestamp)2901 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2902 {
2903 /* checked again under seqlock below */
2904 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2905 return false;
2906
2907 return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2908 tsc_timestamp));
2909 }
2910
2911 /* returns true if host is using TSC based clocksource */
kvm_get_walltime_and_clockread(struct timespec64 * ts,u64 * tsc_timestamp)2912 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2913 u64 *tsc_timestamp)
2914 {
2915 /* checked again under seqlock below */
2916 if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2917 return false;
2918
2919 return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2920 }
2921 #endif
2922
2923 /*
2924 *
2925 * Assuming a stable TSC across physical CPUS, and a stable TSC
2926 * across virtual CPUs, the following condition is possible.
2927 * Each numbered line represents an event visible to both
2928 * CPUs at the next numbered event.
2929 *
2930 * "timespecX" represents host monotonic time. "tscX" represents
2931 * RDTSC value.
2932 *
2933 * VCPU0 on CPU0 | VCPU1 on CPU1
2934 *
2935 * 1. read timespec0,tsc0
2936 * 2. | timespec1 = timespec0 + N
2937 * | tsc1 = tsc0 + M
2938 * 3. transition to guest | transition to guest
2939 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2940 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
2941 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2942 *
2943 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2944 *
2945 * - ret0 < ret1
2946 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2947 * ...
2948 * - 0 < N - M => M < N
2949 *
2950 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2951 * always the case (the difference between two distinct xtime instances
2952 * might be smaller then the difference between corresponding TSC reads,
2953 * when updating guest vcpus pvclock areas).
2954 *
2955 * To avoid that problem, do not allow visibility of distinct
2956 * system_timestamp/tsc_timestamp values simultaneously: use a master
2957 * copy of host monotonic time values. Update that master copy
2958 * in lockstep.
2959 *
2960 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2961 *
2962 */
2963
pvclock_update_vm_gtod_copy(struct kvm * kvm)2964 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2965 {
2966 #ifdef CONFIG_X86_64
2967 struct kvm_arch *ka = &kvm->arch;
2968 int vclock_mode;
2969 bool host_tsc_clocksource, vcpus_matched;
2970
2971 lockdep_assert_held(&kvm->arch.tsc_write_lock);
2972 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2973 atomic_read(&kvm->online_vcpus));
2974
2975 /*
2976 * If the host uses TSC clock, then passthrough TSC as stable
2977 * to the guest.
2978 */
2979 host_tsc_clocksource = kvm_get_time_and_clockread(
2980 &ka->master_kernel_ns,
2981 &ka->master_cycle_now);
2982
2983 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2984 && !ka->backwards_tsc_observed
2985 && !ka->boot_vcpu_runs_old_kvmclock;
2986
2987 if (ka->use_master_clock)
2988 atomic_set(&kvm_guest_has_master_clock, 1);
2989
2990 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2991 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2992 vcpus_matched);
2993 #endif
2994 }
2995
kvm_make_mclock_inprogress_request(struct kvm * kvm)2996 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2997 {
2998 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2999 }
3000
__kvm_start_pvclock_update(struct kvm * kvm)3001 static void __kvm_start_pvclock_update(struct kvm *kvm)
3002 {
3003 raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
3004 write_seqcount_begin(&kvm->arch.pvclock_sc);
3005 }
3006
kvm_start_pvclock_update(struct kvm * kvm)3007 static void kvm_start_pvclock_update(struct kvm *kvm)
3008 {
3009 kvm_make_mclock_inprogress_request(kvm);
3010
3011 /* no guest entries from this point */
3012 __kvm_start_pvclock_update(kvm);
3013 }
3014
kvm_end_pvclock_update(struct kvm * kvm)3015 static void kvm_end_pvclock_update(struct kvm *kvm)
3016 {
3017 struct kvm_arch *ka = &kvm->arch;
3018 struct kvm_vcpu *vcpu;
3019 unsigned long i;
3020
3021 write_seqcount_end(&ka->pvclock_sc);
3022 raw_spin_unlock_irq(&ka->tsc_write_lock);
3023 kvm_for_each_vcpu(i, vcpu, kvm)
3024 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3025
3026 /* guest entries allowed */
3027 kvm_for_each_vcpu(i, vcpu, kvm)
3028 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
3029 }
3030
kvm_update_masterclock(struct kvm * kvm)3031 static void kvm_update_masterclock(struct kvm *kvm)
3032 {
3033 kvm_hv_request_tsc_page_update(kvm);
3034 kvm_start_pvclock_update(kvm);
3035 pvclock_update_vm_gtod_copy(kvm);
3036 kvm_end_pvclock_update(kvm);
3037 }
3038
3039 /*
3040 * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
3041 * per-CPU value (which may be zero if a CPU is going offline). Note, tsc_khz
3042 * can change during boot even if the TSC is constant, as it's possible for KVM
3043 * to be loaded before TSC calibration completes. Ideally, KVM would get a
3044 * notification when calibration completes, but practically speaking calibration
3045 * will complete before userspace is alive enough to create VMs.
3046 */
get_cpu_tsc_khz(void)3047 static unsigned long get_cpu_tsc_khz(void)
3048 {
3049 if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3050 return tsc_khz;
3051 else
3052 return __this_cpu_read(cpu_tsc_khz);
3053 }
3054
3055 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc. */
__get_kvmclock(struct kvm * kvm,struct kvm_clock_data * data)3056 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3057 {
3058 struct kvm_arch *ka = &kvm->arch;
3059 struct pvclock_vcpu_time_info hv_clock;
3060
3061 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
3062 get_cpu();
3063
3064 data->flags = 0;
3065 if (ka->use_master_clock &&
3066 (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3067 #ifdef CONFIG_X86_64
3068 struct timespec64 ts;
3069
3070 if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3071 data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3072 data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3073 } else
3074 #endif
3075 data->host_tsc = rdtsc();
3076
3077 data->flags |= KVM_CLOCK_TSC_STABLE;
3078 hv_clock.tsc_timestamp = ka->master_cycle_now;
3079 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3080 kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3081 &hv_clock.tsc_shift,
3082 &hv_clock.tsc_to_system_mul);
3083 data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3084 } else {
3085 data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3086 }
3087
3088 put_cpu();
3089 }
3090
get_kvmclock(struct kvm * kvm,struct kvm_clock_data * data)3091 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3092 {
3093 struct kvm_arch *ka = &kvm->arch;
3094 unsigned seq;
3095
3096 do {
3097 seq = read_seqcount_begin(&ka->pvclock_sc);
3098 __get_kvmclock(kvm, data);
3099 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3100 }
3101
get_kvmclock_ns(struct kvm * kvm)3102 u64 get_kvmclock_ns(struct kvm *kvm)
3103 {
3104 struct kvm_clock_data data;
3105
3106 get_kvmclock(kvm, &data);
3107 return data.clock;
3108 }
3109
kvm_setup_guest_pvclock(struct kvm_vcpu * v,struct gfn_to_pfn_cache * gpc,unsigned int offset,bool force_tsc_unstable)3110 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3111 struct gfn_to_pfn_cache *gpc,
3112 unsigned int offset,
3113 bool force_tsc_unstable)
3114 {
3115 struct kvm_vcpu_arch *vcpu = &v->arch;
3116 struct pvclock_vcpu_time_info *guest_hv_clock;
3117 unsigned long flags;
3118
3119 read_lock_irqsave(&gpc->lock, flags);
3120 while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3121 read_unlock_irqrestore(&gpc->lock, flags);
3122
3123 if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3124 return;
3125
3126 read_lock_irqsave(&gpc->lock, flags);
3127 }
3128
3129 guest_hv_clock = (void *)(gpc->khva + offset);
3130
3131 /*
3132 * This VCPU is paused, but it's legal for a guest to read another
3133 * VCPU's kvmclock, so we really have to follow the specification where
3134 * it says that version is odd if data is being modified, and even after
3135 * it is consistent.
3136 */
3137
3138 guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3139 smp_wmb();
3140
3141 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3142 vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3143
3144 if (vcpu->pvclock_set_guest_stopped_request) {
3145 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3146 vcpu->pvclock_set_guest_stopped_request = false;
3147 }
3148
3149 memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3150
3151 if (force_tsc_unstable)
3152 guest_hv_clock->flags &= ~PVCLOCK_TSC_STABLE_BIT;
3153
3154 smp_wmb();
3155
3156 guest_hv_clock->version = ++vcpu->hv_clock.version;
3157
3158 mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3159 read_unlock_irqrestore(&gpc->lock, flags);
3160
3161 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3162 }
3163
kvm_guest_time_update(struct kvm_vcpu * v)3164 static int kvm_guest_time_update(struct kvm_vcpu *v)
3165 {
3166 unsigned long flags, tgt_tsc_khz;
3167 unsigned seq;
3168 struct kvm_vcpu_arch *vcpu = &v->arch;
3169 struct kvm_arch *ka = &v->kvm->arch;
3170 s64 kernel_ns;
3171 u64 tsc_timestamp, host_tsc;
3172 u8 pvclock_flags;
3173 bool use_master_clock;
3174 #ifdef CONFIG_KVM_XEN
3175 /*
3176 * For Xen guests we may need to override PVCLOCK_TSC_STABLE_BIT as unless
3177 * explicitly told to use TSC as its clocksource Xen will not set this bit.
3178 * This default behaviour led to bugs in some guest kernels which cause
3179 * problems if they observe PVCLOCK_TSC_STABLE_BIT in the pvclock flags.
3180 */
3181 bool xen_pvclock_tsc_unstable =
3182 ka->xen_hvm_config.flags & KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE;
3183 #endif
3184
3185 kernel_ns = 0;
3186 host_tsc = 0;
3187
3188 /*
3189 * If the host uses TSC clock, then passthrough TSC as stable
3190 * to the guest.
3191 */
3192 do {
3193 seq = read_seqcount_begin(&ka->pvclock_sc);
3194 use_master_clock = ka->use_master_clock;
3195 if (use_master_clock) {
3196 host_tsc = ka->master_cycle_now;
3197 kernel_ns = ka->master_kernel_ns;
3198 }
3199 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3200
3201 /* Keep irq disabled to prevent changes to the clock */
3202 local_irq_save(flags);
3203 tgt_tsc_khz = get_cpu_tsc_khz();
3204 if (unlikely(tgt_tsc_khz == 0)) {
3205 local_irq_restore(flags);
3206 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3207 return 1;
3208 }
3209 if (!use_master_clock) {
3210 host_tsc = rdtsc();
3211 kernel_ns = get_kvmclock_base_ns();
3212 }
3213
3214 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3215
3216 /*
3217 * We may have to catch up the TSC to match elapsed wall clock
3218 * time for two reasons, even if kvmclock is used.
3219 * 1) CPU could have been running below the maximum TSC rate
3220 * 2) Broken TSC compensation resets the base at each VCPU
3221 * entry to avoid unknown leaps of TSC even when running
3222 * again on the same CPU. This may cause apparent elapsed
3223 * time to disappear, and the guest to stand still or run
3224 * very slowly.
3225 */
3226 if (vcpu->tsc_catchup) {
3227 u64 tsc = compute_guest_tsc(v, kernel_ns);
3228 if (tsc > tsc_timestamp) {
3229 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3230 tsc_timestamp = tsc;
3231 }
3232 }
3233
3234 local_irq_restore(flags);
3235
3236 /* With all the info we got, fill in the values */
3237
3238 if (kvm_caps.has_tsc_control)
3239 tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3240 v->arch.l1_tsc_scaling_ratio);
3241
3242 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3243 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3244 &vcpu->hv_clock.tsc_shift,
3245 &vcpu->hv_clock.tsc_to_system_mul);
3246 vcpu->hw_tsc_khz = tgt_tsc_khz;
3247 kvm_xen_update_tsc_info(v);
3248 }
3249
3250 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3251 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3252 vcpu->last_guest_tsc = tsc_timestamp;
3253
3254 /* If the host uses TSC clocksource, then it is stable */
3255 pvclock_flags = 0;
3256 if (use_master_clock)
3257 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3258
3259 vcpu->hv_clock.flags = pvclock_flags;
3260
3261 if (vcpu->pv_time.active)
3262 kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0, false);
3263 #ifdef CONFIG_KVM_XEN
3264 if (vcpu->xen.vcpu_info_cache.active)
3265 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3266 offsetof(struct compat_vcpu_info, time),
3267 xen_pvclock_tsc_unstable);
3268 if (vcpu->xen.vcpu_time_info_cache.active)
3269 kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0,
3270 xen_pvclock_tsc_unstable);
3271 #endif
3272 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3273 return 0;
3274 }
3275
3276 /*
3277 * The pvclock_wall_clock ABI tells the guest the wall clock time at
3278 * which it started (i.e. its epoch, when its kvmclock was zero).
3279 *
3280 * In fact those clocks are subtly different; wall clock frequency is
3281 * adjusted by NTP and has leap seconds, while the kvmclock is a
3282 * simple function of the TSC without any such adjustment.
3283 *
3284 * Perhaps the ABI should have exposed CLOCK_TAI and a ratio between
3285 * that and kvmclock, but even that would be subject to change over
3286 * time.
3287 *
3288 * Attempt to calculate the epoch at a given moment using the *same*
3289 * TSC reading via kvm_get_walltime_and_clockread() to obtain both
3290 * wallclock and kvmclock times, and subtracting one from the other.
3291 *
3292 * Fall back to using their values at slightly different moments by
3293 * calling ktime_get_real_ns() and get_kvmclock_ns() separately.
3294 */
kvm_get_wall_clock_epoch(struct kvm * kvm)3295 uint64_t kvm_get_wall_clock_epoch(struct kvm *kvm)
3296 {
3297 #ifdef CONFIG_X86_64
3298 struct pvclock_vcpu_time_info hv_clock;
3299 struct kvm_arch *ka = &kvm->arch;
3300 unsigned long seq, local_tsc_khz;
3301 struct timespec64 ts;
3302 uint64_t host_tsc;
3303
3304 do {
3305 seq = read_seqcount_begin(&ka->pvclock_sc);
3306
3307 local_tsc_khz = 0;
3308 if (!ka->use_master_clock)
3309 break;
3310
3311 /*
3312 * The TSC read and the call to get_cpu_tsc_khz() must happen
3313 * on the same CPU.
3314 */
3315 get_cpu();
3316
3317 local_tsc_khz = get_cpu_tsc_khz();
3318
3319 if (local_tsc_khz &&
3320 !kvm_get_walltime_and_clockread(&ts, &host_tsc))
3321 local_tsc_khz = 0; /* Fall back to old method */
3322
3323 put_cpu();
3324
3325 /*
3326 * These values must be snapshotted within the seqcount loop.
3327 * After that, it's just mathematics which can happen on any
3328 * CPU at any time.
3329 */
3330 hv_clock.tsc_timestamp = ka->master_cycle_now;
3331 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3332
3333 } while (read_seqcount_retry(&ka->pvclock_sc, seq));
3334
3335 /*
3336 * If the conditions were right, and obtaining the wallclock+TSC was
3337 * successful, calculate the KVM clock at the corresponding time and
3338 * subtract one from the other to get the guest's epoch in nanoseconds
3339 * since 1970-01-01.
3340 */
3341 if (local_tsc_khz) {
3342 kvm_get_time_scale(NSEC_PER_SEC, local_tsc_khz * NSEC_PER_USEC,
3343 &hv_clock.tsc_shift,
3344 &hv_clock.tsc_to_system_mul);
3345 return ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec -
3346 __pvclock_read_cycles(&hv_clock, host_tsc);
3347 }
3348 #endif
3349 return ktime_get_real_ns() - get_kvmclock_ns(kvm);
3350 }
3351
3352 /*
3353 * kvmclock updates which are isolated to a given vcpu, such as
3354 * vcpu->cpu migration, should not allow system_timestamp from
3355 * the rest of the vcpus to remain static. Otherwise ntp frequency
3356 * correction applies to one vcpu's system_timestamp but not
3357 * the others.
3358 *
3359 * So in those cases, request a kvmclock update for all vcpus.
3360 * We need to rate-limit these requests though, as they can
3361 * considerably slow guests that have a large number of vcpus.
3362 * The time for a remote vcpu to update its kvmclock is bound
3363 * by the delay we use to rate-limit the updates.
3364 */
3365
3366 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3367
kvmclock_update_fn(struct work_struct * work)3368 static void kvmclock_update_fn(struct work_struct *work)
3369 {
3370 unsigned long i;
3371 struct delayed_work *dwork = to_delayed_work(work);
3372 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3373 kvmclock_update_work);
3374 struct kvm *kvm = container_of(ka, struct kvm, arch);
3375 struct kvm_vcpu *vcpu;
3376
3377 kvm_for_each_vcpu(i, vcpu, kvm) {
3378 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3379 kvm_vcpu_kick(vcpu);
3380 }
3381 }
3382
kvm_gen_kvmclock_update(struct kvm_vcpu * v)3383 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3384 {
3385 struct kvm *kvm = v->kvm;
3386
3387 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3388 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3389 KVMCLOCK_UPDATE_DELAY);
3390 }
3391
3392 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3393
kvmclock_sync_fn(struct work_struct * work)3394 static void kvmclock_sync_fn(struct work_struct *work)
3395 {
3396 struct delayed_work *dwork = to_delayed_work(work);
3397 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3398 kvmclock_sync_work);
3399 struct kvm *kvm = container_of(ka, struct kvm, arch);
3400
3401 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3402 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3403 KVMCLOCK_SYNC_PERIOD);
3404 }
3405
3406 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
is_mci_control_msr(u32 msr)3407 static bool is_mci_control_msr(u32 msr)
3408 {
3409 return (msr & 3) == 0;
3410 }
is_mci_status_msr(u32 msr)3411 static bool is_mci_status_msr(u32 msr)
3412 {
3413 return (msr & 3) == 1;
3414 }
3415
3416 /*
3417 * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3418 */
can_set_mci_status(struct kvm_vcpu * vcpu)3419 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3420 {
3421 /* McStatusWrEn enabled? */
3422 if (guest_cpuid_is_amd_or_hygon(vcpu))
3423 return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3424
3425 return false;
3426 }
3427
set_msr_mce(struct kvm_vcpu * vcpu,struct msr_data * msr_info)3428 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3429 {
3430 u64 mcg_cap = vcpu->arch.mcg_cap;
3431 unsigned bank_num = mcg_cap & 0xff;
3432 u32 msr = msr_info->index;
3433 u64 data = msr_info->data;
3434 u32 offset, last_msr;
3435
3436 switch (msr) {
3437 case MSR_IA32_MCG_STATUS:
3438 vcpu->arch.mcg_status = data;
3439 break;
3440 case MSR_IA32_MCG_CTL:
3441 if (!(mcg_cap & MCG_CTL_P) &&
3442 (data || !msr_info->host_initiated))
3443 return 1;
3444 if (data != 0 && data != ~(u64)0)
3445 return 1;
3446 vcpu->arch.mcg_ctl = data;
3447 break;
3448 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3449 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3450 if (msr > last_msr)
3451 return 1;
3452
3453 if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3454 return 1;
3455 /* An attempt to write a 1 to a reserved bit raises #GP */
3456 if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3457 return 1;
3458 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3459 last_msr + 1 - MSR_IA32_MC0_CTL2);
3460 vcpu->arch.mci_ctl2_banks[offset] = data;
3461 break;
3462 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3463 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3464 if (msr > last_msr)
3465 return 1;
3466
3467 /*
3468 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3469 * values are architecturally undefined. But, some Linux
3470 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3471 * issue on AMD K8s, allow bit 10 to be clear when setting all
3472 * other bits in order to avoid an uncaught #GP in the guest.
3473 *
3474 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3475 * single-bit ECC data errors.
3476 */
3477 if (is_mci_control_msr(msr) &&
3478 data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3479 return 1;
3480
3481 /*
3482 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3483 * AMD-based CPUs allow non-zero values, but if and only if
3484 * HWCR[McStatusWrEn] is set.
3485 */
3486 if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3487 data != 0 && !can_set_mci_status(vcpu))
3488 return 1;
3489
3490 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3491 last_msr + 1 - MSR_IA32_MC0_CTL);
3492 vcpu->arch.mce_banks[offset] = data;
3493 break;
3494 default:
3495 return 1;
3496 }
3497 return 0;
3498 }
3499
kvm_pv_async_pf_enabled(struct kvm_vcpu * vcpu)3500 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3501 {
3502 u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3503
3504 return (vcpu->arch.apf.msr_en_val & mask) == mask;
3505 }
3506
kvm_pv_enable_async_pf(struct kvm_vcpu * vcpu,u64 data)3507 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3508 {
3509 gpa_t gpa = data & ~0x3f;
3510
3511 /* Bits 4:5 are reserved, Should be zero */
3512 if (data & 0x30)
3513 return 1;
3514
3515 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3516 (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3517 return 1;
3518
3519 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3520 (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3521 return 1;
3522
3523 if (!lapic_in_kernel(vcpu))
3524 return data ? 1 : 0;
3525
3526 vcpu->arch.apf.msr_en_val = data;
3527
3528 if (!kvm_pv_async_pf_enabled(vcpu)) {
3529 kvm_clear_async_pf_completion_queue(vcpu);
3530 kvm_async_pf_hash_reset(vcpu);
3531 return 0;
3532 }
3533
3534 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3535 sizeof(u64)))
3536 return 1;
3537
3538 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3539 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3540
3541 kvm_async_pf_wakeup_all(vcpu);
3542
3543 return 0;
3544 }
3545
kvm_pv_enable_async_pf_int(struct kvm_vcpu * vcpu,u64 data)3546 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3547 {
3548 /* Bits 8-63 are reserved */
3549 if (data >> 8)
3550 return 1;
3551
3552 if (!lapic_in_kernel(vcpu))
3553 return 1;
3554
3555 vcpu->arch.apf.msr_int_val = data;
3556
3557 vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3558
3559 return 0;
3560 }
3561
kvmclock_reset(struct kvm_vcpu * vcpu)3562 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3563 {
3564 kvm_gpc_deactivate(&vcpu->arch.pv_time);
3565 vcpu->arch.time = 0;
3566 }
3567
kvm_vcpu_flush_tlb_all(struct kvm_vcpu * vcpu)3568 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3569 {
3570 ++vcpu->stat.tlb_flush;
3571 static_call(kvm_x86_flush_tlb_all)(vcpu);
3572
3573 /* Flushing all ASIDs flushes the current ASID... */
3574 kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3575 }
3576
kvm_vcpu_flush_tlb_guest(struct kvm_vcpu * vcpu)3577 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3578 {
3579 ++vcpu->stat.tlb_flush;
3580
3581 if (!tdp_enabled) {
3582 /*
3583 * A TLB flush on behalf of the guest is equivalent to
3584 * INVPCID(all), toggling CR4.PGE, etc., which requires
3585 * a forced sync of the shadow page tables. Ensure all the
3586 * roots are synced and the guest TLB in hardware is clean.
3587 */
3588 kvm_mmu_sync_roots(vcpu);
3589 kvm_mmu_sync_prev_roots(vcpu);
3590 }
3591
3592 static_call(kvm_x86_flush_tlb_guest)(vcpu);
3593
3594 /*
3595 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3596 * grained flushing.
3597 */
3598 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3599 }
3600
3601
kvm_vcpu_flush_tlb_current(struct kvm_vcpu * vcpu)3602 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3603 {
3604 ++vcpu->stat.tlb_flush;
3605 static_call(kvm_x86_flush_tlb_current)(vcpu);
3606 }
3607
3608 /*
3609 * Service "local" TLB flush requests, which are specific to the current MMU
3610 * context. In addition to the generic event handling in vcpu_enter_guest(),
3611 * TLB flushes that are targeted at an MMU context also need to be serviced
3612 * prior before nested VM-Enter/VM-Exit.
3613 */
kvm_service_local_tlb_flush_requests(struct kvm_vcpu * vcpu)3614 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3615 {
3616 if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3617 kvm_vcpu_flush_tlb_current(vcpu);
3618
3619 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3620 kvm_vcpu_flush_tlb_guest(vcpu);
3621 }
3622 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3623
record_steal_time(struct kvm_vcpu * vcpu)3624 static void record_steal_time(struct kvm_vcpu *vcpu)
3625 {
3626 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3627 struct kvm_steal_time __user *st;
3628 struct kvm_memslots *slots;
3629 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3630 u64 steal;
3631 u32 version;
3632
3633 if (kvm_xen_msr_enabled(vcpu->kvm)) {
3634 kvm_xen_runstate_set_running(vcpu);
3635 return;
3636 }
3637
3638 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3639 return;
3640
3641 if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3642 return;
3643
3644 slots = kvm_memslots(vcpu->kvm);
3645
3646 if (unlikely(slots->generation != ghc->generation ||
3647 gpa != ghc->gpa ||
3648 kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3649 /* We rely on the fact that it fits in a single page. */
3650 BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3651
3652 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3653 kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3654 return;
3655 }
3656
3657 st = (struct kvm_steal_time __user *)ghc->hva;
3658 /*
3659 * Doing a TLB flush here, on the guest's behalf, can avoid
3660 * expensive IPIs.
3661 */
3662 if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3663 u8 st_preempted = 0;
3664 int err = -EFAULT;
3665
3666 if (!user_access_begin(st, sizeof(*st)))
3667 return;
3668
3669 asm volatile("1: xchgb %0, %2\n"
3670 "xor %1, %1\n"
3671 "2:\n"
3672 _ASM_EXTABLE_UA(1b, 2b)
3673 : "+q" (st_preempted),
3674 "+&r" (err),
3675 "+m" (st->preempted));
3676 if (err)
3677 goto out;
3678
3679 user_access_end();
3680
3681 vcpu->arch.st.preempted = 0;
3682
3683 trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3684 st_preempted & KVM_VCPU_FLUSH_TLB);
3685 if (st_preempted & KVM_VCPU_FLUSH_TLB)
3686 kvm_vcpu_flush_tlb_guest(vcpu);
3687
3688 if (!user_access_begin(st, sizeof(*st)))
3689 goto dirty;
3690 } else {
3691 if (!user_access_begin(st, sizeof(*st)))
3692 return;
3693
3694 unsafe_put_user(0, &st->preempted, out);
3695 vcpu->arch.st.preempted = 0;
3696 }
3697
3698 unsafe_get_user(version, &st->version, out);
3699 if (version & 1)
3700 version += 1; /* first time write, random junk */
3701
3702 version += 1;
3703 unsafe_put_user(version, &st->version, out);
3704
3705 smp_wmb();
3706
3707 unsafe_get_user(steal, &st->steal, out);
3708 steal += current->sched_info.run_delay -
3709 vcpu->arch.st.last_steal;
3710 vcpu->arch.st.last_steal = current->sched_info.run_delay;
3711 unsafe_put_user(steal, &st->steal, out);
3712
3713 version += 1;
3714 unsafe_put_user(version, &st->version, out);
3715
3716 out:
3717 user_access_end();
3718 dirty:
3719 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3720 }
3721
kvm_is_msr_to_save(u32 msr_index)3722 static bool kvm_is_msr_to_save(u32 msr_index)
3723 {
3724 unsigned int i;
3725
3726 for (i = 0; i < num_msrs_to_save; i++) {
3727 if (msrs_to_save[i] == msr_index)
3728 return true;
3729 }
3730
3731 return false;
3732 }
3733
kvm_set_msr_common(struct kvm_vcpu * vcpu,struct msr_data * msr_info)3734 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3735 {
3736 u32 msr = msr_info->index;
3737 u64 data = msr_info->data;
3738
3739 if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3740 return kvm_xen_write_hypercall_page(vcpu, data);
3741
3742 switch (msr) {
3743 case MSR_AMD64_NB_CFG:
3744 case MSR_IA32_UCODE_WRITE:
3745 case MSR_VM_HSAVE_PA:
3746 case MSR_AMD64_PATCH_LOADER:
3747 case MSR_AMD64_BU_CFG2:
3748 case MSR_AMD64_DC_CFG:
3749 case MSR_AMD64_TW_CFG:
3750 case MSR_F15H_EX_CFG:
3751 break;
3752
3753 case MSR_IA32_UCODE_REV:
3754 if (msr_info->host_initiated)
3755 vcpu->arch.microcode_version = data;
3756 break;
3757 case MSR_IA32_ARCH_CAPABILITIES:
3758 if (!msr_info->host_initiated)
3759 return 1;
3760 vcpu->arch.arch_capabilities = data;
3761 break;
3762 case MSR_IA32_PERF_CAPABILITIES:
3763 if (!msr_info->host_initiated)
3764 return 1;
3765 if (data & ~kvm_caps.supported_perf_cap)
3766 return 1;
3767
3768 /*
3769 * Note, this is not just a performance optimization! KVM
3770 * disallows changing feature MSRs after the vCPU has run; PMU
3771 * refresh will bug the VM if called after the vCPU has run.
3772 */
3773 if (vcpu->arch.perf_capabilities == data)
3774 break;
3775
3776 vcpu->arch.perf_capabilities = data;
3777 kvm_pmu_refresh(vcpu);
3778 break;
3779 case MSR_IA32_PRED_CMD: {
3780 u64 reserved_bits = ~(PRED_CMD_IBPB | PRED_CMD_SBPB);
3781
3782 if (!msr_info->host_initiated) {
3783 if ((!guest_has_pred_cmd_msr(vcpu)))
3784 return 1;
3785
3786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
3787 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
3788 reserved_bits |= PRED_CMD_IBPB;
3789
3790 if (!guest_cpuid_has(vcpu, X86_FEATURE_SBPB))
3791 reserved_bits |= PRED_CMD_SBPB;
3792 }
3793
3794 if (!boot_cpu_has(X86_FEATURE_IBPB))
3795 reserved_bits |= PRED_CMD_IBPB;
3796
3797 if (!boot_cpu_has(X86_FEATURE_SBPB))
3798 reserved_bits |= PRED_CMD_SBPB;
3799
3800 if (data & reserved_bits)
3801 return 1;
3802
3803 if (!data)
3804 break;
3805
3806 wrmsrl(MSR_IA32_PRED_CMD, data);
3807 break;
3808 }
3809 case MSR_IA32_FLUSH_CMD:
3810 if (!msr_info->host_initiated &&
3811 !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3812 return 1;
3813
3814 if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3815 return 1;
3816 if (!data)
3817 break;
3818
3819 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3820 break;
3821 case MSR_EFER:
3822 return set_efer(vcpu, msr_info);
3823 case MSR_K7_HWCR:
3824 data &= ~(u64)0x40; /* ignore flush filter disable */
3825 data &= ~(u64)0x100; /* ignore ignne emulation enable */
3826 data &= ~(u64)0x8; /* ignore TLB cache disable */
3827
3828 /*
3829 * Allow McStatusWrEn and TscFreqSel. (Linux guests from v3.2
3830 * through at least v6.6 whine if TscFreqSel is clear,
3831 * depending on F/M/S.
3832 */
3833 if (data & ~(BIT_ULL(18) | BIT_ULL(24))) {
3834 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3835 return 1;
3836 }
3837 vcpu->arch.msr_hwcr = data;
3838 break;
3839 case MSR_FAM10H_MMIO_CONF_BASE:
3840 if (data != 0) {
3841 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3842 return 1;
3843 }
3844 break;
3845 case MSR_IA32_CR_PAT:
3846 if (!kvm_pat_valid(data))
3847 return 1;
3848
3849 vcpu->arch.pat = data;
3850 break;
3851 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
3852 case MSR_MTRRdefType:
3853 return kvm_mtrr_set_msr(vcpu, msr, data);
3854 case MSR_IA32_APICBASE:
3855 return kvm_set_apic_base(vcpu, msr_info);
3856 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3857 return kvm_x2apic_msr_write(vcpu, msr, data);
3858 case MSR_IA32_TSC_DEADLINE:
3859 kvm_set_lapic_tscdeadline_msr(vcpu, data);
3860 break;
3861 case MSR_IA32_TSC_ADJUST:
3862 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3863 if (!msr_info->host_initiated) {
3864 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3865 adjust_tsc_offset_guest(vcpu, adj);
3866 /* Before back to guest, tsc_timestamp must be adjusted
3867 * as well, otherwise guest's percpu pvclock time could jump.
3868 */
3869 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3870 }
3871 vcpu->arch.ia32_tsc_adjust_msr = data;
3872 }
3873 break;
3874 case MSR_IA32_MISC_ENABLE: {
3875 u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3876
3877 if (!msr_info->host_initiated) {
3878 /* RO bits */
3879 if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3880 return 1;
3881
3882 /* R bits, i.e. writes are ignored, but don't fault. */
3883 data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3884 data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3885 }
3886
3887 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3888 ((old_val ^ data) & MSR_IA32_MISC_ENABLE_MWAIT)) {
3889 if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3890 return 1;
3891 vcpu->arch.ia32_misc_enable_msr = data;
3892 kvm_update_cpuid_runtime(vcpu);
3893 } else {
3894 vcpu->arch.ia32_misc_enable_msr = data;
3895 }
3896 break;
3897 }
3898 case MSR_IA32_SMBASE:
3899 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3900 return 1;
3901 vcpu->arch.smbase = data;
3902 break;
3903 case MSR_IA32_POWER_CTL:
3904 vcpu->arch.msr_ia32_power_ctl = data;
3905 break;
3906 case MSR_IA32_TSC:
3907 if (msr_info->host_initiated) {
3908 kvm_synchronize_tsc(vcpu, &data);
3909 } else {
3910 u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3911 adjust_tsc_offset_guest(vcpu, adj);
3912 vcpu->arch.ia32_tsc_adjust_msr += adj;
3913 }
3914 break;
3915 case MSR_IA32_XSS:
3916 if (!msr_info->host_initiated &&
3917 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3918 return 1;
3919 /*
3920 * KVM supports exposing PT to the guest, but does not support
3921 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3922 * XSAVES/XRSTORS to save/restore PT MSRs.
3923 */
3924 if (data & ~kvm_caps.supported_xss)
3925 return 1;
3926 vcpu->arch.ia32_xss = data;
3927 kvm_update_cpuid_runtime(vcpu);
3928 break;
3929 case MSR_SMI_COUNT:
3930 if (!msr_info->host_initiated)
3931 return 1;
3932 vcpu->arch.smi_count = data;
3933 break;
3934 case MSR_KVM_WALL_CLOCK_NEW:
3935 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3936 return 1;
3937
3938 vcpu->kvm->arch.wall_clock = data;
3939 kvm_write_wall_clock(vcpu->kvm, data, 0);
3940 break;
3941 case MSR_KVM_WALL_CLOCK:
3942 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3943 return 1;
3944
3945 vcpu->kvm->arch.wall_clock = data;
3946 kvm_write_wall_clock(vcpu->kvm, data, 0);
3947 break;
3948 case MSR_KVM_SYSTEM_TIME_NEW:
3949 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3950 return 1;
3951
3952 kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3953 break;
3954 case MSR_KVM_SYSTEM_TIME:
3955 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3956 return 1;
3957
3958 kvm_write_system_time(vcpu, data, true, msr_info->host_initiated);
3959 break;
3960 case MSR_KVM_ASYNC_PF_EN:
3961 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3962 return 1;
3963
3964 if (kvm_pv_enable_async_pf(vcpu, data))
3965 return 1;
3966 break;
3967 case MSR_KVM_ASYNC_PF_INT:
3968 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3969 return 1;
3970
3971 if (kvm_pv_enable_async_pf_int(vcpu, data))
3972 return 1;
3973 break;
3974 case MSR_KVM_ASYNC_PF_ACK:
3975 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3976 return 1;
3977 if (data & 0x1) {
3978 vcpu->arch.apf.pageready_pending = false;
3979 kvm_check_async_pf_completion(vcpu);
3980 }
3981 break;
3982 case MSR_KVM_STEAL_TIME:
3983 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3984 return 1;
3985
3986 if (unlikely(!sched_info_on()))
3987 return 1;
3988
3989 if (data & KVM_STEAL_RESERVED_MASK)
3990 return 1;
3991
3992 vcpu->arch.st.msr_val = data;
3993
3994 if (!(data & KVM_MSR_ENABLED))
3995 break;
3996
3997 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3998
3999 break;
4000 case MSR_KVM_PV_EOI_EN:
4001 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4002 return 1;
4003
4004 if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
4005 return 1;
4006 break;
4007
4008 case MSR_KVM_POLL_CONTROL:
4009 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4010 return 1;
4011
4012 /* only enable bit supported */
4013 if (data & (-1ULL << 1))
4014 return 1;
4015
4016 vcpu->arch.msr_kvm_poll_control = data;
4017 break;
4018
4019 case MSR_IA32_MCG_CTL:
4020 case MSR_IA32_MCG_STATUS:
4021 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4022 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4023 return set_msr_mce(vcpu, msr_info);
4024
4025 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4026 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4027 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4028 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4029 if (kvm_pmu_is_valid_msr(vcpu, msr))
4030 return kvm_pmu_set_msr(vcpu, msr_info);
4031
4032 if (data)
4033 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
4034 break;
4035 case MSR_K7_CLK_CTL:
4036 /*
4037 * Ignore all writes to this no longer documented MSR.
4038 * Writes are only relevant for old K7 processors,
4039 * all pre-dating SVM, but a recommended workaround from
4040 * AMD for these chips. It is possible to specify the
4041 * affected processor models on the command line, hence
4042 * the need to ignore the workaround.
4043 */
4044 break;
4045 #ifdef CONFIG_KVM_HYPERV
4046 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4047 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4048 case HV_X64_MSR_SYNDBG_OPTIONS:
4049 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4050 case HV_X64_MSR_CRASH_CTL:
4051 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4052 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4053 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4054 case HV_X64_MSR_TSC_EMULATION_STATUS:
4055 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4056 return kvm_hv_set_msr_common(vcpu, msr, data,
4057 msr_info->host_initiated);
4058 #endif
4059 case MSR_IA32_BBL_CR_CTL3:
4060 /* Drop writes to this legacy MSR -- see rdmsr
4061 * counterpart for further detail.
4062 */
4063 kvm_pr_unimpl_wrmsr(vcpu, msr, data);
4064 break;
4065 case MSR_AMD64_OSVW_ID_LENGTH:
4066 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4067 return 1;
4068 vcpu->arch.osvw.length = data;
4069 break;
4070 case MSR_AMD64_OSVW_STATUS:
4071 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4072 return 1;
4073 vcpu->arch.osvw.status = data;
4074 break;
4075 case MSR_PLATFORM_INFO:
4076 if (!msr_info->host_initiated ||
4077 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
4078 cpuid_fault_enabled(vcpu)))
4079 return 1;
4080 vcpu->arch.msr_platform_info = data;
4081 break;
4082 case MSR_MISC_FEATURES_ENABLES:
4083 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
4084 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
4085 !supports_cpuid_fault(vcpu)))
4086 return 1;
4087 vcpu->arch.msr_misc_features_enables = data;
4088 break;
4089 #ifdef CONFIG_X86_64
4090 case MSR_IA32_XFD:
4091 if (!msr_info->host_initiated &&
4092 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4093 return 1;
4094
4095 if (data & ~kvm_guest_supported_xfd(vcpu))
4096 return 1;
4097
4098 fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
4099 break;
4100 case MSR_IA32_XFD_ERR:
4101 if (!msr_info->host_initiated &&
4102 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4103 return 1;
4104
4105 if (data & ~kvm_guest_supported_xfd(vcpu))
4106 return 1;
4107
4108 vcpu->arch.guest_fpu.xfd_err = data;
4109 break;
4110 #endif
4111 default:
4112 if (kvm_pmu_is_valid_msr(vcpu, msr))
4113 return kvm_pmu_set_msr(vcpu, msr_info);
4114
4115 /*
4116 * Userspace is allowed to write '0' to MSRs that KVM reports
4117 * as to-be-saved, even if an MSRs isn't fully supported.
4118 */
4119 if (msr_info->host_initiated && !data &&
4120 kvm_is_msr_to_save(msr))
4121 break;
4122
4123 return KVM_MSR_RET_INVALID;
4124 }
4125 return 0;
4126 }
4127 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
4128
get_msr_mce(struct kvm_vcpu * vcpu,u32 msr,u64 * pdata,bool host)4129 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
4130 {
4131 u64 data;
4132 u64 mcg_cap = vcpu->arch.mcg_cap;
4133 unsigned bank_num = mcg_cap & 0xff;
4134 u32 offset, last_msr;
4135
4136 switch (msr) {
4137 case MSR_IA32_P5_MC_ADDR:
4138 case MSR_IA32_P5_MC_TYPE:
4139 data = 0;
4140 break;
4141 case MSR_IA32_MCG_CAP:
4142 data = vcpu->arch.mcg_cap;
4143 break;
4144 case MSR_IA32_MCG_CTL:
4145 if (!(mcg_cap & MCG_CTL_P) && !host)
4146 return 1;
4147 data = vcpu->arch.mcg_ctl;
4148 break;
4149 case MSR_IA32_MCG_STATUS:
4150 data = vcpu->arch.mcg_status;
4151 break;
4152 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4153 last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
4154 if (msr > last_msr)
4155 return 1;
4156
4157 if (!(mcg_cap & MCG_CMCI_P) && !host)
4158 return 1;
4159 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
4160 last_msr + 1 - MSR_IA32_MC0_CTL2);
4161 data = vcpu->arch.mci_ctl2_banks[offset];
4162 break;
4163 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4164 last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
4165 if (msr > last_msr)
4166 return 1;
4167
4168 offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
4169 last_msr + 1 - MSR_IA32_MC0_CTL);
4170 data = vcpu->arch.mce_banks[offset];
4171 break;
4172 default:
4173 return 1;
4174 }
4175 *pdata = data;
4176 return 0;
4177 }
4178
kvm_get_msr_common(struct kvm_vcpu * vcpu,struct msr_data * msr_info)4179 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4180 {
4181 switch (msr_info->index) {
4182 case MSR_IA32_PLATFORM_ID:
4183 case MSR_IA32_EBL_CR_POWERON:
4184 case MSR_IA32_LASTBRANCHFROMIP:
4185 case MSR_IA32_LASTBRANCHTOIP:
4186 case MSR_IA32_LASTINTFROMIP:
4187 case MSR_IA32_LASTINTTOIP:
4188 case MSR_AMD64_SYSCFG:
4189 case MSR_K8_TSEG_ADDR:
4190 case MSR_K8_TSEG_MASK:
4191 case MSR_VM_HSAVE_PA:
4192 case MSR_K8_INT_PENDING_MSG:
4193 case MSR_AMD64_NB_CFG:
4194 case MSR_FAM10H_MMIO_CONF_BASE:
4195 case MSR_AMD64_BU_CFG2:
4196 case MSR_IA32_PERF_CTL:
4197 case MSR_AMD64_DC_CFG:
4198 case MSR_AMD64_TW_CFG:
4199 case MSR_F15H_EX_CFG:
4200 /*
4201 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4202 * limit) MSRs. Just return 0, as we do not want to expose the host
4203 * data here. Do not conditionalize this on CPUID, as KVM does not do
4204 * so for existing CPU-specific MSRs.
4205 */
4206 case MSR_RAPL_POWER_UNIT:
4207 case MSR_PP0_ENERGY_STATUS: /* Power plane 0 (core) */
4208 case MSR_PP1_ENERGY_STATUS: /* Power plane 1 (graphics uncore) */
4209 case MSR_PKG_ENERGY_STATUS: /* Total package */
4210 case MSR_DRAM_ENERGY_STATUS: /* DRAM controller */
4211 msr_info->data = 0;
4212 break;
4213 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4214 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4215 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4216 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4217 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4218 return kvm_pmu_get_msr(vcpu, msr_info);
4219 msr_info->data = 0;
4220 break;
4221 case MSR_IA32_UCODE_REV:
4222 msr_info->data = vcpu->arch.microcode_version;
4223 break;
4224 case MSR_IA32_ARCH_CAPABILITIES:
4225 if (!msr_info->host_initiated &&
4226 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4227 return 1;
4228 msr_info->data = vcpu->arch.arch_capabilities;
4229 break;
4230 case MSR_IA32_PERF_CAPABILITIES:
4231 if (!msr_info->host_initiated &&
4232 !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4233 return 1;
4234 msr_info->data = vcpu->arch.perf_capabilities;
4235 break;
4236 case MSR_IA32_POWER_CTL:
4237 msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4238 break;
4239 case MSR_IA32_TSC: {
4240 /*
4241 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4242 * even when not intercepted. AMD manual doesn't explicitly
4243 * state this but appears to behave the same.
4244 *
4245 * On userspace reads and writes, however, we unconditionally
4246 * return L1's TSC value to ensure backwards-compatible
4247 * behavior for migration.
4248 */
4249 u64 offset, ratio;
4250
4251 if (msr_info->host_initiated) {
4252 offset = vcpu->arch.l1_tsc_offset;
4253 ratio = vcpu->arch.l1_tsc_scaling_ratio;
4254 } else {
4255 offset = vcpu->arch.tsc_offset;
4256 ratio = vcpu->arch.tsc_scaling_ratio;
4257 }
4258
4259 msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4260 break;
4261 }
4262 case MSR_IA32_CR_PAT:
4263 msr_info->data = vcpu->arch.pat;
4264 break;
4265 case MSR_MTRRcap:
4266 case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
4267 case MSR_MTRRdefType:
4268 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4269 case 0xcd: /* fsb frequency */
4270 msr_info->data = 3;
4271 break;
4272 /*
4273 * MSR_EBC_FREQUENCY_ID
4274 * Conservative value valid for even the basic CPU models.
4275 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4276 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4277 * and 266MHz for model 3, or 4. Set Core Clock
4278 * Frequency to System Bus Frequency Ratio to 1 (bits
4279 * 31:24) even though these are only valid for CPU
4280 * models > 2, however guests may end up dividing or
4281 * multiplying by zero otherwise.
4282 */
4283 case MSR_EBC_FREQUENCY_ID:
4284 msr_info->data = 1 << 24;
4285 break;
4286 case MSR_IA32_APICBASE:
4287 msr_info->data = kvm_get_apic_base(vcpu);
4288 break;
4289 case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4290 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4291 case MSR_IA32_TSC_DEADLINE:
4292 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4293 break;
4294 case MSR_IA32_TSC_ADJUST:
4295 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4296 break;
4297 case MSR_IA32_MISC_ENABLE:
4298 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4299 break;
4300 case MSR_IA32_SMBASE:
4301 if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4302 return 1;
4303 msr_info->data = vcpu->arch.smbase;
4304 break;
4305 case MSR_SMI_COUNT:
4306 msr_info->data = vcpu->arch.smi_count;
4307 break;
4308 case MSR_IA32_PERF_STATUS:
4309 /* TSC increment by tick */
4310 msr_info->data = 1000ULL;
4311 /* CPU multiplier */
4312 msr_info->data |= (((uint64_t)4ULL) << 40);
4313 break;
4314 case MSR_EFER:
4315 msr_info->data = vcpu->arch.efer;
4316 break;
4317 case MSR_KVM_WALL_CLOCK:
4318 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4319 return 1;
4320
4321 msr_info->data = vcpu->kvm->arch.wall_clock;
4322 break;
4323 case MSR_KVM_WALL_CLOCK_NEW:
4324 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4325 return 1;
4326
4327 msr_info->data = vcpu->kvm->arch.wall_clock;
4328 break;
4329 case MSR_KVM_SYSTEM_TIME:
4330 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4331 return 1;
4332
4333 msr_info->data = vcpu->arch.time;
4334 break;
4335 case MSR_KVM_SYSTEM_TIME_NEW:
4336 if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4337 return 1;
4338
4339 msr_info->data = vcpu->arch.time;
4340 break;
4341 case MSR_KVM_ASYNC_PF_EN:
4342 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4343 return 1;
4344
4345 msr_info->data = vcpu->arch.apf.msr_en_val;
4346 break;
4347 case MSR_KVM_ASYNC_PF_INT:
4348 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4349 return 1;
4350
4351 msr_info->data = vcpu->arch.apf.msr_int_val;
4352 break;
4353 case MSR_KVM_ASYNC_PF_ACK:
4354 if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4355 return 1;
4356
4357 msr_info->data = 0;
4358 break;
4359 case MSR_KVM_STEAL_TIME:
4360 if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4361 return 1;
4362
4363 msr_info->data = vcpu->arch.st.msr_val;
4364 break;
4365 case MSR_KVM_PV_EOI_EN:
4366 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4367 return 1;
4368
4369 msr_info->data = vcpu->arch.pv_eoi.msr_val;
4370 break;
4371 case MSR_KVM_POLL_CONTROL:
4372 if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4373 return 1;
4374
4375 msr_info->data = vcpu->arch.msr_kvm_poll_control;
4376 break;
4377 case MSR_IA32_P5_MC_ADDR:
4378 case MSR_IA32_P5_MC_TYPE:
4379 case MSR_IA32_MCG_CAP:
4380 case MSR_IA32_MCG_CTL:
4381 case MSR_IA32_MCG_STATUS:
4382 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4383 case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4384 return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4385 msr_info->host_initiated);
4386 case MSR_IA32_XSS:
4387 if (!msr_info->host_initiated &&
4388 !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4389 return 1;
4390 msr_info->data = vcpu->arch.ia32_xss;
4391 break;
4392 case MSR_K7_CLK_CTL:
4393 /*
4394 * Provide expected ramp-up count for K7. All other
4395 * are set to zero, indicating minimum divisors for
4396 * every field.
4397 *
4398 * This prevents guest kernels on AMD host with CPU
4399 * type 6, model 8 and higher from exploding due to
4400 * the rdmsr failing.
4401 */
4402 msr_info->data = 0x20000000;
4403 break;
4404 #ifdef CONFIG_KVM_HYPERV
4405 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4406 case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4407 case HV_X64_MSR_SYNDBG_OPTIONS:
4408 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4409 case HV_X64_MSR_CRASH_CTL:
4410 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4411 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4412 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4413 case HV_X64_MSR_TSC_EMULATION_STATUS:
4414 case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4415 return kvm_hv_get_msr_common(vcpu,
4416 msr_info->index, &msr_info->data,
4417 msr_info->host_initiated);
4418 #endif
4419 case MSR_IA32_BBL_CR_CTL3:
4420 /* This legacy MSR exists but isn't fully documented in current
4421 * silicon. It is however accessed by winxp in very narrow
4422 * scenarios where it sets bit #19, itself documented as
4423 * a "reserved" bit. Best effort attempt to source coherent
4424 * read data here should the balance of the register be
4425 * interpreted by the guest:
4426 *
4427 * L2 cache control register 3: 64GB range, 256KB size,
4428 * enabled, latency 0x1, configured
4429 */
4430 msr_info->data = 0xbe702111;
4431 break;
4432 case MSR_AMD64_OSVW_ID_LENGTH:
4433 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4434 return 1;
4435 msr_info->data = vcpu->arch.osvw.length;
4436 break;
4437 case MSR_AMD64_OSVW_STATUS:
4438 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4439 return 1;
4440 msr_info->data = vcpu->arch.osvw.status;
4441 break;
4442 case MSR_PLATFORM_INFO:
4443 if (!msr_info->host_initiated &&
4444 !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4445 return 1;
4446 msr_info->data = vcpu->arch.msr_platform_info;
4447 break;
4448 case MSR_MISC_FEATURES_ENABLES:
4449 msr_info->data = vcpu->arch.msr_misc_features_enables;
4450 break;
4451 case MSR_K7_HWCR:
4452 msr_info->data = vcpu->arch.msr_hwcr;
4453 break;
4454 #ifdef CONFIG_X86_64
4455 case MSR_IA32_XFD:
4456 if (!msr_info->host_initiated &&
4457 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4458 return 1;
4459
4460 msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4461 break;
4462 case MSR_IA32_XFD_ERR:
4463 if (!msr_info->host_initiated &&
4464 !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4465 return 1;
4466
4467 msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4468 break;
4469 #endif
4470 default:
4471 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4472 return kvm_pmu_get_msr(vcpu, msr_info);
4473
4474 /*
4475 * Userspace is allowed to read MSRs that KVM reports as
4476 * to-be-saved, even if an MSR isn't fully supported.
4477 */
4478 if (msr_info->host_initiated &&
4479 kvm_is_msr_to_save(msr_info->index)) {
4480 msr_info->data = 0;
4481 break;
4482 }
4483
4484 return KVM_MSR_RET_INVALID;
4485 }
4486 return 0;
4487 }
4488 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4489
4490 /*
4491 * Read or write a bunch of msrs. All parameters are kernel addresses.
4492 *
4493 * @return number of msrs set successfully.
4494 */
__msr_io(struct kvm_vcpu * vcpu,struct kvm_msrs * msrs,struct kvm_msr_entry * entries,int (* do_msr)(struct kvm_vcpu * vcpu,unsigned index,u64 * data))4495 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4496 struct kvm_msr_entry *entries,
4497 int (*do_msr)(struct kvm_vcpu *vcpu,
4498 unsigned index, u64 *data))
4499 {
4500 int i;
4501
4502 for (i = 0; i < msrs->nmsrs; ++i)
4503 if (do_msr(vcpu, entries[i].index, &entries[i].data))
4504 break;
4505
4506 return i;
4507 }
4508
4509 /*
4510 * Read or write a bunch of msrs. Parameters are user addresses.
4511 *
4512 * @return number of msrs set successfully.
4513 */
msr_io(struct kvm_vcpu * vcpu,struct kvm_msrs __user * user_msrs,int (* do_msr)(struct kvm_vcpu * vcpu,unsigned index,u64 * data),int writeback)4514 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4515 int (*do_msr)(struct kvm_vcpu *vcpu,
4516 unsigned index, u64 *data),
4517 int writeback)
4518 {
4519 struct kvm_msrs msrs;
4520 struct kvm_msr_entry *entries;
4521 unsigned size;
4522 int r;
4523
4524 r = -EFAULT;
4525 if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4526 goto out;
4527
4528 r = -E2BIG;
4529 if (msrs.nmsrs >= MAX_IO_MSRS)
4530 goto out;
4531
4532 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4533 entries = memdup_user(user_msrs->entries, size);
4534 if (IS_ERR(entries)) {
4535 r = PTR_ERR(entries);
4536 goto out;
4537 }
4538
4539 r = __msr_io(vcpu, &msrs, entries, do_msr);
4540
4541 if (writeback && copy_to_user(user_msrs->entries, entries, size))
4542 r = -EFAULT;
4543
4544 kfree(entries);
4545 out:
4546 return r;
4547 }
4548
kvm_can_mwait_in_guest(void)4549 static inline bool kvm_can_mwait_in_guest(void)
4550 {
4551 return boot_cpu_has(X86_FEATURE_MWAIT) &&
4552 !boot_cpu_has_bug(X86_BUG_MONITOR) &&
4553 boot_cpu_has(X86_FEATURE_ARAT);
4554 }
4555
4556 #ifdef CONFIG_KVM_HYPERV
kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu * vcpu,struct kvm_cpuid2 __user * cpuid_arg)4557 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4558 struct kvm_cpuid2 __user *cpuid_arg)
4559 {
4560 struct kvm_cpuid2 cpuid;
4561 int r;
4562
4563 r = -EFAULT;
4564 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4565 return r;
4566
4567 r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4568 if (r)
4569 return r;
4570
4571 r = -EFAULT;
4572 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4573 return r;
4574
4575 return 0;
4576 }
4577 #endif
4578
kvm_is_vm_type_supported(unsigned long type)4579 static bool kvm_is_vm_type_supported(unsigned long type)
4580 {
4581 return type == KVM_X86_DEFAULT_VM ||
4582 (type == KVM_X86_SW_PROTECTED_VM &&
4583 IS_ENABLED(CONFIG_KVM_SW_PROTECTED_VM) && tdp_mmu_enabled);
4584 }
4585
kvm_vm_ioctl_check_extension(struct kvm * kvm,long ext)4586 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4587 {
4588 int r = 0;
4589
4590 switch (ext) {
4591 case KVM_CAP_IRQCHIP:
4592 case KVM_CAP_HLT:
4593 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4594 case KVM_CAP_SET_TSS_ADDR:
4595 case KVM_CAP_EXT_CPUID:
4596 case KVM_CAP_EXT_EMUL_CPUID:
4597 case KVM_CAP_CLOCKSOURCE:
4598 case KVM_CAP_PIT:
4599 case KVM_CAP_NOP_IO_DELAY:
4600 case KVM_CAP_MP_STATE:
4601 case KVM_CAP_SYNC_MMU:
4602 case KVM_CAP_USER_NMI:
4603 case KVM_CAP_REINJECT_CONTROL:
4604 case KVM_CAP_IRQ_INJECT_STATUS:
4605 case KVM_CAP_IOEVENTFD:
4606 case KVM_CAP_IOEVENTFD_NO_LENGTH:
4607 case KVM_CAP_PIT2:
4608 case KVM_CAP_PIT_STATE2:
4609 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4610 case KVM_CAP_VCPU_EVENTS:
4611 #ifdef CONFIG_KVM_HYPERV
4612 case KVM_CAP_HYPERV:
4613 case KVM_CAP_HYPERV_VAPIC:
4614 case KVM_CAP_HYPERV_SPIN:
4615 case KVM_CAP_HYPERV_TIME:
4616 case KVM_CAP_HYPERV_SYNIC:
4617 case KVM_CAP_HYPERV_SYNIC2:
4618 case KVM_CAP_HYPERV_VP_INDEX:
4619 case KVM_CAP_HYPERV_EVENTFD:
4620 case KVM_CAP_HYPERV_TLBFLUSH:
4621 case KVM_CAP_HYPERV_SEND_IPI:
4622 case KVM_CAP_HYPERV_CPUID:
4623 case KVM_CAP_HYPERV_ENFORCE_CPUID:
4624 case KVM_CAP_SYS_HYPERV_CPUID:
4625 #endif
4626 case KVM_CAP_PCI_SEGMENT:
4627 case KVM_CAP_DEBUGREGS:
4628 case KVM_CAP_X86_ROBUST_SINGLESTEP:
4629 case KVM_CAP_XSAVE:
4630 case KVM_CAP_ASYNC_PF:
4631 case KVM_CAP_ASYNC_PF_INT:
4632 case KVM_CAP_GET_TSC_KHZ:
4633 case KVM_CAP_KVMCLOCK_CTRL:
4634 case KVM_CAP_READONLY_MEM:
4635 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4636 case KVM_CAP_TSC_DEADLINE_TIMER:
4637 case KVM_CAP_DISABLE_QUIRKS:
4638 case KVM_CAP_SET_BOOT_CPU_ID:
4639 case KVM_CAP_SPLIT_IRQCHIP:
4640 case KVM_CAP_IMMEDIATE_EXIT:
4641 case KVM_CAP_PMU_EVENT_FILTER:
4642 case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4643 case KVM_CAP_GET_MSR_FEATURES:
4644 case KVM_CAP_MSR_PLATFORM_INFO:
4645 case KVM_CAP_EXCEPTION_PAYLOAD:
4646 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4647 case KVM_CAP_SET_GUEST_DEBUG:
4648 case KVM_CAP_LAST_CPU:
4649 case KVM_CAP_X86_USER_SPACE_MSR:
4650 case KVM_CAP_X86_MSR_FILTER:
4651 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4652 #ifdef CONFIG_X86_SGX_KVM
4653 case KVM_CAP_SGX_ATTRIBUTE:
4654 #endif
4655 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4656 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4657 case KVM_CAP_SREGS2:
4658 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4659 case KVM_CAP_VCPU_ATTRIBUTES:
4660 case KVM_CAP_SYS_ATTRIBUTES:
4661 case KVM_CAP_VAPIC:
4662 case KVM_CAP_ENABLE_CAP:
4663 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4664 case KVM_CAP_IRQFD_RESAMPLE:
4665 case KVM_CAP_MEMORY_FAULT_INFO:
4666 r = 1;
4667 break;
4668 case KVM_CAP_EXIT_HYPERCALL:
4669 r = KVM_EXIT_HYPERCALL_VALID_MASK;
4670 break;
4671 case KVM_CAP_SET_GUEST_DEBUG2:
4672 return KVM_GUESTDBG_VALID_MASK;
4673 #ifdef CONFIG_KVM_XEN
4674 case KVM_CAP_XEN_HVM:
4675 r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4676 KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4677 KVM_XEN_HVM_CONFIG_SHARED_INFO |
4678 KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4679 KVM_XEN_HVM_CONFIG_EVTCHN_SEND |
4680 KVM_XEN_HVM_CONFIG_PVCLOCK_TSC_UNSTABLE;
4681 if (sched_info_on())
4682 r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4683 KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4684 break;
4685 #endif
4686 case KVM_CAP_SYNC_REGS:
4687 r = KVM_SYNC_X86_VALID_FIELDS;
4688 break;
4689 case KVM_CAP_ADJUST_CLOCK:
4690 r = KVM_CLOCK_VALID_FLAGS;
4691 break;
4692 case KVM_CAP_X86_DISABLE_EXITS:
4693 r = KVM_X86_DISABLE_EXITS_PAUSE;
4694
4695 if (!mitigate_smt_rsb) {
4696 r |= KVM_X86_DISABLE_EXITS_HLT |
4697 KVM_X86_DISABLE_EXITS_CSTATE;
4698
4699 if (kvm_can_mwait_in_guest())
4700 r |= KVM_X86_DISABLE_EXITS_MWAIT;
4701 }
4702 break;
4703 case KVM_CAP_X86_SMM:
4704 if (!IS_ENABLED(CONFIG_KVM_SMM))
4705 break;
4706
4707 /* SMBASE is usually relocated above 1M on modern chipsets,
4708 * and SMM handlers might indeed rely on 4G segment limits,
4709 * so do not report SMM to be available if real mode is
4710 * emulated via vm86 mode. Still, do not go to great lengths
4711 * to avoid userspace's usage of the feature, because it is a
4712 * fringe case that is not enabled except via specific settings
4713 * of the module parameters.
4714 */
4715 r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4716 break;
4717 case KVM_CAP_NR_VCPUS:
4718 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4719 break;
4720 case KVM_CAP_MAX_VCPUS:
4721 r = KVM_MAX_VCPUS;
4722 break;
4723 case KVM_CAP_MAX_VCPU_ID:
4724 r = KVM_MAX_VCPU_IDS;
4725 break;
4726 case KVM_CAP_PV_MMU: /* obsolete */
4727 r = 0;
4728 break;
4729 case KVM_CAP_MCE:
4730 r = KVM_MAX_MCE_BANKS;
4731 break;
4732 case KVM_CAP_XCRS:
4733 r = boot_cpu_has(X86_FEATURE_XSAVE);
4734 break;
4735 case KVM_CAP_TSC_CONTROL:
4736 case KVM_CAP_VM_TSC_CONTROL:
4737 r = kvm_caps.has_tsc_control;
4738 break;
4739 case KVM_CAP_X2APIC_API:
4740 r = KVM_X2APIC_API_VALID_FLAGS;
4741 break;
4742 case KVM_CAP_NESTED_STATE:
4743 r = kvm_x86_ops.nested_ops->get_state ?
4744 kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4745 break;
4746 #ifdef CONFIG_KVM_HYPERV
4747 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4748 r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4749 break;
4750 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4751 r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4752 break;
4753 #endif
4754 case KVM_CAP_SMALLER_MAXPHYADDR:
4755 r = (int) allow_smaller_maxphyaddr;
4756 break;
4757 case KVM_CAP_STEAL_TIME:
4758 r = sched_info_on();
4759 break;
4760 case KVM_CAP_X86_BUS_LOCK_EXIT:
4761 if (kvm_caps.has_bus_lock_exit)
4762 r = KVM_BUS_LOCK_DETECTION_OFF |
4763 KVM_BUS_LOCK_DETECTION_EXIT;
4764 else
4765 r = 0;
4766 break;
4767 case KVM_CAP_XSAVE2: {
4768 r = xstate_required_size(kvm_get_filtered_xcr0(), false);
4769 if (r < sizeof(struct kvm_xsave))
4770 r = sizeof(struct kvm_xsave);
4771 break;
4772 }
4773 case KVM_CAP_PMU_CAPABILITY:
4774 r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4775 break;
4776 case KVM_CAP_DISABLE_QUIRKS2:
4777 r = KVM_X86_VALID_QUIRKS;
4778 break;
4779 case KVM_CAP_X86_NOTIFY_VMEXIT:
4780 r = kvm_caps.has_notify_vmexit;
4781 break;
4782 case KVM_CAP_VM_TYPES:
4783 r = BIT(KVM_X86_DEFAULT_VM);
4784 if (kvm_is_vm_type_supported(KVM_X86_SW_PROTECTED_VM))
4785 r |= BIT(KVM_X86_SW_PROTECTED_VM);
4786 break;
4787 default:
4788 break;
4789 }
4790 return r;
4791 }
4792
kvm_get_attr_addr(struct kvm_device_attr * attr)4793 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4794 {
4795 void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4796
4797 if ((u64)(unsigned long)uaddr != attr->addr)
4798 return ERR_PTR_USR(-EFAULT);
4799 return uaddr;
4800 }
4801
kvm_x86_dev_get_attr(struct kvm_device_attr * attr)4802 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4803 {
4804 u64 __user *uaddr = kvm_get_attr_addr(attr);
4805
4806 if (attr->group)
4807 return -ENXIO;
4808
4809 if (IS_ERR(uaddr))
4810 return PTR_ERR(uaddr);
4811
4812 switch (attr->attr) {
4813 case KVM_X86_XCOMP_GUEST_SUPP:
4814 if (put_user(kvm_caps.supported_xcr0, uaddr))
4815 return -EFAULT;
4816 return 0;
4817 default:
4818 return -ENXIO;
4819 }
4820 }
4821
kvm_x86_dev_has_attr(struct kvm_device_attr * attr)4822 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4823 {
4824 if (attr->group)
4825 return -ENXIO;
4826
4827 switch (attr->attr) {
4828 case KVM_X86_XCOMP_GUEST_SUPP:
4829 return 0;
4830 default:
4831 return -ENXIO;
4832 }
4833 }
4834
kvm_arch_dev_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)4835 long kvm_arch_dev_ioctl(struct file *filp,
4836 unsigned int ioctl, unsigned long arg)
4837 {
4838 void __user *argp = (void __user *)arg;
4839 long r;
4840
4841 switch (ioctl) {
4842 case KVM_GET_MSR_INDEX_LIST: {
4843 struct kvm_msr_list __user *user_msr_list = argp;
4844 struct kvm_msr_list msr_list;
4845 unsigned n;
4846
4847 r = -EFAULT;
4848 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4849 goto out;
4850 n = msr_list.nmsrs;
4851 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4852 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4853 goto out;
4854 r = -E2BIG;
4855 if (n < msr_list.nmsrs)
4856 goto out;
4857 r = -EFAULT;
4858 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4859 num_msrs_to_save * sizeof(u32)))
4860 goto out;
4861 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4862 &emulated_msrs,
4863 num_emulated_msrs * sizeof(u32)))
4864 goto out;
4865 r = 0;
4866 break;
4867 }
4868 case KVM_GET_SUPPORTED_CPUID:
4869 case KVM_GET_EMULATED_CPUID: {
4870 struct kvm_cpuid2 __user *cpuid_arg = argp;
4871 struct kvm_cpuid2 cpuid;
4872
4873 r = -EFAULT;
4874 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4875 goto out;
4876
4877 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4878 ioctl);
4879 if (r)
4880 goto out;
4881
4882 r = -EFAULT;
4883 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4884 goto out;
4885 r = 0;
4886 break;
4887 }
4888 case KVM_X86_GET_MCE_CAP_SUPPORTED:
4889 r = -EFAULT;
4890 if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4891 sizeof(kvm_caps.supported_mce_cap)))
4892 goto out;
4893 r = 0;
4894 break;
4895 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4896 struct kvm_msr_list __user *user_msr_list = argp;
4897 struct kvm_msr_list msr_list;
4898 unsigned int n;
4899
4900 r = -EFAULT;
4901 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4902 goto out;
4903 n = msr_list.nmsrs;
4904 msr_list.nmsrs = num_msr_based_features;
4905 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4906 goto out;
4907 r = -E2BIG;
4908 if (n < msr_list.nmsrs)
4909 goto out;
4910 r = -EFAULT;
4911 if (copy_to_user(user_msr_list->indices, &msr_based_features,
4912 num_msr_based_features * sizeof(u32)))
4913 goto out;
4914 r = 0;
4915 break;
4916 }
4917 case KVM_GET_MSRS:
4918 r = msr_io(NULL, argp, do_get_msr_feature, 1);
4919 break;
4920 #ifdef CONFIG_KVM_HYPERV
4921 case KVM_GET_SUPPORTED_HV_CPUID:
4922 r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4923 break;
4924 #endif
4925 case KVM_GET_DEVICE_ATTR: {
4926 struct kvm_device_attr attr;
4927 r = -EFAULT;
4928 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4929 break;
4930 r = kvm_x86_dev_get_attr(&attr);
4931 break;
4932 }
4933 case KVM_HAS_DEVICE_ATTR: {
4934 struct kvm_device_attr attr;
4935 r = -EFAULT;
4936 if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4937 break;
4938 r = kvm_x86_dev_has_attr(&attr);
4939 break;
4940 }
4941 default:
4942 r = -EINVAL;
4943 break;
4944 }
4945 out:
4946 return r;
4947 }
4948
wbinvd_ipi(void * garbage)4949 static void wbinvd_ipi(void *garbage)
4950 {
4951 wbinvd();
4952 }
4953
need_emulate_wbinvd(struct kvm_vcpu * vcpu)4954 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4955 {
4956 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4957 }
4958
kvm_arch_vcpu_load(struct kvm_vcpu * vcpu,int cpu)4959 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4960 {
4961 /* Address WBINVD may be executed by guest */
4962 if (need_emulate_wbinvd(vcpu)) {
4963 if (static_call(kvm_x86_has_wbinvd_exit)())
4964 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4965 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4966 smp_call_function_single(vcpu->cpu,
4967 wbinvd_ipi, NULL, 1);
4968 }
4969
4970 static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4971
4972 /* Save host pkru register if supported */
4973 vcpu->arch.host_pkru = read_pkru();
4974
4975 /* Apply any externally detected TSC adjustments (due to suspend) */
4976 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4977 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4978 vcpu->arch.tsc_offset_adjustment = 0;
4979 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4980 }
4981
4982 if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4983 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4984 rdtsc() - vcpu->arch.last_host_tsc;
4985 if (tsc_delta < 0)
4986 mark_tsc_unstable("KVM discovered backwards TSC");
4987
4988 if (kvm_check_tsc_unstable()) {
4989 u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4990 vcpu->arch.last_guest_tsc);
4991 kvm_vcpu_write_tsc_offset(vcpu, offset);
4992 vcpu->arch.tsc_catchup = 1;
4993 }
4994
4995 if (kvm_lapic_hv_timer_in_use(vcpu))
4996 kvm_lapic_restart_hv_timer(vcpu);
4997
4998 /*
4999 * On a host with synchronized TSC, there is no need to update
5000 * kvmclock on vcpu->cpu migration
5001 */
5002 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
5003 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
5004 if (vcpu->cpu != cpu)
5005 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
5006 vcpu->cpu = cpu;
5007 }
5008
5009 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
5010 }
5011
kvm_steal_time_set_preempted(struct kvm_vcpu * vcpu)5012 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
5013 {
5014 struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
5015 struct kvm_steal_time __user *st;
5016 struct kvm_memslots *slots;
5017 static const u8 preempted = KVM_VCPU_PREEMPTED;
5018 gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
5019
5020 /*
5021 * The vCPU can be marked preempted if and only if the VM-Exit was on
5022 * an instruction boundary and will not trigger guest emulation of any
5023 * kind (see vcpu_run). Vendor specific code controls (conservatively)
5024 * when this is true, for example allowing the vCPU to be marked
5025 * preempted if and only if the VM-Exit was due to a host interrupt.
5026 */
5027 if (!vcpu->arch.at_instruction_boundary) {
5028 vcpu->stat.preemption_other++;
5029 return;
5030 }
5031
5032 vcpu->stat.preemption_reported++;
5033 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
5034 return;
5035
5036 if (vcpu->arch.st.preempted)
5037 return;
5038
5039 /* This happens on process exit */
5040 if (unlikely(current->mm != vcpu->kvm->mm))
5041 return;
5042
5043 slots = kvm_memslots(vcpu->kvm);
5044
5045 if (unlikely(slots->generation != ghc->generation ||
5046 gpa != ghc->gpa ||
5047 kvm_is_error_hva(ghc->hva) || !ghc->memslot))
5048 return;
5049
5050 st = (struct kvm_steal_time __user *)ghc->hva;
5051 BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
5052
5053 if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
5054 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
5055
5056 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
5057 }
5058
kvm_arch_vcpu_put(struct kvm_vcpu * vcpu)5059 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
5060 {
5061 int idx;
5062
5063 if (vcpu->preempted) {
5064 if (!vcpu->arch.guest_state_protected)
5065 vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
5066
5067 /*
5068 * Take the srcu lock as memslots will be accessed to check the gfn
5069 * cache generation against the memslots generation.
5070 */
5071 idx = srcu_read_lock(&vcpu->kvm->srcu);
5072 if (kvm_xen_msr_enabled(vcpu->kvm))
5073 kvm_xen_runstate_set_preempted(vcpu);
5074 else
5075 kvm_steal_time_set_preempted(vcpu);
5076 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5077 }
5078
5079 static_call(kvm_x86_vcpu_put)(vcpu);
5080 vcpu->arch.last_host_tsc = rdtsc();
5081 }
5082
kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu * vcpu,struct kvm_lapic_state * s)5083 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
5084 struct kvm_lapic_state *s)
5085 {
5086 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
5087
5088 return kvm_apic_get_state(vcpu, s);
5089 }
5090
kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu * vcpu,struct kvm_lapic_state * s)5091 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
5092 struct kvm_lapic_state *s)
5093 {
5094 int r;
5095
5096 r = kvm_apic_set_state(vcpu, s);
5097 if (r)
5098 return r;
5099 update_cr8_intercept(vcpu);
5100
5101 return 0;
5102 }
5103
kvm_cpu_accept_dm_intr(struct kvm_vcpu * vcpu)5104 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
5105 {
5106 /*
5107 * We can accept userspace's request for interrupt injection
5108 * as long as we have a place to store the interrupt number.
5109 * The actual injection will happen when the CPU is able to
5110 * deliver the interrupt.
5111 */
5112 if (kvm_cpu_has_extint(vcpu))
5113 return false;
5114
5115 /* Acknowledging ExtINT does not happen if LINT0 is masked. */
5116 return (!lapic_in_kernel(vcpu) ||
5117 kvm_apic_accept_pic_intr(vcpu));
5118 }
5119
kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu * vcpu)5120 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
5121 {
5122 /*
5123 * Do not cause an interrupt window exit if an exception
5124 * is pending or an event needs reinjection; userspace
5125 * might want to inject the interrupt manually using KVM_SET_REGS
5126 * or KVM_SET_SREGS. For that to work, we must be at an
5127 * instruction boundary and with no events half-injected.
5128 */
5129 return (kvm_arch_interrupt_allowed(vcpu) &&
5130 kvm_cpu_accept_dm_intr(vcpu) &&
5131 !kvm_event_needs_reinjection(vcpu) &&
5132 !kvm_is_exception_pending(vcpu));
5133 }
5134
kvm_vcpu_ioctl_interrupt(struct kvm_vcpu * vcpu,struct kvm_interrupt * irq)5135 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
5136 struct kvm_interrupt *irq)
5137 {
5138 if (irq->irq >= KVM_NR_INTERRUPTS)
5139 return -EINVAL;
5140
5141 if (!irqchip_in_kernel(vcpu->kvm)) {
5142 kvm_queue_interrupt(vcpu, irq->irq, false);
5143 kvm_make_request(KVM_REQ_EVENT, vcpu);
5144 return 0;
5145 }
5146
5147 /*
5148 * With in-kernel LAPIC, we only use this to inject EXTINT, so
5149 * fail for in-kernel 8259.
5150 */
5151 if (pic_in_kernel(vcpu->kvm))
5152 return -ENXIO;
5153
5154 if (vcpu->arch.pending_external_vector != -1)
5155 return -EEXIST;
5156
5157 vcpu->arch.pending_external_vector = irq->irq;
5158 kvm_make_request(KVM_REQ_EVENT, vcpu);
5159 return 0;
5160 }
5161
kvm_vcpu_ioctl_nmi(struct kvm_vcpu * vcpu)5162 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
5163 {
5164 kvm_inject_nmi(vcpu);
5165
5166 return 0;
5167 }
5168
vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu * vcpu,struct kvm_tpr_access_ctl * tac)5169 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
5170 struct kvm_tpr_access_ctl *tac)
5171 {
5172 if (tac->flags)
5173 return -EINVAL;
5174 vcpu->arch.tpr_access_reporting = !!tac->enabled;
5175 return 0;
5176 }
5177
kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu * vcpu,u64 mcg_cap)5178 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
5179 u64 mcg_cap)
5180 {
5181 int r;
5182 unsigned bank_num = mcg_cap & 0xff, bank;
5183
5184 r = -EINVAL;
5185 if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
5186 goto out;
5187 if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
5188 goto out;
5189 r = 0;
5190 vcpu->arch.mcg_cap = mcg_cap;
5191 /* Init IA32_MCG_CTL to all 1s */
5192 if (mcg_cap & MCG_CTL_P)
5193 vcpu->arch.mcg_ctl = ~(u64)0;
5194 /* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
5195 for (bank = 0; bank < bank_num; bank++) {
5196 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5197 if (mcg_cap & MCG_CMCI_P)
5198 vcpu->arch.mci_ctl2_banks[bank] = 0;
5199 }
5200
5201 kvm_apic_after_set_mcg_cap(vcpu);
5202
5203 static_call(kvm_x86_setup_mce)(vcpu);
5204 out:
5205 return r;
5206 }
5207
5208 /*
5209 * Validate this is an UCNA (uncorrectable no action) error by checking the
5210 * MCG_STATUS and MCi_STATUS registers:
5211 * - none of the bits for Machine Check Exceptions are set
5212 * - both the VAL (valid) and UC (uncorrectable) bits are set
5213 * MCI_STATUS_PCC - Processor Context Corrupted
5214 * MCI_STATUS_S - Signaled as a Machine Check Exception
5215 * MCI_STATUS_AR - Software recoverable Action Required
5216 */
is_ucna(struct kvm_x86_mce * mce)5217 static bool is_ucna(struct kvm_x86_mce *mce)
5218 {
5219 return !mce->mcg_status &&
5220 !(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5221 (mce->status & MCI_STATUS_VAL) &&
5222 (mce->status & MCI_STATUS_UC);
5223 }
5224
kvm_vcpu_x86_set_ucna(struct kvm_vcpu * vcpu,struct kvm_x86_mce * mce,u64 * banks)5225 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5226 {
5227 u64 mcg_cap = vcpu->arch.mcg_cap;
5228
5229 banks[1] = mce->status;
5230 banks[2] = mce->addr;
5231 banks[3] = mce->misc;
5232 vcpu->arch.mcg_status = mce->mcg_status;
5233
5234 if (!(mcg_cap & MCG_CMCI_P) ||
5235 !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5236 return 0;
5237
5238 if (lapic_in_kernel(vcpu))
5239 kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5240
5241 return 0;
5242 }
5243
kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu * vcpu,struct kvm_x86_mce * mce)5244 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5245 struct kvm_x86_mce *mce)
5246 {
5247 u64 mcg_cap = vcpu->arch.mcg_cap;
5248 unsigned bank_num = mcg_cap & 0xff;
5249 u64 *banks = vcpu->arch.mce_banks;
5250
5251 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5252 return -EINVAL;
5253
5254 banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5255
5256 if (is_ucna(mce))
5257 return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5258
5259 /*
5260 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5261 * reporting is disabled
5262 */
5263 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5264 vcpu->arch.mcg_ctl != ~(u64)0)
5265 return 0;
5266 /*
5267 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5268 * reporting is disabled for the bank
5269 */
5270 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5271 return 0;
5272 if (mce->status & MCI_STATUS_UC) {
5273 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5274 !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5275 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5276 return 0;
5277 }
5278 if (banks[1] & MCI_STATUS_VAL)
5279 mce->status |= MCI_STATUS_OVER;
5280 banks[2] = mce->addr;
5281 banks[3] = mce->misc;
5282 vcpu->arch.mcg_status = mce->mcg_status;
5283 banks[1] = mce->status;
5284 kvm_queue_exception(vcpu, MC_VECTOR);
5285 } else if (!(banks[1] & MCI_STATUS_VAL)
5286 || !(banks[1] & MCI_STATUS_UC)) {
5287 if (banks[1] & MCI_STATUS_VAL)
5288 mce->status |= MCI_STATUS_OVER;
5289 banks[2] = mce->addr;
5290 banks[3] = mce->misc;
5291 banks[1] = mce->status;
5292 } else
5293 banks[1] |= MCI_STATUS_OVER;
5294 return 0;
5295 }
5296
kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu * vcpu,struct kvm_vcpu_events * events)5297 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5298 struct kvm_vcpu_events *events)
5299 {
5300 struct kvm_queued_exception *ex;
5301
5302 process_nmi(vcpu);
5303
5304 #ifdef CONFIG_KVM_SMM
5305 if (kvm_check_request(KVM_REQ_SMI, vcpu))
5306 process_smi(vcpu);
5307 #endif
5308
5309 /*
5310 * KVM's ABI only allows for one exception to be migrated. Luckily,
5311 * the only time there can be two queued exceptions is if there's a
5312 * non-exiting _injected_ exception, and a pending exiting exception.
5313 * In that case, ignore the VM-Exiting exception as it's an extension
5314 * of the injected exception.
5315 */
5316 if (vcpu->arch.exception_vmexit.pending &&
5317 !vcpu->arch.exception.pending &&
5318 !vcpu->arch.exception.injected)
5319 ex = &vcpu->arch.exception_vmexit;
5320 else
5321 ex = &vcpu->arch.exception;
5322
5323 /*
5324 * In guest mode, payload delivery should be deferred if the exception
5325 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5326 * intercepts #PF, ditto for DR6 and #DBs. If the per-VM capability,
5327 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5328 * propagate the payload and so it cannot be safely deferred. Deliver
5329 * the payload if the capability hasn't been requested.
5330 */
5331 if (!vcpu->kvm->arch.exception_payload_enabled &&
5332 ex->pending && ex->has_payload)
5333 kvm_deliver_exception_payload(vcpu, ex);
5334
5335 memset(events, 0, sizeof(*events));
5336
5337 /*
5338 * The API doesn't provide the instruction length for software
5339 * exceptions, so don't report them. As long as the guest RIP
5340 * isn't advanced, we should expect to encounter the exception
5341 * again.
5342 */
5343 if (!kvm_exception_is_soft(ex->vector)) {
5344 events->exception.injected = ex->injected;
5345 events->exception.pending = ex->pending;
5346 /*
5347 * For ABI compatibility, deliberately conflate
5348 * pending and injected exceptions when
5349 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5350 */
5351 if (!vcpu->kvm->arch.exception_payload_enabled)
5352 events->exception.injected |= ex->pending;
5353 }
5354 events->exception.nr = ex->vector;
5355 events->exception.has_error_code = ex->has_error_code;
5356 events->exception.error_code = ex->error_code;
5357 events->exception_has_payload = ex->has_payload;
5358 events->exception_payload = ex->payload;
5359
5360 events->interrupt.injected =
5361 vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5362 events->interrupt.nr = vcpu->arch.interrupt.nr;
5363 events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5364
5365 events->nmi.injected = vcpu->arch.nmi_injected;
5366 events->nmi.pending = kvm_get_nr_pending_nmis(vcpu);
5367 events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5368
5369 /* events->sipi_vector is never valid when reporting to user space */
5370
5371 #ifdef CONFIG_KVM_SMM
5372 events->smi.smm = is_smm(vcpu);
5373 events->smi.pending = vcpu->arch.smi_pending;
5374 events->smi.smm_inside_nmi =
5375 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5376 #endif
5377 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5378
5379 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5380 | KVM_VCPUEVENT_VALID_SHADOW
5381 | KVM_VCPUEVENT_VALID_SMM);
5382 if (vcpu->kvm->arch.exception_payload_enabled)
5383 events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5384 if (vcpu->kvm->arch.triple_fault_event) {
5385 events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5386 events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5387 }
5388 }
5389
kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu * vcpu,struct kvm_vcpu_events * events)5390 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5391 struct kvm_vcpu_events *events)
5392 {
5393 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5394 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5395 | KVM_VCPUEVENT_VALID_SHADOW
5396 | KVM_VCPUEVENT_VALID_SMM
5397 | KVM_VCPUEVENT_VALID_PAYLOAD
5398 | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5399 return -EINVAL;
5400
5401 if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5402 if (!vcpu->kvm->arch.exception_payload_enabled)
5403 return -EINVAL;
5404 if (events->exception.pending)
5405 events->exception.injected = 0;
5406 else
5407 events->exception_has_payload = 0;
5408 } else {
5409 events->exception.pending = 0;
5410 events->exception_has_payload = 0;
5411 }
5412
5413 if ((events->exception.injected || events->exception.pending) &&
5414 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5415 return -EINVAL;
5416
5417 /* INITs are latched while in SMM */
5418 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5419 (events->smi.smm || events->smi.pending) &&
5420 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5421 return -EINVAL;
5422
5423 process_nmi(vcpu);
5424
5425 /*
5426 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5427 * morph the exception to a VM-Exit if appropriate. Do this only for
5428 * pending exceptions, already-injected exceptions are not subject to
5429 * intercpetion. Note, userspace that conflates pending and injected
5430 * is hosed, and will incorrectly convert an injected exception into a
5431 * pending exception, which in turn may cause a spurious VM-Exit.
5432 */
5433 vcpu->arch.exception_from_userspace = events->exception.pending;
5434
5435 vcpu->arch.exception_vmexit.pending = false;
5436
5437 vcpu->arch.exception.injected = events->exception.injected;
5438 vcpu->arch.exception.pending = events->exception.pending;
5439 vcpu->arch.exception.vector = events->exception.nr;
5440 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5441 vcpu->arch.exception.error_code = events->exception.error_code;
5442 vcpu->arch.exception.has_payload = events->exception_has_payload;
5443 vcpu->arch.exception.payload = events->exception_payload;
5444
5445 vcpu->arch.interrupt.injected = events->interrupt.injected;
5446 vcpu->arch.interrupt.nr = events->interrupt.nr;
5447 vcpu->arch.interrupt.soft = events->interrupt.soft;
5448 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5449 static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5450 events->interrupt.shadow);
5451
5452 vcpu->arch.nmi_injected = events->nmi.injected;
5453 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) {
5454 vcpu->arch.nmi_pending = 0;
5455 atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending);
5456 if (events->nmi.pending)
5457 kvm_make_request(KVM_REQ_NMI, vcpu);
5458 }
5459 static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5460
5461 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5462 lapic_in_kernel(vcpu))
5463 vcpu->arch.apic->sipi_vector = events->sipi_vector;
5464
5465 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5466 #ifdef CONFIG_KVM_SMM
5467 if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5468 kvm_leave_nested(vcpu);
5469 kvm_smm_changed(vcpu, events->smi.smm);
5470 }
5471
5472 vcpu->arch.smi_pending = events->smi.pending;
5473
5474 if (events->smi.smm) {
5475 if (events->smi.smm_inside_nmi)
5476 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5477 else
5478 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5479 }
5480
5481 #else
5482 if (events->smi.smm || events->smi.pending ||
5483 events->smi.smm_inside_nmi)
5484 return -EINVAL;
5485 #endif
5486
5487 if (lapic_in_kernel(vcpu)) {
5488 if (events->smi.latched_init)
5489 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5490 else
5491 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5492 }
5493 }
5494
5495 if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5496 if (!vcpu->kvm->arch.triple_fault_event)
5497 return -EINVAL;
5498 if (events->triple_fault.pending)
5499 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5500 else
5501 kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5502 }
5503
5504 kvm_make_request(KVM_REQ_EVENT, vcpu);
5505
5506 return 0;
5507 }
5508
kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu * vcpu,struct kvm_debugregs * dbgregs)5509 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5510 struct kvm_debugregs *dbgregs)
5511 {
5512 unsigned long val;
5513
5514 memset(dbgregs, 0, sizeof(*dbgregs));
5515 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5516 kvm_get_dr(vcpu, 6, &val);
5517 dbgregs->dr6 = val;
5518 dbgregs->dr7 = vcpu->arch.dr7;
5519 }
5520
kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu * vcpu,struct kvm_debugregs * dbgregs)5521 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5522 struct kvm_debugregs *dbgregs)
5523 {
5524 if (dbgregs->flags)
5525 return -EINVAL;
5526
5527 if (!kvm_dr6_valid(dbgregs->dr6))
5528 return -EINVAL;
5529 if (!kvm_dr7_valid(dbgregs->dr7))
5530 return -EINVAL;
5531
5532 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5533 kvm_update_dr0123(vcpu);
5534 vcpu->arch.dr6 = dbgregs->dr6;
5535 vcpu->arch.dr7 = dbgregs->dr7;
5536 kvm_update_dr7(vcpu);
5537
5538 return 0;
5539 }
5540
5541
kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu * vcpu,u8 * state,unsigned int size)5542 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5543 u8 *state, unsigned int size)
5544 {
5545 /*
5546 * Only copy state for features that are enabled for the guest. The
5547 * state itself isn't problematic, but setting bits in the header for
5548 * features that are supported in *this* host but not exposed to the
5549 * guest can result in KVM_SET_XSAVE failing when live migrating to a
5550 * compatible host without the features that are NOT exposed to the
5551 * guest.
5552 *
5553 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
5554 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
5555 * supported by the host.
5556 */
5557 u64 supported_xcr0 = vcpu->arch.guest_supported_xcr0 |
5558 XFEATURE_MASK_FPSSE;
5559
5560 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5561 return;
5562
5563 fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size,
5564 supported_xcr0, vcpu->arch.pkru);
5565 }
5566
kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu * vcpu,struct kvm_xsave * guest_xsave)5567 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5568 struct kvm_xsave *guest_xsave)
5569 {
5570 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region,
5571 sizeof(guest_xsave->region));
5572 }
5573
kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu * vcpu,struct kvm_xsave * guest_xsave)5574 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5575 struct kvm_xsave *guest_xsave)
5576 {
5577 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5578 return 0;
5579
5580 return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5581 guest_xsave->region,
5582 kvm_caps.supported_xcr0,
5583 &vcpu->arch.pkru);
5584 }
5585
kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu * vcpu,struct kvm_xcrs * guest_xcrs)5586 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5587 struct kvm_xcrs *guest_xcrs)
5588 {
5589 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5590 guest_xcrs->nr_xcrs = 0;
5591 return;
5592 }
5593
5594 guest_xcrs->nr_xcrs = 1;
5595 guest_xcrs->flags = 0;
5596 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5597 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5598 }
5599
kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu * vcpu,struct kvm_xcrs * guest_xcrs)5600 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5601 struct kvm_xcrs *guest_xcrs)
5602 {
5603 int i, r = 0;
5604
5605 if (!boot_cpu_has(X86_FEATURE_XSAVE))
5606 return -EINVAL;
5607
5608 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5609 return -EINVAL;
5610
5611 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5612 /* Only support XCR0 currently */
5613 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5614 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5615 guest_xcrs->xcrs[i].value);
5616 break;
5617 }
5618 if (r)
5619 r = -EINVAL;
5620 return r;
5621 }
5622
5623 /*
5624 * kvm_set_guest_paused() indicates to the guest kernel that it has been
5625 * stopped by the hypervisor. This function will be called from the host only.
5626 * EINVAL is returned when the host attempts to set the flag for a guest that
5627 * does not support pv clocks.
5628 */
kvm_set_guest_paused(struct kvm_vcpu * vcpu)5629 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5630 {
5631 if (!vcpu->arch.pv_time.active)
5632 return -EINVAL;
5633 vcpu->arch.pvclock_set_guest_stopped_request = true;
5634 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5635 return 0;
5636 }
5637
kvm_arch_tsc_has_attr(struct kvm_vcpu * vcpu,struct kvm_device_attr * attr)5638 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5639 struct kvm_device_attr *attr)
5640 {
5641 int r;
5642
5643 switch (attr->attr) {
5644 case KVM_VCPU_TSC_OFFSET:
5645 r = 0;
5646 break;
5647 default:
5648 r = -ENXIO;
5649 }
5650
5651 return r;
5652 }
5653
kvm_arch_tsc_get_attr(struct kvm_vcpu * vcpu,struct kvm_device_attr * attr)5654 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5655 struct kvm_device_attr *attr)
5656 {
5657 u64 __user *uaddr = kvm_get_attr_addr(attr);
5658 int r;
5659
5660 if (IS_ERR(uaddr))
5661 return PTR_ERR(uaddr);
5662
5663 switch (attr->attr) {
5664 case KVM_VCPU_TSC_OFFSET:
5665 r = -EFAULT;
5666 if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5667 break;
5668 r = 0;
5669 break;
5670 default:
5671 r = -ENXIO;
5672 }
5673
5674 return r;
5675 }
5676
kvm_arch_tsc_set_attr(struct kvm_vcpu * vcpu,struct kvm_device_attr * attr)5677 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5678 struct kvm_device_attr *attr)
5679 {
5680 u64 __user *uaddr = kvm_get_attr_addr(attr);
5681 struct kvm *kvm = vcpu->kvm;
5682 int r;
5683
5684 if (IS_ERR(uaddr))
5685 return PTR_ERR(uaddr);
5686
5687 switch (attr->attr) {
5688 case KVM_VCPU_TSC_OFFSET: {
5689 u64 offset, tsc, ns;
5690 unsigned long flags;
5691 bool matched;
5692
5693 r = -EFAULT;
5694 if (get_user(offset, uaddr))
5695 break;
5696
5697 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5698
5699 matched = (vcpu->arch.virtual_tsc_khz &&
5700 kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5701 kvm->arch.last_tsc_offset == offset);
5702
5703 tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5704 ns = get_kvmclock_base_ns();
5705
5706 kvm->arch.user_set_tsc = true;
5707 __kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5708 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5709
5710 r = 0;
5711 break;
5712 }
5713 default:
5714 r = -ENXIO;
5715 }
5716
5717 return r;
5718 }
5719
kvm_vcpu_ioctl_device_attr(struct kvm_vcpu * vcpu,unsigned int ioctl,void __user * argp)5720 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5721 unsigned int ioctl,
5722 void __user *argp)
5723 {
5724 struct kvm_device_attr attr;
5725 int r;
5726
5727 if (copy_from_user(&attr, argp, sizeof(attr)))
5728 return -EFAULT;
5729
5730 if (attr.group != KVM_VCPU_TSC_CTRL)
5731 return -ENXIO;
5732
5733 switch (ioctl) {
5734 case KVM_HAS_DEVICE_ATTR:
5735 r = kvm_arch_tsc_has_attr(vcpu, &attr);
5736 break;
5737 case KVM_GET_DEVICE_ATTR:
5738 r = kvm_arch_tsc_get_attr(vcpu, &attr);
5739 break;
5740 case KVM_SET_DEVICE_ATTR:
5741 r = kvm_arch_tsc_set_attr(vcpu, &attr);
5742 break;
5743 }
5744
5745 return r;
5746 }
5747
kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu * vcpu,struct kvm_enable_cap * cap)5748 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5749 struct kvm_enable_cap *cap)
5750 {
5751 if (cap->flags)
5752 return -EINVAL;
5753
5754 switch (cap->cap) {
5755 #ifdef CONFIG_KVM_HYPERV
5756 case KVM_CAP_HYPERV_SYNIC2:
5757 if (cap->args[0])
5758 return -EINVAL;
5759 fallthrough;
5760
5761 case KVM_CAP_HYPERV_SYNIC:
5762 if (!irqchip_in_kernel(vcpu->kvm))
5763 return -EINVAL;
5764 return kvm_hv_activate_synic(vcpu, cap->cap ==
5765 KVM_CAP_HYPERV_SYNIC2);
5766 case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5767 {
5768 int r;
5769 uint16_t vmcs_version;
5770 void __user *user_ptr;
5771
5772 if (!kvm_x86_ops.nested_ops->enable_evmcs)
5773 return -ENOTTY;
5774 r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5775 if (!r) {
5776 user_ptr = (void __user *)(uintptr_t)cap->args[0];
5777 if (copy_to_user(user_ptr, &vmcs_version,
5778 sizeof(vmcs_version)))
5779 r = -EFAULT;
5780 }
5781 return r;
5782 }
5783 case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5784 if (!kvm_x86_ops.enable_l2_tlb_flush)
5785 return -ENOTTY;
5786
5787 return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5788
5789 case KVM_CAP_HYPERV_ENFORCE_CPUID:
5790 return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5791 #endif
5792
5793 case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5794 vcpu->arch.pv_cpuid.enforce = cap->args[0];
5795 if (vcpu->arch.pv_cpuid.enforce)
5796 kvm_update_pv_runtime(vcpu);
5797
5798 return 0;
5799 default:
5800 return -EINVAL;
5801 }
5802 }
5803
kvm_arch_vcpu_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)5804 long kvm_arch_vcpu_ioctl(struct file *filp,
5805 unsigned int ioctl, unsigned long arg)
5806 {
5807 struct kvm_vcpu *vcpu = filp->private_data;
5808 void __user *argp = (void __user *)arg;
5809 int r;
5810 union {
5811 struct kvm_sregs2 *sregs2;
5812 struct kvm_lapic_state *lapic;
5813 struct kvm_xsave *xsave;
5814 struct kvm_xcrs *xcrs;
5815 void *buffer;
5816 } u;
5817
5818 vcpu_load(vcpu);
5819
5820 u.buffer = NULL;
5821 switch (ioctl) {
5822 case KVM_GET_LAPIC: {
5823 r = -EINVAL;
5824 if (!lapic_in_kernel(vcpu))
5825 goto out;
5826 u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5827 GFP_KERNEL_ACCOUNT);
5828
5829 r = -ENOMEM;
5830 if (!u.lapic)
5831 goto out;
5832 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5833 if (r)
5834 goto out;
5835 r = -EFAULT;
5836 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5837 goto out;
5838 r = 0;
5839 break;
5840 }
5841 case KVM_SET_LAPIC: {
5842 r = -EINVAL;
5843 if (!lapic_in_kernel(vcpu))
5844 goto out;
5845 u.lapic = memdup_user(argp, sizeof(*u.lapic));
5846 if (IS_ERR(u.lapic)) {
5847 r = PTR_ERR(u.lapic);
5848 goto out_nofree;
5849 }
5850
5851 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5852 break;
5853 }
5854 case KVM_INTERRUPT: {
5855 struct kvm_interrupt irq;
5856
5857 r = -EFAULT;
5858 if (copy_from_user(&irq, argp, sizeof(irq)))
5859 goto out;
5860 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5861 break;
5862 }
5863 case KVM_NMI: {
5864 r = kvm_vcpu_ioctl_nmi(vcpu);
5865 break;
5866 }
5867 case KVM_SMI: {
5868 r = kvm_inject_smi(vcpu);
5869 break;
5870 }
5871 case KVM_SET_CPUID: {
5872 struct kvm_cpuid __user *cpuid_arg = argp;
5873 struct kvm_cpuid cpuid;
5874
5875 r = -EFAULT;
5876 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5877 goto out;
5878 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5879 break;
5880 }
5881 case KVM_SET_CPUID2: {
5882 struct kvm_cpuid2 __user *cpuid_arg = argp;
5883 struct kvm_cpuid2 cpuid;
5884
5885 r = -EFAULT;
5886 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5887 goto out;
5888 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5889 cpuid_arg->entries);
5890 break;
5891 }
5892 case KVM_GET_CPUID2: {
5893 struct kvm_cpuid2 __user *cpuid_arg = argp;
5894 struct kvm_cpuid2 cpuid;
5895
5896 r = -EFAULT;
5897 if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5898 goto out;
5899 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5900 cpuid_arg->entries);
5901 if (r)
5902 goto out;
5903 r = -EFAULT;
5904 if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5905 goto out;
5906 r = 0;
5907 break;
5908 }
5909 case KVM_GET_MSRS: {
5910 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5911 r = msr_io(vcpu, argp, do_get_msr, 1);
5912 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5913 break;
5914 }
5915 case KVM_SET_MSRS: {
5916 int idx = srcu_read_lock(&vcpu->kvm->srcu);
5917 r = msr_io(vcpu, argp, do_set_msr, 0);
5918 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5919 break;
5920 }
5921 case KVM_TPR_ACCESS_REPORTING: {
5922 struct kvm_tpr_access_ctl tac;
5923
5924 r = -EFAULT;
5925 if (copy_from_user(&tac, argp, sizeof(tac)))
5926 goto out;
5927 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5928 if (r)
5929 goto out;
5930 r = -EFAULT;
5931 if (copy_to_user(argp, &tac, sizeof(tac)))
5932 goto out;
5933 r = 0;
5934 break;
5935 };
5936 case KVM_SET_VAPIC_ADDR: {
5937 struct kvm_vapic_addr va;
5938 int idx;
5939
5940 r = -EINVAL;
5941 if (!lapic_in_kernel(vcpu))
5942 goto out;
5943 r = -EFAULT;
5944 if (copy_from_user(&va, argp, sizeof(va)))
5945 goto out;
5946 idx = srcu_read_lock(&vcpu->kvm->srcu);
5947 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5948 srcu_read_unlock(&vcpu->kvm->srcu, idx);
5949 break;
5950 }
5951 case KVM_X86_SETUP_MCE: {
5952 u64 mcg_cap;
5953
5954 r = -EFAULT;
5955 if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5956 goto out;
5957 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5958 break;
5959 }
5960 case KVM_X86_SET_MCE: {
5961 struct kvm_x86_mce mce;
5962
5963 r = -EFAULT;
5964 if (copy_from_user(&mce, argp, sizeof(mce)))
5965 goto out;
5966 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5967 break;
5968 }
5969 case KVM_GET_VCPU_EVENTS: {
5970 struct kvm_vcpu_events events;
5971
5972 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5973
5974 r = -EFAULT;
5975 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5976 break;
5977 r = 0;
5978 break;
5979 }
5980 case KVM_SET_VCPU_EVENTS: {
5981 struct kvm_vcpu_events events;
5982
5983 r = -EFAULT;
5984 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5985 break;
5986
5987 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5988 break;
5989 }
5990 case KVM_GET_DEBUGREGS: {
5991 struct kvm_debugregs dbgregs;
5992
5993 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5994
5995 r = -EFAULT;
5996 if (copy_to_user(argp, &dbgregs,
5997 sizeof(struct kvm_debugregs)))
5998 break;
5999 r = 0;
6000 break;
6001 }
6002 case KVM_SET_DEBUGREGS: {
6003 struct kvm_debugregs dbgregs;
6004
6005 r = -EFAULT;
6006 if (copy_from_user(&dbgregs, argp,
6007 sizeof(struct kvm_debugregs)))
6008 break;
6009
6010 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
6011 break;
6012 }
6013 case KVM_GET_XSAVE: {
6014 r = -EINVAL;
6015 if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
6016 break;
6017
6018 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
6019 r = -ENOMEM;
6020 if (!u.xsave)
6021 break;
6022
6023 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
6024
6025 r = -EFAULT;
6026 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
6027 break;
6028 r = 0;
6029 break;
6030 }
6031 case KVM_SET_XSAVE: {
6032 int size = vcpu->arch.guest_fpu.uabi_size;
6033
6034 u.xsave = memdup_user(argp, size);
6035 if (IS_ERR(u.xsave)) {
6036 r = PTR_ERR(u.xsave);
6037 goto out_nofree;
6038 }
6039
6040 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
6041 break;
6042 }
6043
6044 case KVM_GET_XSAVE2: {
6045 int size = vcpu->arch.guest_fpu.uabi_size;
6046
6047 u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
6048 r = -ENOMEM;
6049 if (!u.xsave)
6050 break;
6051
6052 kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
6053
6054 r = -EFAULT;
6055 if (copy_to_user(argp, u.xsave, size))
6056 break;
6057
6058 r = 0;
6059 break;
6060 }
6061
6062 case KVM_GET_XCRS: {
6063 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
6064 r = -ENOMEM;
6065 if (!u.xcrs)
6066 break;
6067
6068 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
6069
6070 r = -EFAULT;
6071 if (copy_to_user(argp, u.xcrs,
6072 sizeof(struct kvm_xcrs)))
6073 break;
6074 r = 0;
6075 break;
6076 }
6077 case KVM_SET_XCRS: {
6078 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
6079 if (IS_ERR(u.xcrs)) {
6080 r = PTR_ERR(u.xcrs);
6081 goto out_nofree;
6082 }
6083
6084 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
6085 break;
6086 }
6087 case KVM_SET_TSC_KHZ: {
6088 u32 user_tsc_khz;
6089
6090 r = -EINVAL;
6091 user_tsc_khz = (u32)arg;
6092
6093 if (kvm_caps.has_tsc_control &&
6094 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
6095 goto out;
6096
6097 if (user_tsc_khz == 0)
6098 user_tsc_khz = tsc_khz;
6099
6100 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
6101 r = 0;
6102
6103 goto out;
6104 }
6105 case KVM_GET_TSC_KHZ: {
6106 r = vcpu->arch.virtual_tsc_khz;
6107 goto out;
6108 }
6109 case KVM_KVMCLOCK_CTRL: {
6110 r = kvm_set_guest_paused(vcpu);
6111 goto out;
6112 }
6113 case KVM_ENABLE_CAP: {
6114 struct kvm_enable_cap cap;
6115
6116 r = -EFAULT;
6117 if (copy_from_user(&cap, argp, sizeof(cap)))
6118 goto out;
6119 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
6120 break;
6121 }
6122 case KVM_GET_NESTED_STATE: {
6123 struct kvm_nested_state __user *user_kvm_nested_state = argp;
6124 u32 user_data_size;
6125
6126 r = -EINVAL;
6127 if (!kvm_x86_ops.nested_ops->get_state)
6128 break;
6129
6130 BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
6131 r = -EFAULT;
6132 if (get_user(user_data_size, &user_kvm_nested_state->size))
6133 break;
6134
6135 r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
6136 user_data_size);
6137 if (r < 0)
6138 break;
6139
6140 if (r > user_data_size) {
6141 if (put_user(r, &user_kvm_nested_state->size))
6142 r = -EFAULT;
6143 else
6144 r = -E2BIG;
6145 break;
6146 }
6147
6148 r = 0;
6149 break;
6150 }
6151 case KVM_SET_NESTED_STATE: {
6152 struct kvm_nested_state __user *user_kvm_nested_state = argp;
6153 struct kvm_nested_state kvm_state;
6154 int idx;
6155
6156 r = -EINVAL;
6157 if (!kvm_x86_ops.nested_ops->set_state)
6158 break;
6159
6160 r = -EFAULT;
6161 if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
6162 break;
6163
6164 r = -EINVAL;
6165 if (kvm_state.size < sizeof(kvm_state))
6166 break;
6167
6168 if (kvm_state.flags &
6169 ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
6170 | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
6171 | KVM_STATE_NESTED_GIF_SET))
6172 break;
6173
6174 /* nested_run_pending implies guest_mode. */
6175 if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
6176 && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
6177 break;
6178
6179 idx = srcu_read_lock(&vcpu->kvm->srcu);
6180 r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
6181 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6182 break;
6183 }
6184 #ifdef CONFIG_KVM_HYPERV
6185 case KVM_GET_SUPPORTED_HV_CPUID:
6186 r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
6187 break;
6188 #endif
6189 #ifdef CONFIG_KVM_XEN
6190 case KVM_XEN_VCPU_GET_ATTR: {
6191 struct kvm_xen_vcpu_attr xva;
6192
6193 r = -EFAULT;
6194 if (copy_from_user(&xva, argp, sizeof(xva)))
6195 goto out;
6196 r = kvm_xen_vcpu_get_attr(vcpu, &xva);
6197 if (!r && copy_to_user(argp, &xva, sizeof(xva)))
6198 r = -EFAULT;
6199 break;
6200 }
6201 case KVM_XEN_VCPU_SET_ATTR: {
6202 struct kvm_xen_vcpu_attr xva;
6203
6204 r = -EFAULT;
6205 if (copy_from_user(&xva, argp, sizeof(xva)))
6206 goto out;
6207 r = kvm_xen_vcpu_set_attr(vcpu, &xva);
6208 break;
6209 }
6210 #endif
6211 case KVM_GET_SREGS2: {
6212 u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
6213 r = -ENOMEM;
6214 if (!u.sregs2)
6215 goto out;
6216 __get_sregs2(vcpu, u.sregs2);
6217 r = -EFAULT;
6218 if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
6219 goto out;
6220 r = 0;
6221 break;
6222 }
6223 case KVM_SET_SREGS2: {
6224 u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6225 if (IS_ERR(u.sregs2)) {
6226 r = PTR_ERR(u.sregs2);
6227 u.sregs2 = NULL;
6228 goto out;
6229 }
6230 r = __set_sregs2(vcpu, u.sregs2);
6231 break;
6232 }
6233 case KVM_HAS_DEVICE_ATTR:
6234 case KVM_GET_DEVICE_ATTR:
6235 case KVM_SET_DEVICE_ATTR:
6236 r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6237 break;
6238 default:
6239 r = -EINVAL;
6240 }
6241 out:
6242 kfree(u.buffer);
6243 out_nofree:
6244 vcpu_put(vcpu);
6245 return r;
6246 }
6247
kvm_arch_vcpu_fault(struct kvm_vcpu * vcpu,struct vm_fault * vmf)6248 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6249 {
6250 return VM_FAULT_SIGBUS;
6251 }
6252
kvm_vm_ioctl_set_tss_addr(struct kvm * kvm,unsigned long addr)6253 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6254 {
6255 int ret;
6256
6257 if (addr > (unsigned int)(-3 * PAGE_SIZE))
6258 return -EINVAL;
6259 ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6260 return ret;
6261 }
6262
kvm_vm_ioctl_set_identity_map_addr(struct kvm * kvm,u64 ident_addr)6263 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6264 u64 ident_addr)
6265 {
6266 return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6267 }
6268
kvm_vm_ioctl_set_nr_mmu_pages(struct kvm * kvm,unsigned long kvm_nr_mmu_pages)6269 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6270 unsigned long kvm_nr_mmu_pages)
6271 {
6272 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6273 return -EINVAL;
6274
6275 mutex_lock(&kvm->slots_lock);
6276
6277 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6278 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6279
6280 mutex_unlock(&kvm->slots_lock);
6281 return 0;
6282 }
6283
kvm_vm_ioctl_get_irqchip(struct kvm * kvm,struct kvm_irqchip * chip)6284 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6285 {
6286 struct kvm_pic *pic = kvm->arch.vpic;
6287 int r;
6288
6289 r = 0;
6290 switch (chip->chip_id) {
6291 case KVM_IRQCHIP_PIC_MASTER:
6292 memcpy(&chip->chip.pic, &pic->pics[0],
6293 sizeof(struct kvm_pic_state));
6294 break;
6295 case KVM_IRQCHIP_PIC_SLAVE:
6296 memcpy(&chip->chip.pic, &pic->pics[1],
6297 sizeof(struct kvm_pic_state));
6298 break;
6299 case KVM_IRQCHIP_IOAPIC:
6300 kvm_get_ioapic(kvm, &chip->chip.ioapic);
6301 break;
6302 default:
6303 r = -EINVAL;
6304 break;
6305 }
6306 return r;
6307 }
6308
kvm_vm_ioctl_set_irqchip(struct kvm * kvm,struct kvm_irqchip * chip)6309 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6310 {
6311 struct kvm_pic *pic = kvm->arch.vpic;
6312 int r;
6313
6314 r = 0;
6315 switch (chip->chip_id) {
6316 case KVM_IRQCHIP_PIC_MASTER:
6317 spin_lock(&pic->lock);
6318 memcpy(&pic->pics[0], &chip->chip.pic,
6319 sizeof(struct kvm_pic_state));
6320 spin_unlock(&pic->lock);
6321 break;
6322 case KVM_IRQCHIP_PIC_SLAVE:
6323 spin_lock(&pic->lock);
6324 memcpy(&pic->pics[1], &chip->chip.pic,
6325 sizeof(struct kvm_pic_state));
6326 spin_unlock(&pic->lock);
6327 break;
6328 case KVM_IRQCHIP_IOAPIC:
6329 kvm_set_ioapic(kvm, &chip->chip.ioapic);
6330 break;
6331 default:
6332 r = -EINVAL;
6333 break;
6334 }
6335 kvm_pic_update_irq(pic);
6336 return r;
6337 }
6338
kvm_vm_ioctl_get_pit(struct kvm * kvm,struct kvm_pit_state * ps)6339 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6340 {
6341 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6342
6343 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6344
6345 mutex_lock(&kps->lock);
6346 memcpy(ps, &kps->channels, sizeof(*ps));
6347 mutex_unlock(&kps->lock);
6348 return 0;
6349 }
6350
kvm_vm_ioctl_set_pit(struct kvm * kvm,struct kvm_pit_state * ps)6351 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6352 {
6353 int i;
6354 struct kvm_pit *pit = kvm->arch.vpit;
6355
6356 mutex_lock(&pit->pit_state.lock);
6357 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6358 for (i = 0; i < 3; i++)
6359 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6360 mutex_unlock(&pit->pit_state.lock);
6361 return 0;
6362 }
6363
kvm_vm_ioctl_get_pit2(struct kvm * kvm,struct kvm_pit_state2 * ps)6364 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6365 {
6366 mutex_lock(&kvm->arch.vpit->pit_state.lock);
6367 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6368 sizeof(ps->channels));
6369 ps->flags = kvm->arch.vpit->pit_state.flags;
6370 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6371 memset(&ps->reserved, 0, sizeof(ps->reserved));
6372 return 0;
6373 }
6374
kvm_vm_ioctl_set_pit2(struct kvm * kvm,struct kvm_pit_state2 * ps)6375 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6376 {
6377 int start = 0;
6378 int i;
6379 u32 prev_legacy, cur_legacy;
6380 struct kvm_pit *pit = kvm->arch.vpit;
6381
6382 mutex_lock(&pit->pit_state.lock);
6383 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6384 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6385 if (!prev_legacy && cur_legacy)
6386 start = 1;
6387 memcpy(&pit->pit_state.channels, &ps->channels,
6388 sizeof(pit->pit_state.channels));
6389 pit->pit_state.flags = ps->flags;
6390 for (i = 0; i < 3; i++)
6391 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6392 start && i == 0);
6393 mutex_unlock(&pit->pit_state.lock);
6394 return 0;
6395 }
6396
kvm_vm_ioctl_reinject(struct kvm * kvm,struct kvm_reinject_control * control)6397 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6398 struct kvm_reinject_control *control)
6399 {
6400 struct kvm_pit *pit = kvm->arch.vpit;
6401
6402 /* pit->pit_state.lock was overloaded to prevent userspace from getting
6403 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6404 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
6405 */
6406 mutex_lock(&pit->pit_state.lock);
6407 kvm_pit_set_reinject(pit, control->pit_reinject);
6408 mutex_unlock(&pit->pit_state.lock);
6409
6410 return 0;
6411 }
6412
kvm_arch_sync_dirty_log(struct kvm * kvm,struct kvm_memory_slot * memslot)6413 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6414 {
6415
6416 /*
6417 * Flush all CPUs' dirty log buffers to the dirty_bitmap. Called
6418 * before reporting dirty_bitmap to userspace. KVM flushes the buffers
6419 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6420 * VM-Exit.
6421 */
6422 struct kvm_vcpu *vcpu;
6423 unsigned long i;
6424
6425 if (!kvm_x86_ops.cpu_dirty_log_size)
6426 return;
6427
6428 kvm_for_each_vcpu(i, vcpu, kvm)
6429 kvm_vcpu_kick(vcpu);
6430 }
6431
kvm_vm_ioctl_irq_line(struct kvm * kvm,struct kvm_irq_level * irq_event,bool line_status)6432 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6433 bool line_status)
6434 {
6435 if (!irqchip_in_kernel(kvm))
6436 return -ENXIO;
6437
6438 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6439 irq_event->irq, irq_event->level,
6440 line_status);
6441 return 0;
6442 }
6443
kvm_vm_ioctl_enable_cap(struct kvm * kvm,struct kvm_enable_cap * cap)6444 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6445 struct kvm_enable_cap *cap)
6446 {
6447 int r;
6448
6449 if (cap->flags)
6450 return -EINVAL;
6451
6452 switch (cap->cap) {
6453 case KVM_CAP_DISABLE_QUIRKS2:
6454 r = -EINVAL;
6455 if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6456 break;
6457 fallthrough;
6458 case KVM_CAP_DISABLE_QUIRKS:
6459 kvm->arch.disabled_quirks = cap->args[0];
6460 r = 0;
6461 break;
6462 case KVM_CAP_SPLIT_IRQCHIP: {
6463 mutex_lock(&kvm->lock);
6464 r = -EINVAL;
6465 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6466 goto split_irqchip_unlock;
6467 r = -EEXIST;
6468 if (irqchip_in_kernel(kvm))
6469 goto split_irqchip_unlock;
6470 if (kvm->created_vcpus)
6471 goto split_irqchip_unlock;
6472 r = kvm_setup_empty_irq_routing(kvm);
6473 if (r)
6474 goto split_irqchip_unlock;
6475 /* Pairs with irqchip_in_kernel. */
6476 smp_wmb();
6477 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6478 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6479 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6480 r = 0;
6481 split_irqchip_unlock:
6482 mutex_unlock(&kvm->lock);
6483 break;
6484 }
6485 case KVM_CAP_X2APIC_API:
6486 r = -EINVAL;
6487 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6488 break;
6489
6490 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6491 kvm->arch.x2apic_format = true;
6492 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6493 kvm->arch.x2apic_broadcast_quirk_disabled = true;
6494
6495 r = 0;
6496 break;
6497 case KVM_CAP_X86_DISABLE_EXITS:
6498 r = -EINVAL;
6499 if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6500 break;
6501
6502 if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6503 kvm->arch.pause_in_guest = true;
6504
6505 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6506 "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6507
6508 if (!mitigate_smt_rsb) {
6509 if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6510 (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6511 pr_warn_once(SMT_RSB_MSG);
6512
6513 if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6514 kvm_can_mwait_in_guest())
6515 kvm->arch.mwait_in_guest = true;
6516 if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6517 kvm->arch.hlt_in_guest = true;
6518 if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6519 kvm->arch.cstate_in_guest = true;
6520 }
6521
6522 r = 0;
6523 break;
6524 case KVM_CAP_MSR_PLATFORM_INFO:
6525 kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6526 r = 0;
6527 break;
6528 case KVM_CAP_EXCEPTION_PAYLOAD:
6529 kvm->arch.exception_payload_enabled = cap->args[0];
6530 r = 0;
6531 break;
6532 case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6533 kvm->arch.triple_fault_event = cap->args[0];
6534 r = 0;
6535 break;
6536 case KVM_CAP_X86_USER_SPACE_MSR:
6537 r = -EINVAL;
6538 if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6539 break;
6540 kvm->arch.user_space_msr_mask = cap->args[0];
6541 r = 0;
6542 break;
6543 case KVM_CAP_X86_BUS_LOCK_EXIT:
6544 r = -EINVAL;
6545 if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6546 break;
6547
6548 if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6549 (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6550 break;
6551
6552 if (kvm_caps.has_bus_lock_exit &&
6553 cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6554 kvm->arch.bus_lock_detection_enabled = true;
6555 r = 0;
6556 break;
6557 #ifdef CONFIG_X86_SGX_KVM
6558 case KVM_CAP_SGX_ATTRIBUTE: {
6559 unsigned long allowed_attributes = 0;
6560
6561 r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6562 if (r)
6563 break;
6564
6565 /* KVM only supports the PROVISIONKEY privileged attribute. */
6566 if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6567 !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6568 kvm->arch.sgx_provisioning_allowed = true;
6569 else
6570 r = -EINVAL;
6571 break;
6572 }
6573 #endif
6574 case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6575 r = -EINVAL;
6576 if (!kvm_x86_ops.vm_copy_enc_context_from)
6577 break;
6578
6579 r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6580 break;
6581 case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6582 r = -EINVAL;
6583 if (!kvm_x86_ops.vm_move_enc_context_from)
6584 break;
6585
6586 r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6587 break;
6588 case KVM_CAP_EXIT_HYPERCALL:
6589 if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6590 r = -EINVAL;
6591 break;
6592 }
6593 kvm->arch.hypercall_exit_enabled = cap->args[0];
6594 r = 0;
6595 break;
6596 case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6597 r = -EINVAL;
6598 if (cap->args[0] & ~1)
6599 break;
6600 kvm->arch.exit_on_emulation_error = cap->args[0];
6601 r = 0;
6602 break;
6603 case KVM_CAP_PMU_CAPABILITY:
6604 r = -EINVAL;
6605 if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6606 break;
6607
6608 mutex_lock(&kvm->lock);
6609 if (!kvm->created_vcpus) {
6610 kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6611 r = 0;
6612 }
6613 mutex_unlock(&kvm->lock);
6614 break;
6615 case KVM_CAP_MAX_VCPU_ID:
6616 r = -EINVAL;
6617 if (cap->args[0] > KVM_MAX_VCPU_IDS)
6618 break;
6619
6620 mutex_lock(&kvm->lock);
6621 if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6622 r = 0;
6623 } else if (!kvm->arch.max_vcpu_ids) {
6624 kvm->arch.max_vcpu_ids = cap->args[0];
6625 r = 0;
6626 }
6627 mutex_unlock(&kvm->lock);
6628 break;
6629 case KVM_CAP_X86_NOTIFY_VMEXIT:
6630 r = -EINVAL;
6631 if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6632 break;
6633 if (!kvm_caps.has_notify_vmexit)
6634 break;
6635 if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6636 break;
6637 mutex_lock(&kvm->lock);
6638 if (!kvm->created_vcpus) {
6639 kvm->arch.notify_window = cap->args[0] >> 32;
6640 kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6641 r = 0;
6642 }
6643 mutex_unlock(&kvm->lock);
6644 break;
6645 case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6646 r = -EINVAL;
6647
6648 /*
6649 * Since the risk of disabling NX hugepages is a guest crashing
6650 * the system, ensure the userspace process has permission to
6651 * reboot the system.
6652 *
6653 * Note that unlike the reboot() syscall, the process must have
6654 * this capability in the root namespace because exposing
6655 * /dev/kvm into a container does not limit the scope of the
6656 * iTLB multihit bug to that container. In other words,
6657 * this must use capable(), not ns_capable().
6658 */
6659 if (!capable(CAP_SYS_BOOT)) {
6660 r = -EPERM;
6661 break;
6662 }
6663
6664 if (cap->args[0])
6665 break;
6666
6667 mutex_lock(&kvm->lock);
6668 if (!kvm->created_vcpus) {
6669 kvm->arch.disable_nx_huge_pages = true;
6670 r = 0;
6671 }
6672 mutex_unlock(&kvm->lock);
6673 break;
6674 default:
6675 r = -EINVAL;
6676 break;
6677 }
6678 return r;
6679 }
6680
kvm_alloc_msr_filter(bool default_allow)6681 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6682 {
6683 struct kvm_x86_msr_filter *msr_filter;
6684
6685 msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6686 if (!msr_filter)
6687 return NULL;
6688
6689 msr_filter->default_allow = default_allow;
6690 return msr_filter;
6691 }
6692
kvm_free_msr_filter(struct kvm_x86_msr_filter * msr_filter)6693 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6694 {
6695 u32 i;
6696
6697 if (!msr_filter)
6698 return;
6699
6700 for (i = 0; i < msr_filter->count; i++)
6701 kfree(msr_filter->ranges[i].bitmap);
6702
6703 kfree(msr_filter);
6704 }
6705
kvm_add_msr_filter(struct kvm_x86_msr_filter * msr_filter,struct kvm_msr_filter_range * user_range)6706 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6707 struct kvm_msr_filter_range *user_range)
6708 {
6709 unsigned long *bitmap;
6710 size_t bitmap_size;
6711
6712 if (!user_range->nmsrs)
6713 return 0;
6714
6715 if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6716 return -EINVAL;
6717
6718 if (!user_range->flags)
6719 return -EINVAL;
6720
6721 bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6722 if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6723 return -EINVAL;
6724
6725 bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6726 if (IS_ERR(bitmap))
6727 return PTR_ERR(bitmap);
6728
6729 msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6730 .flags = user_range->flags,
6731 .base = user_range->base,
6732 .nmsrs = user_range->nmsrs,
6733 .bitmap = bitmap,
6734 };
6735
6736 msr_filter->count++;
6737 return 0;
6738 }
6739
kvm_vm_ioctl_set_msr_filter(struct kvm * kvm,struct kvm_msr_filter * filter)6740 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6741 struct kvm_msr_filter *filter)
6742 {
6743 struct kvm_x86_msr_filter *new_filter, *old_filter;
6744 bool default_allow;
6745 bool empty = true;
6746 int r;
6747 u32 i;
6748
6749 if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6750 return -EINVAL;
6751
6752 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6753 empty &= !filter->ranges[i].nmsrs;
6754
6755 default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6756 if (empty && !default_allow)
6757 return -EINVAL;
6758
6759 new_filter = kvm_alloc_msr_filter(default_allow);
6760 if (!new_filter)
6761 return -ENOMEM;
6762
6763 for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6764 r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6765 if (r) {
6766 kvm_free_msr_filter(new_filter);
6767 return r;
6768 }
6769 }
6770
6771 mutex_lock(&kvm->lock);
6772 old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6773 mutex_is_locked(&kvm->lock));
6774 mutex_unlock(&kvm->lock);
6775 synchronize_srcu(&kvm->srcu);
6776
6777 kvm_free_msr_filter(old_filter);
6778
6779 kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6780
6781 return 0;
6782 }
6783
6784 #ifdef CONFIG_KVM_COMPAT
6785 /* for KVM_X86_SET_MSR_FILTER */
6786 struct kvm_msr_filter_range_compat {
6787 __u32 flags;
6788 __u32 nmsrs;
6789 __u32 base;
6790 __u32 bitmap;
6791 };
6792
6793 struct kvm_msr_filter_compat {
6794 __u32 flags;
6795 struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6796 };
6797
6798 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6799
kvm_arch_vm_compat_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)6800 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6801 unsigned long arg)
6802 {
6803 void __user *argp = (void __user *)arg;
6804 struct kvm *kvm = filp->private_data;
6805 long r = -ENOTTY;
6806
6807 switch (ioctl) {
6808 case KVM_X86_SET_MSR_FILTER_COMPAT: {
6809 struct kvm_msr_filter __user *user_msr_filter = argp;
6810 struct kvm_msr_filter_compat filter_compat;
6811 struct kvm_msr_filter filter;
6812 int i;
6813
6814 if (copy_from_user(&filter_compat, user_msr_filter,
6815 sizeof(filter_compat)))
6816 return -EFAULT;
6817
6818 filter.flags = filter_compat.flags;
6819 for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6820 struct kvm_msr_filter_range_compat *cr;
6821
6822 cr = &filter_compat.ranges[i];
6823 filter.ranges[i] = (struct kvm_msr_filter_range) {
6824 .flags = cr->flags,
6825 .nmsrs = cr->nmsrs,
6826 .base = cr->base,
6827 .bitmap = (__u8 *)(ulong)cr->bitmap,
6828 };
6829 }
6830
6831 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6832 break;
6833 }
6834 }
6835
6836 return r;
6837 }
6838 #endif
6839
6840 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
kvm_arch_suspend_notifier(struct kvm * kvm)6841 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6842 {
6843 struct kvm_vcpu *vcpu;
6844 unsigned long i;
6845 int ret = 0;
6846
6847 mutex_lock(&kvm->lock);
6848 kvm_for_each_vcpu(i, vcpu, kvm) {
6849 if (!vcpu->arch.pv_time.active)
6850 continue;
6851
6852 ret = kvm_set_guest_paused(vcpu);
6853 if (ret) {
6854 kvm_err("Failed to pause guest VCPU%d: %d\n",
6855 vcpu->vcpu_id, ret);
6856 break;
6857 }
6858 }
6859 mutex_unlock(&kvm->lock);
6860
6861 return ret ? NOTIFY_BAD : NOTIFY_DONE;
6862 }
6863
kvm_arch_pm_notifier(struct kvm * kvm,unsigned long state)6864 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6865 {
6866 switch (state) {
6867 case PM_HIBERNATION_PREPARE:
6868 case PM_SUSPEND_PREPARE:
6869 return kvm_arch_suspend_notifier(kvm);
6870 }
6871
6872 return NOTIFY_DONE;
6873 }
6874 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6875
kvm_vm_ioctl_get_clock(struct kvm * kvm,void __user * argp)6876 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6877 {
6878 struct kvm_clock_data data = { 0 };
6879
6880 get_kvmclock(kvm, &data);
6881 if (copy_to_user(argp, &data, sizeof(data)))
6882 return -EFAULT;
6883
6884 return 0;
6885 }
6886
kvm_vm_ioctl_set_clock(struct kvm * kvm,void __user * argp)6887 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6888 {
6889 struct kvm_arch *ka = &kvm->arch;
6890 struct kvm_clock_data data;
6891 u64 now_raw_ns;
6892
6893 if (copy_from_user(&data, argp, sizeof(data)))
6894 return -EFAULT;
6895
6896 /*
6897 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6898 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6899 */
6900 if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6901 return -EINVAL;
6902
6903 kvm_hv_request_tsc_page_update(kvm);
6904 kvm_start_pvclock_update(kvm);
6905 pvclock_update_vm_gtod_copy(kvm);
6906
6907 /*
6908 * This pairs with kvm_guest_time_update(): when masterclock is
6909 * in use, we use master_kernel_ns + kvmclock_offset to set
6910 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6911 * is slightly ahead) here we risk going negative on unsigned
6912 * 'system_time' when 'data.clock' is very small.
6913 */
6914 if (data.flags & KVM_CLOCK_REALTIME) {
6915 u64 now_real_ns = ktime_get_real_ns();
6916
6917 /*
6918 * Avoid stepping the kvmclock backwards.
6919 */
6920 if (now_real_ns > data.realtime)
6921 data.clock += now_real_ns - data.realtime;
6922 }
6923
6924 if (ka->use_master_clock)
6925 now_raw_ns = ka->master_kernel_ns;
6926 else
6927 now_raw_ns = get_kvmclock_base_ns();
6928 ka->kvmclock_offset = data.clock - now_raw_ns;
6929 kvm_end_pvclock_update(kvm);
6930 return 0;
6931 }
6932
kvm_arch_vm_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)6933 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6934 {
6935 struct kvm *kvm = filp->private_data;
6936 void __user *argp = (void __user *)arg;
6937 int r = -ENOTTY;
6938 /*
6939 * This union makes it completely explicit to gcc-3.x
6940 * that these two variables' stack usage should be
6941 * combined, not added together.
6942 */
6943 union {
6944 struct kvm_pit_state ps;
6945 struct kvm_pit_state2 ps2;
6946 struct kvm_pit_config pit_config;
6947 } u;
6948
6949 switch (ioctl) {
6950 case KVM_SET_TSS_ADDR:
6951 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6952 break;
6953 case KVM_SET_IDENTITY_MAP_ADDR: {
6954 u64 ident_addr;
6955
6956 mutex_lock(&kvm->lock);
6957 r = -EINVAL;
6958 if (kvm->created_vcpus)
6959 goto set_identity_unlock;
6960 r = -EFAULT;
6961 if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6962 goto set_identity_unlock;
6963 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6964 set_identity_unlock:
6965 mutex_unlock(&kvm->lock);
6966 break;
6967 }
6968 case KVM_SET_NR_MMU_PAGES:
6969 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6970 break;
6971 case KVM_CREATE_IRQCHIP: {
6972 mutex_lock(&kvm->lock);
6973
6974 r = -EEXIST;
6975 if (irqchip_in_kernel(kvm))
6976 goto create_irqchip_unlock;
6977
6978 r = -EINVAL;
6979 if (kvm->created_vcpus)
6980 goto create_irqchip_unlock;
6981
6982 r = kvm_pic_init(kvm);
6983 if (r)
6984 goto create_irqchip_unlock;
6985
6986 r = kvm_ioapic_init(kvm);
6987 if (r) {
6988 kvm_pic_destroy(kvm);
6989 goto create_irqchip_unlock;
6990 }
6991
6992 r = kvm_setup_default_irq_routing(kvm);
6993 if (r) {
6994 kvm_ioapic_destroy(kvm);
6995 kvm_pic_destroy(kvm);
6996 goto create_irqchip_unlock;
6997 }
6998 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6999 smp_wmb();
7000 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
7001 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
7002 create_irqchip_unlock:
7003 mutex_unlock(&kvm->lock);
7004 break;
7005 }
7006 case KVM_CREATE_PIT:
7007 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
7008 goto create_pit;
7009 case KVM_CREATE_PIT2:
7010 r = -EFAULT;
7011 if (copy_from_user(&u.pit_config, argp,
7012 sizeof(struct kvm_pit_config)))
7013 goto out;
7014 create_pit:
7015 mutex_lock(&kvm->lock);
7016 r = -EEXIST;
7017 if (kvm->arch.vpit)
7018 goto create_pit_unlock;
7019 r = -ENOENT;
7020 if (!pic_in_kernel(kvm))
7021 goto create_pit_unlock;
7022 r = -ENOMEM;
7023 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7024 if (kvm->arch.vpit)
7025 r = 0;
7026 create_pit_unlock:
7027 mutex_unlock(&kvm->lock);
7028 break;
7029 case KVM_GET_IRQCHIP: {
7030 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
7031 struct kvm_irqchip *chip;
7032
7033 chip = memdup_user(argp, sizeof(*chip));
7034 if (IS_ERR(chip)) {
7035 r = PTR_ERR(chip);
7036 goto out;
7037 }
7038
7039 r = -ENXIO;
7040 if (!irqchip_kernel(kvm))
7041 goto get_irqchip_out;
7042 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
7043 if (r)
7044 goto get_irqchip_out;
7045 r = -EFAULT;
7046 if (copy_to_user(argp, chip, sizeof(*chip)))
7047 goto get_irqchip_out;
7048 r = 0;
7049 get_irqchip_out:
7050 kfree(chip);
7051 break;
7052 }
7053 case KVM_SET_IRQCHIP: {
7054 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
7055 struct kvm_irqchip *chip;
7056
7057 chip = memdup_user(argp, sizeof(*chip));
7058 if (IS_ERR(chip)) {
7059 r = PTR_ERR(chip);
7060 goto out;
7061 }
7062
7063 r = -ENXIO;
7064 if (!irqchip_kernel(kvm))
7065 goto set_irqchip_out;
7066 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
7067 set_irqchip_out:
7068 kfree(chip);
7069 break;
7070 }
7071 case KVM_GET_PIT: {
7072 r = -EFAULT;
7073 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
7074 goto out;
7075 r = -ENXIO;
7076 if (!kvm->arch.vpit)
7077 goto out;
7078 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
7079 if (r)
7080 goto out;
7081 r = -EFAULT;
7082 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
7083 goto out;
7084 r = 0;
7085 break;
7086 }
7087 case KVM_SET_PIT: {
7088 r = -EFAULT;
7089 if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
7090 goto out;
7091 mutex_lock(&kvm->lock);
7092 r = -ENXIO;
7093 if (!kvm->arch.vpit)
7094 goto set_pit_out;
7095 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
7096 set_pit_out:
7097 mutex_unlock(&kvm->lock);
7098 break;
7099 }
7100 case KVM_GET_PIT2: {
7101 r = -ENXIO;
7102 if (!kvm->arch.vpit)
7103 goto out;
7104 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
7105 if (r)
7106 goto out;
7107 r = -EFAULT;
7108 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
7109 goto out;
7110 r = 0;
7111 break;
7112 }
7113 case KVM_SET_PIT2: {
7114 r = -EFAULT;
7115 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
7116 goto out;
7117 mutex_lock(&kvm->lock);
7118 r = -ENXIO;
7119 if (!kvm->arch.vpit)
7120 goto set_pit2_out;
7121 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
7122 set_pit2_out:
7123 mutex_unlock(&kvm->lock);
7124 break;
7125 }
7126 case KVM_REINJECT_CONTROL: {
7127 struct kvm_reinject_control control;
7128 r = -EFAULT;
7129 if (copy_from_user(&control, argp, sizeof(control)))
7130 goto out;
7131 r = -ENXIO;
7132 if (!kvm->arch.vpit)
7133 goto out;
7134 r = kvm_vm_ioctl_reinject(kvm, &control);
7135 break;
7136 }
7137 case KVM_SET_BOOT_CPU_ID:
7138 r = 0;
7139 mutex_lock(&kvm->lock);
7140 if (kvm->created_vcpus)
7141 r = -EBUSY;
7142 else
7143 kvm->arch.bsp_vcpu_id = arg;
7144 mutex_unlock(&kvm->lock);
7145 break;
7146 #ifdef CONFIG_KVM_XEN
7147 case KVM_XEN_HVM_CONFIG: {
7148 struct kvm_xen_hvm_config xhc;
7149 r = -EFAULT;
7150 if (copy_from_user(&xhc, argp, sizeof(xhc)))
7151 goto out;
7152 r = kvm_xen_hvm_config(kvm, &xhc);
7153 break;
7154 }
7155 case KVM_XEN_HVM_GET_ATTR: {
7156 struct kvm_xen_hvm_attr xha;
7157
7158 r = -EFAULT;
7159 if (copy_from_user(&xha, argp, sizeof(xha)))
7160 goto out;
7161 r = kvm_xen_hvm_get_attr(kvm, &xha);
7162 if (!r && copy_to_user(argp, &xha, sizeof(xha)))
7163 r = -EFAULT;
7164 break;
7165 }
7166 case KVM_XEN_HVM_SET_ATTR: {
7167 struct kvm_xen_hvm_attr xha;
7168
7169 r = -EFAULT;
7170 if (copy_from_user(&xha, argp, sizeof(xha)))
7171 goto out;
7172 r = kvm_xen_hvm_set_attr(kvm, &xha);
7173 break;
7174 }
7175 case KVM_XEN_HVM_EVTCHN_SEND: {
7176 struct kvm_irq_routing_xen_evtchn uxe;
7177
7178 r = -EFAULT;
7179 if (copy_from_user(&uxe, argp, sizeof(uxe)))
7180 goto out;
7181 r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
7182 break;
7183 }
7184 #endif
7185 case KVM_SET_CLOCK:
7186 r = kvm_vm_ioctl_set_clock(kvm, argp);
7187 break;
7188 case KVM_GET_CLOCK:
7189 r = kvm_vm_ioctl_get_clock(kvm, argp);
7190 break;
7191 case KVM_SET_TSC_KHZ: {
7192 u32 user_tsc_khz;
7193
7194 r = -EINVAL;
7195 user_tsc_khz = (u32)arg;
7196
7197 if (kvm_caps.has_tsc_control &&
7198 user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
7199 goto out;
7200
7201 if (user_tsc_khz == 0)
7202 user_tsc_khz = tsc_khz;
7203
7204 WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
7205 r = 0;
7206
7207 goto out;
7208 }
7209 case KVM_GET_TSC_KHZ: {
7210 r = READ_ONCE(kvm->arch.default_tsc_khz);
7211 goto out;
7212 }
7213 case KVM_MEMORY_ENCRYPT_OP: {
7214 r = -ENOTTY;
7215 if (!kvm_x86_ops.mem_enc_ioctl)
7216 goto out;
7217
7218 r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
7219 break;
7220 }
7221 case KVM_MEMORY_ENCRYPT_REG_REGION: {
7222 struct kvm_enc_region region;
7223
7224 r = -EFAULT;
7225 if (copy_from_user(®ion, argp, sizeof(region)))
7226 goto out;
7227
7228 r = -ENOTTY;
7229 if (!kvm_x86_ops.mem_enc_register_region)
7230 goto out;
7231
7232 r = static_call(kvm_x86_mem_enc_register_region)(kvm, ®ion);
7233 break;
7234 }
7235 case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7236 struct kvm_enc_region region;
7237
7238 r = -EFAULT;
7239 if (copy_from_user(®ion, argp, sizeof(region)))
7240 goto out;
7241
7242 r = -ENOTTY;
7243 if (!kvm_x86_ops.mem_enc_unregister_region)
7244 goto out;
7245
7246 r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, ®ion);
7247 break;
7248 }
7249 #ifdef CONFIG_KVM_HYPERV
7250 case KVM_HYPERV_EVENTFD: {
7251 struct kvm_hyperv_eventfd hvevfd;
7252
7253 r = -EFAULT;
7254 if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7255 goto out;
7256 r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7257 break;
7258 }
7259 #endif
7260 case KVM_SET_PMU_EVENT_FILTER:
7261 r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7262 break;
7263 case KVM_X86_SET_MSR_FILTER: {
7264 struct kvm_msr_filter __user *user_msr_filter = argp;
7265 struct kvm_msr_filter filter;
7266
7267 if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7268 return -EFAULT;
7269
7270 r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7271 break;
7272 }
7273 default:
7274 r = -ENOTTY;
7275 }
7276 out:
7277 return r;
7278 }
7279
kvm_probe_feature_msr(u32 msr_index)7280 static void kvm_probe_feature_msr(u32 msr_index)
7281 {
7282 struct kvm_msr_entry msr = {
7283 .index = msr_index,
7284 };
7285
7286 if (kvm_get_msr_feature(&msr))
7287 return;
7288
7289 msr_based_features[num_msr_based_features++] = msr_index;
7290 }
7291
kvm_probe_msr_to_save(u32 msr_index)7292 static void kvm_probe_msr_to_save(u32 msr_index)
7293 {
7294 u32 dummy[2];
7295
7296 if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7297 return;
7298
7299 /*
7300 * Even MSRs that are valid in the host may not be exposed to guests in
7301 * some cases.
7302 */
7303 switch (msr_index) {
7304 case MSR_IA32_BNDCFGS:
7305 if (!kvm_mpx_supported())
7306 return;
7307 break;
7308 case MSR_TSC_AUX:
7309 if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7310 !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7311 return;
7312 break;
7313 case MSR_IA32_UMWAIT_CONTROL:
7314 if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7315 return;
7316 break;
7317 case MSR_IA32_RTIT_CTL:
7318 case MSR_IA32_RTIT_STATUS:
7319 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7320 return;
7321 break;
7322 case MSR_IA32_RTIT_CR3_MATCH:
7323 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7324 !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7325 return;
7326 break;
7327 case MSR_IA32_RTIT_OUTPUT_BASE:
7328 case MSR_IA32_RTIT_OUTPUT_MASK:
7329 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7330 (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7331 !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7332 return;
7333 break;
7334 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7335 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7336 (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7337 intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7338 return;
7339 break;
7340 case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7341 if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7342 kvm_pmu_cap.num_counters_gp)
7343 return;
7344 break;
7345 case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7346 if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7347 kvm_pmu_cap.num_counters_gp)
7348 return;
7349 break;
7350 case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7351 if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7352 kvm_pmu_cap.num_counters_fixed)
7353 return;
7354 break;
7355 case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
7356 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
7357 case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
7358 if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
7359 return;
7360 break;
7361 case MSR_IA32_XFD:
7362 case MSR_IA32_XFD_ERR:
7363 if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7364 return;
7365 break;
7366 case MSR_IA32_TSX_CTRL:
7367 if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR))
7368 return;
7369 break;
7370 default:
7371 break;
7372 }
7373
7374 msrs_to_save[num_msrs_to_save++] = msr_index;
7375 }
7376
kvm_init_msr_lists(void)7377 static void kvm_init_msr_lists(void)
7378 {
7379 unsigned i;
7380
7381 BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7382 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7383
7384 num_msrs_to_save = 0;
7385 num_emulated_msrs = 0;
7386 num_msr_based_features = 0;
7387
7388 for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7389 kvm_probe_msr_to_save(msrs_to_save_base[i]);
7390
7391 if (enable_pmu) {
7392 for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7393 kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7394 }
7395
7396 for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7397 if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7398 continue;
7399
7400 emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7401 }
7402
7403 for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++)
7404 kvm_probe_feature_msr(i);
7405
7406 for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++)
7407 kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]);
7408 }
7409
vcpu_mmio_write(struct kvm_vcpu * vcpu,gpa_t addr,int len,const void * v)7410 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7411 const void *v)
7412 {
7413 int handled = 0;
7414 int n;
7415
7416 do {
7417 n = min(len, 8);
7418 if (!(lapic_in_kernel(vcpu) &&
7419 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7420 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7421 break;
7422 handled += n;
7423 addr += n;
7424 len -= n;
7425 v += n;
7426 } while (len);
7427
7428 return handled;
7429 }
7430
vcpu_mmio_read(struct kvm_vcpu * vcpu,gpa_t addr,int len,void * v)7431 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7432 {
7433 int handled = 0;
7434 int n;
7435
7436 do {
7437 n = min(len, 8);
7438 if (!(lapic_in_kernel(vcpu) &&
7439 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7440 addr, n, v))
7441 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7442 break;
7443 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7444 handled += n;
7445 addr += n;
7446 len -= n;
7447 v += n;
7448 } while (len);
7449
7450 return handled;
7451 }
7452
kvm_set_segment(struct kvm_vcpu * vcpu,struct kvm_segment * var,int seg)7453 void kvm_set_segment(struct kvm_vcpu *vcpu,
7454 struct kvm_segment *var, int seg)
7455 {
7456 static_call(kvm_x86_set_segment)(vcpu, var, seg);
7457 }
7458
kvm_get_segment(struct kvm_vcpu * vcpu,struct kvm_segment * var,int seg)7459 void kvm_get_segment(struct kvm_vcpu *vcpu,
7460 struct kvm_segment *var, int seg)
7461 {
7462 static_call(kvm_x86_get_segment)(vcpu, var, seg);
7463 }
7464
translate_nested_gpa(struct kvm_vcpu * vcpu,gpa_t gpa,u64 access,struct x86_exception * exception)7465 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7466 struct x86_exception *exception)
7467 {
7468 struct kvm_mmu *mmu = vcpu->arch.mmu;
7469 gpa_t t_gpa;
7470
7471 BUG_ON(!mmu_is_nested(vcpu));
7472
7473 /* NPT walks are always user-walks */
7474 access |= PFERR_USER_MASK;
7475 t_gpa = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7476
7477 return t_gpa;
7478 }
7479
kvm_mmu_gva_to_gpa_read(struct kvm_vcpu * vcpu,gva_t gva,struct x86_exception * exception)7480 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7481 struct x86_exception *exception)
7482 {
7483 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7484
7485 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7486 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7487 }
7488 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7489
kvm_mmu_gva_to_gpa_write(struct kvm_vcpu * vcpu,gva_t gva,struct x86_exception * exception)7490 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7491 struct x86_exception *exception)
7492 {
7493 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7494
7495 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7496 access |= PFERR_WRITE_MASK;
7497 return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7498 }
7499 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7500
7501 /* uses this to access any guest's mapped memory without checking CPL */
kvm_mmu_gva_to_gpa_system(struct kvm_vcpu * vcpu,gva_t gva,struct x86_exception * exception)7502 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7503 struct x86_exception *exception)
7504 {
7505 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7506
7507 return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7508 }
7509
kvm_read_guest_virt_helper(gva_t addr,void * val,unsigned int bytes,struct kvm_vcpu * vcpu,u64 access,struct x86_exception * exception)7510 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7511 struct kvm_vcpu *vcpu, u64 access,
7512 struct x86_exception *exception)
7513 {
7514 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7515 void *data = val;
7516 int r = X86EMUL_CONTINUE;
7517
7518 while (bytes) {
7519 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7520 unsigned offset = addr & (PAGE_SIZE-1);
7521 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7522 int ret;
7523
7524 if (gpa == INVALID_GPA)
7525 return X86EMUL_PROPAGATE_FAULT;
7526 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7527 offset, toread);
7528 if (ret < 0) {
7529 r = X86EMUL_IO_NEEDED;
7530 goto out;
7531 }
7532
7533 bytes -= toread;
7534 data += toread;
7535 addr += toread;
7536 }
7537 out:
7538 return r;
7539 }
7540
7541 /* used for instruction fetching */
kvm_fetch_guest_virt(struct x86_emulate_ctxt * ctxt,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception)7542 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7543 gva_t addr, void *val, unsigned int bytes,
7544 struct x86_exception *exception)
7545 {
7546 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7547 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7548 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7549 unsigned offset;
7550 int ret;
7551
7552 /* Inline kvm_read_guest_virt_helper for speed. */
7553 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7554 exception);
7555 if (unlikely(gpa == INVALID_GPA))
7556 return X86EMUL_PROPAGATE_FAULT;
7557
7558 offset = addr & (PAGE_SIZE-1);
7559 if (WARN_ON(offset + bytes > PAGE_SIZE))
7560 bytes = (unsigned)PAGE_SIZE - offset;
7561 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7562 offset, bytes);
7563 if (unlikely(ret < 0))
7564 return X86EMUL_IO_NEEDED;
7565
7566 return X86EMUL_CONTINUE;
7567 }
7568
kvm_read_guest_virt(struct kvm_vcpu * vcpu,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception)7569 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7570 gva_t addr, void *val, unsigned int bytes,
7571 struct x86_exception *exception)
7572 {
7573 u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7574
7575 /*
7576 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7577 * is returned, but our callers are not ready for that and they blindly
7578 * call kvm_inject_page_fault. Ensure that they at least do not leak
7579 * uninitialized kernel stack memory into cr2 and error code.
7580 */
7581 memset(exception, 0, sizeof(*exception));
7582 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7583 exception);
7584 }
7585 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7586
emulator_read_std(struct x86_emulate_ctxt * ctxt,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception,bool system)7587 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7588 gva_t addr, void *val, unsigned int bytes,
7589 struct x86_exception *exception, bool system)
7590 {
7591 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7592 u64 access = 0;
7593
7594 if (system)
7595 access |= PFERR_IMPLICIT_ACCESS;
7596 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7597 access |= PFERR_USER_MASK;
7598
7599 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7600 }
7601
kvm_write_guest_virt_helper(gva_t addr,void * val,unsigned int bytes,struct kvm_vcpu * vcpu,u64 access,struct x86_exception * exception)7602 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7603 struct kvm_vcpu *vcpu, u64 access,
7604 struct x86_exception *exception)
7605 {
7606 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7607 void *data = val;
7608 int r = X86EMUL_CONTINUE;
7609
7610 while (bytes) {
7611 gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7612 unsigned offset = addr & (PAGE_SIZE-1);
7613 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7614 int ret;
7615
7616 if (gpa == INVALID_GPA)
7617 return X86EMUL_PROPAGATE_FAULT;
7618 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7619 if (ret < 0) {
7620 r = X86EMUL_IO_NEEDED;
7621 goto out;
7622 }
7623
7624 bytes -= towrite;
7625 data += towrite;
7626 addr += towrite;
7627 }
7628 out:
7629 return r;
7630 }
7631
emulator_write_std(struct x86_emulate_ctxt * ctxt,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception,bool system)7632 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7633 unsigned int bytes, struct x86_exception *exception,
7634 bool system)
7635 {
7636 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7637 u64 access = PFERR_WRITE_MASK;
7638
7639 if (system)
7640 access |= PFERR_IMPLICIT_ACCESS;
7641 else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7642 access |= PFERR_USER_MASK;
7643
7644 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7645 access, exception);
7646 }
7647
kvm_write_guest_virt_system(struct kvm_vcpu * vcpu,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception)7648 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7649 unsigned int bytes, struct x86_exception *exception)
7650 {
7651 /* kvm_write_guest_virt_system can pull in tons of pages. */
7652 vcpu->arch.l1tf_flush_l1d = true;
7653
7654 return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7655 PFERR_WRITE_MASK, exception);
7656 }
7657 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7658
kvm_check_emulate_insn(struct kvm_vcpu * vcpu,int emul_type,void * insn,int insn_len)7659 static int kvm_check_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7660 void *insn, int insn_len)
7661 {
7662 return static_call(kvm_x86_check_emulate_instruction)(vcpu, emul_type,
7663 insn, insn_len);
7664 }
7665
handle_ud(struct kvm_vcpu * vcpu)7666 int handle_ud(struct kvm_vcpu *vcpu)
7667 {
7668 static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7669 int fep_flags = READ_ONCE(force_emulation_prefix);
7670 int emul_type = EMULTYPE_TRAP_UD;
7671 char sig[5]; /* ud2; .ascii "kvm" */
7672 struct x86_exception e;
7673 int r;
7674
7675 r = kvm_check_emulate_insn(vcpu, emul_type, NULL, 0);
7676 if (r != X86EMUL_CONTINUE)
7677 return 1;
7678
7679 if (fep_flags &&
7680 kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7681 sig, sizeof(sig), &e) == 0 &&
7682 memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7683 if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7684 kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7685 kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7686 emul_type = EMULTYPE_TRAP_UD_FORCED;
7687 }
7688
7689 return kvm_emulate_instruction(vcpu, emul_type);
7690 }
7691 EXPORT_SYMBOL_GPL(handle_ud);
7692
vcpu_is_mmio_gpa(struct kvm_vcpu * vcpu,unsigned long gva,gpa_t gpa,bool write)7693 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7694 gpa_t gpa, bool write)
7695 {
7696 /* For APIC access vmexit */
7697 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7698 return 1;
7699
7700 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7701 trace_vcpu_match_mmio(gva, gpa, write, true);
7702 return 1;
7703 }
7704
7705 return 0;
7706 }
7707
vcpu_mmio_gva_to_gpa(struct kvm_vcpu * vcpu,unsigned long gva,gpa_t * gpa,struct x86_exception * exception,bool write)7708 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7709 gpa_t *gpa, struct x86_exception *exception,
7710 bool write)
7711 {
7712 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7713 u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7714 | (write ? PFERR_WRITE_MASK : 0);
7715
7716 /*
7717 * currently PKRU is only applied to ept enabled guest so
7718 * there is no pkey in EPT page table for L1 guest or EPT
7719 * shadow page table for L2 guest.
7720 */
7721 if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7722 !permission_fault(vcpu, vcpu->arch.walk_mmu,
7723 vcpu->arch.mmio_access, 0, access))) {
7724 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7725 (gva & (PAGE_SIZE - 1));
7726 trace_vcpu_match_mmio(gva, *gpa, write, false);
7727 return 1;
7728 }
7729
7730 *gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7731
7732 if (*gpa == INVALID_GPA)
7733 return -1;
7734
7735 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7736 }
7737
emulator_write_phys(struct kvm_vcpu * vcpu,gpa_t gpa,const void * val,int bytes)7738 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7739 const void *val, int bytes)
7740 {
7741 int ret;
7742
7743 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7744 if (ret < 0)
7745 return 0;
7746 kvm_page_track_write(vcpu, gpa, val, bytes);
7747 return 1;
7748 }
7749
7750 struct read_write_emulator_ops {
7751 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7752 int bytes);
7753 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7754 void *val, int bytes);
7755 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7756 int bytes, void *val);
7757 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7758 void *val, int bytes);
7759 bool write;
7760 };
7761
read_prepare(struct kvm_vcpu * vcpu,void * val,int bytes)7762 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7763 {
7764 if (vcpu->mmio_read_completed) {
7765 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7766 vcpu->mmio_fragments[0].gpa, val);
7767 vcpu->mmio_read_completed = 0;
7768 return 1;
7769 }
7770
7771 return 0;
7772 }
7773
read_emulate(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7774 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7775 void *val, int bytes)
7776 {
7777 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7778 }
7779
write_emulate(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7780 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7781 void *val, int bytes)
7782 {
7783 return emulator_write_phys(vcpu, gpa, val, bytes);
7784 }
7785
write_mmio(struct kvm_vcpu * vcpu,gpa_t gpa,int bytes,void * val)7786 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7787 {
7788 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7789 return vcpu_mmio_write(vcpu, gpa, bytes, val);
7790 }
7791
read_exit_mmio(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7792 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7793 void *val, int bytes)
7794 {
7795 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7796 return X86EMUL_IO_NEEDED;
7797 }
7798
write_exit_mmio(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7799 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7800 void *val, int bytes)
7801 {
7802 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7803
7804 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7805 return X86EMUL_CONTINUE;
7806 }
7807
7808 static const struct read_write_emulator_ops read_emultor = {
7809 .read_write_prepare = read_prepare,
7810 .read_write_emulate = read_emulate,
7811 .read_write_mmio = vcpu_mmio_read,
7812 .read_write_exit_mmio = read_exit_mmio,
7813 };
7814
7815 static const struct read_write_emulator_ops write_emultor = {
7816 .read_write_emulate = write_emulate,
7817 .read_write_mmio = write_mmio,
7818 .read_write_exit_mmio = write_exit_mmio,
7819 .write = true,
7820 };
7821
emulator_read_write_onepage(unsigned long addr,void * val,unsigned int bytes,struct x86_exception * exception,struct kvm_vcpu * vcpu,const struct read_write_emulator_ops * ops)7822 static int emulator_read_write_onepage(unsigned long addr, void *val,
7823 unsigned int bytes,
7824 struct x86_exception *exception,
7825 struct kvm_vcpu *vcpu,
7826 const struct read_write_emulator_ops *ops)
7827 {
7828 gpa_t gpa;
7829 int handled, ret;
7830 bool write = ops->write;
7831 struct kvm_mmio_fragment *frag;
7832 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7833
7834 /*
7835 * If the exit was due to a NPF we may already have a GPA.
7836 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7837 * Note, this cannot be used on string operations since string
7838 * operation using rep will only have the initial GPA from the NPF
7839 * occurred.
7840 */
7841 if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7842 (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7843 gpa = ctxt->gpa_val;
7844 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7845 } else {
7846 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7847 if (ret < 0)
7848 return X86EMUL_PROPAGATE_FAULT;
7849 }
7850
7851 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7852 return X86EMUL_CONTINUE;
7853
7854 /*
7855 * Is this MMIO handled locally?
7856 */
7857 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7858 if (handled == bytes)
7859 return X86EMUL_CONTINUE;
7860
7861 gpa += handled;
7862 bytes -= handled;
7863 val += handled;
7864
7865 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7866 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7867 frag->gpa = gpa;
7868 frag->data = val;
7869 frag->len = bytes;
7870 return X86EMUL_CONTINUE;
7871 }
7872
emulator_read_write(struct x86_emulate_ctxt * ctxt,unsigned long addr,void * val,unsigned int bytes,struct x86_exception * exception,const struct read_write_emulator_ops * ops)7873 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7874 unsigned long addr,
7875 void *val, unsigned int bytes,
7876 struct x86_exception *exception,
7877 const struct read_write_emulator_ops *ops)
7878 {
7879 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7880 gpa_t gpa;
7881 int rc;
7882
7883 if (ops->read_write_prepare &&
7884 ops->read_write_prepare(vcpu, val, bytes))
7885 return X86EMUL_CONTINUE;
7886
7887 vcpu->mmio_nr_fragments = 0;
7888
7889 /* Crossing a page boundary? */
7890 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7891 int now;
7892
7893 now = -addr & ~PAGE_MASK;
7894 rc = emulator_read_write_onepage(addr, val, now, exception,
7895 vcpu, ops);
7896
7897 if (rc != X86EMUL_CONTINUE)
7898 return rc;
7899 addr += now;
7900 if (ctxt->mode != X86EMUL_MODE_PROT64)
7901 addr = (u32)addr;
7902 val += now;
7903 bytes -= now;
7904 }
7905
7906 rc = emulator_read_write_onepage(addr, val, bytes, exception,
7907 vcpu, ops);
7908 if (rc != X86EMUL_CONTINUE)
7909 return rc;
7910
7911 if (!vcpu->mmio_nr_fragments)
7912 return rc;
7913
7914 gpa = vcpu->mmio_fragments[0].gpa;
7915
7916 vcpu->mmio_needed = 1;
7917 vcpu->mmio_cur_fragment = 0;
7918
7919 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7920 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7921 vcpu->run->exit_reason = KVM_EXIT_MMIO;
7922 vcpu->run->mmio.phys_addr = gpa;
7923
7924 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7925 }
7926
emulator_read_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,void * val,unsigned int bytes,struct x86_exception * exception)7927 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7928 unsigned long addr,
7929 void *val,
7930 unsigned int bytes,
7931 struct x86_exception *exception)
7932 {
7933 return emulator_read_write(ctxt, addr, val, bytes,
7934 exception, &read_emultor);
7935 }
7936
emulator_write_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,const void * val,unsigned int bytes,struct x86_exception * exception)7937 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7938 unsigned long addr,
7939 const void *val,
7940 unsigned int bytes,
7941 struct x86_exception *exception)
7942 {
7943 return emulator_read_write(ctxt, addr, (void *)val, bytes,
7944 exception, &write_emultor);
7945 }
7946
7947 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7948 (__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7949
emulator_cmpxchg_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,const void * old,const void * new,unsigned int bytes,struct x86_exception * exception)7950 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7951 unsigned long addr,
7952 const void *old,
7953 const void *new,
7954 unsigned int bytes,
7955 struct x86_exception *exception)
7956 {
7957 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7958 u64 page_line_mask;
7959 unsigned long hva;
7960 gpa_t gpa;
7961 int r;
7962
7963 /* guests cmpxchg8b have to be emulated atomically */
7964 if (bytes > 8 || (bytes & (bytes - 1)))
7965 goto emul_write;
7966
7967 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7968
7969 if (gpa == INVALID_GPA ||
7970 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7971 goto emul_write;
7972
7973 /*
7974 * Emulate the atomic as a straight write to avoid #AC if SLD is
7975 * enabled in the host and the access splits a cache line.
7976 */
7977 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7978 page_line_mask = ~(cache_line_size() - 1);
7979 else
7980 page_line_mask = PAGE_MASK;
7981
7982 if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7983 goto emul_write;
7984
7985 hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7986 if (kvm_is_error_hva(hva))
7987 goto emul_write;
7988
7989 hva += offset_in_page(gpa);
7990
7991 switch (bytes) {
7992 case 1:
7993 r = emulator_try_cmpxchg_user(u8, hva, old, new);
7994 break;
7995 case 2:
7996 r = emulator_try_cmpxchg_user(u16, hva, old, new);
7997 break;
7998 case 4:
7999 r = emulator_try_cmpxchg_user(u32, hva, old, new);
8000 break;
8001 case 8:
8002 r = emulator_try_cmpxchg_user(u64, hva, old, new);
8003 break;
8004 default:
8005 BUG();
8006 }
8007
8008 if (r < 0)
8009 return X86EMUL_UNHANDLEABLE;
8010
8011 /*
8012 * Mark the page dirty _before_ checking whether or not the CMPXCHG was
8013 * successful, as the old value is written back on failure. Note, for
8014 * live migration, this is unnecessarily conservative as CMPXCHG writes
8015 * back the original value and the access is atomic, but KVM's ABI is
8016 * that all writes are dirty logged, regardless of the value written.
8017 */
8018 kvm_vcpu_mark_page_dirty(vcpu, gpa_to_gfn(gpa));
8019
8020 if (r)
8021 return X86EMUL_CMPXCHG_FAILED;
8022
8023 kvm_page_track_write(vcpu, gpa, new, bytes);
8024
8025 return X86EMUL_CONTINUE;
8026
8027 emul_write:
8028 pr_warn_once("emulating exchange as write\n");
8029
8030 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
8031 }
8032
emulator_pio_in_out(struct kvm_vcpu * vcpu,int size,unsigned short port,void * data,unsigned int count,bool in)8033 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
8034 unsigned short port, void *data,
8035 unsigned int count, bool in)
8036 {
8037 unsigned i;
8038 int r;
8039
8040 WARN_ON_ONCE(vcpu->arch.pio.count);
8041 for (i = 0; i < count; i++) {
8042 if (in)
8043 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
8044 else
8045 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
8046
8047 if (r) {
8048 if (i == 0)
8049 goto userspace_io;
8050
8051 /*
8052 * Userspace must have unregistered the device while PIO
8053 * was running. Drop writes / read as 0.
8054 */
8055 if (in)
8056 memset(data, 0, size * (count - i));
8057 break;
8058 }
8059
8060 data += size;
8061 }
8062 return 1;
8063
8064 userspace_io:
8065 vcpu->arch.pio.port = port;
8066 vcpu->arch.pio.in = in;
8067 vcpu->arch.pio.count = count;
8068 vcpu->arch.pio.size = size;
8069
8070 if (in)
8071 memset(vcpu->arch.pio_data, 0, size * count);
8072 else
8073 memcpy(vcpu->arch.pio_data, data, size * count);
8074
8075 vcpu->run->exit_reason = KVM_EXIT_IO;
8076 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
8077 vcpu->run->io.size = size;
8078 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
8079 vcpu->run->io.count = count;
8080 vcpu->run->io.port = port;
8081 return 0;
8082 }
8083
emulator_pio_in(struct kvm_vcpu * vcpu,int size,unsigned short port,void * val,unsigned int count)8084 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
8085 unsigned short port, void *val, unsigned int count)
8086 {
8087 int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
8088 if (r)
8089 trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
8090
8091 return r;
8092 }
8093
complete_emulator_pio_in(struct kvm_vcpu * vcpu,void * val)8094 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
8095 {
8096 int size = vcpu->arch.pio.size;
8097 unsigned int count = vcpu->arch.pio.count;
8098 memcpy(val, vcpu->arch.pio_data, size * count);
8099 trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
8100 vcpu->arch.pio.count = 0;
8101 }
8102
emulator_pio_in_emulated(struct x86_emulate_ctxt * ctxt,int size,unsigned short port,void * val,unsigned int count)8103 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
8104 int size, unsigned short port, void *val,
8105 unsigned int count)
8106 {
8107 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8108 if (vcpu->arch.pio.count) {
8109 /*
8110 * Complete a previous iteration that required userspace I/O.
8111 * Note, @count isn't guaranteed to match pio.count as userspace
8112 * can modify ECX before rerunning the vCPU. Ignore any such
8113 * shenanigans as KVM doesn't support modifying the rep count,
8114 * and the emulator ensures @count doesn't overflow the buffer.
8115 */
8116 complete_emulator_pio_in(vcpu, val);
8117 return 1;
8118 }
8119
8120 return emulator_pio_in(vcpu, size, port, val, count);
8121 }
8122
emulator_pio_out(struct kvm_vcpu * vcpu,int size,unsigned short port,const void * val,unsigned int count)8123 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
8124 unsigned short port, const void *val,
8125 unsigned int count)
8126 {
8127 trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
8128 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
8129 }
8130
emulator_pio_out_emulated(struct x86_emulate_ctxt * ctxt,int size,unsigned short port,const void * val,unsigned int count)8131 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
8132 int size, unsigned short port,
8133 const void *val, unsigned int count)
8134 {
8135 return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
8136 }
8137
get_segment_base(struct kvm_vcpu * vcpu,int seg)8138 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
8139 {
8140 return static_call(kvm_x86_get_segment_base)(vcpu, seg);
8141 }
8142
emulator_invlpg(struct x86_emulate_ctxt * ctxt,ulong address)8143 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
8144 {
8145 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
8146 }
8147
kvm_emulate_wbinvd_noskip(struct kvm_vcpu * vcpu)8148 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
8149 {
8150 if (!need_emulate_wbinvd(vcpu))
8151 return X86EMUL_CONTINUE;
8152
8153 if (static_call(kvm_x86_has_wbinvd_exit)()) {
8154 int cpu = get_cpu();
8155
8156 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
8157 on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
8158 wbinvd_ipi, NULL, 1);
8159 put_cpu();
8160 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
8161 } else
8162 wbinvd();
8163 return X86EMUL_CONTINUE;
8164 }
8165
kvm_emulate_wbinvd(struct kvm_vcpu * vcpu)8166 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
8167 {
8168 kvm_emulate_wbinvd_noskip(vcpu);
8169 return kvm_skip_emulated_instruction(vcpu);
8170 }
8171 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
8172
8173
8174
emulator_wbinvd(struct x86_emulate_ctxt * ctxt)8175 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
8176 {
8177 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
8178 }
8179
emulator_get_dr(struct x86_emulate_ctxt * ctxt,int dr,unsigned long * dest)8180 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
8181 unsigned long *dest)
8182 {
8183 kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
8184 }
8185
emulator_set_dr(struct x86_emulate_ctxt * ctxt,int dr,unsigned long value)8186 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
8187 unsigned long value)
8188 {
8189
8190 return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
8191 }
8192
mk_cr_64(u64 curr_cr,u32 new_val)8193 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
8194 {
8195 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
8196 }
8197
emulator_get_cr(struct x86_emulate_ctxt * ctxt,int cr)8198 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
8199 {
8200 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8201 unsigned long value;
8202
8203 switch (cr) {
8204 case 0:
8205 value = kvm_read_cr0(vcpu);
8206 break;
8207 case 2:
8208 value = vcpu->arch.cr2;
8209 break;
8210 case 3:
8211 value = kvm_read_cr3(vcpu);
8212 break;
8213 case 4:
8214 value = kvm_read_cr4(vcpu);
8215 break;
8216 case 8:
8217 value = kvm_get_cr8(vcpu);
8218 break;
8219 default:
8220 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8221 return 0;
8222 }
8223
8224 return value;
8225 }
8226
emulator_set_cr(struct x86_emulate_ctxt * ctxt,int cr,ulong val)8227 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
8228 {
8229 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8230 int res = 0;
8231
8232 switch (cr) {
8233 case 0:
8234 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
8235 break;
8236 case 2:
8237 vcpu->arch.cr2 = val;
8238 break;
8239 case 3:
8240 res = kvm_set_cr3(vcpu, val);
8241 break;
8242 case 4:
8243 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8244 break;
8245 case 8:
8246 res = kvm_set_cr8(vcpu, val);
8247 break;
8248 default:
8249 kvm_err("%s: unexpected cr %u\n", __func__, cr);
8250 res = -1;
8251 }
8252
8253 return res;
8254 }
8255
emulator_get_cpl(struct x86_emulate_ctxt * ctxt)8256 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
8257 {
8258 return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
8259 }
8260
emulator_get_gdt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8261 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8262 {
8263 static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8264 }
8265
emulator_get_idt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8266 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8267 {
8268 static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8269 }
8270
emulator_set_gdt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8271 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8272 {
8273 static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8274 }
8275
emulator_set_idt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8276 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8277 {
8278 static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8279 }
8280
emulator_get_cached_segment_base(struct x86_emulate_ctxt * ctxt,int seg)8281 static unsigned long emulator_get_cached_segment_base(
8282 struct x86_emulate_ctxt *ctxt, int seg)
8283 {
8284 return get_segment_base(emul_to_vcpu(ctxt), seg);
8285 }
8286
emulator_get_segment(struct x86_emulate_ctxt * ctxt,u16 * selector,struct desc_struct * desc,u32 * base3,int seg)8287 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8288 struct desc_struct *desc, u32 *base3,
8289 int seg)
8290 {
8291 struct kvm_segment var;
8292
8293 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8294 *selector = var.selector;
8295
8296 if (var.unusable) {
8297 memset(desc, 0, sizeof(*desc));
8298 if (base3)
8299 *base3 = 0;
8300 return false;
8301 }
8302
8303 if (var.g)
8304 var.limit >>= 12;
8305 set_desc_limit(desc, var.limit);
8306 set_desc_base(desc, (unsigned long)var.base);
8307 #ifdef CONFIG_X86_64
8308 if (base3)
8309 *base3 = var.base >> 32;
8310 #endif
8311 desc->type = var.type;
8312 desc->s = var.s;
8313 desc->dpl = var.dpl;
8314 desc->p = var.present;
8315 desc->avl = var.avl;
8316 desc->l = var.l;
8317 desc->d = var.db;
8318 desc->g = var.g;
8319
8320 return true;
8321 }
8322
emulator_set_segment(struct x86_emulate_ctxt * ctxt,u16 selector,struct desc_struct * desc,u32 base3,int seg)8323 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8324 struct desc_struct *desc, u32 base3,
8325 int seg)
8326 {
8327 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8328 struct kvm_segment var;
8329
8330 var.selector = selector;
8331 var.base = get_desc_base(desc);
8332 #ifdef CONFIG_X86_64
8333 var.base |= ((u64)base3) << 32;
8334 #endif
8335 var.limit = get_desc_limit(desc);
8336 if (desc->g)
8337 var.limit = (var.limit << 12) | 0xfff;
8338 var.type = desc->type;
8339 var.dpl = desc->dpl;
8340 var.db = desc->d;
8341 var.s = desc->s;
8342 var.l = desc->l;
8343 var.g = desc->g;
8344 var.avl = desc->avl;
8345 var.present = desc->p;
8346 var.unusable = !var.present;
8347 var.padding = 0;
8348
8349 kvm_set_segment(vcpu, &var, seg);
8350 return;
8351 }
8352
emulator_get_msr_with_filter(struct x86_emulate_ctxt * ctxt,u32 msr_index,u64 * pdata)8353 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8354 u32 msr_index, u64 *pdata)
8355 {
8356 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8357 int r;
8358
8359 r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8360 if (r < 0)
8361 return X86EMUL_UNHANDLEABLE;
8362
8363 if (r) {
8364 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8365 complete_emulated_rdmsr, r))
8366 return X86EMUL_IO_NEEDED;
8367
8368 trace_kvm_msr_read_ex(msr_index);
8369 return X86EMUL_PROPAGATE_FAULT;
8370 }
8371
8372 trace_kvm_msr_read(msr_index, *pdata);
8373 return X86EMUL_CONTINUE;
8374 }
8375
emulator_set_msr_with_filter(struct x86_emulate_ctxt * ctxt,u32 msr_index,u64 data)8376 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8377 u32 msr_index, u64 data)
8378 {
8379 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8380 int r;
8381
8382 r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8383 if (r < 0)
8384 return X86EMUL_UNHANDLEABLE;
8385
8386 if (r) {
8387 if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8388 complete_emulated_msr_access, r))
8389 return X86EMUL_IO_NEEDED;
8390
8391 trace_kvm_msr_write_ex(msr_index, data);
8392 return X86EMUL_PROPAGATE_FAULT;
8393 }
8394
8395 trace_kvm_msr_write(msr_index, data);
8396 return X86EMUL_CONTINUE;
8397 }
8398
emulator_get_msr(struct x86_emulate_ctxt * ctxt,u32 msr_index,u64 * pdata)8399 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8400 u32 msr_index, u64 *pdata)
8401 {
8402 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8403 }
8404
emulator_check_pmc(struct x86_emulate_ctxt * ctxt,u32 pmc)8405 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8406 u32 pmc)
8407 {
8408 if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8409 return 0;
8410 return -EINVAL;
8411 }
8412
emulator_read_pmc(struct x86_emulate_ctxt * ctxt,u32 pmc,u64 * pdata)8413 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8414 u32 pmc, u64 *pdata)
8415 {
8416 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8417 }
8418
emulator_halt(struct x86_emulate_ctxt * ctxt)8419 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8420 {
8421 emul_to_vcpu(ctxt)->arch.halt_request = 1;
8422 }
8423
emulator_intercept(struct x86_emulate_ctxt * ctxt,struct x86_instruction_info * info,enum x86_intercept_stage stage)8424 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8425 struct x86_instruction_info *info,
8426 enum x86_intercept_stage stage)
8427 {
8428 return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8429 &ctxt->exception);
8430 }
8431
emulator_get_cpuid(struct x86_emulate_ctxt * ctxt,u32 * eax,u32 * ebx,u32 * ecx,u32 * edx,bool exact_only)8432 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8433 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8434 bool exact_only)
8435 {
8436 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8437 }
8438
emulator_guest_has_movbe(struct x86_emulate_ctxt * ctxt)8439 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8440 {
8441 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8442 }
8443
emulator_guest_has_fxsr(struct x86_emulate_ctxt * ctxt)8444 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8445 {
8446 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8447 }
8448
emulator_guest_has_rdpid(struct x86_emulate_ctxt * ctxt)8449 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8450 {
8451 return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8452 }
8453
emulator_read_gpr(struct x86_emulate_ctxt * ctxt,unsigned reg)8454 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8455 {
8456 return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8457 }
8458
emulator_write_gpr(struct x86_emulate_ctxt * ctxt,unsigned reg,ulong val)8459 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8460 {
8461 kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8462 }
8463
emulator_set_nmi_mask(struct x86_emulate_ctxt * ctxt,bool masked)8464 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8465 {
8466 static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8467 }
8468
emulator_is_smm(struct x86_emulate_ctxt * ctxt)8469 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8470 {
8471 return is_smm(emul_to_vcpu(ctxt));
8472 }
8473
emulator_is_guest_mode(struct x86_emulate_ctxt * ctxt)8474 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8475 {
8476 return is_guest_mode(emul_to_vcpu(ctxt));
8477 }
8478
8479 #ifndef CONFIG_KVM_SMM
emulator_leave_smm(struct x86_emulate_ctxt * ctxt)8480 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8481 {
8482 WARN_ON_ONCE(1);
8483 return X86EMUL_UNHANDLEABLE;
8484 }
8485 #endif
8486
emulator_triple_fault(struct x86_emulate_ctxt * ctxt)8487 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8488 {
8489 kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8490 }
8491
emulator_set_xcr(struct x86_emulate_ctxt * ctxt,u32 index,u64 xcr)8492 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8493 {
8494 return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8495 }
8496
emulator_vm_bugged(struct x86_emulate_ctxt * ctxt)8497 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8498 {
8499 struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8500
8501 if (!kvm->vm_bugged)
8502 kvm_vm_bugged(kvm);
8503 }
8504
emulator_get_untagged_addr(struct x86_emulate_ctxt * ctxt,gva_t addr,unsigned int flags)8505 static gva_t emulator_get_untagged_addr(struct x86_emulate_ctxt *ctxt,
8506 gva_t addr, unsigned int flags)
8507 {
8508 if (!kvm_x86_ops.get_untagged_addr)
8509 return addr;
8510
8511 return static_call(kvm_x86_get_untagged_addr)(emul_to_vcpu(ctxt), addr, flags);
8512 }
8513
8514 static const struct x86_emulate_ops emulate_ops = {
8515 .vm_bugged = emulator_vm_bugged,
8516 .read_gpr = emulator_read_gpr,
8517 .write_gpr = emulator_write_gpr,
8518 .read_std = emulator_read_std,
8519 .write_std = emulator_write_std,
8520 .fetch = kvm_fetch_guest_virt,
8521 .read_emulated = emulator_read_emulated,
8522 .write_emulated = emulator_write_emulated,
8523 .cmpxchg_emulated = emulator_cmpxchg_emulated,
8524 .invlpg = emulator_invlpg,
8525 .pio_in_emulated = emulator_pio_in_emulated,
8526 .pio_out_emulated = emulator_pio_out_emulated,
8527 .get_segment = emulator_get_segment,
8528 .set_segment = emulator_set_segment,
8529 .get_cached_segment_base = emulator_get_cached_segment_base,
8530 .get_gdt = emulator_get_gdt,
8531 .get_idt = emulator_get_idt,
8532 .set_gdt = emulator_set_gdt,
8533 .set_idt = emulator_set_idt,
8534 .get_cr = emulator_get_cr,
8535 .set_cr = emulator_set_cr,
8536 .cpl = emulator_get_cpl,
8537 .get_dr = emulator_get_dr,
8538 .set_dr = emulator_set_dr,
8539 .set_msr_with_filter = emulator_set_msr_with_filter,
8540 .get_msr_with_filter = emulator_get_msr_with_filter,
8541 .get_msr = emulator_get_msr,
8542 .check_pmc = emulator_check_pmc,
8543 .read_pmc = emulator_read_pmc,
8544 .halt = emulator_halt,
8545 .wbinvd = emulator_wbinvd,
8546 .fix_hypercall = emulator_fix_hypercall,
8547 .intercept = emulator_intercept,
8548 .get_cpuid = emulator_get_cpuid,
8549 .guest_has_movbe = emulator_guest_has_movbe,
8550 .guest_has_fxsr = emulator_guest_has_fxsr,
8551 .guest_has_rdpid = emulator_guest_has_rdpid,
8552 .set_nmi_mask = emulator_set_nmi_mask,
8553 .is_smm = emulator_is_smm,
8554 .is_guest_mode = emulator_is_guest_mode,
8555 .leave_smm = emulator_leave_smm,
8556 .triple_fault = emulator_triple_fault,
8557 .set_xcr = emulator_set_xcr,
8558 .get_untagged_addr = emulator_get_untagged_addr,
8559 };
8560
toggle_interruptibility(struct kvm_vcpu * vcpu,u32 mask)8561 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8562 {
8563 u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8564 /*
8565 * an sti; sti; sequence only disable interrupts for the first
8566 * instruction. So, if the last instruction, be it emulated or
8567 * not, left the system with the INT_STI flag enabled, it
8568 * means that the last instruction is an sti. We should not
8569 * leave the flag on in this case. The same goes for mov ss
8570 */
8571 if (int_shadow & mask)
8572 mask = 0;
8573 if (unlikely(int_shadow || mask)) {
8574 static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8575 if (!mask)
8576 kvm_make_request(KVM_REQ_EVENT, vcpu);
8577 }
8578 }
8579
inject_emulated_exception(struct kvm_vcpu * vcpu)8580 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8581 {
8582 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8583
8584 if (ctxt->exception.vector == PF_VECTOR)
8585 kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8586 else if (ctxt->exception.error_code_valid)
8587 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8588 ctxt->exception.error_code);
8589 else
8590 kvm_queue_exception(vcpu, ctxt->exception.vector);
8591 }
8592
alloc_emulate_ctxt(struct kvm_vcpu * vcpu)8593 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8594 {
8595 struct x86_emulate_ctxt *ctxt;
8596
8597 ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8598 if (!ctxt) {
8599 pr_err("failed to allocate vcpu's emulator\n");
8600 return NULL;
8601 }
8602
8603 ctxt->vcpu = vcpu;
8604 ctxt->ops = &emulate_ops;
8605 vcpu->arch.emulate_ctxt = ctxt;
8606
8607 return ctxt;
8608 }
8609
init_emulate_ctxt(struct kvm_vcpu * vcpu)8610 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8611 {
8612 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8613 int cs_db, cs_l;
8614
8615 static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8616
8617 ctxt->gpa_available = false;
8618 ctxt->eflags = kvm_get_rflags(vcpu);
8619 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8620
8621 ctxt->eip = kvm_rip_read(vcpu);
8622 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
8623 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
8624 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
8625 cs_db ? X86EMUL_MODE_PROT32 :
8626 X86EMUL_MODE_PROT16;
8627 ctxt->interruptibility = 0;
8628 ctxt->have_exception = false;
8629 ctxt->exception.vector = -1;
8630 ctxt->perm_ok = false;
8631
8632 init_decode_cache(ctxt);
8633 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8634 }
8635
kvm_inject_realmode_interrupt(struct kvm_vcpu * vcpu,int irq,int inc_eip)8636 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8637 {
8638 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8639 int ret;
8640
8641 init_emulate_ctxt(vcpu);
8642
8643 ctxt->op_bytes = 2;
8644 ctxt->ad_bytes = 2;
8645 ctxt->_eip = ctxt->eip + inc_eip;
8646 ret = emulate_int_real(ctxt, irq);
8647
8648 if (ret != X86EMUL_CONTINUE) {
8649 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8650 } else {
8651 ctxt->eip = ctxt->_eip;
8652 kvm_rip_write(vcpu, ctxt->eip);
8653 kvm_set_rflags(vcpu, ctxt->eflags);
8654 }
8655 }
8656 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8657
prepare_emulation_failure_exit(struct kvm_vcpu * vcpu,u64 * data,u8 ndata,u8 * insn_bytes,u8 insn_size)8658 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8659 u8 ndata, u8 *insn_bytes, u8 insn_size)
8660 {
8661 struct kvm_run *run = vcpu->run;
8662 u64 info[5];
8663 u8 info_start;
8664
8665 /*
8666 * Zero the whole array used to retrieve the exit info, as casting to
8667 * u32 for select entries will leave some chunks uninitialized.
8668 */
8669 memset(&info, 0, sizeof(info));
8670
8671 static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8672 &info[2], (u32 *)&info[3],
8673 (u32 *)&info[4]);
8674
8675 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8676 run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8677
8678 /*
8679 * There's currently space for 13 entries, but 5 are used for the exit
8680 * reason and info. Restrict to 4 to reduce the maintenance burden
8681 * when expanding kvm_run.emulation_failure in the future.
8682 */
8683 if (WARN_ON_ONCE(ndata > 4))
8684 ndata = 4;
8685
8686 /* Always include the flags as a 'data' entry. */
8687 info_start = 1;
8688 run->emulation_failure.flags = 0;
8689
8690 if (insn_size) {
8691 BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8692 sizeof(run->emulation_failure.insn_bytes) != 16));
8693 info_start += 2;
8694 run->emulation_failure.flags |=
8695 KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8696 run->emulation_failure.insn_size = insn_size;
8697 memset(run->emulation_failure.insn_bytes, 0x90,
8698 sizeof(run->emulation_failure.insn_bytes));
8699 memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8700 }
8701
8702 memcpy(&run->internal.data[info_start], info, sizeof(info));
8703 memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8704 ndata * sizeof(data[0]));
8705
8706 run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8707 }
8708
prepare_emulation_ctxt_failure_exit(struct kvm_vcpu * vcpu)8709 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8710 {
8711 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8712
8713 prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8714 ctxt->fetch.end - ctxt->fetch.data);
8715 }
8716
__kvm_prepare_emulation_failure_exit(struct kvm_vcpu * vcpu,u64 * data,u8 ndata)8717 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8718 u8 ndata)
8719 {
8720 prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8721 }
8722 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8723
kvm_prepare_emulation_failure_exit(struct kvm_vcpu * vcpu)8724 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8725 {
8726 __kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8727 }
8728 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8729
handle_emulation_failure(struct kvm_vcpu * vcpu,int emulation_type)8730 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8731 {
8732 struct kvm *kvm = vcpu->kvm;
8733
8734 ++vcpu->stat.insn_emulation_fail;
8735 trace_kvm_emulate_insn_failed(vcpu);
8736
8737 if (emulation_type & EMULTYPE_VMWARE_GP) {
8738 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8739 return 1;
8740 }
8741
8742 if (kvm->arch.exit_on_emulation_error ||
8743 (emulation_type & EMULTYPE_SKIP)) {
8744 prepare_emulation_ctxt_failure_exit(vcpu);
8745 return 0;
8746 }
8747
8748 kvm_queue_exception(vcpu, UD_VECTOR);
8749
8750 if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8751 prepare_emulation_ctxt_failure_exit(vcpu);
8752 return 0;
8753 }
8754
8755 return 1;
8756 }
8757
reexecute_instruction(struct kvm_vcpu * vcpu,gpa_t cr2_or_gpa,int emulation_type)8758 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8759 int emulation_type)
8760 {
8761 gpa_t gpa = cr2_or_gpa;
8762 kvm_pfn_t pfn;
8763
8764 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8765 return false;
8766
8767 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8768 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8769 return false;
8770
8771 if (!vcpu->arch.mmu->root_role.direct) {
8772 /*
8773 * Write permission should be allowed since only
8774 * write access need to be emulated.
8775 */
8776 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8777
8778 /*
8779 * If the mapping is invalid in guest, let cpu retry
8780 * it to generate fault.
8781 */
8782 if (gpa == INVALID_GPA)
8783 return true;
8784 }
8785
8786 /*
8787 * Do not retry the unhandleable instruction if it faults on the
8788 * readonly host memory, otherwise it will goto a infinite loop:
8789 * retry instruction -> write #PF -> emulation fail -> retry
8790 * instruction -> ...
8791 */
8792 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8793
8794 /*
8795 * If the instruction failed on the error pfn, it can not be fixed,
8796 * report the error to userspace.
8797 */
8798 if (is_error_noslot_pfn(pfn))
8799 return false;
8800
8801 kvm_release_pfn_clean(pfn);
8802
8803 /* The instructions are well-emulated on direct mmu. */
8804 if (vcpu->arch.mmu->root_role.direct) {
8805 unsigned int indirect_shadow_pages;
8806
8807 write_lock(&vcpu->kvm->mmu_lock);
8808 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8809 write_unlock(&vcpu->kvm->mmu_lock);
8810
8811 if (indirect_shadow_pages)
8812 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8813
8814 return true;
8815 }
8816
8817 /*
8818 * if emulation was due to access to shadowed page table
8819 * and it failed try to unshadow page and re-enter the
8820 * guest to let CPU execute the instruction.
8821 */
8822 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8823
8824 /*
8825 * If the access faults on its page table, it can not
8826 * be fixed by unprotecting shadow page and it should
8827 * be reported to userspace.
8828 */
8829 return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8830 }
8831
retry_instruction(struct x86_emulate_ctxt * ctxt,gpa_t cr2_or_gpa,int emulation_type)8832 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8833 gpa_t cr2_or_gpa, int emulation_type)
8834 {
8835 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8836 unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8837
8838 last_retry_eip = vcpu->arch.last_retry_eip;
8839 last_retry_addr = vcpu->arch.last_retry_addr;
8840
8841 /*
8842 * If the emulation is caused by #PF and it is non-page_table
8843 * writing instruction, it means the VM-EXIT is caused by shadow
8844 * page protected, we can zap the shadow page and retry this
8845 * instruction directly.
8846 *
8847 * Note: if the guest uses a non-page-table modifying instruction
8848 * on the PDE that points to the instruction, then we will unmap
8849 * the instruction and go to an infinite loop. So, we cache the
8850 * last retried eip and the last fault address, if we meet the eip
8851 * and the address again, we can break out of the potential infinite
8852 * loop.
8853 */
8854 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8855
8856 if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8857 return false;
8858
8859 if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8860 WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8861 return false;
8862
8863 if (x86_page_table_writing_insn(ctxt))
8864 return false;
8865
8866 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8867 return false;
8868
8869 vcpu->arch.last_retry_eip = ctxt->eip;
8870 vcpu->arch.last_retry_addr = cr2_or_gpa;
8871
8872 if (!vcpu->arch.mmu->root_role.direct)
8873 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8874
8875 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8876
8877 return true;
8878 }
8879
8880 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8881 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8882
kvm_vcpu_check_hw_bp(unsigned long addr,u32 type,u32 dr7,unsigned long * db)8883 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8884 unsigned long *db)
8885 {
8886 u32 dr6 = 0;
8887 int i;
8888 u32 enable, rwlen;
8889
8890 enable = dr7;
8891 rwlen = dr7 >> 16;
8892 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8893 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8894 dr6 |= (1 << i);
8895 return dr6;
8896 }
8897
kvm_vcpu_do_singlestep(struct kvm_vcpu * vcpu)8898 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8899 {
8900 struct kvm_run *kvm_run = vcpu->run;
8901
8902 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8903 kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8904 kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8905 kvm_run->debug.arch.exception = DB_VECTOR;
8906 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8907 return 0;
8908 }
8909 kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8910 return 1;
8911 }
8912
kvm_skip_emulated_instruction(struct kvm_vcpu * vcpu)8913 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8914 {
8915 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8916 int r;
8917
8918 r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8919 if (unlikely(!r))
8920 return 0;
8921
8922 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8923
8924 /*
8925 * rflags is the old, "raw" value of the flags. The new value has
8926 * not been saved yet.
8927 *
8928 * This is correct even for TF set by the guest, because "the
8929 * processor will not generate this exception after the instruction
8930 * that sets the TF flag".
8931 */
8932 if (unlikely(rflags & X86_EFLAGS_TF))
8933 r = kvm_vcpu_do_singlestep(vcpu);
8934 return r;
8935 }
8936 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8937
kvm_is_code_breakpoint_inhibited(struct kvm_vcpu * vcpu)8938 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8939 {
8940 u32 shadow;
8941
8942 if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8943 return true;
8944
8945 /*
8946 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8947 * but AMD CPUs do not. MOV/POP SS blocking is rare, check that first
8948 * to avoid the relatively expensive CPUID lookup.
8949 */
8950 shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8951 return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8952 guest_cpuid_is_intel(vcpu);
8953 }
8954
kvm_vcpu_check_code_breakpoint(struct kvm_vcpu * vcpu,int emulation_type,int * r)8955 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8956 int emulation_type, int *r)
8957 {
8958 WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8959
8960 /*
8961 * Do not check for code breakpoints if hardware has already done the
8962 * checks, as inferred from the emulation type. On NO_DECODE and SKIP,
8963 * the instruction has passed all exception checks, and all intercepted
8964 * exceptions that trigger emulation have lower priority than code
8965 * breakpoints, i.e. the fact that the intercepted exception occurred
8966 * means any code breakpoints have already been serviced.
8967 *
8968 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8969 * hardware has checked the RIP of the magic prefix, but not the RIP of
8970 * the instruction being emulated. The intent of forced emulation is
8971 * to behave as if KVM intercepted the instruction without an exception
8972 * and without a prefix.
8973 */
8974 if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8975 EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8976 return false;
8977
8978 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8979 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8980 struct kvm_run *kvm_run = vcpu->run;
8981 unsigned long eip = kvm_get_linear_rip(vcpu);
8982 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8983 vcpu->arch.guest_debug_dr7,
8984 vcpu->arch.eff_db);
8985
8986 if (dr6 != 0) {
8987 kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8988 kvm_run->debug.arch.pc = eip;
8989 kvm_run->debug.arch.exception = DB_VECTOR;
8990 kvm_run->exit_reason = KVM_EXIT_DEBUG;
8991 *r = 0;
8992 return true;
8993 }
8994 }
8995
8996 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8997 !kvm_is_code_breakpoint_inhibited(vcpu)) {
8998 unsigned long eip = kvm_get_linear_rip(vcpu);
8999 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
9000 vcpu->arch.dr7,
9001 vcpu->arch.db);
9002
9003 if (dr6 != 0) {
9004 kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
9005 *r = 1;
9006 return true;
9007 }
9008 }
9009
9010 return false;
9011 }
9012
is_vmware_backdoor_opcode(struct x86_emulate_ctxt * ctxt)9013 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
9014 {
9015 switch (ctxt->opcode_len) {
9016 case 1:
9017 switch (ctxt->b) {
9018 case 0xe4: /* IN */
9019 case 0xe5:
9020 case 0xec:
9021 case 0xed:
9022 case 0xe6: /* OUT */
9023 case 0xe7:
9024 case 0xee:
9025 case 0xef:
9026 case 0x6c: /* INS */
9027 case 0x6d:
9028 case 0x6e: /* OUTS */
9029 case 0x6f:
9030 return true;
9031 }
9032 break;
9033 case 2:
9034 switch (ctxt->b) {
9035 case 0x33: /* RDPMC */
9036 return true;
9037 }
9038 break;
9039 }
9040
9041 return false;
9042 }
9043
9044 /*
9045 * Decode an instruction for emulation. The caller is responsible for handling
9046 * code breakpoints. Note, manually detecting code breakpoints is unnecessary
9047 * (and wrong) when emulating on an intercepted fault-like exception[*], as
9048 * code breakpoints have higher priority and thus have already been done by
9049 * hardware.
9050 *
9051 * [*] Except #MC, which is higher priority, but KVM should never emulate in
9052 * response to a machine check.
9053 */
x86_decode_emulated_instruction(struct kvm_vcpu * vcpu,int emulation_type,void * insn,int insn_len)9054 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
9055 void *insn, int insn_len)
9056 {
9057 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9058 int r;
9059
9060 init_emulate_ctxt(vcpu);
9061
9062 r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
9063
9064 trace_kvm_emulate_insn_start(vcpu);
9065 ++vcpu->stat.insn_emulation;
9066
9067 return r;
9068 }
9069 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
9070
x86_emulate_instruction(struct kvm_vcpu * vcpu,gpa_t cr2_or_gpa,int emulation_type,void * insn,int insn_len)9071 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
9072 int emulation_type, void *insn, int insn_len)
9073 {
9074 int r;
9075 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
9076 bool writeback = true;
9077
9078 r = kvm_check_emulate_insn(vcpu, emulation_type, insn, insn_len);
9079 if (r != X86EMUL_CONTINUE) {
9080 if (r == X86EMUL_RETRY_INSTR || r == X86EMUL_PROPAGATE_FAULT)
9081 return 1;
9082
9083 WARN_ON_ONCE(r != X86EMUL_UNHANDLEABLE);
9084 return handle_emulation_failure(vcpu, emulation_type);
9085 }
9086
9087 vcpu->arch.l1tf_flush_l1d = true;
9088
9089 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
9090 kvm_clear_exception_queue(vcpu);
9091
9092 /*
9093 * Return immediately if RIP hits a code breakpoint, such #DBs
9094 * are fault-like and are higher priority than any faults on
9095 * the code fetch itself.
9096 */
9097 if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
9098 return r;
9099
9100 r = x86_decode_emulated_instruction(vcpu, emulation_type,
9101 insn, insn_len);
9102 if (r != EMULATION_OK) {
9103 if ((emulation_type & EMULTYPE_TRAP_UD) ||
9104 (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
9105 kvm_queue_exception(vcpu, UD_VECTOR);
9106 return 1;
9107 }
9108 if (reexecute_instruction(vcpu, cr2_or_gpa,
9109 emulation_type))
9110 return 1;
9111
9112 if (ctxt->have_exception &&
9113 !(emulation_type & EMULTYPE_SKIP)) {
9114 /*
9115 * #UD should result in just EMULATION_FAILED, and trap-like
9116 * exception should not be encountered during decode.
9117 */
9118 WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
9119 exception_type(ctxt->exception.vector) == EXCPT_TRAP);
9120 inject_emulated_exception(vcpu);
9121 return 1;
9122 }
9123 return handle_emulation_failure(vcpu, emulation_type);
9124 }
9125 }
9126
9127 if ((emulation_type & EMULTYPE_VMWARE_GP) &&
9128 !is_vmware_backdoor_opcode(ctxt)) {
9129 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
9130 return 1;
9131 }
9132
9133 /*
9134 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
9135 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
9136 * The caller is responsible for updating interruptibility state and
9137 * injecting single-step #DBs.
9138 */
9139 if (emulation_type & EMULTYPE_SKIP) {
9140 if (ctxt->mode != X86EMUL_MODE_PROT64)
9141 ctxt->eip = (u32)ctxt->_eip;
9142 else
9143 ctxt->eip = ctxt->_eip;
9144
9145 if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
9146 r = 1;
9147 goto writeback;
9148 }
9149
9150 kvm_rip_write(vcpu, ctxt->eip);
9151 if (ctxt->eflags & X86_EFLAGS_RF)
9152 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
9153 return 1;
9154 }
9155
9156 if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
9157 return 1;
9158
9159 /* this is needed for vmware backdoor interface to work since it
9160 changes registers values during IO operation */
9161 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
9162 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9163 emulator_invalidate_register_cache(ctxt);
9164 }
9165
9166 restart:
9167 if (emulation_type & EMULTYPE_PF) {
9168 /* Save the faulting GPA (cr2) in the address field */
9169 ctxt->exception.address = cr2_or_gpa;
9170
9171 /* With shadow page tables, cr2 contains a GVA or nGPA. */
9172 if (vcpu->arch.mmu->root_role.direct) {
9173 ctxt->gpa_available = true;
9174 ctxt->gpa_val = cr2_or_gpa;
9175 }
9176 } else {
9177 /* Sanitize the address out of an abundance of paranoia. */
9178 ctxt->exception.address = 0;
9179 }
9180
9181 r = x86_emulate_insn(ctxt);
9182
9183 if (r == EMULATION_INTERCEPTED)
9184 return 1;
9185
9186 if (r == EMULATION_FAILED) {
9187 if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
9188 return 1;
9189
9190 return handle_emulation_failure(vcpu, emulation_type);
9191 }
9192
9193 if (ctxt->have_exception) {
9194 WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write);
9195 vcpu->mmio_needed = false;
9196 r = 1;
9197 inject_emulated_exception(vcpu);
9198 } else if (vcpu->arch.pio.count) {
9199 if (!vcpu->arch.pio.in) {
9200 /* FIXME: return into emulator if single-stepping. */
9201 vcpu->arch.pio.count = 0;
9202 } else {
9203 writeback = false;
9204 vcpu->arch.complete_userspace_io = complete_emulated_pio;
9205 }
9206 r = 0;
9207 } else if (vcpu->mmio_needed) {
9208 ++vcpu->stat.mmio_exits;
9209
9210 if (!vcpu->mmio_is_write)
9211 writeback = false;
9212 r = 0;
9213 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9214 } else if (vcpu->arch.complete_userspace_io) {
9215 writeback = false;
9216 r = 0;
9217 } else if (r == EMULATION_RESTART)
9218 goto restart;
9219 else
9220 r = 1;
9221
9222 writeback:
9223 if (writeback) {
9224 unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
9225 toggle_interruptibility(vcpu, ctxt->interruptibility);
9226 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9227
9228 /*
9229 * Note, EXCPT_DB is assumed to be fault-like as the emulator
9230 * only supports code breakpoints and general detect #DB, both
9231 * of which are fault-like.
9232 */
9233 if (!ctxt->have_exception ||
9234 exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
9235 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
9236 if (ctxt->is_branch)
9237 kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
9238 kvm_rip_write(vcpu, ctxt->eip);
9239 if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
9240 r = kvm_vcpu_do_singlestep(vcpu);
9241 static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
9242 __kvm_set_rflags(vcpu, ctxt->eflags);
9243 }
9244
9245 /*
9246 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
9247 * do nothing, and it will be requested again as soon as
9248 * the shadow expires. But we still need to check here,
9249 * because POPF has no interrupt shadow.
9250 */
9251 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9252 kvm_make_request(KVM_REQ_EVENT, vcpu);
9253 } else
9254 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9255
9256 return r;
9257 }
9258
kvm_emulate_instruction(struct kvm_vcpu * vcpu,int emulation_type)9259 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9260 {
9261 return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9262 }
9263 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9264
kvm_emulate_instruction_from_buffer(struct kvm_vcpu * vcpu,void * insn,int insn_len)9265 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9266 void *insn, int insn_len)
9267 {
9268 return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9269 }
9270 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9271
complete_fast_pio_out_port_0x7e(struct kvm_vcpu * vcpu)9272 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9273 {
9274 vcpu->arch.pio.count = 0;
9275 return 1;
9276 }
9277
complete_fast_pio_out(struct kvm_vcpu * vcpu)9278 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9279 {
9280 vcpu->arch.pio.count = 0;
9281
9282 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9283 return 1;
9284
9285 return kvm_skip_emulated_instruction(vcpu);
9286 }
9287
kvm_fast_pio_out(struct kvm_vcpu * vcpu,int size,unsigned short port)9288 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9289 unsigned short port)
9290 {
9291 unsigned long val = kvm_rax_read(vcpu);
9292 int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9293
9294 if (ret)
9295 return ret;
9296
9297 /*
9298 * Workaround userspace that relies on old KVM behavior of %rip being
9299 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9300 */
9301 if (port == 0x7e &&
9302 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9303 vcpu->arch.complete_userspace_io =
9304 complete_fast_pio_out_port_0x7e;
9305 kvm_skip_emulated_instruction(vcpu);
9306 } else {
9307 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9308 vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9309 }
9310 return 0;
9311 }
9312
complete_fast_pio_in(struct kvm_vcpu * vcpu)9313 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9314 {
9315 unsigned long val;
9316
9317 /* We should only ever be called with arch.pio.count equal to 1 */
9318 BUG_ON(vcpu->arch.pio.count != 1);
9319
9320 if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9321 vcpu->arch.pio.count = 0;
9322 return 1;
9323 }
9324
9325 /* For size less than 4 we merge, else we zero extend */
9326 val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9327
9328 complete_emulator_pio_in(vcpu, &val);
9329 kvm_rax_write(vcpu, val);
9330
9331 return kvm_skip_emulated_instruction(vcpu);
9332 }
9333
kvm_fast_pio_in(struct kvm_vcpu * vcpu,int size,unsigned short port)9334 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9335 unsigned short port)
9336 {
9337 unsigned long val;
9338 int ret;
9339
9340 /* For size less than 4 we merge, else we zero extend */
9341 val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9342
9343 ret = emulator_pio_in(vcpu, size, port, &val, 1);
9344 if (ret) {
9345 kvm_rax_write(vcpu, val);
9346 return ret;
9347 }
9348
9349 vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9350 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9351
9352 return 0;
9353 }
9354
kvm_fast_pio(struct kvm_vcpu * vcpu,int size,unsigned short port,int in)9355 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9356 {
9357 int ret;
9358
9359 if (in)
9360 ret = kvm_fast_pio_in(vcpu, size, port);
9361 else
9362 ret = kvm_fast_pio_out(vcpu, size, port);
9363 return ret && kvm_skip_emulated_instruction(vcpu);
9364 }
9365 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9366
kvmclock_cpu_down_prep(unsigned int cpu)9367 static int kvmclock_cpu_down_prep(unsigned int cpu)
9368 {
9369 __this_cpu_write(cpu_tsc_khz, 0);
9370 return 0;
9371 }
9372
tsc_khz_changed(void * data)9373 static void tsc_khz_changed(void *data)
9374 {
9375 struct cpufreq_freqs *freq = data;
9376 unsigned long khz;
9377
9378 WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9379
9380 if (data)
9381 khz = freq->new;
9382 else
9383 khz = cpufreq_quick_get(raw_smp_processor_id());
9384 if (!khz)
9385 khz = tsc_khz;
9386 __this_cpu_write(cpu_tsc_khz, khz);
9387 }
9388
9389 #ifdef CONFIG_X86_64
kvm_hyperv_tsc_notifier(void)9390 static void kvm_hyperv_tsc_notifier(void)
9391 {
9392 struct kvm *kvm;
9393 int cpu;
9394
9395 mutex_lock(&kvm_lock);
9396 list_for_each_entry(kvm, &vm_list, vm_list)
9397 kvm_make_mclock_inprogress_request(kvm);
9398
9399 /* no guest entries from this point */
9400 hyperv_stop_tsc_emulation();
9401
9402 /* TSC frequency always matches when on Hyper-V */
9403 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9404 for_each_present_cpu(cpu)
9405 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9406 }
9407 kvm_caps.max_guest_tsc_khz = tsc_khz;
9408
9409 list_for_each_entry(kvm, &vm_list, vm_list) {
9410 __kvm_start_pvclock_update(kvm);
9411 pvclock_update_vm_gtod_copy(kvm);
9412 kvm_end_pvclock_update(kvm);
9413 }
9414
9415 mutex_unlock(&kvm_lock);
9416 }
9417 #endif
9418
__kvmclock_cpufreq_notifier(struct cpufreq_freqs * freq,int cpu)9419 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9420 {
9421 struct kvm *kvm;
9422 struct kvm_vcpu *vcpu;
9423 int send_ipi = 0;
9424 unsigned long i;
9425
9426 /*
9427 * We allow guests to temporarily run on slowing clocks,
9428 * provided we notify them after, or to run on accelerating
9429 * clocks, provided we notify them before. Thus time never
9430 * goes backwards.
9431 *
9432 * However, we have a problem. We can't atomically update
9433 * the frequency of a given CPU from this function; it is
9434 * merely a notifier, which can be called from any CPU.
9435 * Changing the TSC frequency at arbitrary points in time
9436 * requires a recomputation of local variables related to
9437 * the TSC for each VCPU. We must flag these local variables
9438 * to be updated and be sure the update takes place with the
9439 * new frequency before any guests proceed.
9440 *
9441 * Unfortunately, the combination of hotplug CPU and frequency
9442 * change creates an intractable locking scenario; the order
9443 * of when these callouts happen is undefined with respect to
9444 * CPU hotplug, and they can race with each other. As such,
9445 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9446 * undefined; you can actually have a CPU frequency change take
9447 * place in between the computation of X and the setting of the
9448 * variable. To protect against this problem, all updates of
9449 * the per_cpu tsc_khz variable are done in an interrupt
9450 * protected IPI, and all callers wishing to update the value
9451 * must wait for a synchronous IPI to complete (which is trivial
9452 * if the caller is on the CPU already). This establishes the
9453 * necessary total order on variable updates.
9454 *
9455 * Note that because a guest time update may take place
9456 * anytime after the setting of the VCPU's request bit, the
9457 * correct TSC value must be set before the request. However,
9458 * to ensure the update actually makes it to any guest which
9459 * starts running in hardware virtualization between the set
9460 * and the acquisition of the spinlock, we must also ping the
9461 * CPU after setting the request bit.
9462 *
9463 */
9464
9465 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9466
9467 mutex_lock(&kvm_lock);
9468 list_for_each_entry(kvm, &vm_list, vm_list) {
9469 kvm_for_each_vcpu(i, vcpu, kvm) {
9470 if (vcpu->cpu != cpu)
9471 continue;
9472 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9473 if (vcpu->cpu != raw_smp_processor_id())
9474 send_ipi = 1;
9475 }
9476 }
9477 mutex_unlock(&kvm_lock);
9478
9479 if (freq->old < freq->new && send_ipi) {
9480 /*
9481 * We upscale the frequency. Must make the guest
9482 * doesn't see old kvmclock values while running with
9483 * the new frequency, otherwise we risk the guest sees
9484 * time go backwards.
9485 *
9486 * In case we update the frequency for another cpu
9487 * (which might be in guest context) send an interrupt
9488 * to kick the cpu out of guest context. Next time
9489 * guest context is entered kvmclock will be updated,
9490 * so the guest will not see stale values.
9491 */
9492 smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9493 }
9494 }
9495
kvmclock_cpufreq_notifier(struct notifier_block * nb,unsigned long val,void * data)9496 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9497 void *data)
9498 {
9499 struct cpufreq_freqs *freq = data;
9500 int cpu;
9501
9502 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9503 return 0;
9504 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9505 return 0;
9506
9507 for_each_cpu(cpu, freq->policy->cpus)
9508 __kvmclock_cpufreq_notifier(freq, cpu);
9509
9510 return 0;
9511 }
9512
9513 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9514 .notifier_call = kvmclock_cpufreq_notifier
9515 };
9516
kvmclock_cpu_online(unsigned int cpu)9517 static int kvmclock_cpu_online(unsigned int cpu)
9518 {
9519 tsc_khz_changed(NULL);
9520 return 0;
9521 }
9522
kvm_timer_init(void)9523 static void kvm_timer_init(void)
9524 {
9525 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9526 max_tsc_khz = tsc_khz;
9527
9528 if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9529 struct cpufreq_policy *policy;
9530 int cpu;
9531
9532 cpu = get_cpu();
9533 policy = cpufreq_cpu_get(cpu);
9534 if (policy) {
9535 if (policy->cpuinfo.max_freq)
9536 max_tsc_khz = policy->cpuinfo.max_freq;
9537 cpufreq_cpu_put(policy);
9538 }
9539 put_cpu();
9540 }
9541 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9542 CPUFREQ_TRANSITION_NOTIFIER);
9543
9544 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9545 kvmclock_cpu_online, kvmclock_cpu_down_prep);
9546 }
9547 }
9548
9549 #ifdef CONFIG_X86_64
pvclock_gtod_update_fn(struct work_struct * work)9550 static void pvclock_gtod_update_fn(struct work_struct *work)
9551 {
9552 struct kvm *kvm;
9553 struct kvm_vcpu *vcpu;
9554 unsigned long i;
9555
9556 mutex_lock(&kvm_lock);
9557 list_for_each_entry(kvm, &vm_list, vm_list)
9558 kvm_for_each_vcpu(i, vcpu, kvm)
9559 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9560 atomic_set(&kvm_guest_has_master_clock, 0);
9561 mutex_unlock(&kvm_lock);
9562 }
9563
9564 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9565
9566 /*
9567 * Indirection to move queue_work() out of the tk_core.seq write held
9568 * region to prevent possible deadlocks against time accessors which
9569 * are invoked with work related locks held.
9570 */
pvclock_irq_work_fn(struct irq_work * w)9571 static void pvclock_irq_work_fn(struct irq_work *w)
9572 {
9573 queue_work(system_long_wq, &pvclock_gtod_work);
9574 }
9575
9576 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9577
9578 /*
9579 * Notification about pvclock gtod data update.
9580 */
pvclock_gtod_notify(struct notifier_block * nb,unsigned long unused,void * priv)9581 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9582 void *priv)
9583 {
9584 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9585 struct timekeeper *tk = priv;
9586
9587 update_pvclock_gtod(tk);
9588
9589 /*
9590 * Disable master clock if host does not trust, or does not use,
9591 * TSC based clocksource. Delegate queue_work() to irq_work as
9592 * this is invoked with tk_core.seq write held.
9593 */
9594 if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9595 atomic_read(&kvm_guest_has_master_clock) != 0)
9596 irq_work_queue(&pvclock_irq_work);
9597 return 0;
9598 }
9599
9600 static struct notifier_block pvclock_gtod_notifier = {
9601 .notifier_call = pvclock_gtod_notify,
9602 };
9603 #endif
9604
kvm_ops_update(struct kvm_x86_init_ops * ops)9605 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9606 {
9607 memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9608
9609 #define __KVM_X86_OP(func) \
9610 static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9611 #define KVM_X86_OP(func) \
9612 WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9613 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9614 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9615 static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9616 (void *)__static_call_return0);
9617 #include <asm/kvm-x86-ops.h>
9618 #undef __KVM_X86_OP
9619
9620 kvm_pmu_ops_update(ops->pmu_ops);
9621 }
9622
kvm_x86_check_processor_compatibility(void)9623 static int kvm_x86_check_processor_compatibility(void)
9624 {
9625 int cpu = smp_processor_id();
9626 struct cpuinfo_x86 *c = &cpu_data(cpu);
9627
9628 /*
9629 * Compatibility checks are done when loading KVM and when enabling
9630 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9631 * compatible, i.e. KVM should never perform a compatibility check on
9632 * an offline CPU.
9633 */
9634 WARN_ON(!cpu_online(cpu));
9635
9636 if (__cr4_reserved_bits(cpu_has, c) !=
9637 __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9638 return -EIO;
9639
9640 return static_call(kvm_x86_check_processor_compatibility)();
9641 }
9642
kvm_x86_check_cpu_compat(void * ret)9643 static void kvm_x86_check_cpu_compat(void *ret)
9644 {
9645 *(int *)ret = kvm_x86_check_processor_compatibility();
9646 }
9647
__kvm_x86_vendor_init(struct kvm_x86_init_ops * ops)9648 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9649 {
9650 u64 host_pat;
9651 int r, cpu;
9652
9653 if (kvm_x86_ops.hardware_enable) {
9654 pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9655 return -EEXIST;
9656 }
9657
9658 /*
9659 * KVM explicitly assumes that the guest has an FPU and
9660 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9661 * vCPU's FPU state as a fxregs_state struct.
9662 */
9663 if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9664 pr_err("inadequate fpu\n");
9665 return -EOPNOTSUPP;
9666 }
9667
9668 if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9669 pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9670 return -EOPNOTSUPP;
9671 }
9672
9673 /*
9674 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9675 * the PAT bits in SPTEs. Bail if PAT[0] is programmed to something
9676 * other than WB. Note, EPT doesn't utilize the PAT, but don't bother
9677 * with an exception. PAT[0] is set to WB on RESET and also by the
9678 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9679 */
9680 if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9681 (host_pat & GENMASK(2, 0)) != 6) {
9682 pr_err("host PAT[0] is not WB\n");
9683 return -EIO;
9684 }
9685
9686 x86_emulator_cache = kvm_alloc_emulator_cache();
9687 if (!x86_emulator_cache) {
9688 pr_err("failed to allocate cache for x86 emulator\n");
9689 return -ENOMEM;
9690 }
9691
9692 user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9693 if (!user_return_msrs) {
9694 pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9695 r = -ENOMEM;
9696 goto out_free_x86_emulator_cache;
9697 }
9698 kvm_nr_uret_msrs = 0;
9699
9700 r = kvm_mmu_vendor_module_init();
9701 if (r)
9702 goto out_free_percpu;
9703
9704 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9705 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9706 kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9707 }
9708
9709 rdmsrl_safe(MSR_EFER, &host_efer);
9710
9711 if (boot_cpu_has(X86_FEATURE_XSAVES))
9712 rdmsrl(MSR_IA32_XSS, host_xss);
9713
9714 kvm_init_pmu_capability(ops->pmu_ops);
9715
9716 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
9717 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, host_arch_capabilities);
9718
9719 r = ops->hardware_setup();
9720 if (r != 0)
9721 goto out_mmu_exit;
9722
9723 kvm_ops_update(ops);
9724
9725 for_each_online_cpu(cpu) {
9726 smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9727 if (r < 0)
9728 goto out_unwind_ops;
9729 }
9730
9731 /*
9732 * Point of no return! DO NOT add error paths below this point unless
9733 * absolutely necessary, as most operations from this point forward
9734 * require unwinding.
9735 */
9736 kvm_timer_init();
9737
9738 if (pi_inject_timer == -1)
9739 pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9740 #ifdef CONFIG_X86_64
9741 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9742
9743 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9744 set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9745 #endif
9746
9747 kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9748
9749 if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9750 kvm_caps.supported_xss = 0;
9751
9752 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9753 cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9754 #undef __kvm_cpu_cap_has
9755
9756 if (kvm_caps.has_tsc_control) {
9757 /*
9758 * Make sure the user can only configure tsc_khz values that
9759 * fit into a signed integer.
9760 * A min value is not calculated because it will always
9761 * be 1 on all machines.
9762 */
9763 u64 max = min(0x7fffffffULL,
9764 __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9765 kvm_caps.max_guest_tsc_khz = max;
9766 }
9767 kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9768 kvm_init_msr_lists();
9769 return 0;
9770
9771 out_unwind_ops:
9772 kvm_x86_ops.hardware_enable = NULL;
9773 static_call(kvm_x86_hardware_unsetup)();
9774 out_mmu_exit:
9775 kvm_mmu_vendor_module_exit();
9776 out_free_percpu:
9777 free_percpu(user_return_msrs);
9778 out_free_x86_emulator_cache:
9779 kmem_cache_destroy(x86_emulator_cache);
9780 return r;
9781 }
9782
kvm_x86_vendor_init(struct kvm_x86_init_ops * ops)9783 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9784 {
9785 int r;
9786
9787 mutex_lock(&vendor_module_lock);
9788 r = __kvm_x86_vendor_init(ops);
9789 mutex_unlock(&vendor_module_lock);
9790
9791 return r;
9792 }
9793 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9794
kvm_x86_vendor_exit(void)9795 void kvm_x86_vendor_exit(void)
9796 {
9797 kvm_unregister_perf_callbacks();
9798
9799 #ifdef CONFIG_X86_64
9800 if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9801 clear_hv_tscchange_cb();
9802 #endif
9803 kvm_lapic_exit();
9804
9805 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9806 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9807 CPUFREQ_TRANSITION_NOTIFIER);
9808 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9809 }
9810 #ifdef CONFIG_X86_64
9811 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9812 irq_work_sync(&pvclock_irq_work);
9813 cancel_work_sync(&pvclock_gtod_work);
9814 #endif
9815 static_call(kvm_x86_hardware_unsetup)();
9816 kvm_mmu_vendor_module_exit();
9817 free_percpu(user_return_msrs);
9818 kmem_cache_destroy(x86_emulator_cache);
9819 #ifdef CONFIG_KVM_XEN
9820 static_key_deferred_flush(&kvm_xen_enabled);
9821 WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9822 #endif
9823 mutex_lock(&vendor_module_lock);
9824 kvm_x86_ops.hardware_enable = NULL;
9825 mutex_unlock(&vendor_module_lock);
9826 }
9827 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9828
__kvm_emulate_halt(struct kvm_vcpu * vcpu,int state,int reason)9829 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9830 {
9831 /*
9832 * The vCPU has halted, e.g. executed HLT. Update the run state if the
9833 * local APIC is in-kernel, the run loop will detect the non-runnable
9834 * state and halt the vCPU. Exit to userspace if the local APIC is
9835 * managed by userspace, in which case userspace is responsible for
9836 * handling wake events.
9837 */
9838 ++vcpu->stat.halt_exits;
9839 if (lapic_in_kernel(vcpu)) {
9840 vcpu->arch.mp_state = state;
9841 return 1;
9842 } else {
9843 vcpu->run->exit_reason = reason;
9844 return 0;
9845 }
9846 }
9847
kvm_emulate_halt_noskip(struct kvm_vcpu * vcpu)9848 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9849 {
9850 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9851 }
9852 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9853
kvm_emulate_halt(struct kvm_vcpu * vcpu)9854 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9855 {
9856 int ret = kvm_skip_emulated_instruction(vcpu);
9857 /*
9858 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9859 * KVM_EXIT_DEBUG here.
9860 */
9861 return kvm_emulate_halt_noskip(vcpu) && ret;
9862 }
9863 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9864
kvm_emulate_ap_reset_hold(struct kvm_vcpu * vcpu)9865 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9866 {
9867 int ret = kvm_skip_emulated_instruction(vcpu);
9868
9869 return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9870 KVM_EXIT_AP_RESET_HOLD) && ret;
9871 }
9872 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9873
9874 #ifdef CONFIG_X86_64
kvm_pv_clock_pairing(struct kvm_vcpu * vcpu,gpa_t paddr,unsigned long clock_type)9875 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9876 unsigned long clock_type)
9877 {
9878 struct kvm_clock_pairing clock_pairing;
9879 struct timespec64 ts;
9880 u64 cycle;
9881 int ret;
9882
9883 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9884 return -KVM_EOPNOTSUPP;
9885
9886 /*
9887 * When tsc is in permanent catchup mode guests won't be able to use
9888 * pvclock_read_retry loop to get consistent view of pvclock
9889 */
9890 if (vcpu->arch.tsc_always_catchup)
9891 return -KVM_EOPNOTSUPP;
9892
9893 if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9894 return -KVM_EOPNOTSUPP;
9895
9896 clock_pairing.sec = ts.tv_sec;
9897 clock_pairing.nsec = ts.tv_nsec;
9898 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9899 clock_pairing.flags = 0;
9900 memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9901
9902 ret = 0;
9903 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9904 sizeof(struct kvm_clock_pairing)))
9905 ret = -KVM_EFAULT;
9906
9907 return ret;
9908 }
9909 #endif
9910
9911 /*
9912 * kvm_pv_kick_cpu_op: Kick a vcpu.
9913 *
9914 * @apicid - apicid of vcpu to be kicked.
9915 */
kvm_pv_kick_cpu_op(struct kvm * kvm,int apicid)9916 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9917 {
9918 /*
9919 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9920 * common code, e.g. for tracing. Defer initialization to the compiler.
9921 */
9922 struct kvm_lapic_irq lapic_irq = {
9923 .delivery_mode = APIC_DM_REMRD,
9924 .dest_mode = APIC_DEST_PHYSICAL,
9925 .shorthand = APIC_DEST_NOSHORT,
9926 .dest_id = apicid,
9927 };
9928
9929 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9930 }
9931
kvm_apicv_activated(struct kvm * kvm)9932 bool kvm_apicv_activated(struct kvm *kvm)
9933 {
9934 return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9935 }
9936 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9937
kvm_vcpu_apicv_activated(struct kvm_vcpu * vcpu)9938 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9939 {
9940 ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9941 ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9942
9943 return (vm_reasons | vcpu_reasons) == 0;
9944 }
9945 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9946
set_or_clear_apicv_inhibit(unsigned long * inhibits,enum kvm_apicv_inhibit reason,bool set)9947 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9948 enum kvm_apicv_inhibit reason, bool set)
9949 {
9950 if (set)
9951 __set_bit(reason, inhibits);
9952 else
9953 __clear_bit(reason, inhibits);
9954
9955 trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9956 }
9957
kvm_apicv_init(struct kvm * kvm)9958 static void kvm_apicv_init(struct kvm *kvm)
9959 {
9960 unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9961
9962 init_rwsem(&kvm->arch.apicv_update_lock);
9963
9964 set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9965
9966 if (!enable_apicv)
9967 set_or_clear_apicv_inhibit(inhibits,
9968 APICV_INHIBIT_REASON_DISABLE, true);
9969 }
9970
kvm_sched_yield(struct kvm_vcpu * vcpu,unsigned long dest_id)9971 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9972 {
9973 struct kvm_vcpu *target = NULL;
9974 struct kvm_apic_map *map;
9975
9976 vcpu->stat.directed_yield_attempted++;
9977
9978 if (single_task_running())
9979 goto no_yield;
9980
9981 rcu_read_lock();
9982 map = rcu_dereference(vcpu->kvm->arch.apic_map);
9983
9984 if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9985 target = map->phys_map[dest_id]->vcpu;
9986
9987 rcu_read_unlock();
9988
9989 if (!target || !READ_ONCE(target->ready))
9990 goto no_yield;
9991
9992 /* Ignore requests to yield to self */
9993 if (vcpu == target)
9994 goto no_yield;
9995
9996 if (kvm_vcpu_yield_to(target) <= 0)
9997 goto no_yield;
9998
9999 vcpu->stat.directed_yield_successful++;
10000
10001 no_yield:
10002 return;
10003 }
10004
complete_hypercall_exit(struct kvm_vcpu * vcpu)10005 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
10006 {
10007 u64 ret = vcpu->run->hypercall.ret;
10008
10009 if (!is_64_bit_mode(vcpu))
10010 ret = (u32)ret;
10011 kvm_rax_write(vcpu, ret);
10012 ++vcpu->stat.hypercalls;
10013 return kvm_skip_emulated_instruction(vcpu);
10014 }
10015
kvm_emulate_hypercall(struct kvm_vcpu * vcpu)10016 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
10017 {
10018 unsigned long nr, a0, a1, a2, a3, ret;
10019 int op_64_bit;
10020
10021 if (kvm_xen_hypercall_enabled(vcpu->kvm))
10022 return kvm_xen_hypercall(vcpu);
10023
10024 if (kvm_hv_hypercall_enabled(vcpu))
10025 return kvm_hv_hypercall(vcpu);
10026
10027 nr = kvm_rax_read(vcpu);
10028 a0 = kvm_rbx_read(vcpu);
10029 a1 = kvm_rcx_read(vcpu);
10030 a2 = kvm_rdx_read(vcpu);
10031 a3 = kvm_rsi_read(vcpu);
10032
10033 trace_kvm_hypercall(nr, a0, a1, a2, a3);
10034
10035 op_64_bit = is_64_bit_hypercall(vcpu);
10036 if (!op_64_bit) {
10037 nr &= 0xFFFFFFFF;
10038 a0 &= 0xFFFFFFFF;
10039 a1 &= 0xFFFFFFFF;
10040 a2 &= 0xFFFFFFFF;
10041 a3 &= 0xFFFFFFFF;
10042 }
10043
10044 if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
10045 ret = -KVM_EPERM;
10046 goto out;
10047 }
10048
10049 ret = -KVM_ENOSYS;
10050
10051 switch (nr) {
10052 case KVM_HC_VAPIC_POLL_IRQ:
10053 ret = 0;
10054 break;
10055 case KVM_HC_KICK_CPU:
10056 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
10057 break;
10058
10059 kvm_pv_kick_cpu_op(vcpu->kvm, a1);
10060 kvm_sched_yield(vcpu, a1);
10061 ret = 0;
10062 break;
10063 #ifdef CONFIG_X86_64
10064 case KVM_HC_CLOCK_PAIRING:
10065 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
10066 break;
10067 #endif
10068 case KVM_HC_SEND_IPI:
10069 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
10070 break;
10071
10072 ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
10073 break;
10074 case KVM_HC_SCHED_YIELD:
10075 if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
10076 break;
10077
10078 kvm_sched_yield(vcpu, a0);
10079 ret = 0;
10080 break;
10081 case KVM_HC_MAP_GPA_RANGE: {
10082 u64 gpa = a0, npages = a1, attrs = a2;
10083
10084 ret = -KVM_ENOSYS;
10085 if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
10086 break;
10087
10088 if (!PAGE_ALIGNED(gpa) || !npages ||
10089 gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
10090 ret = -KVM_EINVAL;
10091 break;
10092 }
10093
10094 vcpu->run->exit_reason = KVM_EXIT_HYPERCALL;
10095 vcpu->run->hypercall.nr = KVM_HC_MAP_GPA_RANGE;
10096 vcpu->run->hypercall.args[0] = gpa;
10097 vcpu->run->hypercall.args[1] = npages;
10098 vcpu->run->hypercall.args[2] = attrs;
10099 vcpu->run->hypercall.flags = 0;
10100 if (op_64_bit)
10101 vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
10102
10103 WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
10104 vcpu->arch.complete_userspace_io = complete_hypercall_exit;
10105 return 0;
10106 }
10107 default:
10108 ret = -KVM_ENOSYS;
10109 break;
10110 }
10111 out:
10112 if (!op_64_bit)
10113 ret = (u32)ret;
10114 kvm_rax_write(vcpu, ret);
10115
10116 ++vcpu->stat.hypercalls;
10117 return kvm_skip_emulated_instruction(vcpu);
10118 }
10119 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
10120
emulator_fix_hypercall(struct x86_emulate_ctxt * ctxt)10121 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
10122 {
10123 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
10124 char instruction[3];
10125 unsigned long rip = kvm_rip_read(vcpu);
10126
10127 /*
10128 * If the quirk is disabled, synthesize a #UD and let the guest pick up
10129 * the pieces.
10130 */
10131 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
10132 ctxt->exception.error_code_valid = false;
10133 ctxt->exception.vector = UD_VECTOR;
10134 ctxt->have_exception = true;
10135 return X86EMUL_PROPAGATE_FAULT;
10136 }
10137
10138 static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
10139
10140 return emulator_write_emulated(ctxt, rip, instruction, 3,
10141 &ctxt->exception);
10142 }
10143
dm_request_for_irq_injection(struct kvm_vcpu * vcpu)10144 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
10145 {
10146 return vcpu->run->request_interrupt_window &&
10147 likely(!pic_in_kernel(vcpu->kvm));
10148 }
10149
10150 /* Called within kvm->srcu read side. */
post_kvm_run_save(struct kvm_vcpu * vcpu)10151 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
10152 {
10153 struct kvm_run *kvm_run = vcpu->run;
10154
10155 kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
10156 kvm_run->cr8 = kvm_get_cr8(vcpu);
10157 kvm_run->apic_base = kvm_get_apic_base(vcpu);
10158
10159 kvm_run->ready_for_interrupt_injection =
10160 pic_in_kernel(vcpu->kvm) ||
10161 kvm_vcpu_ready_for_interrupt_injection(vcpu);
10162
10163 if (is_smm(vcpu))
10164 kvm_run->flags |= KVM_RUN_X86_SMM;
10165 }
10166
update_cr8_intercept(struct kvm_vcpu * vcpu)10167 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
10168 {
10169 int max_irr, tpr;
10170
10171 if (!kvm_x86_ops.update_cr8_intercept)
10172 return;
10173
10174 if (!lapic_in_kernel(vcpu))
10175 return;
10176
10177 if (vcpu->arch.apic->apicv_active)
10178 return;
10179
10180 if (!vcpu->arch.apic->vapic_addr)
10181 max_irr = kvm_lapic_find_highest_irr(vcpu);
10182 else
10183 max_irr = -1;
10184
10185 if (max_irr != -1)
10186 max_irr >>= 4;
10187
10188 tpr = kvm_lapic_get_cr8(vcpu);
10189
10190 static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
10191 }
10192
10193
kvm_check_nested_events(struct kvm_vcpu * vcpu)10194 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
10195 {
10196 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10197 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10198 return 1;
10199 }
10200
10201 return kvm_x86_ops.nested_ops->check_events(vcpu);
10202 }
10203
kvm_inject_exception(struct kvm_vcpu * vcpu)10204 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
10205 {
10206 /*
10207 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
10208 * exceptions don't report error codes. The presence of an error code
10209 * is carried with the exception and only stripped when the exception
10210 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
10211 * report an error code despite the CPU being in Real Mode.
10212 */
10213 vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
10214
10215 trace_kvm_inj_exception(vcpu->arch.exception.vector,
10216 vcpu->arch.exception.has_error_code,
10217 vcpu->arch.exception.error_code,
10218 vcpu->arch.exception.injected);
10219
10220 static_call(kvm_x86_inject_exception)(vcpu);
10221 }
10222
10223 /*
10224 * Check for any event (interrupt or exception) that is ready to be injected,
10225 * and if there is at least one event, inject the event with the highest
10226 * priority. This handles both "pending" events, i.e. events that have never
10227 * been injected into the guest, and "injected" events, i.e. events that were
10228 * injected as part of a previous VM-Enter, but weren't successfully delivered
10229 * and need to be re-injected.
10230 *
10231 * Note, this is not guaranteed to be invoked on a guest instruction boundary,
10232 * i.e. doesn't guarantee that there's an event window in the guest. KVM must
10233 * be able to inject exceptions in the "middle" of an instruction, and so must
10234 * also be able to re-inject NMIs and IRQs in the middle of an instruction.
10235 * I.e. for exceptions and re-injected events, NOT invoking this on instruction
10236 * boundaries is necessary and correct.
10237 *
10238 * For simplicity, KVM uses a single path to inject all events (except events
10239 * that are injected directly from L1 to L2) and doesn't explicitly track
10240 * instruction boundaries for asynchronous events. However, because VM-Exits
10241 * that can occur during instruction execution typically result in KVM skipping
10242 * the instruction or injecting an exception, e.g. instruction and exception
10243 * intercepts, and because pending exceptions have higher priority than pending
10244 * interrupts, KVM still honors instruction boundaries in most scenarios.
10245 *
10246 * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
10247 * the instruction or inject an exception, then KVM can incorrecty inject a new
10248 * asynchronous event if the event became pending after the CPU fetched the
10249 * instruction (in the guest). E.g. if a page fault (#PF, #NPF, EPT violation)
10250 * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
10251 * injected on the restarted instruction instead of being deferred until the
10252 * instruction completes.
10253 *
10254 * In practice, this virtualization hole is unlikely to be observed by the
10255 * guest, and even less likely to cause functional problems. To detect the
10256 * hole, the guest would have to trigger an event on a side effect of an early
10257 * phase of instruction execution, e.g. on the instruction fetch from memory.
10258 * And for it to be a functional problem, the guest would need to depend on the
10259 * ordering between that side effect, the instruction completing, _and_ the
10260 * delivery of the asynchronous event.
10261 */
kvm_check_and_inject_events(struct kvm_vcpu * vcpu,bool * req_immediate_exit)10262 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
10263 bool *req_immediate_exit)
10264 {
10265 bool can_inject;
10266 int r;
10267
10268 /*
10269 * Process nested events first, as nested VM-Exit supersedes event
10270 * re-injection. If there's an event queued for re-injection, it will
10271 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
10272 */
10273 if (is_guest_mode(vcpu))
10274 r = kvm_check_nested_events(vcpu);
10275 else
10276 r = 0;
10277
10278 /*
10279 * Re-inject exceptions and events *especially* if immediate entry+exit
10280 * to/from L2 is needed, as any event that has already been injected
10281 * into L2 needs to complete its lifecycle before injecting a new event.
10282 *
10283 * Don't re-inject an NMI or interrupt if there is a pending exception.
10284 * This collision arises if an exception occurred while vectoring the
10285 * injected event, KVM intercepted said exception, and KVM ultimately
10286 * determined the fault belongs to the guest and queues the exception
10287 * for injection back into the guest.
10288 *
10289 * "Injected" interrupts can also collide with pending exceptions if
10290 * userspace ignores the "ready for injection" flag and blindly queues
10291 * an interrupt. In that case, prioritizing the exception is correct,
10292 * as the exception "occurred" before the exit to userspace. Trap-like
10293 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10294 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10295 * priority, they're only generated (pended) during instruction
10296 * execution, and interrupts are recognized at instruction boundaries.
10297 * Thus a pending fault-like exception means the fault occurred on the
10298 * *previous* instruction and must be serviced prior to recognizing any
10299 * new events in order to fully complete the previous instruction.
10300 */
10301 if (vcpu->arch.exception.injected)
10302 kvm_inject_exception(vcpu);
10303 else if (kvm_is_exception_pending(vcpu))
10304 ; /* see above */
10305 else if (vcpu->arch.nmi_injected)
10306 static_call(kvm_x86_inject_nmi)(vcpu);
10307 else if (vcpu->arch.interrupt.injected)
10308 static_call(kvm_x86_inject_irq)(vcpu, true);
10309
10310 /*
10311 * Exceptions that morph to VM-Exits are handled above, and pending
10312 * exceptions on top of injected exceptions that do not VM-Exit should
10313 * either morph to #DF or, sadly, override the injected exception.
10314 */
10315 WARN_ON_ONCE(vcpu->arch.exception.injected &&
10316 vcpu->arch.exception.pending);
10317
10318 /*
10319 * Bail if immediate entry+exit to/from the guest is needed to complete
10320 * nested VM-Enter or event re-injection so that a different pending
10321 * event can be serviced (or if KVM needs to exit to userspace).
10322 *
10323 * Otherwise, continue processing events even if VM-Exit occurred. The
10324 * VM-Exit will have cleared exceptions that were meant for L2, but
10325 * there may now be events that can be injected into L1.
10326 */
10327 if (r < 0)
10328 goto out;
10329
10330 /*
10331 * A pending exception VM-Exit should either result in nested VM-Exit
10332 * or force an immediate re-entry and exit to/from L2, and exception
10333 * VM-Exits cannot be injected (flag should _never_ be set).
10334 */
10335 WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10336 vcpu->arch.exception_vmexit.pending);
10337
10338 /*
10339 * New events, other than exceptions, cannot be injected if KVM needs
10340 * to re-inject a previous event. See above comments on re-injecting
10341 * for why pending exceptions get priority.
10342 */
10343 can_inject = !kvm_event_needs_reinjection(vcpu);
10344
10345 if (vcpu->arch.exception.pending) {
10346 /*
10347 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10348 * value pushed on the stack. Trap-like exception and all #DBs
10349 * leave RF as-is (KVM follows Intel's behavior in this regard;
10350 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10351 *
10352 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10353 * describe the behavior of General Detect #DBs, which are
10354 * fault-like. They do _not_ set RF, a la code breakpoints.
10355 */
10356 if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10357 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10358 X86_EFLAGS_RF);
10359
10360 if (vcpu->arch.exception.vector == DB_VECTOR) {
10361 kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10362 if (vcpu->arch.dr7 & DR7_GD) {
10363 vcpu->arch.dr7 &= ~DR7_GD;
10364 kvm_update_dr7(vcpu);
10365 }
10366 }
10367
10368 kvm_inject_exception(vcpu);
10369
10370 vcpu->arch.exception.pending = false;
10371 vcpu->arch.exception.injected = true;
10372
10373 can_inject = false;
10374 }
10375
10376 /* Don't inject interrupts if the user asked to avoid doing so */
10377 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10378 return 0;
10379
10380 /*
10381 * Finally, inject interrupt events. If an event cannot be injected
10382 * due to architectural conditions (e.g. IF=0) a window-open exit
10383 * will re-request KVM_REQ_EVENT. Sometimes however an event is pending
10384 * and can architecturally be injected, but we cannot do it right now:
10385 * an interrupt could have arrived just now and we have to inject it
10386 * as a vmexit, or there could already an event in the queue, which is
10387 * indicated by can_inject. In that case we request an immediate exit
10388 * in order to make progress and get back here for another iteration.
10389 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10390 */
10391 #ifdef CONFIG_KVM_SMM
10392 if (vcpu->arch.smi_pending) {
10393 r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10394 if (r < 0)
10395 goto out;
10396 if (r) {
10397 vcpu->arch.smi_pending = false;
10398 ++vcpu->arch.smi_count;
10399 enter_smm(vcpu);
10400 can_inject = false;
10401 } else
10402 static_call(kvm_x86_enable_smi_window)(vcpu);
10403 }
10404 #endif
10405
10406 if (vcpu->arch.nmi_pending) {
10407 r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10408 if (r < 0)
10409 goto out;
10410 if (r) {
10411 --vcpu->arch.nmi_pending;
10412 vcpu->arch.nmi_injected = true;
10413 static_call(kvm_x86_inject_nmi)(vcpu);
10414 can_inject = false;
10415 WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10416 }
10417 if (vcpu->arch.nmi_pending)
10418 static_call(kvm_x86_enable_nmi_window)(vcpu);
10419 }
10420
10421 if (kvm_cpu_has_injectable_intr(vcpu)) {
10422 r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10423 if (r < 0)
10424 goto out;
10425 if (r) {
10426 int irq = kvm_cpu_get_interrupt(vcpu);
10427
10428 if (!WARN_ON_ONCE(irq == -1)) {
10429 kvm_queue_interrupt(vcpu, irq, false);
10430 static_call(kvm_x86_inject_irq)(vcpu, false);
10431 WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10432 }
10433 }
10434 if (kvm_cpu_has_injectable_intr(vcpu))
10435 static_call(kvm_x86_enable_irq_window)(vcpu);
10436 }
10437
10438 if (is_guest_mode(vcpu) &&
10439 kvm_x86_ops.nested_ops->has_events &&
10440 kvm_x86_ops.nested_ops->has_events(vcpu))
10441 *req_immediate_exit = true;
10442
10443 /*
10444 * KVM must never queue a new exception while injecting an event; KVM
10445 * is done emulating and should only propagate the to-be-injected event
10446 * to the VMCS/VMCB. Queueing a new exception can put the vCPU into an
10447 * infinite loop as KVM will bail from VM-Enter to inject the pending
10448 * exception and start the cycle all over.
10449 *
10450 * Exempt triple faults as they have special handling and won't put the
10451 * vCPU into an infinite loop. Triple fault can be queued when running
10452 * VMX without unrestricted guest, as that requires KVM to emulate Real
10453 * Mode events (see kvm_inject_realmode_interrupt()).
10454 */
10455 WARN_ON_ONCE(vcpu->arch.exception.pending ||
10456 vcpu->arch.exception_vmexit.pending);
10457 return 0;
10458
10459 out:
10460 if (r == -EBUSY) {
10461 *req_immediate_exit = true;
10462 r = 0;
10463 }
10464 return r;
10465 }
10466
process_nmi(struct kvm_vcpu * vcpu)10467 static void process_nmi(struct kvm_vcpu *vcpu)
10468 {
10469 unsigned int limit;
10470
10471 /*
10472 * x86 is limited to one NMI pending, but because KVM can't react to
10473 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is
10474 * scheduled out, KVM needs to play nice with two queued NMIs showing
10475 * up at the same time. To handle this scenario, allow two NMIs to be
10476 * (temporarily) pending so long as NMIs are not blocked and KVM is not
10477 * waiting for a previous NMI injection to complete (which effectively
10478 * blocks NMIs). KVM will immediately inject one of the two NMIs, and
10479 * will request an NMI window to handle the second NMI.
10480 */
10481 if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10482 limit = 1;
10483 else
10484 limit = 2;
10485
10486 /*
10487 * Adjust the limit to account for pending virtual NMIs, which aren't
10488 * tracked in vcpu->arch.nmi_pending.
10489 */
10490 if (static_call(kvm_x86_is_vnmi_pending)(vcpu))
10491 limit--;
10492
10493 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10494 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10495
10496 if (vcpu->arch.nmi_pending &&
10497 (static_call(kvm_x86_set_vnmi_pending)(vcpu)))
10498 vcpu->arch.nmi_pending--;
10499
10500 if (vcpu->arch.nmi_pending)
10501 kvm_make_request(KVM_REQ_EVENT, vcpu);
10502 }
10503
10504 /* Return total number of NMIs pending injection to the VM */
kvm_get_nr_pending_nmis(struct kvm_vcpu * vcpu)10505 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu)
10506 {
10507 return vcpu->arch.nmi_pending +
10508 static_call(kvm_x86_is_vnmi_pending)(vcpu);
10509 }
10510
kvm_make_scan_ioapic_request_mask(struct kvm * kvm,unsigned long * vcpu_bitmap)10511 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10512 unsigned long *vcpu_bitmap)
10513 {
10514 kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10515 }
10516
kvm_make_scan_ioapic_request(struct kvm * kvm)10517 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10518 {
10519 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10520 }
10521
__kvm_vcpu_update_apicv(struct kvm_vcpu * vcpu)10522 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10523 {
10524 struct kvm_lapic *apic = vcpu->arch.apic;
10525 bool activate;
10526
10527 if (!lapic_in_kernel(vcpu))
10528 return;
10529
10530 down_read(&vcpu->kvm->arch.apicv_update_lock);
10531 preempt_disable();
10532
10533 /* Do not activate APICV when APIC is disabled */
10534 activate = kvm_vcpu_apicv_activated(vcpu) &&
10535 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10536
10537 if (apic->apicv_active == activate)
10538 goto out;
10539
10540 apic->apicv_active = activate;
10541 kvm_apic_update_apicv(vcpu);
10542 static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10543
10544 /*
10545 * When APICv gets disabled, we may still have injected interrupts
10546 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10547 * still active when the interrupt got accepted. Make sure
10548 * kvm_check_and_inject_events() is called to check for that.
10549 */
10550 if (!apic->apicv_active)
10551 kvm_make_request(KVM_REQ_EVENT, vcpu);
10552
10553 out:
10554 preempt_enable();
10555 up_read(&vcpu->kvm->arch.apicv_update_lock);
10556 }
10557 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10558
kvm_vcpu_update_apicv(struct kvm_vcpu * vcpu)10559 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10560 {
10561 if (!lapic_in_kernel(vcpu))
10562 return;
10563
10564 /*
10565 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10566 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10567 * and hardware doesn't support x2APIC virtualization. E.g. some AMD
10568 * CPUs support AVIC but not x2APIC. KVM still allows enabling AVIC in
10569 * this case so that KVM can the AVIC doorbell to inject interrupts to
10570 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10571 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10572 * despite being in x2APIC mode. For simplicity, inhibiting the APIC
10573 * access page is sticky.
10574 */
10575 if (apic_x2apic_mode(vcpu->arch.apic) &&
10576 kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10577 kvm_inhibit_apic_access_page(vcpu);
10578
10579 __kvm_vcpu_update_apicv(vcpu);
10580 }
10581
__kvm_set_or_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason,bool set)10582 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10583 enum kvm_apicv_inhibit reason, bool set)
10584 {
10585 unsigned long old, new;
10586
10587 lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10588
10589 if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10590 return;
10591
10592 old = new = kvm->arch.apicv_inhibit_reasons;
10593
10594 set_or_clear_apicv_inhibit(&new, reason, set);
10595
10596 if (!!old != !!new) {
10597 /*
10598 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10599 * false positives in the sanity check WARN in svm_vcpu_run().
10600 * This task will wait for all vCPUs to ack the kick IRQ before
10601 * updating apicv_inhibit_reasons, and all other vCPUs will
10602 * block on acquiring apicv_update_lock so that vCPUs can't
10603 * redo svm_vcpu_run() without seeing the new inhibit state.
10604 *
10605 * Note, holding apicv_update_lock and taking it in the read
10606 * side (handling the request) also prevents other vCPUs from
10607 * servicing the request with a stale apicv_inhibit_reasons.
10608 */
10609 kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10610 kvm->arch.apicv_inhibit_reasons = new;
10611 if (new) {
10612 unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10613 int idx = srcu_read_lock(&kvm->srcu);
10614
10615 kvm_zap_gfn_range(kvm, gfn, gfn+1);
10616 srcu_read_unlock(&kvm->srcu, idx);
10617 }
10618 } else {
10619 kvm->arch.apicv_inhibit_reasons = new;
10620 }
10621 }
10622
kvm_set_or_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason,bool set)10623 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10624 enum kvm_apicv_inhibit reason, bool set)
10625 {
10626 if (!enable_apicv)
10627 return;
10628
10629 down_write(&kvm->arch.apicv_update_lock);
10630 __kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10631 up_write(&kvm->arch.apicv_update_lock);
10632 }
10633 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10634
vcpu_scan_ioapic(struct kvm_vcpu * vcpu)10635 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10636 {
10637 if (!kvm_apic_present(vcpu))
10638 return;
10639
10640 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10641
10642 if (irqchip_split(vcpu->kvm))
10643 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10644 else {
10645 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10646 if (ioapic_in_kernel(vcpu->kvm))
10647 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10648 }
10649
10650 if (is_guest_mode(vcpu))
10651 vcpu->arch.load_eoi_exitmap_pending = true;
10652 else
10653 kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10654 }
10655
vcpu_load_eoi_exitmap(struct kvm_vcpu * vcpu)10656 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10657 {
10658 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10659 return;
10660
10661 #ifdef CONFIG_KVM_HYPERV
10662 if (to_hv_vcpu(vcpu)) {
10663 u64 eoi_exit_bitmap[4];
10664
10665 bitmap_or((ulong *)eoi_exit_bitmap,
10666 vcpu->arch.ioapic_handled_vectors,
10667 to_hv_synic(vcpu)->vec_bitmap, 256);
10668 static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10669 return;
10670 }
10671 #endif
10672 static_call_cond(kvm_x86_load_eoi_exitmap)(
10673 vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10674 }
10675
kvm_arch_guest_memory_reclaimed(struct kvm * kvm)10676 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10677 {
10678 static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10679 }
10680
kvm_vcpu_reload_apic_access_page(struct kvm_vcpu * vcpu)10681 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10682 {
10683 if (!lapic_in_kernel(vcpu))
10684 return;
10685
10686 static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10687 }
10688
__kvm_request_immediate_exit(struct kvm_vcpu * vcpu)10689 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10690 {
10691 smp_send_reschedule(vcpu->cpu);
10692 }
10693 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10694
10695 /*
10696 * Called within kvm->srcu read side.
10697 * Returns 1 to let vcpu_run() continue the guest execution loop without
10698 * exiting to the userspace. Otherwise, the value will be returned to the
10699 * userspace.
10700 */
vcpu_enter_guest(struct kvm_vcpu * vcpu)10701 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10702 {
10703 int r;
10704 bool req_int_win =
10705 dm_request_for_irq_injection(vcpu) &&
10706 kvm_cpu_accept_dm_intr(vcpu);
10707 fastpath_t exit_fastpath;
10708
10709 bool req_immediate_exit = false;
10710
10711 if (kvm_request_pending(vcpu)) {
10712 if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10713 r = -EIO;
10714 goto out;
10715 }
10716
10717 if (kvm_dirty_ring_check_request(vcpu)) {
10718 r = 0;
10719 goto out;
10720 }
10721
10722 if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10723 if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10724 r = 0;
10725 goto out;
10726 }
10727 }
10728 if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10729 kvm_mmu_free_obsolete_roots(vcpu);
10730 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10731 __kvm_migrate_timers(vcpu);
10732 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10733 kvm_update_masterclock(vcpu->kvm);
10734 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10735 kvm_gen_kvmclock_update(vcpu);
10736 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10737 r = kvm_guest_time_update(vcpu);
10738 if (unlikely(r))
10739 goto out;
10740 }
10741 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10742 kvm_mmu_sync_roots(vcpu);
10743 if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10744 kvm_mmu_load_pgd(vcpu);
10745
10746 /*
10747 * Note, the order matters here, as flushing "all" TLB entries
10748 * also flushes the "current" TLB entries, i.e. servicing the
10749 * flush "all" will clear any request to flush "current".
10750 */
10751 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10752 kvm_vcpu_flush_tlb_all(vcpu);
10753
10754 kvm_service_local_tlb_flush_requests(vcpu);
10755
10756 /*
10757 * Fall back to a "full" guest flush if Hyper-V's precise
10758 * flushing fails. Note, Hyper-V's flushing is per-vCPU, but
10759 * the flushes are considered "remote" and not "local" because
10760 * the requests can be initiated from other vCPUs.
10761 */
10762 #ifdef CONFIG_KVM_HYPERV
10763 if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10764 kvm_hv_vcpu_flush_tlb(vcpu))
10765 kvm_vcpu_flush_tlb_guest(vcpu);
10766 #endif
10767
10768 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10769 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10770 r = 0;
10771 goto out;
10772 }
10773 if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10774 if (is_guest_mode(vcpu))
10775 kvm_x86_ops.nested_ops->triple_fault(vcpu);
10776
10777 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10778 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10779 vcpu->mmio_needed = 0;
10780 r = 0;
10781 goto out;
10782 }
10783 }
10784 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10785 /* Page is swapped out. Do synthetic halt */
10786 vcpu->arch.apf.halted = true;
10787 r = 1;
10788 goto out;
10789 }
10790 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10791 record_steal_time(vcpu);
10792 if (kvm_check_request(KVM_REQ_PMU, vcpu))
10793 kvm_pmu_handle_event(vcpu);
10794 if (kvm_check_request(KVM_REQ_PMI, vcpu))
10795 kvm_pmu_deliver_pmi(vcpu);
10796 #ifdef CONFIG_KVM_SMM
10797 if (kvm_check_request(KVM_REQ_SMI, vcpu))
10798 process_smi(vcpu);
10799 #endif
10800 if (kvm_check_request(KVM_REQ_NMI, vcpu))
10801 process_nmi(vcpu);
10802 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10803 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10804 if (test_bit(vcpu->arch.pending_ioapic_eoi,
10805 vcpu->arch.ioapic_handled_vectors)) {
10806 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10807 vcpu->run->eoi.vector =
10808 vcpu->arch.pending_ioapic_eoi;
10809 r = 0;
10810 goto out;
10811 }
10812 }
10813 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10814 vcpu_scan_ioapic(vcpu);
10815 if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10816 vcpu_load_eoi_exitmap(vcpu);
10817 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10818 kvm_vcpu_reload_apic_access_page(vcpu);
10819 #ifdef CONFIG_KVM_HYPERV
10820 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10821 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10822 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10823 vcpu->run->system_event.ndata = 0;
10824 r = 0;
10825 goto out;
10826 }
10827 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10828 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10829 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10830 vcpu->run->system_event.ndata = 0;
10831 r = 0;
10832 goto out;
10833 }
10834 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10835 struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10836
10837 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10838 vcpu->run->hyperv = hv_vcpu->exit;
10839 r = 0;
10840 goto out;
10841 }
10842
10843 /*
10844 * KVM_REQ_HV_STIMER has to be processed after
10845 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10846 * depend on the guest clock being up-to-date
10847 */
10848 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10849 kvm_hv_process_stimers(vcpu);
10850 #endif
10851 if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10852 kvm_vcpu_update_apicv(vcpu);
10853 if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10854 kvm_check_async_pf_completion(vcpu);
10855 if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10856 static_call(kvm_x86_msr_filter_changed)(vcpu);
10857
10858 if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10859 static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10860 }
10861
10862 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10863 kvm_xen_has_interrupt(vcpu)) {
10864 ++vcpu->stat.req_event;
10865 r = kvm_apic_accept_events(vcpu);
10866 if (r < 0) {
10867 r = 0;
10868 goto out;
10869 }
10870 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10871 r = 1;
10872 goto out;
10873 }
10874
10875 r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10876 if (r < 0) {
10877 r = 0;
10878 goto out;
10879 }
10880 if (req_int_win)
10881 static_call(kvm_x86_enable_irq_window)(vcpu);
10882
10883 if (kvm_lapic_enabled(vcpu)) {
10884 update_cr8_intercept(vcpu);
10885 kvm_lapic_sync_to_vapic(vcpu);
10886 }
10887 }
10888
10889 r = kvm_mmu_reload(vcpu);
10890 if (unlikely(r)) {
10891 goto cancel_injection;
10892 }
10893
10894 preempt_disable();
10895
10896 static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10897
10898 /*
10899 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
10900 * IPI are then delayed after guest entry, which ensures that they
10901 * result in virtual interrupt delivery.
10902 */
10903 local_irq_disable();
10904
10905 /* Store vcpu->apicv_active before vcpu->mode. */
10906 smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10907
10908 kvm_vcpu_srcu_read_unlock(vcpu);
10909
10910 /*
10911 * 1) We should set ->mode before checking ->requests. Please see
10912 * the comment in kvm_vcpu_exiting_guest_mode().
10913 *
10914 * 2) For APICv, we should set ->mode before checking PID.ON. This
10915 * pairs with the memory barrier implicit in pi_test_and_set_on
10916 * (see vmx_deliver_posted_interrupt).
10917 *
10918 * 3) This also orders the write to mode from any reads to the page
10919 * tables done while the VCPU is running. Please see the comment
10920 * in kvm_flush_remote_tlbs.
10921 */
10922 smp_mb__after_srcu_read_unlock();
10923
10924 /*
10925 * Process pending posted interrupts to handle the case where the
10926 * notification IRQ arrived in the host, or was never sent (because the
10927 * target vCPU wasn't running). Do this regardless of the vCPU's APICv
10928 * status, KVM doesn't update assigned devices when APICv is inhibited,
10929 * i.e. they can post interrupts even if APICv is temporarily disabled.
10930 */
10931 if (kvm_lapic_enabled(vcpu))
10932 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10933
10934 if (kvm_vcpu_exit_request(vcpu)) {
10935 vcpu->mode = OUTSIDE_GUEST_MODE;
10936 smp_wmb();
10937 local_irq_enable();
10938 preempt_enable();
10939 kvm_vcpu_srcu_read_lock(vcpu);
10940 r = 1;
10941 goto cancel_injection;
10942 }
10943
10944 if (req_immediate_exit) {
10945 kvm_make_request(KVM_REQ_EVENT, vcpu);
10946 static_call(kvm_x86_request_immediate_exit)(vcpu);
10947 }
10948
10949 fpregs_assert_state_consistent();
10950 if (test_thread_flag(TIF_NEED_FPU_LOAD))
10951 switch_fpu_return();
10952
10953 if (vcpu->arch.guest_fpu.xfd_err)
10954 wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10955
10956 if (unlikely(vcpu->arch.switch_db_regs)) {
10957 set_debugreg(0, 7);
10958 set_debugreg(vcpu->arch.eff_db[0], 0);
10959 set_debugreg(vcpu->arch.eff_db[1], 1);
10960 set_debugreg(vcpu->arch.eff_db[2], 2);
10961 set_debugreg(vcpu->arch.eff_db[3], 3);
10962 } else if (unlikely(hw_breakpoint_active())) {
10963 set_debugreg(0, 7);
10964 }
10965
10966 guest_timing_enter_irqoff();
10967
10968 for (;;) {
10969 /*
10970 * Assert that vCPU vs. VM APICv state is consistent. An APICv
10971 * update must kick and wait for all vCPUs before toggling the
10972 * per-VM state, and responding vCPUs must wait for the update
10973 * to complete before servicing KVM_REQ_APICV_UPDATE.
10974 */
10975 WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10976 (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10977
10978 exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10979 if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10980 break;
10981
10982 if (kvm_lapic_enabled(vcpu))
10983 static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10984
10985 if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10986 exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10987 break;
10988 }
10989
10990 /* Note, VM-Exits that go down the "slow" path are accounted below. */
10991 ++vcpu->stat.exits;
10992 }
10993
10994 /*
10995 * Do this here before restoring debug registers on the host. And
10996 * since we do this before handling the vmexit, a DR access vmexit
10997 * can (a) read the correct value of the debug registers, (b) set
10998 * KVM_DEBUGREG_WONT_EXIT again.
10999 */
11000 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
11001 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
11002 static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
11003 kvm_update_dr0123(vcpu);
11004 kvm_update_dr7(vcpu);
11005 }
11006
11007 /*
11008 * If the guest has used debug registers, at least dr7
11009 * will be disabled while returning to the host.
11010 * If we don't have active breakpoints in the host, we don't
11011 * care about the messed up debug address registers. But if
11012 * we have some of them active, restore the old state.
11013 */
11014 if (hw_breakpoint_active())
11015 hw_breakpoint_restore();
11016
11017 vcpu->arch.last_vmentry_cpu = vcpu->cpu;
11018 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
11019
11020 vcpu->mode = OUTSIDE_GUEST_MODE;
11021 smp_wmb();
11022
11023 /*
11024 * Sync xfd before calling handle_exit_irqoff() which may
11025 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
11026 * in #NM irqoff handler).
11027 */
11028 if (vcpu->arch.xfd_no_write_intercept)
11029 fpu_sync_guest_vmexit_xfd_state();
11030
11031 static_call(kvm_x86_handle_exit_irqoff)(vcpu);
11032
11033 if (vcpu->arch.guest_fpu.xfd_err)
11034 wrmsrl(MSR_IA32_XFD_ERR, 0);
11035
11036 /*
11037 * Consume any pending interrupts, including the possible source of
11038 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
11039 * An instruction is required after local_irq_enable() to fully unblock
11040 * interrupts on processors that implement an interrupt shadow, the
11041 * stat.exits increment will do nicely.
11042 */
11043 kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
11044 local_irq_enable();
11045 ++vcpu->stat.exits;
11046 local_irq_disable();
11047 kvm_after_interrupt(vcpu);
11048
11049 /*
11050 * Wait until after servicing IRQs to account guest time so that any
11051 * ticks that occurred while running the guest are properly accounted
11052 * to the guest. Waiting until IRQs are enabled degrades the accuracy
11053 * of accounting via context tracking, but the loss of accuracy is
11054 * acceptable for all known use cases.
11055 */
11056 guest_timing_exit_irqoff();
11057
11058 local_irq_enable();
11059 preempt_enable();
11060
11061 kvm_vcpu_srcu_read_lock(vcpu);
11062
11063 /*
11064 * Profile KVM exit RIPs:
11065 */
11066 if (unlikely(prof_on == KVM_PROFILING)) {
11067 unsigned long rip = kvm_rip_read(vcpu);
11068 profile_hit(KVM_PROFILING, (void *)rip);
11069 }
11070
11071 if (unlikely(vcpu->arch.tsc_always_catchup))
11072 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
11073
11074 if (vcpu->arch.apic_attention)
11075 kvm_lapic_sync_from_vapic(vcpu);
11076
11077 r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
11078 return r;
11079
11080 cancel_injection:
11081 if (req_immediate_exit)
11082 kvm_make_request(KVM_REQ_EVENT, vcpu);
11083 static_call(kvm_x86_cancel_injection)(vcpu);
11084 if (unlikely(vcpu->arch.apic_attention))
11085 kvm_lapic_sync_from_vapic(vcpu);
11086 out:
11087 return r;
11088 }
11089
11090 /* Called within kvm->srcu read side. */
vcpu_block(struct kvm_vcpu * vcpu)11091 static inline int vcpu_block(struct kvm_vcpu *vcpu)
11092 {
11093 bool hv_timer;
11094
11095 if (!kvm_arch_vcpu_runnable(vcpu)) {
11096 /*
11097 * Switch to the software timer before halt-polling/blocking as
11098 * the guest's timer may be a break event for the vCPU, and the
11099 * hypervisor timer runs only when the CPU is in guest mode.
11100 * Switch before halt-polling so that KVM recognizes an expired
11101 * timer before blocking.
11102 */
11103 hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
11104 if (hv_timer)
11105 kvm_lapic_switch_to_sw_timer(vcpu);
11106
11107 kvm_vcpu_srcu_read_unlock(vcpu);
11108 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
11109 kvm_vcpu_halt(vcpu);
11110 else
11111 kvm_vcpu_block(vcpu);
11112 kvm_vcpu_srcu_read_lock(vcpu);
11113
11114 if (hv_timer)
11115 kvm_lapic_switch_to_hv_timer(vcpu);
11116
11117 /*
11118 * If the vCPU is not runnable, a signal or another host event
11119 * of some kind is pending; service it without changing the
11120 * vCPU's activity state.
11121 */
11122 if (!kvm_arch_vcpu_runnable(vcpu))
11123 return 1;
11124 }
11125
11126 /*
11127 * Evaluate nested events before exiting the halted state. This allows
11128 * the halt state to be recorded properly in the VMCS12's activity
11129 * state field (AMD does not have a similar field and a VM-Exit always
11130 * causes a spurious wakeup from HLT).
11131 */
11132 if (is_guest_mode(vcpu)) {
11133 if (kvm_check_nested_events(vcpu) < 0)
11134 return 0;
11135 }
11136
11137 if (kvm_apic_accept_events(vcpu) < 0)
11138 return 0;
11139 switch(vcpu->arch.mp_state) {
11140 case KVM_MP_STATE_HALTED:
11141 case KVM_MP_STATE_AP_RESET_HOLD:
11142 vcpu->arch.pv.pv_unhalted = false;
11143 vcpu->arch.mp_state =
11144 KVM_MP_STATE_RUNNABLE;
11145 fallthrough;
11146 case KVM_MP_STATE_RUNNABLE:
11147 vcpu->arch.apf.halted = false;
11148 break;
11149 case KVM_MP_STATE_INIT_RECEIVED:
11150 break;
11151 default:
11152 WARN_ON_ONCE(1);
11153 break;
11154 }
11155 return 1;
11156 }
11157
kvm_vcpu_running(struct kvm_vcpu * vcpu)11158 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
11159 {
11160 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
11161 !vcpu->arch.apf.halted);
11162 }
11163
11164 /* Called within kvm->srcu read side. */
vcpu_run(struct kvm_vcpu * vcpu)11165 static int vcpu_run(struct kvm_vcpu *vcpu)
11166 {
11167 int r;
11168
11169 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
11170 vcpu->arch.l1tf_flush_l1d = true;
11171
11172 for (;;) {
11173 /*
11174 * If another guest vCPU requests a PV TLB flush in the middle
11175 * of instruction emulation, the rest of the emulation could
11176 * use a stale page translation. Assume that any code after
11177 * this point can start executing an instruction.
11178 */
11179 vcpu->arch.at_instruction_boundary = false;
11180 if (kvm_vcpu_running(vcpu)) {
11181 r = vcpu_enter_guest(vcpu);
11182 } else {
11183 r = vcpu_block(vcpu);
11184 }
11185
11186 if (r <= 0)
11187 break;
11188
11189 kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
11190 if (kvm_xen_has_pending_events(vcpu))
11191 kvm_xen_inject_pending_events(vcpu);
11192
11193 if (kvm_cpu_has_pending_timer(vcpu))
11194 kvm_inject_pending_timer_irqs(vcpu);
11195
11196 if (dm_request_for_irq_injection(vcpu) &&
11197 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
11198 r = 0;
11199 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
11200 ++vcpu->stat.request_irq_exits;
11201 break;
11202 }
11203
11204 if (__xfer_to_guest_mode_work_pending()) {
11205 kvm_vcpu_srcu_read_unlock(vcpu);
11206 r = xfer_to_guest_mode_handle_work(vcpu);
11207 kvm_vcpu_srcu_read_lock(vcpu);
11208 if (r)
11209 return r;
11210 }
11211 }
11212
11213 return r;
11214 }
11215
complete_emulated_io(struct kvm_vcpu * vcpu)11216 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
11217 {
11218 return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
11219 }
11220
complete_emulated_pio(struct kvm_vcpu * vcpu)11221 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
11222 {
11223 BUG_ON(!vcpu->arch.pio.count);
11224
11225 return complete_emulated_io(vcpu);
11226 }
11227
11228 /*
11229 * Implements the following, as a state machine:
11230 *
11231 * read:
11232 * for each fragment
11233 * for each mmio piece in the fragment
11234 * write gpa, len
11235 * exit
11236 * copy data
11237 * execute insn
11238 *
11239 * write:
11240 * for each fragment
11241 * for each mmio piece in the fragment
11242 * write gpa, len
11243 * copy data
11244 * exit
11245 */
complete_emulated_mmio(struct kvm_vcpu * vcpu)11246 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11247 {
11248 struct kvm_run *run = vcpu->run;
11249 struct kvm_mmio_fragment *frag;
11250 unsigned len;
11251
11252 BUG_ON(!vcpu->mmio_needed);
11253
11254 /* Complete previous fragment */
11255 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11256 len = min(8u, frag->len);
11257 if (!vcpu->mmio_is_write)
11258 memcpy(frag->data, run->mmio.data, len);
11259
11260 if (frag->len <= 8) {
11261 /* Switch to the next fragment. */
11262 frag++;
11263 vcpu->mmio_cur_fragment++;
11264 } else {
11265 /* Go forward to the next mmio piece. */
11266 frag->data += len;
11267 frag->gpa += len;
11268 frag->len -= len;
11269 }
11270
11271 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11272 vcpu->mmio_needed = 0;
11273
11274 /* FIXME: return into emulator if single-stepping. */
11275 if (vcpu->mmio_is_write)
11276 return 1;
11277 vcpu->mmio_read_completed = 1;
11278 return complete_emulated_io(vcpu);
11279 }
11280
11281 run->exit_reason = KVM_EXIT_MMIO;
11282 run->mmio.phys_addr = frag->gpa;
11283 if (vcpu->mmio_is_write)
11284 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11285 run->mmio.len = min(8u, frag->len);
11286 run->mmio.is_write = vcpu->mmio_is_write;
11287 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11288 return 0;
11289 }
11290
11291 /* Swap (qemu) user FPU context for the guest FPU context. */
kvm_load_guest_fpu(struct kvm_vcpu * vcpu)11292 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11293 {
11294 /* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11295 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11296 trace_kvm_fpu(1);
11297 }
11298
11299 /* When vcpu_run ends, restore user space FPU context. */
kvm_put_guest_fpu(struct kvm_vcpu * vcpu)11300 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11301 {
11302 fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11303 ++vcpu->stat.fpu_reload;
11304 trace_kvm_fpu(0);
11305 }
11306
kvm_arch_vcpu_ioctl_run(struct kvm_vcpu * vcpu)11307 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11308 {
11309 struct kvm_queued_exception *ex = &vcpu->arch.exception;
11310 struct kvm_run *kvm_run = vcpu->run;
11311 int r;
11312
11313 vcpu_load(vcpu);
11314 kvm_sigset_activate(vcpu);
11315 kvm_run->flags = 0;
11316 kvm_load_guest_fpu(vcpu);
11317
11318 kvm_vcpu_srcu_read_lock(vcpu);
11319 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11320 if (kvm_run->immediate_exit) {
11321 r = -EINTR;
11322 goto out;
11323 }
11324
11325 /*
11326 * Don't bother switching APIC timer emulation from the
11327 * hypervisor timer to the software timer, the only way for the
11328 * APIC timer to be active is if userspace stuffed vCPU state,
11329 * i.e. put the vCPU into a nonsensical state. Only an INIT
11330 * will transition the vCPU out of UNINITIALIZED (without more
11331 * state stuffing from userspace), which will reset the local
11332 * APIC and thus cancel the timer or drop the IRQ (if the timer
11333 * already expired).
11334 */
11335 kvm_vcpu_srcu_read_unlock(vcpu);
11336 kvm_vcpu_block(vcpu);
11337 kvm_vcpu_srcu_read_lock(vcpu);
11338
11339 if (kvm_apic_accept_events(vcpu) < 0) {
11340 r = 0;
11341 goto out;
11342 }
11343 r = -EAGAIN;
11344 if (signal_pending(current)) {
11345 r = -EINTR;
11346 kvm_run->exit_reason = KVM_EXIT_INTR;
11347 ++vcpu->stat.signal_exits;
11348 }
11349 goto out;
11350 }
11351
11352 if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11353 (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11354 r = -EINVAL;
11355 goto out;
11356 }
11357
11358 if (kvm_run->kvm_dirty_regs) {
11359 r = sync_regs(vcpu);
11360 if (r != 0)
11361 goto out;
11362 }
11363
11364 /* re-sync apic's tpr */
11365 if (!lapic_in_kernel(vcpu)) {
11366 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11367 r = -EINVAL;
11368 goto out;
11369 }
11370 }
11371
11372 /*
11373 * If userspace set a pending exception and L2 is active, convert it to
11374 * a pending VM-Exit if L1 wants to intercept the exception.
11375 */
11376 if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11377 kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11378 ex->error_code)) {
11379 kvm_queue_exception_vmexit(vcpu, ex->vector,
11380 ex->has_error_code, ex->error_code,
11381 ex->has_payload, ex->payload);
11382 ex->injected = false;
11383 ex->pending = false;
11384 }
11385 vcpu->arch.exception_from_userspace = false;
11386
11387 if (unlikely(vcpu->arch.complete_userspace_io)) {
11388 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11389 vcpu->arch.complete_userspace_io = NULL;
11390 r = cui(vcpu);
11391 if (r <= 0)
11392 goto out;
11393 } else {
11394 WARN_ON_ONCE(vcpu->arch.pio.count);
11395 WARN_ON_ONCE(vcpu->mmio_needed);
11396 }
11397
11398 if (kvm_run->immediate_exit) {
11399 r = -EINTR;
11400 goto out;
11401 }
11402
11403 r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11404 if (r <= 0)
11405 goto out;
11406
11407 r = vcpu_run(vcpu);
11408
11409 out:
11410 kvm_put_guest_fpu(vcpu);
11411 if (kvm_run->kvm_valid_regs)
11412 store_regs(vcpu);
11413 post_kvm_run_save(vcpu);
11414 kvm_vcpu_srcu_read_unlock(vcpu);
11415
11416 kvm_sigset_deactivate(vcpu);
11417 vcpu_put(vcpu);
11418 return r;
11419 }
11420
__get_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11421 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11422 {
11423 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11424 /*
11425 * We are here if userspace calls get_regs() in the middle of
11426 * instruction emulation. Registers state needs to be copied
11427 * back from emulation context to vcpu. Userspace shouldn't do
11428 * that usually, but some bad designed PV devices (vmware
11429 * backdoor interface) need this to work
11430 */
11431 emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11432 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11433 }
11434 regs->rax = kvm_rax_read(vcpu);
11435 regs->rbx = kvm_rbx_read(vcpu);
11436 regs->rcx = kvm_rcx_read(vcpu);
11437 regs->rdx = kvm_rdx_read(vcpu);
11438 regs->rsi = kvm_rsi_read(vcpu);
11439 regs->rdi = kvm_rdi_read(vcpu);
11440 regs->rsp = kvm_rsp_read(vcpu);
11441 regs->rbp = kvm_rbp_read(vcpu);
11442 #ifdef CONFIG_X86_64
11443 regs->r8 = kvm_r8_read(vcpu);
11444 regs->r9 = kvm_r9_read(vcpu);
11445 regs->r10 = kvm_r10_read(vcpu);
11446 regs->r11 = kvm_r11_read(vcpu);
11447 regs->r12 = kvm_r12_read(vcpu);
11448 regs->r13 = kvm_r13_read(vcpu);
11449 regs->r14 = kvm_r14_read(vcpu);
11450 regs->r15 = kvm_r15_read(vcpu);
11451 #endif
11452
11453 regs->rip = kvm_rip_read(vcpu);
11454 regs->rflags = kvm_get_rflags(vcpu);
11455 }
11456
kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11457 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11458 {
11459 vcpu_load(vcpu);
11460 __get_regs(vcpu, regs);
11461 vcpu_put(vcpu);
11462 return 0;
11463 }
11464
__set_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11465 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11466 {
11467 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11468 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11469
11470 kvm_rax_write(vcpu, regs->rax);
11471 kvm_rbx_write(vcpu, regs->rbx);
11472 kvm_rcx_write(vcpu, regs->rcx);
11473 kvm_rdx_write(vcpu, regs->rdx);
11474 kvm_rsi_write(vcpu, regs->rsi);
11475 kvm_rdi_write(vcpu, regs->rdi);
11476 kvm_rsp_write(vcpu, regs->rsp);
11477 kvm_rbp_write(vcpu, regs->rbp);
11478 #ifdef CONFIG_X86_64
11479 kvm_r8_write(vcpu, regs->r8);
11480 kvm_r9_write(vcpu, regs->r9);
11481 kvm_r10_write(vcpu, regs->r10);
11482 kvm_r11_write(vcpu, regs->r11);
11483 kvm_r12_write(vcpu, regs->r12);
11484 kvm_r13_write(vcpu, regs->r13);
11485 kvm_r14_write(vcpu, regs->r14);
11486 kvm_r15_write(vcpu, regs->r15);
11487 #endif
11488
11489 kvm_rip_write(vcpu, regs->rip);
11490 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11491
11492 vcpu->arch.exception.pending = false;
11493 vcpu->arch.exception_vmexit.pending = false;
11494
11495 kvm_make_request(KVM_REQ_EVENT, vcpu);
11496 }
11497
kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11498 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11499 {
11500 vcpu_load(vcpu);
11501 __set_regs(vcpu, regs);
11502 vcpu_put(vcpu);
11503 return 0;
11504 }
11505
__get_sregs_common(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11506 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11507 {
11508 struct desc_ptr dt;
11509
11510 if (vcpu->arch.guest_state_protected)
11511 goto skip_protected_regs;
11512
11513 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11514 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11515 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11516 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11517 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11518 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11519
11520 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11521 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11522
11523 static_call(kvm_x86_get_idt)(vcpu, &dt);
11524 sregs->idt.limit = dt.size;
11525 sregs->idt.base = dt.address;
11526 static_call(kvm_x86_get_gdt)(vcpu, &dt);
11527 sregs->gdt.limit = dt.size;
11528 sregs->gdt.base = dt.address;
11529
11530 sregs->cr2 = vcpu->arch.cr2;
11531 sregs->cr3 = kvm_read_cr3(vcpu);
11532
11533 skip_protected_regs:
11534 sregs->cr0 = kvm_read_cr0(vcpu);
11535 sregs->cr4 = kvm_read_cr4(vcpu);
11536 sregs->cr8 = kvm_get_cr8(vcpu);
11537 sregs->efer = vcpu->arch.efer;
11538 sregs->apic_base = kvm_get_apic_base(vcpu);
11539 }
11540
__get_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11541 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11542 {
11543 __get_sregs_common(vcpu, sregs);
11544
11545 if (vcpu->arch.guest_state_protected)
11546 return;
11547
11548 if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11549 set_bit(vcpu->arch.interrupt.nr,
11550 (unsigned long *)sregs->interrupt_bitmap);
11551 }
11552
__get_sregs2(struct kvm_vcpu * vcpu,struct kvm_sregs2 * sregs2)11553 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11554 {
11555 int i;
11556
11557 __get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11558
11559 if (vcpu->arch.guest_state_protected)
11560 return;
11561
11562 if (is_pae_paging(vcpu)) {
11563 for (i = 0 ; i < 4 ; i++)
11564 sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11565 sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11566 }
11567 }
11568
kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11569 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11570 struct kvm_sregs *sregs)
11571 {
11572 vcpu_load(vcpu);
11573 __get_sregs(vcpu, sregs);
11574 vcpu_put(vcpu);
11575 return 0;
11576 }
11577
kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)11578 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11579 struct kvm_mp_state *mp_state)
11580 {
11581 int r;
11582
11583 vcpu_load(vcpu);
11584 if (kvm_mpx_supported())
11585 kvm_load_guest_fpu(vcpu);
11586
11587 r = kvm_apic_accept_events(vcpu);
11588 if (r < 0)
11589 goto out;
11590 r = 0;
11591
11592 if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11593 vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11594 vcpu->arch.pv.pv_unhalted)
11595 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11596 else
11597 mp_state->mp_state = vcpu->arch.mp_state;
11598
11599 out:
11600 if (kvm_mpx_supported())
11601 kvm_put_guest_fpu(vcpu);
11602 vcpu_put(vcpu);
11603 return r;
11604 }
11605
kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)11606 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11607 struct kvm_mp_state *mp_state)
11608 {
11609 int ret = -EINVAL;
11610
11611 vcpu_load(vcpu);
11612
11613 switch (mp_state->mp_state) {
11614 case KVM_MP_STATE_UNINITIALIZED:
11615 case KVM_MP_STATE_HALTED:
11616 case KVM_MP_STATE_AP_RESET_HOLD:
11617 case KVM_MP_STATE_INIT_RECEIVED:
11618 case KVM_MP_STATE_SIPI_RECEIVED:
11619 if (!lapic_in_kernel(vcpu))
11620 goto out;
11621 break;
11622
11623 case KVM_MP_STATE_RUNNABLE:
11624 break;
11625
11626 default:
11627 goto out;
11628 }
11629
11630 /*
11631 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11632 * forcing the guest into INIT/SIPI if those events are supposed to be
11633 * blocked. KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11634 * if an SMI is pending as well.
11635 */
11636 if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11637 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11638 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11639 goto out;
11640
11641 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11642 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11643 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11644 } else
11645 vcpu->arch.mp_state = mp_state->mp_state;
11646 kvm_make_request(KVM_REQ_EVENT, vcpu);
11647
11648 ret = 0;
11649 out:
11650 vcpu_put(vcpu);
11651 return ret;
11652 }
11653
kvm_task_switch(struct kvm_vcpu * vcpu,u16 tss_selector,int idt_index,int reason,bool has_error_code,u32 error_code)11654 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11655 int reason, bool has_error_code, u32 error_code)
11656 {
11657 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11658 int ret;
11659
11660 init_emulate_ctxt(vcpu);
11661
11662 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11663 has_error_code, error_code);
11664 if (ret) {
11665 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11666 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11667 vcpu->run->internal.ndata = 0;
11668 return 0;
11669 }
11670
11671 kvm_rip_write(vcpu, ctxt->eip);
11672 kvm_set_rflags(vcpu, ctxt->eflags);
11673 return 1;
11674 }
11675 EXPORT_SYMBOL_GPL(kvm_task_switch);
11676
kvm_is_valid_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11677 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11678 {
11679 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11680 /*
11681 * When EFER.LME and CR0.PG are set, the processor is in
11682 * 64-bit mode (though maybe in a 32-bit code segment).
11683 * CR4.PAE and EFER.LMA must be set.
11684 */
11685 if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11686 return false;
11687 if (!kvm_vcpu_is_legal_cr3(vcpu, sregs->cr3))
11688 return false;
11689 } else {
11690 /*
11691 * Not in 64-bit mode: EFER.LMA is clear and the code
11692 * segment cannot be 64-bit.
11693 */
11694 if (sregs->efer & EFER_LMA || sregs->cs.l)
11695 return false;
11696 }
11697
11698 return kvm_is_valid_cr4(vcpu, sregs->cr4) &&
11699 kvm_is_valid_cr0(vcpu, sregs->cr0);
11700 }
11701
__set_sregs_common(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs,int * mmu_reset_needed,bool update_pdptrs)11702 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11703 int *mmu_reset_needed, bool update_pdptrs)
11704 {
11705 struct msr_data apic_base_msr;
11706 int idx;
11707 struct desc_ptr dt;
11708
11709 if (!kvm_is_valid_sregs(vcpu, sregs))
11710 return -EINVAL;
11711
11712 apic_base_msr.data = sregs->apic_base;
11713 apic_base_msr.host_initiated = true;
11714 if (kvm_set_apic_base(vcpu, &apic_base_msr))
11715 return -EINVAL;
11716
11717 if (vcpu->arch.guest_state_protected)
11718 return 0;
11719
11720 dt.size = sregs->idt.limit;
11721 dt.address = sregs->idt.base;
11722 static_call(kvm_x86_set_idt)(vcpu, &dt);
11723 dt.size = sregs->gdt.limit;
11724 dt.address = sregs->gdt.base;
11725 static_call(kvm_x86_set_gdt)(vcpu, &dt);
11726
11727 vcpu->arch.cr2 = sregs->cr2;
11728 *mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11729 vcpu->arch.cr3 = sregs->cr3;
11730 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11731 static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11732
11733 kvm_set_cr8(vcpu, sregs->cr8);
11734
11735 *mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11736 static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11737
11738 *mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11739 static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11740
11741 *mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11742 static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11743
11744 if (update_pdptrs) {
11745 idx = srcu_read_lock(&vcpu->kvm->srcu);
11746 if (is_pae_paging(vcpu)) {
11747 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11748 *mmu_reset_needed = 1;
11749 }
11750 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11751 }
11752
11753 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11754 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11755 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11756 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11757 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11758 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11759
11760 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11761 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11762
11763 update_cr8_intercept(vcpu);
11764
11765 /* Older userspace won't unhalt the vcpu on reset. */
11766 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11767 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11768 !is_protmode(vcpu))
11769 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11770
11771 return 0;
11772 }
11773
__set_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11774 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11775 {
11776 int pending_vec, max_bits;
11777 int mmu_reset_needed = 0;
11778 int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11779
11780 if (ret)
11781 return ret;
11782
11783 if (mmu_reset_needed) {
11784 kvm_mmu_reset_context(vcpu);
11785 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11786 }
11787
11788 max_bits = KVM_NR_INTERRUPTS;
11789 pending_vec = find_first_bit(
11790 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
11791
11792 if (pending_vec < max_bits) {
11793 kvm_queue_interrupt(vcpu, pending_vec, false);
11794 pr_debug("Set back pending irq %d\n", pending_vec);
11795 kvm_make_request(KVM_REQ_EVENT, vcpu);
11796 }
11797 return 0;
11798 }
11799
__set_sregs2(struct kvm_vcpu * vcpu,struct kvm_sregs2 * sregs2)11800 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11801 {
11802 int mmu_reset_needed = 0;
11803 bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11804 bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11805 !(sregs2->efer & EFER_LMA);
11806 int i, ret;
11807
11808 if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11809 return -EINVAL;
11810
11811 if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11812 return -EINVAL;
11813
11814 ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11815 &mmu_reset_needed, !valid_pdptrs);
11816 if (ret)
11817 return ret;
11818
11819 if (valid_pdptrs) {
11820 for (i = 0; i < 4 ; i++)
11821 kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11822
11823 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11824 mmu_reset_needed = 1;
11825 vcpu->arch.pdptrs_from_userspace = true;
11826 }
11827 if (mmu_reset_needed) {
11828 kvm_mmu_reset_context(vcpu);
11829 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
11830 }
11831 return 0;
11832 }
11833
kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11834 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11835 struct kvm_sregs *sregs)
11836 {
11837 int ret;
11838
11839 vcpu_load(vcpu);
11840 ret = __set_sregs(vcpu, sregs);
11841 vcpu_put(vcpu);
11842 return ret;
11843 }
11844
kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm * kvm)11845 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11846 {
11847 bool set = false;
11848 struct kvm_vcpu *vcpu;
11849 unsigned long i;
11850
11851 if (!enable_apicv)
11852 return;
11853
11854 down_write(&kvm->arch.apicv_update_lock);
11855
11856 kvm_for_each_vcpu(i, vcpu, kvm) {
11857 if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11858 set = true;
11859 break;
11860 }
11861 }
11862 __kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11863 up_write(&kvm->arch.apicv_update_lock);
11864 }
11865
kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu * vcpu,struct kvm_guest_debug * dbg)11866 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11867 struct kvm_guest_debug *dbg)
11868 {
11869 unsigned long rflags;
11870 int i, r;
11871
11872 if (vcpu->arch.guest_state_protected)
11873 return -EINVAL;
11874
11875 vcpu_load(vcpu);
11876
11877 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11878 r = -EBUSY;
11879 if (kvm_is_exception_pending(vcpu))
11880 goto out;
11881 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11882 kvm_queue_exception(vcpu, DB_VECTOR);
11883 else
11884 kvm_queue_exception(vcpu, BP_VECTOR);
11885 }
11886
11887 /*
11888 * Read rflags as long as potentially injected trace flags are still
11889 * filtered out.
11890 */
11891 rflags = kvm_get_rflags(vcpu);
11892
11893 vcpu->guest_debug = dbg->control;
11894 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11895 vcpu->guest_debug = 0;
11896
11897 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11898 for (i = 0; i < KVM_NR_DB_REGS; ++i)
11899 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11900 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11901 } else {
11902 for (i = 0; i < KVM_NR_DB_REGS; i++)
11903 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11904 }
11905 kvm_update_dr7(vcpu);
11906
11907 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11908 vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11909
11910 /*
11911 * Trigger an rflags update that will inject or remove the trace
11912 * flags.
11913 */
11914 kvm_set_rflags(vcpu, rflags);
11915
11916 static_call(kvm_x86_update_exception_bitmap)(vcpu);
11917
11918 kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11919
11920 r = 0;
11921
11922 out:
11923 vcpu_put(vcpu);
11924 return r;
11925 }
11926
11927 /*
11928 * Translate a guest virtual address to a guest physical address.
11929 */
kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu * vcpu,struct kvm_translation * tr)11930 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11931 struct kvm_translation *tr)
11932 {
11933 unsigned long vaddr = tr->linear_address;
11934 gpa_t gpa;
11935 int idx;
11936
11937 vcpu_load(vcpu);
11938
11939 idx = srcu_read_lock(&vcpu->kvm->srcu);
11940 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11941 srcu_read_unlock(&vcpu->kvm->srcu, idx);
11942 tr->physical_address = gpa;
11943 tr->valid = gpa != INVALID_GPA;
11944 tr->writeable = 1;
11945 tr->usermode = 0;
11946
11947 vcpu_put(vcpu);
11948 return 0;
11949 }
11950
kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)11951 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11952 {
11953 struct fxregs_state *fxsave;
11954
11955 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11956 return 0;
11957
11958 vcpu_load(vcpu);
11959
11960 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11961 memcpy(fpu->fpr, fxsave->st_space, 128);
11962 fpu->fcw = fxsave->cwd;
11963 fpu->fsw = fxsave->swd;
11964 fpu->ftwx = fxsave->twd;
11965 fpu->last_opcode = fxsave->fop;
11966 fpu->last_ip = fxsave->rip;
11967 fpu->last_dp = fxsave->rdp;
11968 memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11969
11970 vcpu_put(vcpu);
11971 return 0;
11972 }
11973
kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)11974 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11975 {
11976 struct fxregs_state *fxsave;
11977
11978 if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11979 return 0;
11980
11981 vcpu_load(vcpu);
11982
11983 fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11984
11985 memcpy(fxsave->st_space, fpu->fpr, 128);
11986 fxsave->cwd = fpu->fcw;
11987 fxsave->swd = fpu->fsw;
11988 fxsave->twd = fpu->ftwx;
11989 fxsave->fop = fpu->last_opcode;
11990 fxsave->rip = fpu->last_ip;
11991 fxsave->rdp = fpu->last_dp;
11992 memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11993
11994 vcpu_put(vcpu);
11995 return 0;
11996 }
11997
store_regs(struct kvm_vcpu * vcpu)11998 static void store_regs(struct kvm_vcpu *vcpu)
11999 {
12000 BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
12001
12002 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
12003 __get_regs(vcpu, &vcpu->run->s.regs.regs);
12004
12005 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
12006 __get_sregs(vcpu, &vcpu->run->s.regs.sregs);
12007
12008 if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
12009 kvm_vcpu_ioctl_x86_get_vcpu_events(
12010 vcpu, &vcpu->run->s.regs.events);
12011 }
12012
sync_regs(struct kvm_vcpu * vcpu)12013 static int sync_regs(struct kvm_vcpu *vcpu)
12014 {
12015 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
12016 __set_regs(vcpu, &vcpu->run->s.regs.regs);
12017 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
12018 }
12019
12020 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
12021 struct kvm_sregs sregs = vcpu->run->s.regs.sregs;
12022
12023 if (__set_sregs(vcpu, &sregs))
12024 return -EINVAL;
12025
12026 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
12027 }
12028
12029 if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
12030 struct kvm_vcpu_events events = vcpu->run->s.regs.events;
12031
12032 if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events))
12033 return -EINVAL;
12034
12035 vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
12036 }
12037
12038 return 0;
12039 }
12040
kvm_arch_vcpu_precreate(struct kvm * kvm,unsigned int id)12041 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
12042 {
12043 if (kvm_check_tsc_unstable() && kvm->created_vcpus)
12044 pr_warn_once("SMP vm created on host with unstable TSC; "
12045 "guest TSC will not be reliable\n");
12046
12047 if (!kvm->arch.max_vcpu_ids)
12048 kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
12049
12050 if (id >= kvm->arch.max_vcpu_ids)
12051 return -EINVAL;
12052
12053 return static_call(kvm_x86_vcpu_precreate)(kvm);
12054 }
12055
kvm_arch_vcpu_create(struct kvm_vcpu * vcpu)12056 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
12057 {
12058 struct page *page;
12059 int r;
12060
12061 vcpu->arch.last_vmentry_cpu = -1;
12062 vcpu->arch.regs_avail = ~0;
12063 vcpu->arch.regs_dirty = ~0;
12064
12065 kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
12066
12067 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
12068 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
12069 else
12070 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
12071
12072 r = kvm_mmu_create(vcpu);
12073 if (r < 0)
12074 return r;
12075
12076 if (irqchip_in_kernel(vcpu->kvm)) {
12077 r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
12078 if (r < 0)
12079 goto fail_mmu_destroy;
12080
12081 /*
12082 * Defer evaluating inhibits until the vCPU is first run, as
12083 * this vCPU will not get notified of any changes until this
12084 * vCPU is visible to other vCPUs (marked online and added to
12085 * the set of vCPUs). Opportunistically mark APICv active as
12086 * VMX in particularly is highly unlikely to have inhibits.
12087 * Ignore the current per-VM APICv state so that vCPU creation
12088 * is guaranteed to run with a deterministic value, the request
12089 * will ensure the vCPU gets the correct state before VM-Entry.
12090 */
12091 if (enable_apicv) {
12092 vcpu->arch.apic->apicv_active = true;
12093 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
12094 }
12095 } else
12096 static_branch_inc(&kvm_has_noapic_vcpu);
12097
12098 r = -ENOMEM;
12099
12100 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
12101 if (!page)
12102 goto fail_free_lapic;
12103 vcpu->arch.pio_data = page_address(page);
12104
12105 vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
12106 GFP_KERNEL_ACCOUNT);
12107 vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
12108 GFP_KERNEL_ACCOUNT);
12109 if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
12110 goto fail_free_mce_banks;
12111 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
12112
12113 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
12114 GFP_KERNEL_ACCOUNT))
12115 goto fail_free_mce_banks;
12116
12117 if (!alloc_emulate_ctxt(vcpu))
12118 goto free_wbinvd_dirty_mask;
12119
12120 if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
12121 pr_err("failed to allocate vcpu's fpu\n");
12122 goto free_emulate_ctxt;
12123 }
12124
12125 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
12126 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
12127
12128 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
12129
12130 kvm_async_pf_hash_reset(vcpu);
12131
12132 vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
12133 kvm_pmu_init(vcpu);
12134
12135 vcpu->arch.pending_external_vector = -1;
12136 vcpu->arch.preempted_in_kernel = false;
12137
12138 #if IS_ENABLED(CONFIG_HYPERV)
12139 vcpu->arch.hv_root_tdp = INVALID_PAGE;
12140 #endif
12141
12142 r = static_call(kvm_x86_vcpu_create)(vcpu);
12143 if (r)
12144 goto free_guest_fpu;
12145
12146 vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
12147 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
12148 kvm_xen_init_vcpu(vcpu);
12149 kvm_vcpu_mtrr_init(vcpu);
12150 vcpu_load(vcpu);
12151 kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
12152 kvm_vcpu_reset(vcpu, false);
12153 kvm_init_mmu(vcpu);
12154 vcpu_put(vcpu);
12155 return 0;
12156
12157 free_guest_fpu:
12158 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12159 free_emulate_ctxt:
12160 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12161 free_wbinvd_dirty_mask:
12162 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12163 fail_free_mce_banks:
12164 kfree(vcpu->arch.mce_banks);
12165 kfree(vcpu->arch.mci_ctl2_banks);
12166 free_page((unsigned long)vcpu->arch.pio_data);
12167 fail_free_lapic:
12168 kvm_free_lapic(vcpu);
12169 fail_mmu_destroy:
12170 kvm_mmu_destroy(vcpu);
12171 return r;
12172 }
12173
kvm_arch_vcpu_postcreate(struct kvm_vcpu * vcpu)12174 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
12175 {
12176 struct kvm *kvm = vcpu->kvm;
12177
12178 if (mutex_lock_killable(&vcpu->mutex))
12179 return;
12180 vcpu_load(vcpu);
12181 kvm_synchronize_tsc(vcpu, NULL);
12182 vcpu_put(vcpu);
12183
12184 /* poll control enabled by default */
12185 vcpu->arch.msr_kvm_poll_control = 1;
12186
12187 mutex_unlock(&vcpu->mutex);
12188
12189 if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
12190 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
12191 KVMCLOCK_SYNC_PERIOD);
12192 }
12193
kvm_arch_vcpu_destroy(struct kvm_vcpu * vcpu)12194 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
12195 {
12196 int idx;
12197
12198 kvmclock_reset(vcpu);
12199
12200 static_call(kvm_x86_vcpu_free)(vcpu);
12201
12202 kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12203 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12204 fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12205
12206 kvm_xen_destroy_vcpu(vcpu);
12207 kvm_hv_vcpu_uninit(vcpu);
12208 kvm_pmu_destroy(vcpu);
12209 kfree(vcpu->arch.mce_banks);
12210 kfree(vcpu->arch.mci_ctl2_banks);
12211 kvm_free_lapic(vcpu);
12212 idx = srcu_read_lock(&vcpu->kvm->srcu);
12213 kvm_mmu_destroy(vcpu);
12214 srcu_read_unlock(&vcpu->kvm->srcu, idx);
12215 free_page((unsigned long)vcpu->arch.pio_data);
12216 kvfree(vcpu->arch.cpuid_entries);
12217 if (!lapic_in_kernel(vcpu))
12218 static_branch_dec(&kvm_has_noapic_vcpu);
12219 }
12220
kvm_vcpu_reset(struct kvm_vcpu * vcpu,bool init_event)12221 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
12222 {
12223 struct kvm_cpuid_entry2 *cpuid_0x1;
12224 unsigned long old_cr0 = kvm_read_cr0(vcpu);
12225 unsigned long new_cr0;
12226
12227 /*
12228 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12229 * to handle side effects. RESET emulation hits those flows and relies
12230 * on emulated/virtualized registers, including those that are loaded
12231 * into hardware, to be zeroed at vCPU creation. Use CRs as a sentinel
12232 * to detect improper or missing initialization.
12233 */
12234 WARN_ON_ONCE(!init_event &&
12235 (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
12236
12237 /*
12238 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
12239 * possible to INIT the vCPU while L2 is active. Force the vCPU back
12240 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
12241 * bits), i.e. virtualization is disabled.
12242 */
12243 if (is_guest_mode(vcpu))
12244 kvm_leave_nested(vcpu);
12245
12246 kvm_lapic_reset(vcpu, init_event);
12247
12248 WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12249 vcpu->arch.hflags = 0;
12250
12251 vcpu->arch.smi_pending = 0;
12252 vcpu->arch.smi_count = 0;
12253 atomic_set(&vcpu->arch.nmi_queued, 0);
12254 vcpu->arch.nmi_pending = 0;
12255 vcpu->arch.nmi_injected = false;
12256 kvm_clear_interrupt_queue(vcpu);
12257 kvm_clear_exception_queue(vcpu);
12258
12259 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12260 kvm_update_dr0123(vcpu);
12261 vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12262 vcpu->arch.dr7 = DR7_FIXED_1;
12263 kvm_update_dr7(vcpu);
12264
12265 vcpu->arch.cr2 = 0;
12266
12267 kvm_make_request(KVM_REQ_EVENT, vcpu);
12268 vcpu->arch.apf.msr_en_val = 0;
12269 vcpu->arch.apf.msr_int_val = 0;
12270 vcpu->arch.st.msr_val = 0;
12271
12272 kvmclock_reset(vcpu);
12273
12274 kvm_clear_async_pf_completion_queue(vcpu);
12275 kvm_async_pf_hash_reset(vcpu);
12276 vcpu->arch.apf.halted = false;
12277
12278 if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12279 struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12280
12281 /*
12282 * All paths that lead to INIT are required to load the guest's
12283 * FPU state (because most paths are buried in KVM_RUN).
12284 */
12285 if (init_event)
12286 kvm_put_guest_fpu(vcpu);
12287
12288 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12289 fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12290
12291 if (init_event)
12292 kvm_load_guest_fpu(vcpu);
12293 }
12294
12295 if (!init_event) {
12296 vcpu->arch.smbase = 0x30000;
12297
12298 vcpu->arch.msr_misc_features_enables = 0;
12299 vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12300 MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12301
12302 __kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12303 __kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12304 }
12305
12306 /* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12307 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12308 kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12309
12310 /*
12311 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12312 * if no CPUID match is found. Note, it's impossible to get a match at
12313 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12314 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12315 * on RESET. But, go through the motions in case that's ever remedied.
12316 */
12317 cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12318 kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12319
12320 static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12321
12322 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12323 kvm_rip_write(vcpu, 0xfff0);
12324
12325 vcpu->arch.cr3 = 0;
12326 kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12327
12328 /*
12329 * CR0.CD/NW are set on RESET, preserved on INIT. Note, some versions
12330 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12331 * (or qualify) that with a footnote stating that CD/NW are preserved.
12332 */
12333 new_cr0 = X86_CR0_ET;
12334 if (init_event)
12335 new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12336 else
12337 new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12338
12339 static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12340 static_call(kvm_x86_set_cr4)(vcpu, 0);
12341 static_call(kvm_x86_set_efer)(vcpu, 0);
12342 static_call(kvm_x86_update_exception_bitmap)(vcpu);
12343
12344 /*
12345 * On the standard CR0/CR4/EFER modification paths, there are several
12346 * complex conditions determining whether the MMU has to be reset and/or
12347 * which PCIDs have to be flushed. However, CR0.WP and the paging-related
12348 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12349 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12350 * CR0 will be '0' prior to RESET). So we only need to check CR0.PG here.
12351 */
12352 if (old_cr0 & X86_CR0_PG) {
12353 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12354 kvm_mmu_reset_context(vcpu);
12355 }
12356
12357 /*
12358 * Intel's SDM states that all TLB entries are flushed on INIT. AMD's
12359 * APM states the TLBs are untouched by INIT, but it also states that
12360 * the TLBs are flushed on "External initialization of the processor."
12361 * Flush the guest TLB regardless of vendor, there is no meaningful
12362 * benefit in relying on the guest to flush the TLB immediately after
12363 * INIT. A spurious TLB flush is benign and likely negligible from a
12364 * performance perspective.
12365 */
12366 if (init_event)
12367 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12368 }
12369 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12370
kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu * vcpu,u8 vector)12371 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12372 {
12373 struct kvm_segment cs;
12374
12375 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12376 cs.selector = vector << 8;
12377 cs.base = vector << 12;
12378 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12379 kvm_rip_write(vcpu, 0);
12380 }
12381 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12382
kvm_arch_hardware_enable(void)12383 int kvm_arch_hardware_enable(void)
12384 {
12385 struct kvm *kvm;
12386 struct kvm_vcpu *vcpu;
12387 unsigned long i;
12388 int ret;
12389 u64 local_tsc;
12390 u64 max_tsc = 0;
12391 bool stable, backwards_tsc = false;
12392
12393 kvm_user_return_msr_cpu_online();
12394
12395 ret = kvm_x86_check_processor_compatibility();
12396 if (ret)
12397 return ret;
12398
12399 ret = static_call(kvm_x86_hardware_enable)();
12400 if (ret != 0)
12401 return ret;
12402
12403 local_tsc = rdtsc();
12404 stable = !kvm_check_tsc_unstable();
12405 list_for_each_entry(kvm, &vm_list, vm_list) {
12406 kvm_for_each_vcpu(i, vcpu, kvm) {
12407 if (!stable && vcpu->cpu == smp_processor_id())
12408 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12409 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12410 backwards_tsc = true;
12411 if (vcpu->arch.last_host_tsc > max_tsc)
12412 max_tsc = vcpu->arch.last_host_tsc;
12413 }
12414 }
12415 }
12416
12417 /*
12418 * Sometimes, even reliable TSCs go backwards. This happens on
12419 * platforms that reset TSC during suspend or hibernate actions, but
12420 * maintain synchronization. We must compensate. Fortunately, we can
12421 * detect that condition here, which happens early in CPU bringup,
12422 * before any KVM threads can be running. Unfortunately, we can't
12423 * bring the TSCs fully up to date with real time, as we aren't yet far
12424 * enough into CPU bringup that we know how much real time has actually
12425 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12426 * variables that haven't been updated yet.
12427 *
12428 * So we simply find the maximum observed TSC above, then record the
12429 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
12430 * the adjustment will be applied. Note that we accumulate
12431 * adjustments, in case multiple suspend cycles happen before some VCPU
12432 * gets a chance to run again. In the event that no KVM threads get a
12433 * chance to run, we will miss the entire elapsed period, as we'll have
12434 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12435 * loose cycle time. This isn't too big a deal, since the loss will be
12436 * uniform across all VCPUs (not to mention the scenario is extremely
12437 * unlikely). It is possible that a second hibernate recovery happens
12438 * much faster than a first, causing the observed TSC here to be
12439 * smaller; this would require additional padding adjustment, which is
12440 * why we set last_host_tsc to the local tsc observed here.
12441 *
12442 * N.B. - this code below runs only on platforms with reliable TSC,
12443 * as that is the only way backwards_tsc is set above. Also note
12444 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12445 * have the same delta_cyc adjustment applied if backwards_tsc
12446 * is detected. Note further, this adjustment is only done once,
12447 * as we reset last_host_tsc on all VCPUs to stop this from being
12448 * called multiple times (one for each physical CPU bringup).
12449 *
12450 * Platforms with unreliable TSCs don't have to deal with this, they
12451 * will be compensated by the logic in vcpu_load, which sets the TSC to
12452 * catchup mode. This will catchup all VCPUs to real time, but cannot
12453 * guarantee that they stay in perfect synchronization.
12454 */
12455 if (backwards_tsc) {
12456 u64 delta_cyc = max_tsc - local_tsc;
12457 list_for_each_entry(kvm, &vm_list, vm_list) {
12458 kvm->arch.backwards_tsc_observed = true;
12459 kvm_for_each_vcpu(i, vcpu, kvm) {
12460 vcpu->arch.tsc_offset_adjustment += delta_cyc;
12461 vcpu->arch.last_host_tsc = local_tsc;
12462 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12463 }
12464
12465 /*
12466 * We have to disable TSC offset matching.. if you were
12467 * booting a VM while issuing an S4 host suspend....
12468 * you may have some problem. Solving this issue is
12469 * left as an exercise to the reader.
12470 */
12471 kvm->arch.last_tsc_nsec = 0;
12472 kvm->arch.last_tsc_write = 0;
12473 }
12474
12475 }
12476 return 0;
12477 }
12478
kvm_arch_hardware_disable(void)12479 void kvm_arch_hardware_disable(void)
12480 {
12481 static_call(kvm_x86_hardware_disable)();
12482 drop_user_return_notifiers();
12483 }
12484
kvm_vcpu_is_reset_bsp(struct kvm_vcpu * vcpu)12485 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12486 {
12487 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12488 }
12489
kvm_vcpu_is_bsp(struct kvm_vcpu * vcpu)12490 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12491 {
12492 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12493 }
12494
12495 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12496 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12497
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)12498 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12499 {
12500 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12501
12502 vcpu->arch.l1tf_flush_l1d = true;
12503 if (pmu->version && unlikely(pmu->event_count)) {
12504 pmu->need_cleanup = true;
12505 kvm_make_request(KVM_REQ_PMU, vcpu);
12506 }
12507 static_call(kvm_x86_sched_in)(vcpu, cpu);
12508 }
12509
kvm_arch_free_vm(struct kvm * kvm)12510 void kvm_arch_free_vm(struct kvm *kvm)
12511 {
12512 #if IS_ENABLED(CONFIG_HYPERV)
12513 kfree(kvm->arch.hv_pa_pg);
12514 #endif
12515 __kvm_arch_free_vm(kvm);
12516 }
12517
12518
kvm_arch_init_vm(struct kvm * kvm,unsigned long type)12519 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12520 {
12521 int ret;
12522 unsigned long flags;
12523
12524 if (!kvm_is_vm_type_supported(type))
12525 return -EINVAL;
12526
12527 kvm->arch.vm_type = type;
12528
12529 ret = kvm_page_track_init(kvm);
12530 if (ret)
12531 goto out;
12532
12533 kvm_mmu_init_vm(kvm);
12534
12535 ret = static_call(kvm_x86_vm_init)(kvm);
12536 if (ret)
12537 goto out_uninit_mmu;
12538
12539 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12540 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12541
12542 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12543 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12544 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12545 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12546 &kvm->arch.irq_sources_bitmap);
12547
12548 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12549 mutex_init(&kvm->arch.apic_map_lock);
12550 seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12551 kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12552
12553 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12554 pvclock_update_vm_gtod_copy(kvm);
12555 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12556
12557 kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12558 kvm->arch.guest_can_read_msr_platform_info = true;
12559 kvm->arch.enable_pmu = enable_pmu;
12560
12561 #if IS_ENABLED(CONFIG_HYPERV)
12562 spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12563 kvm->arch.hv_root_tdp = INVALID_PAGE;
12564 #endif
12565
12566 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12567 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12568
12569 kvm_apicv_init(kvm);
12570 kvm_hv_init_vm(kvm);
12571 kvm_xen_init_vm(kvm);
12572
12573 return 0;
12574
12575 out_uninit_mmu:
12576 kvm_mmu_uninit_vm(kvm);
12577 kvm_page_track_cleanup(kvm);
12578 out:
12579 return ret;
12580 }
12581
kvm_arch_post_init_vm(struct kvm * kvm)12582 int kvm_arch_post_init_vm(struct kvm *kvm)
12583 {
12584 return kvm_mmu_post_init_vm(kvm);
12585 }
12586
kvm_unload_vcpu_mmu(struct kvm_vcpu * vcpu)12587 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12588 {
12589 vcpu_load(vcpu);
12590 kvm_mmu_unload(vcpu);
12591 vcpu_put(vcpu);
12592 }
12593
kvm_unload_vcpu_mmus(struct kvm * kvm)12594 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12595 {
12596 unsigned long i;
12597 struct kvm_vcpu *vcpu;
12598
12599 kvm_for_each_vcpu(i, vcpu, kvm) {
12600 kvm_clear_async_pf_completion_queue(vcpu);
12601 kvm_unload_vcpu_mmu(vcpu);
12602 }
12603 }
12604
kvm_arch_sync_events(struct kvm * kvm)12605 void kvm_arch_sync_events(struct kvm *kvm)
12606 {
12607 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12608 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12609 kvm_free_pit(kvm);
12610 }
12611
12612 /**
12613 * __x86_set_memory_region: Setup KVM internal memory slot
12614 *
12615 * @kvm: the kvm pointer to the VM.
12616 * @id: the slot ID to setup.
12617 * @gpa: the GPA to install the slot (unused when @size == 0).
12618 * @size: the size of the slot. Set to zero to uninstall a slot.
12619 *
12620 * This function helps to setup a KVM internal memory slot. Specify
12621 * @size > 0 to install a new slot, while @size == 0 to uninstall a
12622 * slot. The return code can be one of the following:
12623 *
12624 * HVA: on success (uninstall will return a bogus HVA)
12625 * -errno: on error
12626 *
12627 * The caller should always use IS_ERR() to check the return value
12628 * before use. Note, the KVM internal memory slots are guaranteed to
12629 * remain valid and unchanged until the VM is destroyed, i.e., the
12630 * GPA->HVA translation will not change. However, the HVA is a user
12631 * address, i.e. its accessibility is not guaranteed, and must be
12632 * accessed via __copy_{to,from}_user().
12633 */
__x86_set_memory_region(struct kvm * kvm,int id,gpa_t gpa,u32 size)12634 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12635 u32 size)
12636 {
12637 int i, r;
12638 unsigned long hva, old_npages;
12639 struct kvm_memslots *slots = kvm_memslots(kvm);
12640 struct kvm_memory_slot *slot;
12641
12642 /* Called with kvm->slots_lock held. */
12643 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12644 return ERR_PTR_USR(-EINVAL);
12645
12646 slot = id_to_memslot(slots, id);
12647 if (size) {
12648 if (slot && slot->npages)
12649 return ERR_PTR_USR(-EEXIST);
12650
12651 /*
12652 * MAP_SHARED to prevent internal slot pages from being moved
12653 * by fork()/COW.
12654 */
12655 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12656 MAP_SHARED | MAP_ANONYMOUS, 0);
12657 if (IS_ERR_VALUE(hva))
12658 return (void __user *)hva;
12659 } else {
12660 if (!slot || !slot->npages)
12661 return NULL;
12662
12663 old_npages = slot->npages;
12664 hva = slot->userspace_addr;
12665 }
12666
12667 for (i = 0; i < kvm_arch_nr_memslot_as_ids(kvm); i++) {
12668 struct kvm_userspace_memory_region2 m;
12669
12670 m.slot = id | (i << 16);
12671 m.flags = 0;
12672 m.guest_phys_addr = gpa;
12673 m.userspace_addr = hva;
12674 m.memory_size = size;
12675 r = __kvm_set_memory_region(kvm, &m);
12676 if (r < 0)
12677 return ERR_PTR_USR(r);
12678 }
12679
12680 if (!size)
12681 vm_munmap(hva, old_npages * PAGE_SIZE);
12682
12683 return (void __user *)hva;
12684 }
12685 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12686
kvm_arch_pre_destroy_vm(struct kvm * kvm)12687 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12688 {
12689 kvm_mmu_pre_destroy_vm(kvm);
12690 }
12691
kvm_arch_destroy_vm(struct kvm * kvm)12692 void kvm_arch_destroy_vm(struct kvm *kvm)
12693 {
12694 if (current->mm == kvm->mm) {
12695 /*
12696 * Free memory regions allocated on behalf of userspace,
12697 * unless the memory map has changed due to process exit
12698 * or fd copying.
12699 */
12700 mutex_lock(&kvm->slots_lock);
12701 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12702 0, 0);
12703 __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12704 0, 0);
12705 __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12706 mutex_unlock(&kvm->slots_lock);
12707 }
12708 kvm_unload_vcpu_mmus(kvm);
12709 static_call_cond(kvm_x86_vm_destroy)(kvm);
12710 kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12711 kvm_pic_destroy(kvm);
12712 kvm_ioapic_destroy(kvm);
12713 kvm_destroy_vcpus(kvm);
12714 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12715 kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12716 kvm_mmu_uninit_vm(kvm);
12717 kvm_page_track_cleanup(kvm);
12718 kvm_xen_destroy_vm(kvm);
12719 kvm_hv_destroy_vm(kvm);
12720 }
12721
memslot_rmap_free(struct kvm_memory_slot * slot)12722 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12723 {
12724 int i;
12725
12726 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12727 kvfree(slot->arch.rmap[i]);
12728 slot->arch.rmap[i] = NULL;
12729 }
12730 }
12731
kvm_arch_free_memslot(struct kvm * kvm,struct kvm_memory_slot * slot)12732 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12733 {
12734 int i;
12735
12736 memslot_rmap_free(slot);
12737
12738 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12739 kvfree(slot->arch.lpage_info[i - 1]);
12740 slot->arch.lpage_info[i - 1] = NULL;
12741 }
12742
12743 kvm_page_track_free_memslot(slot);
12744 }
12745
memslot_rmap_alloc(struct kvm_memory_slot * slot,unsigned long npages)12746 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12747 {
12748 const int sz = sizeof(*slot->arch.rmap[0]);
12749 int i;
12750
12751 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12752 int level = i + 1;
12753 int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12754
12755 if (slot->arch.rmap[i])
12756 continue;
12757
12758 slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12759 if (!slot->arch.rmap[i]) {
12760 memslot_rmap_free(slot);
12761 return -ENOMEM;
12762 }
12763 }
12764
12765 return 0;
12766 }
12767
kvm_alloc_memslot_metadata(struct kvm * kvm,struct kvm_memory_slot * slot)12768 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12769 struct kvm_memory_slot *slot)
12770 {
12771 unsigned long npages = slot->npages;
12772 int i, r;
12773
12774 /*
12775 * Clear out the previous array pointers for the KVM_MR_MOVE case. The
12776 * old arrays will be freed by __kvm_set_memory_region() if installing
12777 * the new memslot is successful.
12778 */
12779 memset(&slot->arch, 0, sizeof(slot->arch));
12780
12781 if (kvm_memslots_have_rmaps(kvm)) {
12782 r = memslot_rmap_alloc(slot, npages);
12783 if (r)
12784 return r;
12785 }
12786
12787 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12788 struct kvm_lpage_info *linfo;
12789 unsigned long ugfn;
12790 int lpages;
12791 int level = i + 1;
12792
12793 lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12794
12795 linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12796 if (!linfo)
12797 goto out_free;
12798
12799 slot->arch.lpage_info[i - 1] = linfo;
12800
12801 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12802 linfo[0].disallow_lpage = 1;
12803 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12804 linfo[lpages - 1].disallow_lpage = 1;
12805 ugfn = slot->userspace_addr >> PAGE_SHIFT;
12806 /*
12807 * If the gfn and userspace address are not aligned wrt each
12808 * other, disable large page support for this slot.
12809 */
12810 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12811 unsigned long j;
12812
12813 for (j = 0; j < lpages; ++j)
12814 linfo[j].disallow_lpage = 1;
12815 }
12816 }
12817
12818 #ifdef CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES
12819 kvm_mmu_init_memslot_memory_attributes(kvm, slot);
12820 #endif
12821
12822 if (kvm_page_track_create_memslot(kvm, slot, npages))
12823 goto out_free;
12824
12825 return 0;
12826
12827 out_free:
12828 memslot_rmap_free(slot);
12829
12830 for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12831 kvfree(slot->arch.lpage_info[i - 1]);
12832 slot->arch.lpage_info[i - 1] = NULL;
12833 }
12834 return -ENOMEM;
12835 }
12836
kvm_arch_memslots_updated(struct kvm * kvm,u64 gen)12837 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12838 {
12839 struct kvm_vcpu *vcpu;
12840 unsigned long i;
12841
12842 /*
12843 * memslots->generation has been incremented.
12844 * mmio generation may have reached its maximum value.
12845 */
12846 kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12847
12848 /* Force re-initialization of steal_time cache */
12849 kvm_for_each_vcpu(i, vcpu, kvm)
12850 kvm_vcpu_kick(vcpu);
12851 }
12852
kvm_arch_prepare_memory_region(struct kvm * kvm,const struct kvm_memory_slot * old,struct kvm_memory_slot * new,enum kvm_mr_change change)12853 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12854 const struct kvm_memory_slot *old,
12855 struct kvm_memory_slot *new,
12856 enum kvm_mr_change change)
12857 {
12858 /*
12859 * KVM doesn't support moving memslots when there are external page
12860 * trackers attached to the VM, i.e. if KVMGT is in use.
12861 */
12862 if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm))
12863 return -EINVAL;
12864
12865 if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12866 if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12867 return -EINVAL;
12868
12869 return kvm_alloc_memslot_metadata(kvm, new);
12870 }
12871
12872 if (change == KVM_MR_FLAGS_ONLY)
12873 memcpy(&new->arch, &old->arch, sizeof(old->arch));
12874 else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12875 return -EIO;
12876
12877 return 0;
12878 }
12879
12880
kvm_mmu_update_cpu_dirty_logging(struct kvm * kvm,bool enable)12881 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12882 {
12883 int nr_slots;
12884
12885 if (!kvm_x86_ops.cpu_dirty_log_size)
12886 return;
12887
12888 nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12889 if ((enable && nr_slots == 1) || !nr_slots)
12890 kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12891 }
12892
kvm_mmu_slot_apply_flags(struct kvm * kvm,struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)12893 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12894 struct kvm_memory_slot *old,
12895 const struct kvm_memory_slot *new,
12896 enum kvm_mr_change change)
12897 {
12898 u32 old_flags = old ? old->flags : 0;
12899 u32 new_flags = new ? new->flags : 0;
12900 bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12901
12902 /*
12903 * Update CPU dirty logging if dirty logging is being toggled. This
12904 * applies to all operations.
12905 */
12906 if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12907 kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12908
12909 /*
12910 * Nothing more to do for RO slots (which can't be dirtied and can't be
12911 * made writable) or CREATE/MOVE/DELETE of a slot.
12912 *
12913 * For a memslot with dirty logging disabled:
12914 * CREATE: No dirty mappings will already exist.
12915 * MOVE/DELETE: The old mappings will already have been cleaned up by
12916 * kvm_arch_flush_shadow_memslot()
12917 *
12918 * For a memslot with dirty logging enabled:
12919 * CREATE: No shadow pages exist, thus nothing to write-protect
12920 * and no dirty bits to clear.
12921 * MOVE/DELETE: The old mappings will already have been cleaned up by
12922 * kvm_arch_flush_shadow_memslot().
12923 */
12924 if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12925 return;
12926
12927 /*
12928 * READONLY and non-flags changes were filtered out above, and the only
12929 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12930 * logging isn't being toggled on or off.
12931 */
12932 if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12933 return;
12934
12935 if (!log_dirty_pages) {
12936 /*
12937 * Dirty logging tracks sptes in 4k granularity, meaning that
12938 * large sptes have to be split. If live migration succeeds,
12939 * the guest in the source machine will be destroyed and large
12940 * sptes will be created in the destination. However, if the
12941 * guest continues to run in the source machine (for example if
12942 * live migration fails), small sptes will remain around and
12943 * cause bad performance.
12944 *
12945 * Scan sptes if dirty logging has been stopped, dropping those
12946 * which can be collapsed into a single large-page spte. Later
12947 * page faults will create the large-page sptes.
12948 */
12949 kvm_mmu_zap_collapsible_sptes(kvm, new);
12950 } else {
12951 /*
12952 * Initially-all-set does not require write protecting any page,
12953 * because they're all assumed to be dirty.
12954 */
12955 if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12956 return;
12957
12958 if (READ_ONCE(eager_page_split))
12959 kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12960
12961 if (kvm_x86_ops.cpu_dirty_log_size) {
12962 kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12963 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12964 } else {
12965 kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12966 }
12967
12968 /*
12969 * Unconditionally flush the TLBs after enabling dirty logging.
12970 * A flush is almost always going to be necessary (see below),
12971 * and unconditionally flushing allows the helpers to omit
12972 * the subtly complex checks when removing write access.
12973 *
12974 * Do the flush outside of mmu_lock to reduce the amount of
12975 * time mmu_lock is held. Flushing after dropping mmu_lock is
12976 * safe as KVM only needs to guarantee the slot is fully
12977 * write-protected before returning to userspace, i.e. before
12978 * userspace can consume the dirty status.
12979 *
12980 * Flushing outside of mmu_lock requires KVM to be careful when
12981 * making decisions based on writable status of an SPTE, e.g. a
12982 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12983 *
12984 * Specifically, KVM also write-protects guest page tables to
12985 * monitor changes when using shadow paging, and must guarantee
12986 * no CPUs can write to those page before mmu_lock is dropped.
12987 * Because CPUs may have stale TLB entries at this point, a
12988 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12989 *
12990 * KVM also allows making SPTES writable outside of mmu_lock,
12991 * e.g. to allow dirty logging without taking mmu_lock.
12992 *
12993 * To handle these scenarios, KVM uses a separate software-only
12994 * bit (MMU-writable) to track if a SPTE is !writable due to
12995 * a guest page table being write-protected (KVM clears the
12996 * MMU-writable flag when write-protecting for shadow paging).
12997 *
12998 * The use of MMU-writable is also the primary motivation for
12999 * the unconditional flush. Because KVM must guarantee that a
13000 * CPU doesn't contain stale, writable TLB entries for a
13001 * !MMU-writable SPTE, KVM must flush if it encounters any
13002 * MMU-writable SPTE regardless of whether the actual hardware
13003 * writable bit was set. I.e. KVM is almost guaranteed to need
13004 * to flush, while unconditionally flushing allows the "remove
13005 * write access" helpers to ignore MMU-writable entirely.
13006 *
13007 * See is_writable_pte() for more details (the case involving
13008 * access-tracked SPTEs is particularly relevant).
13009 */
13010 kvm_flush_remote_tlbs_memslot(kvm, new);
13011 }
13012 }
13013
kvm_arch_commit_memory_region(struct kvm * kvm,struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)13014 void kvm_arch_commit_memory_region(struct kvm *kvm,
13015 struct kvm_memory_slot *old,
13016 const struct kvm_memory_slot *new,
13017 enum kvm_mr_change change)
13018 {
13019 if (change == KVM_MR_DELETE)
13020 kvm_page_track_delete_slot(kvm, old);
13021
13022 if (!kvm->arch.n_requested_mmu_pages &&
13023 (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
13024 unsigned long nr_mmu_pages;
13025
13026 nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
13027 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
13028 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
13029 }
13030
13031 kvm_mmu_slot_apply_flags(kvm, old, new, change);
13032
13033 /* Free the arrays associated with the old memslot. */
13034 if (change == KVM_MR_MOVE)
13035 kvm_arch_free_memslot(kvm, old);
13036 }
13037
kvm_guest_apic_has_interrupt(struct kvm_vcpu * vcpu)13038 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
13039 {
13040 return (is_guest_mode(vcpu) &&
13041 static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
13042 }
13043
kvm_vcpu_has_events(struct kvm_vcpu * vcpu)13044 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
13045 {
13046 if (!list_empty_careful(&vcpu->async_pf.done))
13047 return true;
13048
13049 if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
13050 kvm_apic_init_sipi_allowed(vcpu))
13051 return true;
13052
13053 if (vcpu->arch.pv.pv_unhalted)
13054 return true;
13055
13056 if (kvm_is_exception_pending(vcpu))
13057 return true;
13058
13059 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
13060 (vcpu->arch.nmi_pending &&
13061 static_call(kvm_x86_nmi_allowed)(vcpu, false)))
13062 return true;
13063
13064 #ifdef CONFIG_KVM_SMM
13065 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
13066 (vcpu->arch.smi_pending &&
13067 static_call(kvm_x86_smi_allowed)(vcpu, false)))
13068 return true;
13069 #endif
13070
13071 if (kvm_test_request(KVM_REQ_PMI, vcpu))
13072 return true;
13073
13074 if (kvm_arch_interrupt_allowed(vcpu) &&
13075 (kvm_cpu_has_interrupt(vcpu) ||
13076 kvm_guest_apic_has_interrupt(vcpu)))
13077 return true;
13078
13079 if (kvm_hv_has_stimer_pending(vcpu))
13080 return true;
13081
13082 if (is_guest_mode(vcpu) &&
13083 kvm_x86_ops.nested_ops->has_events &&
13084 kvm_x86_ops.nested_ops->has_events(vcpu))
13085 return true;
13086
13087 if (kvm_xen_has_pending_events(vcpu))
13088 return true;
13089
13090 return false;
13091 }
13092
kvm_arch_vcpu_runnable(struct kvm_vcpu * vcpu)13093 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
13094 {
13095 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
13096 }
13097
kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu * vcpu)13098 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
13099 {
13100 if (kvm_vcpu_apicv_active(vcpu) &&
13101 static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
13102 return true;
13103
13104 return false;
13105 }
13106
kvm_arch_dy_runnable(struct kvm_vcpu * vcpu)13107 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
13108 {
13109 if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
13110 return true;
13111
13112 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
13113 #ifdef CONFIG_KVM_SMM
13114 kvm_test_request(KVM_REQ_SMI, vcpu) ||
13115 #endif
13116 kvm_test_request(KVM_REQ_EVENT, vcpu))
13117 return true;
13118
13119 return kvm_arch_dy_has_pending_interrupt(vcpu);
13120 }
13121
kvm_arch_vcpu_in_kernel(struct kvm_vcpu * vcpu)13122 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
13123 {
13124 if (vcpu->arch.guest_state_protected)
13125 return true;
13126
13127 if (vcpu != kvm_get_running_vcpu())
13128 return vcpu->arch.preempted_in_kernel;
13129
13130 return static_call(kvm_x86_get_cpl)(vcpu) == 0;
13131 }
13132
kvm_arch_vcpu_get_ip(struct kvm_vcpu * vcpu)13133 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
13134 {
13135 return kvm_rip_read(vcpu);
13136 }
13137
kvm_arch_vcpu_should_kick(struct kvm_vcpu * vcpu)13138 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
13139 {
13140 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
13141 }
13142
kvm_arch_interrupt_allowed(struct kvm_vcpu * vcpu)13143 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
13144 {
13145 return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
13146 }
13147
kvm_get_linear_rip(struct kvm_vcpu * vcpu)13148 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
13149 {
13150 /* Can't read the RIP when guest state is protected, just return 0 */
13151 if (vcpu->arch.guest_state_protected)
13152 return 0;
13153
13154 if (is_64_bit_mode(vcpu))
13155 return kvm_rip_read(vcpu);
13156 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
13157 kvm_rip_read(vcpu));
13158 }
13159 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
13160
kvm_is_linear_rip(struct kvm_vcpu * vcpu,unsigned long linear_rip)13161 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
13162 {
13163 return kvm_get_linear_rip(vcpu) == linear_rip;
13164 }
13165 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
13166
kvm_get_rflags(struct kvm_vcpu * vcpu)13167 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
13168 {
13169 unsigned long rflags;
13170
13171 rflags = static_call(kvm_x86_get_rflags)(vcpu);
13172 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
13173 rflags &= ~X86_EFLAGS_TF;
13174 return rflags;
13175 }
13176 EXPORT_SYMBOL_GPL(kvm_get_rflags);
13177
__kvm_set_rflags(struct kvm_vcpu * vcpu,unsigned long rflags)13178 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13179 {
13180 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
13181 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
13182 rflags |= X86_EFLAGS_TF;
13183 static_call(kvm_x86_set_rflags)(vcpu, rflags);
13184 }
13185
kvm_set_rflags(struct kvm_vcpu * vcpu,unsigned long rflags)13186 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
13187 {
13188 __kvm_set_rflags(vcpu, rflags);
13189 kvm_make_request(KVM_REQ_EVENT, vcpu);
13190 }
13191 EXPORT_SYMBOL_GPL(kvm_set_rflags);
13192
kvm_async_pf_hash_fn(gfn_t gfn)13193 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
13194 {
13195 BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
13196
13197 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
13198 }
13199
kvm_async_pf_next_probe(u32 key)13200 static inline u32 kvm_async_pf_next_probe(u32 key)
13201 {
13202 return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
13203 }
13204
kvm_add_async_pf_gfn(struct kvm_vcpu * vcpu,gfn_t gfn)13205 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13206 {
13207 u32 key = kvm_async_pf_hash_fn(gfn);
13208
13209 while (vcpu->arch.apf.gfns[key] != ~0)
13210 key = kvm_async_pf_next_probe(key);
13211
13212 vcpu->arch.apf.gfns[key] = gfn;
13213 }
13214
kvm_async_pf_gfn_slot(struct kvm_vcpu * vcpu,gfn_t gfn)13215 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
13216 {
13217 int i;
13218 u32 key = kvm_async_pf_hash_fn(gfn);
13219
13220 for (i = 0; i < ASYNC_PF_PER_VCPU &&
13221 (vcpu->arch.apf.gfns[key] != gfn &&
13222 vcpu->arch.apf.gfns[key] != ~0); i++)
13223 key = kvm_async_pf_next_probe(key);
13224
13225 return key;
13226 }
13227
kvm_find_async_pf_gfn(struct kvm_vcpu * vcpu,gfn_t gfn)13228 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13229 {
13230 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
13231 }
13232
kvm_del_async_pf_gfn(struct kvm_vcpu * vcpu,gfn_t gfn)13233 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13234 {
13235 u32 i, j, k;
13236
13237 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
13238
13239 if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
13240 return;
13241
13242 while (true) {
13243 vcpu->arch.apf.gfns[i] = ~0;
13244 do {
13245 j = kvm_async_pf_next_probe(j);
13246 if (vcpu->arch.apf.gfns[j] == ~0)
13247 return;
13248 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
13249 /*
13250 * k lies cyclically in ]i,j]
13251 * | i.k.j |
13252 * |....j i.k.| or |.k..j i...|
13253 */
13254 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13255 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13256 i = j;
13257 }
13258 }
13259
apf_put_user_notpresent(struct kvm_vcpu * vcpu)13260 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13261 {
13262 u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13263
13264 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13265 sizeof(reason));
13266 }
13267
apf_put_user_ready(struct kvm_vcpu * vcpu,u32 token)13268 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13269 {
13270 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13271
13272 return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13273 &token, offset, sizeof(token));
13274 }
13275
apf_pageready_slot_free(struct kvm_vcpu * vcpu)13276 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13277 {
13278 unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13279 u32 val;
13280
13281 if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13282 &val, offset, sizeof(val)))
13283 return false;
13284
13285 return !val;
13286 }
13287
kvm_can_deliver_async_pf(struct kvm_vcpu * vcpu)13288 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13289 {
13290
13291 if (!kvm_pv_async_pf_enabled(vcpu))
13292 return false;
13293
13294 if (vcpu->arch.apf.send_user_only &&
13295 static_call(kvm_x86_get_cpl)(vcpu) == 0)
13296 return false;
13297
13298 if (is_guest_mode(vcpu)) {
13299 /*
13300 * L1 needs to opt into the special #PF vmexits that are
13301 * used to deliver async page faults.
13302 */
13303 return vcpu->arch.apf.delivery_as_pf_vmexit;
13304 } else {
13305 /*
13306 * Play it safe in case the guest temporarily disables paging.
13307 * The real mode IDT in particular is unlikely to have a #PF
13308 * exception setup.
13309 */
13310 return is_paging(vcpu);
13311 }
13312 }
13313
kvm_can_do_async_pf(struct kvm_vcpu * vcpu)13314 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13315 {
13316 if (unlikely(!lapic_in_kernel(vcpu) ||
13317 kvm_event_needs_reinjection(vcpu) ||
13318 kvm_is_exception_pending(vcpu)))
13319 return false;
13320
13321 if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13322 return false;
13323
13324 /*
13325 * If interrupts are off we cannot even use an artificial
13326 * halt state.
13327 */
13328 return kvm_arch_interrupt_allowed(vcpu);
13329 }
13330
kvm_arch_async_page_not_present(struct kvm_vcpu * vcpu,struct kvm_async_pf * work)13331 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13332 struct kvm_async_pf *work)
13333 {
13334 struct x86_exception fault;
13335
13336 trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13337 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13338
13339 if (kvm_can_deliver_async_pf(vcpu) &&
13340 !apf_put_user_notpresent(vcpu)) {
13341 fault.vector = PF_VECTOR;
13342 fault.error_code_valid = true;
13343 fault.error_code = 0;
13344 fault.nested_page_fault = false;
13345 fault.address = work->arch.token;
13346 fault.async_page_fault = true;
13347 kvm_inject_page_fault(vcpu, &fault);
13348 return true;
13349 } else {
13350 /*
13351 * It is not possible to deliver a paravirtualized asynchronous
13352 * page fault, but putting the guest in an artificial halt state
13353 * can be beneficial nevertheless: if an interrupt arrives, we
13354 * can deliver it timely and perhaps the guest will schedule
13355 * another process. When the instruction that triggered a page
13356 * fault is retried, hopefully the page will be ready in the host.
13357 */
13358 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13359 return false;
13360 }
13361 }
13362
kvm_arch_async_page_present(struct kvm_vcpu * vcpu,struct kvm_async_pf * work)13363 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13364 struct kvm_async_pf *work)
13365 {
13366 struct kvm_lapic_irq irq = {
13367 .delivery_mode = APIC_DM_FIXED,
13368 .vector = vcpu->arch.apf.vec
13369 };
13370
13371 if (work->wakeup_all)
13372 work->arch.token = ~0; /* broadcast wakeup */
13373 else
13374 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13375 trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13376
13377 if ((work->wakeup_all || work->notpresent_injected) &&
13378 kvm_pv_async_pf_enabled(vcpu) &&
13379 !apf_put_user_ready(vcpu, work->arch.token)) {
13380 vcpu->arch.apf.pageready_pending = true;
13381 kvm_apic_set_irq(vcpu, &irq, NULL);
13382 }
13383
13384 vcpu->arch.apf.halted = false;
13385 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13386 }
13387
kvm_arch_async_page_present_queued(struct kvm_vcpu * vcpu)13388 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13389 {
13390 kvm_make_request(KVM_REQ_APF_READY, vcpu);
13391 if (!vcpu->arch.apf.pageready_pending)
13392 kvm_vcpu_kick(vcpu);
13393 }
13394
kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu * vcpu)13395 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13396 {
13397 if (!kvm_pv_async_pf_enabled(vcpu))
13398 return true;
13399 else
13400 return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13401 }
13402
kvm_arch_start_assignment(struct kvm * kvm)13403 void kvm_arch_start_assignment(struct kvm *kvm)
13404 {
13405 if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13406 static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13407 }
13408 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13409
kvm_arch_end_assignment(struct kvm * kvm)13410 void kvm_arch_end_assignment(struct kvm *kvm)
13411 {
13412 atomic_dec(&kvm->arch.assigned_device_count);
13413 }
13414 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13415
kvm_arch_has_assigned_device(struct kvm * kvm)13416 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13417 {
13418 return raw_atomic_read(&kvm->arch.assigned_device_count);
13419 }
13420 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13421
kvm_noncoherent_dma_assignment_start_or_stop(struct kvm * kvm)13422 static void kvm_noncoherent_dma_assignment_start_or_stop(struct kvm *kvm)
13423 {
13424 /*
13425 * Non-coherent DMA assignment and de-assignment will affect
13426 * whether KVM honors guest MTRRs and cause changes in memtypes
13427 * in TDP.
13428 * So, pass %true unconditionally to indicate non-coherent DMA was,
13429 * or will be involved, and that zapping SPTEs might be necessary.
13430 */
13431 if (__kvm_mmu_honors_guest_mtrrs(true))
13432 kvm_zap_gfn_range(kvm, gpa_to_gfn(0), gpa_to_gfn(~0ULL));
13433 }
13434
kvm_arch_register_noncoherent_dma(struct kvm * kvm)13435 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13436 {
13437 if (atomic_inc_return(&kvm->arch.noncoherent_dma_count) == 1)
13438 kvm_noncoherent_dma_assignment_start_or_stop(kvm);
13439 }
13440 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13441
kvm_arch_unregister_noncoherent_dma(struct kvm * kvm)13442 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13443 {
13444 if (!atomic_dec_return(&kvm->arch.noncoherent_dma_count))
13445 kvm_noncoherent_dma_assignment_start_or_stop(kvm);
13446 }
13447 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13448
kvm_arch_has_noncoherent_dma(struct kvm * kvm)13449 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13450 {
13451 return atomic_read(&kvm->arch.noncoherent_dma_count);
13452 }
13453 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13454
kvm_arch_has_irq_bypass(void)13455 bool kvm_arch_has_irq_bypass(void)
13456 {
13457 return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP);
13458 }
13459
kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer * cons,struct irq_bypass_producer * prod)13460 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13461 struct irq_bypass_producer *prod)
13462 {
13463 struct kvm_kernel_irqfd *irqfd =
13464 container_of(cons, struct kvm_kernel_irqfd, consumer);
13465 int ret;
13466
13467 irqfd->producer = prod;
13468 kvm_arch_start_assignment(irqfd->kvm);
13469 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13470 prod->irq, irqfd->gsi, 1);
13471
13472 if (ret)
13473 kvm_arch_end_assignment(irqfd->kvm);
13474
13475 return ret;
13476 }
13477
kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer * cons,struct irq_bypass_producer * prod)13478 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13479 struct irq_bypass_producer *prod)
13480 {
13481 int ret;
13482 struct kvm_kernel_irqfd *irqfd =
13483 container_of(cons, struct kvm_kernel_irqfd, consumer);
13484
13485 WARN_ON(irqfd->producer != prod);
13486 irqfd->producer = NULL;
13487
13488 /*
13489 * When producer of consumer is unregistered, we change back to
13490 * remapped mode, so we can re-use the current implementation
13491 * when the irq is masked/disabled or the consumer side (KVM
13492 * int this case doesn't want to receive the interrupts.
13493 */
13494 ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13495 if (ret)
13496 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13497 " fails: %d\n", irqfd->consumer.token, ret);
13498
13499 kvm_arch_end_assignment(irqfd->kvm);
13500 }
13501
kvm_arch_update_irqfd_routing(struct kvm * kvm,unsigned int host_irq,uint32_t guest_irq,bool set)13502 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13503 uint32_t guest_irq, bool set)
13504 {
13505 return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13506 }
13507
kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry * old,struct kvm_kernel_irq_routing_entry * new)13508 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13509 struct kvm_kernel_irq_routing_entry *new)
13510 {
13511 if (new->type != KVM_IRQ_ROUTING_MSI)
13512 return true;
13513
13514 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13515 }
13516
kvm_vector_hashing_enabled(void)13517 bool kvm_vector_hashing_enabled(void)
13518 {
13519 return vector_hashing;
13520 }
13521
kvm_arch_no_poll(struct kvm_vcpu * vcpu)13522 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13523 {
13524 return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13525 }
13526 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13527
13528
kvm_spec_ctrl_test_value(u64 value)13529 int kvm_spec_ctrl_test_value(u64 value)
13530 {
13531 /*
13532 * test that setting IA32_SPEC_CTRL to given value
13533 * is allowed by the host processor
13534 */
13535
13536 u64 saved_value;
13537 unsigned long flags;
13538 int ret = 0;
13539
13540 local_irq_save(flags);
13541
13542 if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13543 ret = 1;
13544 else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13545 ret = 1;
13546 else
13547 wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13548
13549 local_irq_restore(flags);
13550
13551 return ret;
13552 }
13553 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13554
kvm_fixup_and_inject_pf_error(struct kvm_vcpu * vcpu,gva_t gva,u16 error_code)13555 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13556 {
13557 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13558 struct x86_exception fault;
13559 u64 access = error_code &
13560 (PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13561
13562 if (!(error_code & PFERR_PRESENT_MASK) ||
13563 mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13564 /*
13565 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13566 * tables probably do not match the TLB. Just proceed
13567 * with the error code that the processor gave.
13568 */
13569 fault.vector = PF_VECTOR;
13570 fault.error_code_valid = true;
13571 fault.error_code = error_code;
13572 fault.nested_page_fault = false;
13573 fault.address = gva;
13574 fault.async_page_fault = false;
13575 }
13576 vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13577 }
13578 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13579
13580 /*
13581 * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13582 * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13583 * indicates whether exit to userspace is needed.
13584 */
kvm_handle_memory_failure(struct kvm_vcpu * vcpu,int r,struct x86_exception * e)13585 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13586 struct x86_exception *e)
13587 {
13588 if (r == X86EMUL_PROPAGATE_FAULT) {
13589 if (KVM_BUG_ON(!e, vcpu->kvm))
13590 return -EIO;
13591
13592 kvm_inject_emulated_page_fault(vcpu, e);
13593 return 1;
13594 }
13595
13596 /*
13597 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13598 * while handling a VMX instruction KVM could've handled the request
13599 * correctly by exiting to userspace and performing I/O but there
13600 * doesn't seem to be a real use-case behind such requests, just return
13601 * KVM_EXIT_INTERNAL_ERROR for now.
13602 */
13603 kvm_prepare_emulation_failure_exit(vcpu);
13604
13605 return 0;
13606 }
13607 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13608
kvm_handle_invpcid(struct kvm_vcpu * vcpu,unsigned long type,gva_t gva)13609 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13610 {
13611 bool pcid_enabled;
13612 struct x86_exception e;
13613 struct {
13614 u64 pcid;
13615 u64 gla;
13616 } operand;
13617 int r;
13618
13619 r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13620 if (r != X86EMUL_CONTINUE)
13621 return kvm_handle_memory_failure(vcpu, r, &e);
13622
13623 if (operand.pcid >> 12 != 0) {
13624 kvm_inject_gp(vcpu, 0);
13625 return 1;
13626 }
13627
13628 pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13629
13630 switch (type) {
13631 case INVPCID_TYPE_INDIV_ADDR:
13632 /*
13633 * LAM doesn't apply to addresses that are inputs to TLB
13634 * invalidation.
13635 */
13636 if ((!pcid_enabled && (operand.pcid != 0)) ||
13637 is_noncanonical_address(operand.gla, vcpu)) {
13638 kvm_inject_gp(vcpu, 0);
13639 return 1;
13640 }
13641 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13642 return kvm_skip_emulated_instruction(vcpu);
13643
13644 case INVPCID_TYPE_SINGLE_CTXT:
13645 if (!pcid_enabled && (operand.pcid != 0)) {
13646 kvm_inject_gp(vcpu, 0);
13647 return 1;
13648 }
13649
13650 kvm_invalidate_pcid(vcpu, operand.pcid);
13651 return kvm_skip_emulated_instruction(vcpu);
13652
13653 case INVPCID_TYPE_ALL_NON_GLOBAL:
13654 /*
13655 * Currently, KVM doesn't mark global entries in the shadow
13656 * page tables, so a non-global flush just degenerates to a
13657 * global flush. If needed, we could optimize this later by
13658 * keeping track of global entries in shadow page tables.
13659 */
13660
13661 fallthrough;
13662 case INVPCID_TYPE_ALL_INCL_GLOBAL:
13663 kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13664 return kvm_skip_emulated_instruction(vcpu);
13665
13666 default:
13667 kvm_inject_gp(vcpu, 0);
13668 return 1;
13669 }
13670 }
13671 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13672
complete_sev_es_emulated_mmio(struct kvm_vcpu * vcpu)13673 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13674 {
13675 struct kvm_run *run = vcpu->run;
13676 struct kvm_mmio_fragment *frag;
13677 unsigned int len;
13678
13679 BUG_ON(!vcpu->mmio_needed);
13680
13681 /* Complete previous fragment */
13682 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13683 len = min(8u, frag->len);
13684 if (!vcpu->mmio_is_write)
13685 memcpy(frag->data, run->mmio.data, len);
13686
13687 if (frag->len <= 8) {
13688 /* Switch to the next fragment. */
13689 frag++;
13690 vcpu->mmio_cur_fragment++;
13691 } else {
13692 /* Go forward to the next mmio piece. */
13693 frag->data += len;
13694 frag->gpa += len;
13695 frag->len -= len;
13696 }
13697
13698 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13699 vcpu->mmio_needed = 0;
13700
13701 // VMG change, at this point, we're always done
13702 // RIP has already been advanced
13703 return 1;
13704 }
13705
13706 // More MMIO is needed
13707 run->mmio.phys_addr = frag->gpa;
13708 run->mmio.len = min(8u, frag->len);
13709 run->mmio.is_write = vcpu->mmio_is_write;
13710 if (run->mmio.is_write)
13711 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13712 run->exit_reason = KVM_EXIT_MMIO;
13713
13714 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13715
13716 return 0;
13717 }
13718
kvm_sev_es_mmio_write(struct kvm_vcpu * vcpu,gpa_t gpa,unsigned int bytes,void * data)13719 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13720 void *data)
13721 {
13722 int handled;
13723 struct kvm_mmio_fragment *frag;
13724
13725 if (!data)
13726 return -EINVAL;
13727
13728 handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13729 if (handled == bytes)
13730 return 1;
13731
13732 bytes -= handled;
13733 gpa += handled;
13734 data += handled;
13735
13736 /*TODO: Check if need to increment number of frags */
13737 frag = vcpu->mmio_fragments;
13738 vcpu->mmio_nr_fragments = 1;
13739 frag->len = bytes;
13740 frag->gpa = gpa;
13741 frag->data = data;
13742
13743 vcpu->mmio_needed = 1;
13744 vcpu->mmio_cur_fragment = 0;
13745
13746 vcpu->run->mmio.phys_addr = gpa;
13747 vcpu->run->mmio.len = min(8u, frag->len);
13748 vcpu->run->mmio.is_write = 1;
13749 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13750 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13751
13752 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13753
13754 return 0;
13755 }
13756 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13757
kvm_sev_es_mmio_read(struct kvm_vcpu * vcpu,gpa_t gpa,unsigned int bytes,void * data)13758 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13759 void *data)
13760 {
13761 int handled;
13762 struct kvm_mmio_fragment *frag;
13763
13764 if (!data)
13765 return -EINVAL;
13766
13767 handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13768 if (handled == bytes)
13769 return 1;
13770
13771 bytes -= handled;
13772 gpa += handled;
13773 data += handled;
13774
13775 /*TODO: Check if need to increment number of frags */
13776 frag = vcpu->mmio_fragments;
13777 vcpu->mmio_nr_fragments = 1;
13778 frag->len = bytes;
13779 frag->gpa = gpa;
13780 frag->data = data;
13781
13782 vcpu->mmio_needed = 1;
13783 vcpu->mmio_cur_fragment = 0;
13784
13785 vcpu->run->mmio.phys_addr = gpa;
13786 vcpu->run->mmio.len = min(8u, frag->len);
13787 vcpu->run->mmio.is_write = 0;
13788 vcpu->run->exit_reason = KVM_EXIT_MMIO;
13789
13790 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13791
13792 return 0;
13793 }
13794 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13795
advance_sev_es_emulated_pio(struct kvm_vcpu * vcpu,unsigned count,int size)13796 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13797 {
13798 vcpu->arch.sev_pio_count -= count;
13799 vcpu->arch.sev_pio_data += count * size;
13800 }
13801
13802 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13803 unsigned int port);
13804
complete_sev_es_emulated_outs(struct kvm_vcpu * vcpu)13805 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13806 {
13807 int size = vcpu->arch.pio.size;
13808 int port = vcpu->arch.pio.port;
13809
13810 vcpu->arch.pio.count = 0;
13811 if (vcpu->arch.sev_pio_count)
13812 return kvm_sev_es_outs(vcpu, size, port);
13813 return 1;
13814 }
13815
kvm_sev_es_outs(struct kvm_vcpu * vcpu,unsigned int size,unsigned int port)13816 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13817 unsigned int port)
13818 {
13819 for (;;) {
13820 unsigned int count =
13821 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13822 int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13823
13824 /* memcpy done already by emulator_pio_out. */
13825 advance_sev_es_emulated_pio(vcpu, count, size);
13826 if (!ret)
13827 break;
13828
13829 /* Emulation done by the kernel. */
13830 if (!vcpu->arch.sev_pio_count)
13831 return 1;
13832 }
13833
13834 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13835 return 0;
13836 }
13837
13838 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13839 unsigned int port);
13840
complete_sev_es_emulated_ins(struct kvm_vcpu * vcpu)13841 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13842 {
13843 unsigned count = vcpu->arch.pio.count;
13844 int size = vcpu->arch.pio.size;
13845 int port = vcpu->arch.pio.port;
13846
13847 complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13848 advance_sev_es_emulated_pio(vcpu, count, size);
13849 if (vcpu->arch.sev_pio_count)
13850 return kvm_sev_es_ins(vcpu, size, port);
13851 return 1;
13852 }
13853
kvm_sev_es_ins(struct kvm_vcpu * vcpu,unsigned int size,unsigned int port)13854 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13855 unsigned int port)
13856 {
13857 for (;;) {
13858 unsigned int count =
13859 min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13860 if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13861 break;
13862
13863 /* Emulation done by the kernel. */
13864 advance_sev_es_emulated_pio(vcpu, count, size);
13865 if (!vcpu->arch.sev_pio_count)
13866 return 1;
13867 }
13868
13869 vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13870 return 0;
13871 }
13872
kvm_sev_es_string_io(struct kvm_vcpu * vcpu,unsigned int size,unsigned int port,void * data,unsigned int count,int in)13873 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13874 unsigned int port, void *data, unsigned int count,
13875 int in)
13876 {
13877 vcpu->arch.sev_pio_data = data;
13878 vcpu->arch.sev_pio_count = count;
13879 return in ? kvm_sev_es_ins(vcpu, size, port)
13880 : kvm_sev_es_outs(vcpu, size, port);
13881 }
13882 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13883
13884 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13885 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13886 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13887 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13888 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13889 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13890 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13891 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13892 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13893 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13894 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13895 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13896 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13897 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13898 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13899 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13900 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13901 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13902 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13903 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13904 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13905 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13906 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13907 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13908 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13909 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13910 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13911 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13912 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13913
kvm_x86_init(void)13914 static int __init kvm_x86_init(void)
13915 {
13916 kvm_mmu_x86_module_init();
13917 mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13918 return 0;
13919 }
13920 module_init(kvm_x86_init);
13921
kvm_x86_exit(void)13922 static void __exit kvm_x86_exit(void)
13923 {
13924 /*
13925 * If module_init() is implemented, module_exit() must also be
13926 * implemented to allow module unload.
13927 */
13928 }
13929 module_exit(kvm_x86_exit);
13930