1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include "qapi/visitor.h"
19 #include <math.h>
20 #include <sys/ioctl.h>
21 #include <sys/utsname.h>
22 #include <sys/syscall.h>
23 #include <sys/resource.h>
24 #include <sys/time.h>
25
26 #include <linux/kvm.h>
27 #include <linux/kvm_para.h>
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
30
31 #include "cpu.h"
32 #include "host-cpu.h"
33 #include "vmsr_energy.h"
34 #include "system/system.h"
35 #include "system/hw_accel.h"
36 #include "system/kvm_int.h"
37 #include "system/runstate.h"
38 #include "kvm_i386.h"
39 #include "../confidential-guest.h"
40 #include "sev.h"
41 #include "tdx.h"
42 #include "xen-emu.h"
43 #include "hyperv.h"
44 #include "hyperv-proto.h"
45
46 #include "gdbstub/enums.h"
47 #include "qemu/host-utils.h"
48 #include "qemu/main-loop.h"
49 #include "qemu/ratelimit.h"
50 #include "qemu/config-file.h"
51 #include "qemu/error-report.h"
52 #include "qemu/memalign.h"
53 #include "hw/i386/x86.h"
54 #include "hw/i386/kvm/xen_evtchn.h"
55 #include "hw/i386/pc.h"
56 #include "hw/i386/apic.h"
57 #include "hw/i386/apic_internal.h"
58 #include "hw/i386/apic-msidef.h"
59 #include "hw/i386/intel_iommu.h"
60 #include "hw/i386/topology.h"
61 #include "hw/i386/x86-iommu.h"
62 #include "hw/i386/e820_memory_layout.h"
63
64 #include "hw/xen/xen.h"
65
66 #include "hw/pci/pci.h"
67 #include "hw/pci/msi.h"
68 #include "hw/pci/msix.h"
69 #include "migration/blocker.h"
70 #include "exec/memattrs.h"
71 #include "exec/target_page.h"
72 #include "trace.h"
73
74 #include CONFIG_DEVICES
75
76 //#define DEBUG_KVM
77
78 #ifdef DEBUG_KVM
79 #define DPRINTF(fmt, ...) \
80 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define DPRINTF(fmt, ...) \
83 do { } while (0)
84 #endif
85
86 /*
87 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
88 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
89 * Since these must be part of guest physical memory, we need to allocate
90 * them, both by setting their start addresses in the kernel and by
91 * creating a corresponding e820 entry. We need 4 pages before the BIOS,
92 * so this value allows up to 16M BIOSes.
93 */
94 #define KVM_IDENTITY_BASE 0xfeffc000
95
96 /* From arch/x86/kvm/lapic.h */
97 #define KVM_APIC_BUS_CYCLE_NS 1
98 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
99
100 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
101 * 255 kvm_msr_entry structs */
102 #define MSR_BUF_SIZE 4096
103
104 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val);
105 typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val);
106 typedef struct {
107 uint32_t msr;
108 QEMURDMSRHandler *rdmsr;
109 QEMUWRMSRHandler *wrmsr;
110 } KVMMSRHandlers;
111
112 static void kvm_init_msrs(X86CPU *cpu);
113 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
114 QEMUWRMSRHandler *wrmsr);
115
116 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
117 KVM_CAP_INFO(SET_TSS_ADDR),
118 KVM_CAP_INFO(EXT_CPUID),
119 KVM_CAP_INFO(MP_STATE),
120 KVM_CAP_INFO(SIGNAL_MSI),
121 KVM_CAP_INFO(IRQ_ROUTING),
122 KVM_CAP_INFO(DEBUGREGS),
123 KVM_CAP_INFO(XSAVE),
124 KVM_CAP_INFO(VCPU_EVENTS),
125 KVM_CAP_INFO(X86_ROBUST_SINGLESTEP),
126 KVM_CAP_INFO(MCE),
127 KVM_CAP_INFO(ADJUST_CLOCK),
128 KVM_CAP_INFO(SET_IDENTITY_MAP_ADDR),
129 KVM_CAP_LAST_INFO
130 };
131
132 static bool has_msr_star;
133 static bool has_msr_hsave_pa;
134 static bool has_msr_tsc_aux;
135 static bool has_msr_tsc_adjust;
136 static bool has_msr_tsc_deadline;
137 static bool has_msr_feature_control;
138 static bool has_msr_misc_enable;
139 static bool has_msr_smbase;
140 static bool has_msr_bndcfgs;
141 static int lm_capable_kernel;
142 static bool has_msr_hv_hypercall;
143 static bool has_msr_hv_crash;
144 static bool has_msr_hv_reset;
145 static bool has_msr_hv_vpindex;
146 static bool hv_vpindex_settable;
147 static bool has_msr_hv_runtime;
148 static bool has_msr_hv_synic;
149 static bool has_msr_hv_stimer;
150 static bool has_msr_hv_frequencies;
151 static bool has_msr_hv_reenlightenment;
152 static bool has_msr_hv_syndbg_options;
153 static bool has_msr_xss;
154 static bool has_msr_umwait;
155 static bool has_msr_spec_ctrl;
156 static bool has_tsc_scale_msr;
157 static bool has_msr_tsx_ctrl;
158 static bool has_msr_virt_ssbd;
159 static bool has_msr_smi_count;
160 static bool has_msr_arch_capabs;
161 static bool has_msr_core_capabs;
162 static bool has_msr_vmx_vmfunc;
163 static bool has_msr_ucode_rev;
164 static bool has_msr_vmx_procbased_ctls2;
165 static bool has_msr_perf_capabs;
166 static bool has_msr_pkrs;
167 static bool has_msr_hwcr;
168
169 static uint32_t has_architectural_pmu_version;
170 static uint32_t num_architectural_pmu_gp_counters;
171 static uint32_t num_architectural_pmu_fixed_counters;
172
173 static int has_xsave2;
174 static int has_xcrs;
175 static int has_sregs2;
176 static int has_exception_payload;
177 static int has_triple_fault_event;
178
179 static bool has_msr_mcg_ext_ctl;
180
181 static struct kvm_cpuid2 *cpuid_cache;
182 static struct kvm_cpuid2 *hv_cpuid_cache;
183 static struct kvm_msr_list *kvm_feature_msrs;
184
185 static KVMMSRHandlers msr_handlers[KVM_MSR_FILTER_MAX_RANGES];
186
187 #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
188 static RateLimit bus_lock_ratelimit_ctrl;
189 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
190
191 static const char *vm_type_name[] = {
192 [KVM_X86_DEFAULT_VM] = "default",
193 [KVM_X86_SEV_VM] = "SEV",
194 [KVM_X86_SEV_ES_VM] = "SEV-ES",
195 [KVM_X86_SNP_VM] = "SEV-SNP",
196 [KVM_X86_TDX_VM] = "TDX",
197 };
198
kvm_is_vm_type_supported(int type)199 bool kvm_is_vm_type_supported(int type)
200 {
201 uint32_t machine_types;
202
203 /*
204 * old KVM doesn't support KVM_CAP_VM_TYPES but KVM_X86_DEFAULT_VM
205 * is always supported
206 */
207 if (type == KVM_X86_DEFAULT_VM) {
208 return true;
209 }
210
211 machine_types = kvm_check_extension(KVM_STATE(current_machine->accelerator),
212 KVM_CAP_VM_TYPES);
213 return !!(machine_types & BIT(type));
214 }
215
kvm_get_vm_type(MachineState * ms)216 int kvm_get_vm_type(MachineState *ms)
217 {
218 int kvm_type = KVM_X86_DEFAULT_VM;
219
220 if (ms->cgs) {
221 if (!object_dynamic_cast(OBJECT(ms->cgs), TYPE_X86_CONFIDENTIAL_GUEST)) {
222 error_report("configuration type %s not supported for x86 guests",
223 object_get_typename(OBJECT(ms->cgs)));
224 exit(1);
225 }
226 kvm_type = x86_confidential_guest_kvm_type(
227 X86_CONFIDENTIAL_GUEST(ms->cgs));
228 }
229
230 if (!kvm_is_vm_type_supported(kvm_type)) {
231 error_report("vm-type %s not supported by KVM", vm_type_name[kvm_type]);
232 exit(1);
233 }
234
235 return kvm_type;
236 }
237
kvm_enable_hypercall(uint64_t enable_mask)238 bool kvm_enable_hypercall(uint64_t enable_mask)
239 {
240 KVMState *s = KVM_STATE(current_accel());
241
242 return !kvm_vm_enable_cap(s, KVM_CAP_EXIT_HYPERCALL, 0, enable_mask);
243 }
244
kvm_has_smm(void)245 bool kvm_has_smm(void)
246 {
247 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
248 }
249
kvm_has_adjust_clock_stable(void)250 bool kvm_has_adjust_clock_stable(void)
251 {
252 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
253
254 return (ret & KVM_CLOCK_TSC_STABLE);
255 }
256
kvm_has_exception_payload(void)257 bool kvm_has_exception_payload(void)
258 {
259 return has_exception_payload;
260 }
261
kvm_x2apic_api_set_flags(uint64_t flags)262 static bool kvm_x2apic_api_set_flags(uint64_t flags)
263 {
264 KVMState *s = KVM_STATE(current_accel());
265
266 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
267 }
268
269 #define MEMORIZE(fn, _result) \
270 ({ \
271 static bool _memorized; \
272 \
273 if (_memorized) { \
274 return _result; \
275 } \
276 _memorized = true; \
277 _result = fn; \
278 })
279
280 static bool has_x2apic_api;
281
kvm_has_x2apic_api(void)282 bool kvm_has_x2apic_api(void)
283 {
284 return has_x2apic_api;
285 }
286
kvm_enable_x2apic(void)287 bool kvm_enable_x2apic(void)
288 {
289 return MEMORIZE(
290 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
291 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
292 has_x2apic_api);
293 }
294
kvm_hv_vpindex_settable(void)295 bool kvm_hv_vpindex_settable(void)
296 {
297 return hv_vpindex_settable;
298 }
299
kvm_get_tsc(CPUState * cs)300 static int kvm_get_tsc(CPUState *cs)
301 {
302 X86CPU *cpu = X86_CPU(cs);
303 CPUX86State *env = &cpu->env;
304 uint64_t value;
305 int ret;
306
307 if (env->tsc_valid) {
308 return 0;
309 }
310
311 env->tsc_valid = !runstate_is_running();
312
313 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
314 if (ret < 0) {
315 return ret;
316 }
317
318 env->tsc = value;
319 return 0;
320 }
321
do_kvm_synchronize_tsc(CPUState * cpu,run_on_cpu_data arg)322 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
323 {
324 kvm_get_tsc(cpu);
325 }
326
kvm_synchronize_all_tsc(void)327 void kvm_synchronize_all_tsc(void)
328 {
329 CPUState *cpu;
330
331 if (kvm_enabled() && !is_tdx_vm()) {
332 CPU_FOREACH(cpu) {
333 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
334 }
335 }
336 }
337
try_get_cpuid(KVMState * s,int max)338 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
339 {
340 struct kvm_cpuid2 *cpuid;
341 int r, size;
342
343 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
344 cpuid = g_malloc0(size);
345 cpuid->nent = max;
346 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
347 if (r == 0 && cpuid->nent >= max) {
348 r = -E2BIG;
349 }
350 if (r < 0) {
351 if (r == -E2BIG) {
352 g_free(cpuid);
353 return NULL;
354 } else {
355 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
356 strerror(-r));
357 exit(1);
358 }
359 }
360 return cpuid;
361 }
362
363 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
364 * for all entries.
365 */
get_supported_cpuid(KVMState * s)366 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
367 {
368 struct kvm_cpuid2 *cpuid;
369 int max = 1;
370
371 if (cpuid_cache != NULL) {
372 return cpuid_cache;
373 }
374 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
375 max *= 2;
376 }
377 cpuid_cache = cpuid;
378 return cpuid;
379 }
380
host_tsx_broken(void)381 static bool host_tsx_broken(void)
382 {
383 int family, model, stepping;\
384 char vendor[CPUID_VENDOR_SZ + 1];
385
386 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
387
388 /* Check if we are running on a Haswell host known to have broken TSX */
389 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
390 (family == 6) &&
391 ((model == 63 && stepping < 4) ||
392 model == 60 || model == 69 || model == 70);
393 }
394
395 /* Returns the value for a specific register on the cpuid entry
396 */
cpuid_entry_get_reg(struct kvm_cpuid_entry2 * entry,int reg)397 uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
398 {
399 uint32_t ret = 0;
400 switch (reg) {
401 case R_EAX:
402 ret = entry->eax;
403 break;
404 case R_EBX:
405 ret = entry->ebx;
406 break;
407 case R_ECX:
408 ret = entry->ecx;
409 break;
410 case R_EDX:
411 ret = entry->edx;
412 break;
413 }
414 return ret;
415 }
416
417 /* Find matching entry for function/index on kvm_cpuid2 struct
418 */
cpuid_find_entry(struct kvm_cpuid2 * cpuid,uint32_t function,uint32_t index)419 struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
420 uint32_t function,
421 uint32_t index)
422 {
423 int i;
424 for (i = 0; i < cpuid->nent; ++i) {
425 if (cpuid->entries[i].function == function &&
426 cpuid->entries[i].index == index) {
427 return &cpuid->entries[i];
428 }
429 }
430 /* not found: */
431 return NULL;
432 }
433
kvm_arch_get_supported_cpuid(KVMState * s,uint32_t function,uint32_t index,int reg)434 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
435 uint32_t index, int reg)
436 {
437 struct kvm_cpuid2 *cpuid;
438 uint32_t ret = 0;
439 uint32_t cpuid_1_edx, unused;
440 uint64_t bitmask;
441
442 cpuid = get_supported_cpuid(s);
443
444 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
445 if (entry) {
446 ret = cpuid_entry_get_reg(entry, reg);
447 }
448
449 /* Fixups for the data returned by KVM, below */
450
451 if (function == 1 && reg == R_EDX) {
452 /* KVM before 2.6.30 misreports the following features */
453 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
454 /* KVM never reports CPUID_HT but QEMU can support when vcpus > 1 */
455 ret |= CPUID_HT;
456 } else if (function == 1 && reg == R_ECX) {
457 /* We can set the hypervisor flag, even if KVM does not return it on
458 * GET_SUPPORTED_CPUID
459 */
460 ret |= CPUID_EXT_HYPERVISOR;
461 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
462 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
463 * and the irqchip is in the kernel.
464 */
465 if (kvm_irqchip_in_kernel() &&
466 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
467 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
468 }
469
470 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
471 * without the in-kernel irqchip
472 */
473 if (!kvm_irqchip_in_kernel()) {
474 ret &= ~CPUID_EXT_X2APIC;
475 }
476
477 if (enable_cpu_pm) {
478 int disable_exits = kvm_check_extension(s,
479 KVM_CAP_X86_DISABLE_EXITS);
480
481 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
482 ret |= CPUID_EXT_MONITOR;
483 }
484 }
485 } else if (function == 6 && reg == R_EAX) {
486 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
487 } else if (function == 7 && index == 0 && reg == R_EBX) {
488 /* Not new instructions, just an optimization. */
489 uint32_t ebx;
490 host_cpuid(7, 0, &unused, &ebx, &unused, &unused);
491 ret |= ebx & CPUID_7_0_EBX_ERMS;
492
493 if (host_tsx_broken()) {
494 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
495 }
496 } else if (function == 7 && index == 0 && reg == R_EDX) {
497 /* Not new instructions, just an optimization. */
498 uint32_t edx;
499 host_cpuid(7, 0, &unused, &unused, &unused, &edx);
500 ret |= edx & CPUID_7_0_EDX_FSRM;
501
502 /*
503 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
504 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
505 * returned by KVM_GET_MSR_INDEX_LIST.
506 */
507 if (!has_msr_arch_capabs) {
508 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
509 }
510 } else if (function == 7 && index == 1 && reg == R_EAX) {
511 /* Not new instructions, just an optimization. */
512 uint32_t eax;
513 host_cpuid(7, 1, &eax, &unused, &unused, &unused);
514 ret |= eax & (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC);
515 } else if (function == 7 && index == 2 && reg == R_EDX) {
516 uint32_t edx;
517 host_cpuid(7, 2, &unused, &unused, &unused, &edx);
518 ret |= edx & CPUID_7_2_EDX_MCDT_NO;
519 } else if (function == 0xd && index == 0 &&
520 (reg == R_EAX || reg == R_EDX)) {
521 /*
522 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
523 * features that still have to be enabled with the arch_prctl
524 * system call. QEMU needs the full value, which is retrieved
525 * with KVM_GET_DEVICE_ATTR.
526 */
527 struct kvm_device_attr attr = {
528 .group = 0,
529 .attr = KVM_X86_XCOMP_GUEST_SUPP,
530 .addr = (unsigned long) &bitmask
531 };
532
533 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
534 if (!sys_attr) {
535 return ret;
536 }
537
538 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
539 if (rc < 0) {
540 if (rc != -ENXIO) {
541 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
542 "error: %d", rc);
543 }
544 return ret;
545 }
546 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
547 } else if (function == 0x80000001 && reg == R_ECX) {
548 /*
549 * It's safe to enable TOPOEXT even if it's not returned by
550 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
551 * us to keep CPU models including TOPOEXT runnable on older kernels.
552 */
553 ret |= CPUID_EXT3_TOPOEXT;
554 } else if (function == 0x80000001 && reg == R_EDX) {
555 /* On Intel, kvm returns cpuid according to the Intel spec,
556 * so add missing bits according to the AMD spec:
557 */
558 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
559 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
560 } else if (function == 0x80000007 && reg == R_EBX) {
561 ret |= CPUID_8000_0007_EBX_OVERFLOW_RECOV | CPUID_8000_0007_EBX_SUCCOR;
562 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
563 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
564 * be enabled without the in-kernel irqchip
565 */
566 if (!kvm_irqchip_in_kernel()) {
567 ret &= ~CPUID_KVM_PV_UNHALT;
568 }
569 if (kvm_irqchip_is_split()) {
570 ret |= CPUID_KVM_MSI_EXT_DEST_ID;
571 }
572 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
573 ret |= CPUID_KVM_HINTS_REALTIME;
574 }
575
576 if (current_machine->cgs) {
577 ret = x86_confidential_guest_adjust_cpuid_features(
578 X86_CONFIDENTIAL_GUEST(current_machine->cgs),
579 function, index, reg, ret);
580 }
581 return ret;
582 }
583
kvm_arch_get_supported_msr_feature(KVMState * s,uint32_t index)584 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
585 {
586 struct {
587 struct kvm_msrs info;
588 struct kvm_msr_entry entries[1];
589 } msr_data = {};
590 uint64_t value;
591 uint32_t ret, can_be_one, must_be_one;
592
593 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
594 return 0;
595 }
596
597 /* Check if requested MSR is supported feature MSR */
598 int i;
599 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
600 if (kvm_feature_msrs->indices[i] == index) {
601 break;
602 }
603 if (i == kvm_feature_msrs->nmsrs) {
604 return 0; /* if the feature MSR is not supported, simply return 0 */
605 }
606
607 msr_data.info.nmsrs = 1;
608 msr_data.entries[0].index = index;
609
610 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
611 if (ret != 1) {
612 error_report("KVM get MSR (index=0x%x) feature failed, %s",
613 index, strerror(-ret));
614 exit(1);
615 }
616
617 value = msr_data.entries[0].data;
618 switch (index) {
619 case MSR_IA32_VMX_PROCBASED_CTLS2:
620 if (!has_msr_vmx_procbased_ctls2) {
621 /* KVM forgot to add these bits for some time, do this ourselves. */
622 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
623 CPUID_XSAVE_XSAVES) {
624 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
625 }
626 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
627 CPUID_EXT_RDRAND) {
628 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
629 }
630 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
631 CPUID_7_0_EBX_INVPCID) {
632 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
633 }
634 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
635 CPUID_7_0_EBX_RDSEED) {
636 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
637 }
638 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
639 CPUID_EXT2_RDTSCP) {
640 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
641 }
642 }
643 /* fall through */
644 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
645 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
646 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
647 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
648 /*
649 * Return true for bits that can be one, but do not have to be one.
650 * The SDM tells us which bits could have a "must be one" setting,
651 * so we can do the opposite transformation in make_vmx_msr_value.
652 */
653 must_be_one = (uint32_t)value;
654 can_be_one = (uint32_t)(value >> 32);
655 return can_be_one & ~must_be_one;
656
657 default:
658 return value;
659 }
660 }
661
kvm_get_mce_cap_supported(KVMState * s,uint64_t * mce_cap,int * max_banks)662 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
663 int *max_banks)
664 {
665 *max_banks = kvm_check_extension(s, KVM_CAP_MCE);
666 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
667 }
668
kvm_mce_inject(X86CPU * cpu,hwaddr paddr,int code)669 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
670 {
671 CPUState *cs = CPU(cpu);
672 CPUX86State *env = &cpu->env;
673 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_MISCV |
674 MCI_STATUS_ADDRV;
675 uint64_t mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
676 int flags = 0;
677
678 if (!IS_AMD_CPU(env)) {
679 status |= MCI_STATUS_S | MCI_STATUS_UC;
680 if (code == BUS_MCEERR_AR) {
681 status |= MCI_STATUS_AR | 0x134;
682 mcg_status |= MCG_STATUS_EIPV;
683 } else {
684 status |= 0xc0;
685 }
686 } else {
687 if (code == BUS_MCEERR_AR) {
688 status |= MCI_STATUS_UC | MCI_STATUS_POISON;
689 mcg_status |= MCG_STATUS_EIPV;
690 } else {
691 /* Setting the POISON bit for deferred errors indicates to the
692 * guest kernel that the address provided by the MCE is valid
693 * and usable which will ensure that the guest kernel will send
694 * a SIGBUS_AO signal to the guest process. This allows for
695 * more desirable behavior in the case that the guest process
696 * with poisoned memory has set the MCE_KILL_EARLY prctl flag
697 * which indicates that the process would prefer to handle or
698 * shutdown due to the poisoned memory condition before the
699 * memory has been accessed.
700 *
701 * While the POISON bit would not be set in a deferred error
702 * sent from hardware, the bit is not meaningful for deferred
703 * errors and can be reused in this scenario.
704 */
705 status |= MCI_STATUS_DEFERRED | MCI_STATUS_POISON;
706 }
707 }
708
709 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
710 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
711 * guest kernel back into env->mcg_ext_ctl.
712 */
713 cpu_synchronize_state(cs);
714 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
715 mcg_status |= MCG_STATUS_LMCE;
716 flags = 0;
717 }
718
719 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
720 (MCM_ADDR_PHYS << 6) | 0xc, flags);
721 }
722
emit_hypervisor_memory_failure(MemoryFailureAction action,bool ar)723 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
724 {
725 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
726
727 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
728 &mff);
729 }
730
hardware_memory_error(void * host_addr)731 static void hardware_memory_error(void *host_addr)
732 {
733 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
734 error_report("QEMU got Hardware memory error at addr %p", host_addr);
735 exit(1);
736 }
737
kvm_arch_on_sigbus_vcpu(CPUState * c,int code,void * addr)738 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
739 {
740 X86CPU *cpu = X86_CPU(c);
741 CPUX86State *env = &cpu->env;
742 ram_addr_t ram_addr;
743 hwaddr paddr;
744
745 /* If we get an action required MCE, it has been injected by KVM
746 * while the VM was running. An action optional MCE instead should
747 * be coming from the main thread, which qemu_init_sigbus identifies
748 * as the "early kill" thread.
749 */
750 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
751
752 if ((env->mcg_cap & MCG_SER_P) && addr) {
753 ram_addr = qemu_ram_addr_from_host(addr);
754 if (ram_addr != RAM_ADDR_INVALID &&
755 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
756 kvm_hwpoison_page_add(ram_addr);
757 kvm_mce_inject(cpu, paddr, code);
758
759 /*
760 * Use different logging severity based on error type.
761 * If there is additional MCE reporting on the hypervisor, QEMU VA
762 * could be another source to identify the PA and MCE details.
763 */
764 if (code == BUS_MCEERR_AR) {
765 error_report("Guest MCE Memory Error at QEMU addr %p and "
766 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
767 addr, paddr, "BUS_MCEERR_AR");
768 } else {
769 warn_report("Guest MCE Memory Error at QEMU addr %p and "
770 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
771 addr, paddr, "BUS_MCEERR_AO");
772 }
773
774 return;
775 }
776
777 if (code == BUS_MCEERR_AO) {
778 warn_report("Hardware memory error at addr %p of type %s "
779 "for memory used by QEMU itself instead of guest system!",
780 addr, "BUS_MCEERR_AO");
781 }
782 }
783
784 if (code == BUS_MCEERR_AR) {
785 hardware_memory_error(addr);
786 }
787
788 /* Hope we are lucky for AO MCE, just notify a event */
789 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
790 }
791
kvm_queue_exception(CPUX86State * env,int32_t exception_nr,uint8_t exception_has_payload,uint64_t exception_payload)792 static void kvm_queue_exception(CPUX86State *env,
793 int32_t exception_nr,
794 uint8_t exception_has_payload,
795 uint64_t exception_payload)
796 {
797 assert(env->exception_nr == -1);
798 assert(!env->exception_pending);
799 assert(!env->exception_injected);
800 assert(!env->exception_has_payload);
801
802 env->exception_nr = exception_nr;
803
804 if (has_exception_payload) {
805 env->exception_pending = 1;
806
807 env->exception_has_payload = exception_has_payload;
808 env->exception_payload = exception_payload;
809 } else {
810 env->exception_injected = 1;
811
812 if (exception_nr == EXCP01_DB) {
813 assert(exception_has_payload);
814 env->dr[6] = exception_payload;
815 } else if (exception_nr == EXCP0E_PAGE) {
816 assert(exception_has_payload);
817 env->cr[2] = exception_payload;
818 } else {
819 assert(!exception_has_payload);
820 }
821 }
822 }
823
cpu_update_state(void * opaque,bool running,RunState state)824 static void cpu_update_state(void *opaque, bool running, RunState state)
825 {
826 CPUX86State *env = opaque;
827
828 if (running) {
829 env->tsc_valid = false;
830 }
831 }
832
kvm_arch_vcpu_id(CPUState * cs)833 unsigned long kvm_arch_vcpu_id(CPUState *cs)
834 {
835 X86CPU *cpu = X86_CPU(cs);
836 return cpu->apic_id;
837 }
838
839 #ifndef KVM_CPUID_SIGNATURE_NEXT
840 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
841 #endif
842
hyperv_enabled(X86CPU * cpu)843 static bool hyperv_enabled(X86CPU *cpu)
844 {
845 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
846 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
847 cpu->hyperv_features || cpu->hyperv_passthrough);
848 }
849
850 /*
851 * Check whether target_freq is within conservative
852 * ntp correctable bounds (250ppm) of freq
853 */
freq_within_bounds(int freq,int target_freq)854 static inline bool freq_within_bounds(int freq, int target_freq)
855 {
856 int max_freq = freq + (freq * 250 / 1000000);
857 int min_freq = freq - (freq * 250 / 1000000);
858
859 if (target_freq >= min_freq && target_freq <= max_freq) {
860 return true;
861 }
862
863 return false;
864 }
865
kvm_arch_set_tsc_khz(CPUState * cs)866 static int kvm_arch_set_tsc_khz(CPUState *cs)
867 {
868 X86CPU *cpu = X86_CPU(cs);
869 CPUX86State *env = &cpu->env;
870 int r, cur_freq;
871 bool set_ioctl = false;
872
873 /*
874 * TSC of TD vcpu is immutable, it cannot be set/changed via vcpu scope
875 * VM_SET_TSC_KHZ, but only be initialized via VM scope VM_SET_TSC_KHZ
876 * before ioctl KVM_TDX_INIT_VM in tdx_pre_create_vcpu()
877 */
878 if (is_tdx_vm()) {
879 return 0;
880 }
881
882 if (!env->tsc_khz) {
883 return 0;
884 }
885
886 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
887 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
888
889 /*
890 * If TSC scaling is supported, attempt to set TSC frequency.
891 */
892 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
893 set_ioctl = true;
894 }
895
896 /*
897 * If desired TSC frequency is within bounds of NTP correction,
898 * attempt to set TSC frequency.
899 */
900 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
901 set_ioctl = true;
902 }
903
904 r = set_ioctl ?
905 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
906 -ENOTSUP;
907
908 if (r < 0) {
909 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
910 * TSC frequency doesn't match the one we want.
911 */
912 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
913 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
914 -ENOTSUP;
915 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
916 warn_report("TSC frequency mismatch between "
917 "VM (%" PRId64 " kHz) and host (%d kHz), "
918 "and TSC scaling unavailable",
919 env->tsc_khz, cur_freq);
920 return r;
921 }
922 }
923
924 return 0;
925 }
926
tsc_is_stable_and_known(CPUX86State * env)927 static bool tsc_is_stable_and_known(CPUX86State *env)
928 {
929 if (!env->tsc_khz) {
930 return false;
931 }
932 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
933 || env->user_tsc_khz;
934 }
935
936 #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
937
938 static struct {
939 const char *desc;
940 struct {
941 uint32_t func;
942 int reg;
943 uint32_t bits;
944 } flags[2];
945 uint64_t dependencies;
946 bool skip_passthrough;
947 } kvm_hyperv_properties[] = {
948 [HYPERV_FEAT_RELAXED] = {
949 .desc = "relaxed timing (hv-relaxed)",
950 .flags = {
951 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
952 .bits = HV_RELAXED_TIMING_RECOMMENDED}
953 }
954 },
955 [HYPERV_FEAT_VAPIC] = {
956 .desc = "virtual APIC (hv-vapic)",
957 .flags = {
958 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
959 .bits = HV_APIC_ACCESS_AVAILABLE}
960 }
961 },
962 [HYPERV_FEAT_TIME] = {
963 .desc = "clocksources (hv-time)",
964 .flags = {
965 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
966 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
967 }
968 },
969 [HYPERV_FEAT_CRASH] = {
970 .desc = "crash MSRs (hv-crash)",
971 .flags = {
972 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
973 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
974 }
975 },
976 [HYPERV_FEAT_RESET] = {
977 .desc = "reset MSR (hv-reset)",
978 .flags = {
979 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
980 .bits = HV_RESET_AVAILABLE}
981 }
982 },
983 [HYPERV_FEAT_VPINDEX] = {
984 .desc = "VP_INDEX MSR (hv-vpindex)",
985 .flags = {
986 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
987 .bits = HV_VP_INDEX_AVAILABLE}
988 }
989 },
990 [HYPERV_FEAT_RUNTIME] = {
991 .desc = "VP_RUNTIME MSR (hv-runtime)",
992 .flags = {
993 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
994 .bits = HV_VP_RUNTIME_AVAILABLE}
995 }
996 },
997 [HYPERV_FEAT_SYNIC] = {
998 .desc = "synthetic interrupt controller (hv-synic)",
999 .flags = {
1000 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1001 .bits = HV_SYNIC_AVAILABLE}
1002 }
1003 },
1004 [HYPERV_FEAT_STIMER] = {
1005 .desc = "synthetic timers (hv-stimer)",
1006 .flags = {
1007 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1008 .bits = HV_SYNTIMERS_AVAILABLE}
1009 },
1010 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
1011 },
1012 [HYPERV_FEAT_FREQUENCIES] = {
1013 .desc = "frequency MSRs (hv-frequencies)",
1014 .flags = {
1015 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1016 .bits = HV_ACCESS_FREQUENCY_MSRS},
1017 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1018 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
1019 }
1020 },
1021 [HYPERV_FEAT_REENLIGHTENMENT] = {
1022 .desc = "reenlightenment MSRs (hv-reenlightenment)",
1023 .flags = {
1024 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
1025 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
1026 }
1027 },
1028 [HYPERV_FEAT_TLBFLUSH] = {
1029 .desc = "paravirtualized TLB flush (hv-tlbflush)",
1030 .flags = {
1031 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1032 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
1033 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1034 },
1035 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1036 },
1037 [HYPERV_FEAT_EVMCS] = {
1038 .desc = "enlightened VMCS (hv-evmcs)",
1039 .flags = {
1040 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1041 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
1042 },
1043 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1044 },
1045 [HYPERV_FEAT_IPI] = {
1046 .desc = "paravirtualized IPI (hv-ipi)",
1047 .flags = {
1048 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1049 .bits = HV_CLUSTER_IPI_RECOMMENDED |
1050 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
1051 },
1052 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
1053 },
1054 [HYPERV_FEAT_STIMER_DIRECT] = {
1055 .desc = "direct mode synthetic timers (hv-stimer-direct)",
1056 .flags = {
1057 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1058 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
1059 },
1060 .dependencies = BIT(HYPERV_FEAT_STIMER)
1061 },
1062 [HYPERV_FEAT_AVIC] = {
1063 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
1064 .flags = {
1065 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
1066 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
1067 }
1068 },
1069 [HYPERV_FEAT_SYNDBG] = {
1070 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
1071 .flags = {
1072 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1073 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
1074 },
1075 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED),
1076 .skip_passthrough = true,
1077 },
1078 [HYPERV_FEAT_MSR_BITMAP] = {
1079 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
1080 .flags = {
1081 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1082 .bits = HV_NESTED_MSR_BITMAP}
1083 }
1084 },
1085 [HYPERV_FEAT_XMM_INPUT] = {
1086 .desc = "XMM fast hypercall input (hv-xmm-input)",
1087 .flags = {
1088 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1089 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
1090 }
1091 },
1092 [HYPERV_FEAT_TLBFLUSH_EXT] = {
1093 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
1094 .flags = {
1095 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
1096 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
1097 },
1098 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
1099 },
1100 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1101 .desc = "direct TLB flush (hv-tlbflush-direct)",
1102 .flags = {
1103 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1104 .bits = HV_NESTED_DIRECT_FLUSH}
1105 },
1106 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1107 },
1108 };
1109
try_get_hv_cpuid(CPUState * cs,int max,bool do_sys_ioctl)1110 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1111 bool do_sys_ioctl)
1112 {
1113 struct kvm_cpuid2 *cpuid;
1114 int r, size;
1115
1116 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1117 cpuid = g_malloc0(size);
1118 cpuid->nent = max;
1119
1120 if (do_sys_ioctl) {
1121 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1122 } else {
1123 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1124 }
1125 if (r == 0 && cpuid->nent >= max) {
1126 r = -E2BIG;
1127 }
1128 if (r < 0) {
1129 if (r == -E2BIG) {
1130 g_free(cpuid);
1131 return NULL;
1132 } else {
1133 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1134 strerror(-r));
1135 exit(1);
1136 }
1137 }
1138 return cpuid;
1139 }
1140
1141 /*
1142 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1143 * for all entries.
1144 */
get_supported_hv_cpuid(CPUState * cs)1145 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1146 {
1147 struct kvm_cpuid2 *cpuid;
1148 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1149 int max = 11;
1150 int i;
1151 bool do_sys_ioctl;
1152
1153 do_sys_ioctl =
1154 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
1155
1156 /*
1157 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1158 * unsupported, kvm_hyperv_expand_features() checks for that.
1159 */
1160 assert(do_sys_ioctl || cs->kvm_state);
1161
1162 /*
1163 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1164 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1165 * it and re-trying until we succeed.
1166 */
1167 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
1168 max++;
1169 }
1170
1171 /*
1172 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1173 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1174 * information early, just check for the capability and set the bit
1175 * manually.
1176 */
1177 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
1178 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1179 for (i = 0; i < cpuid->nent; i++) {
1180 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1181 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1182 }
1183 }
1184 }
1185
1186 return cpuid;
1187 }
1188
1189 /*
1190 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1191 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1192 */
get_supported_hv_cpuid_legacy(CPUState * cs)1193 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1194 {
1195 X86CPU *cpu = X86_CPU(cs);
1196 struct kvm_cpuid2 *cpuid;
1197 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1198
1199 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1200 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1201 cpuid->nent = 2;
1202
1203 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1204 entry_feat = &cpuid->entries[0];
1205 entry_feat->function = HV_CPUID_FEATURES;
1206
1207 entry_recomm = &cpuid->entries[1];
1208 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1209 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1210
1211 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1212 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1213 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1214 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1215 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1216 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1217 }
1218
1219 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1220 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1221 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1222 }
1223
1224 if (has_msr_hv_frequencies) {
1225 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1226 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1227 }
1228
1229 if (has_msr_hv_crash) {
1230 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1231 }
1232
1233 if (has_msr_hv_reenlightenment) {
1234 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1235 }
1236
1237 if (has_msr_hv_reset) {
1238 entry_feat->eax |= HV_RESET_AVAILABLE;
1239 }
1240
1241 if (has_msr_hv_vpindex) {
1242 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1243 }
1244
1245 if (has_msr_hv_runtime) {
1246 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1247 }
1248
1249 if (has_msr_hv_synic) {
1250 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1251 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1252
1253 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1254 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1255 }
1256 }
1257
1258 if (has_msr_hv_stimer) {
1259 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1260 }
1261
1262 if (has_msr_hv_syndbg_options) {
1263 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1264 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1265 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1266 }
1267
1268 if (kvm_check_extension(cs->kvm_state,
1269 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1270 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1271 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1272 }
1273
1274 if (kvm_check_extension(cs->kvm_state,
1275 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1276 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1277 }
1278
1279 if (kvm_check_extension(cs->kvm_state,
1280 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1281 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1282 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1283 }
1284
1285 return cpuid;
1286 }
1287
hv_cpuid_get_host(CPUState * cs,uint32_t func,int reg)1288 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1289 {
1290 struct kvm_cpuid_entry2 *entry;
1291 struct kvm_cpuid2 *cpuid;
1292
1293 if (hv_cpuid_cache) {
1294 cpuid = hv_cpuid_cache;
1295 } else {
1296 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1297 cpuid = get_supported_hv_cpuid(cs);
1298 } else {
1299 /*
1300 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1301 * before KVM context is created but this is only done when
1302 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1303 * KVM_CAP_HYPERV_CPUID.
1304 */
1305 assert(cs->kvm_state);
1306
1307 cpuid = get_supported_hv_cpuid_legacy(cs);
1308 }
1309 hv_cpuid_cache = cpuid;
1310 }
1311
1312 if (!cpuid) {
1313 return 0;
1314 }
1315
1316 entry = cpuid_find_entry(cpuid, func, 0);
1317 if (!entry) {
1318 return 0;
1319 }
1320
1321 return cpuid_entry_get_reg(entry, reg);
1322 }
1323
hyperv_feature_supported(CPUState * cs,int feature)1324 static bool hyperv_feature_supported(CPUState *cs, int feature)
1325 {
1326 uint32_t func, bits;
1327 int i, reg;
1328
1329 /*
1330 * kvm_hyperv_properties needs to define at least one CPUID flag which
1331 * must be used to detect the feature, it's hard to say whether it is
1332 * supported or not otherwise.
1333 */
1334 assert(kvm_hyperv_properties[feature].flags[0].func);
1335
1336 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1337
1338 func = kvm_hyperv_properties[feature].flags[i].func;
1339 reg = kvm_hyperv_properties[feature].flags[i].reg;
1340 bits = kvm_hyperv_properties[feature].flags[i].bits;
1341
1342 if (!func) {
1343 continue;
1344 }
1345
1346 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1347 return false;
1348 }
1349 }
1350
1351 return true;
1352 }
1353
1354 /* Checks that all feature dependencies are enabled */
hv_feature_check_deps(X86CPU * cpu,int feature,Error ** errp)1355 static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
1356 {
1357 uint64_t deps;
1358 int dep_feat;
1359
1360 deps = kvm_hyperv_properties[feature].dependencies;
1361 while (deps) {
1362 dep_feat = ctz64(deps);
1363 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1364 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1365 kvm_hyperv_properties[feature].desc,
1366 kvm_hyperv_properties[dep_feat].desc);
1367 return false;
1368 }
1369 deps &= ~(1ull << dep_feat);
1370 }
1371
1372 return true;
1373 }
1374
hv_build_cpuid_leaf(CPUState * cs,uint32_t func,int reg)1375 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1376 {
1377 X86CPU *cpu = X86_CPU(cs);
1378 uint32_t r = 0;
1379 int i, j;
1380
1381 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1382 if (!hyperv_feat_enabled(cpu, i)) {
1383 continue;
1384 }
1385
1386 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1387 if (kvm_hyperv_properties[i].flags[j].func != func) {
1388 continue;
1389 }
1390 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1391 continue;
1392 }
1393
1394 r |= kvm_hyperv_properties[i].flags[j].bits;
1395 }
1396 }
1397
1398 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1399 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1400 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1401 r |= DEFAULT_EVMCS_VERSION;
1402 }
1403 }
1404
1405 return r;
1406 }
1407
1408 /*
1409 * Expand Hyper-V CPU features. In partucular, check that all the requested
1410 * features are supported by the host and the sanity of the configuration
1411 * (that all the required dependencies are included). Also, this takes care
1412 * of 'hv_passthrough' mode and fills the environment with all supported
1413 * Hyper-V features.
1414 */
kvm_hyperv_expand_features(X86CPU * cpu,Error ** errp)1415 bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
1416 {
1417 CPUState *cs = CPU(cpu);
1418 Error *local_err = NULL;
1419 int feat;
1420
1421 if (!hyperv_enabled(cpu))
1422 return true;
1423
1424 /*
1425 * When kvm_hyperv_expand_features is called at CPU feature expansion
1426 * time per-CPU kvm_state is not available yet so we can only proceed
1427 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1428 */
1429 if (!cs->kvm_state &&
1430 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1431 return true;
1432
1433 if (cpu->hyperv_passthrough) {
1434 cpu->hyperv_vendor_id[0] =
1435 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1436 cpu->hyperv_vendor_id[1] =
1437 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1438 cpu->hyperv_vendor_id[2] =
1439 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1440 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1441 sizeof(cpu->hyperv_vendor_id) + 1);
1442 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1443 sizeof(cpu->hyperv_vendor_id));
1444 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1445
1446 cpu->hyperv_interface_id[0] =
1447 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1448 cpu->hyperv_interface_id[1] =
1449 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1450 cpu->hyperv_interface_id[2] =
1451 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1452 cpu->hyperv_interface_id[3] =
1453 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1454
1455 cpu->hyperv_ver_id_build =
1456 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1457 cpu->hyperv_ver_id_major =
1458 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1459 cpu->hyperv_ver_id_minor =
1460 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1461 cpu->hyperv_ver_id_sp =
1462 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1463 cpu->hyperv_ver_id_sb =
1464 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1465 cpu->hyperv_ver_id_sn =
1466 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
1467
1468 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1469 R_EAX);
1470 cpu->hyperv_limits[0] =
1471 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1472 cpu->hyperv_limits[1] =
1473 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1474 cpu->hyperv_limits[2] =
1475 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1476
1477 cpu->hyperv_spinlock_attempts =
1478 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1479
1480 /*
1481 * Mark feature as enabled in 'cpu->hyperv_features' as
1482 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1483 */
1484 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1485 if (hyperv_feature_supported(cs, feat) &&
1486 !kvm_hyperv_properties[feat].skip_passthrough) {
1487 cpu->hyperv_features |= BIT(feat);
1488 }
1489 }
1490 } else {
1491 /* Check features availability and dependencies */
1492 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1493 /* If the feature was not requested skip it. */
1494 if (!hyperv_feat_enabled(cpu, feat)) {
1495 continue;
1496 }
1497
1498 /* Check if the feature is supported by KVM */
1499 if (!hyperv_feature_supported(cs, feat)) {
1500 error_setg(errp, "Hyper-V %s is not supported by kernel",
1501 kvm_hyperv_properties[feat].desc);
1502 return false;
1503 }
1504
1505 /* Check dependencies */
1506 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1507 error_propagate(errp, local_err);
1508 return false;
1509 }
1510 }
1511 }
1512
1513 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1514 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1515 !cpu->hyperv_synic_kvm_only &&
1516 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1517 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1518 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1519 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1520 return false;
1521 }
1522
1523 return true;
1524 }
1525
1526 /*
1527 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1528 */
hyperv_fill_cpuids(CPUState * cs,struct kvm_cpuid_entry2 * cpuid_ent)1529 static int hyperv_fill_cpuids(CPUState *cs,
1530 struct kvm_cpuid_entry2 *cpuid_ent)
1531 {
1532 X86CPU *cpu = X86_CPU(cs);
1533 struct kvm_cpuid_entry2 *c;
1534 uint32_t signature[3];
1535 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
1536 uint32_t nested_eax =
1537 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
1538
1539 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1540 HV_CPUID_IMPLEMENT_LIMITS;
1541
1542 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1543 max_cpuid_leaf =
1544 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1545 }
1546
1547 c = &cpuid_ent[cpuid_i++];
1548 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1549 c->eax = max_cpuid_leaf;
1550 c->ebx = cpu->hyperv_vendor_id[0];
1551 c->ecx = cpu->hyperv_vendor_id[1];
1552 c->edx = cpu->hyperv_vendor_id[2];
1553
1554 c = &cpuid_ent[cpuid_i++];
1555 c->function = HV_CPUID_INTERFACE;
1556 c->eax = cpu->hyperv_interface_id[0];
1557 c->ebx = cpu->hyperv_interface_id[1];
1558 c->ecx = cpu->hyperv_interface_id[2];
1559 c->edx = cpu->hyperv_interface_id[3];
1560
1561 c = &cpuid_ent[cpuid_i++];
1562 c->function = HV_CPUID_VERSION;
1563 c->eax = cpu->hyperv_ver_id_build;
1564 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1565 cpu->hyperv_ver_id_minor;
1566 c->ecx = cpu->hyperv_ver_id_sp;
1567 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1568 (cpu->hyperv_ver_id_sn & 0xffffff);
1569
1570 c = &cpuid_ent[cpuid_i++];
1571 c->function = HV_CPUID_FEATURES;
1572 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1573 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1574 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1575
1576 /* Unconditionally required with any Hyper-V enlightenment */
1577 c->eax |= HV_HYPERCALL_AVAILABLE;
1578
1579 /* SynIC and Vmbus devices require messages/signals hypercalls */
1580 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1581 !cpu->hyperv_synic_kvm_only) {
1582 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1583 }
1584
1585
1586 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1587 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1588
1589 c = &cpuid_ent[cpuid_i++];
1590 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1591 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1592 c->ebx = cpu->hyperv_spinlock_attempts;
1593
1594 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1595 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
1596 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1597 }
1598
1599 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1600 c->eax |= HV_NO_NONARCH_CORESHARING;
1601 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1602 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1603 HV_NO_NONARCH_CORESHARING;
1604 }
1605
1606 c = &cpuid_ent[cpuid_i++];
1607 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1608 c->eax = cpu->hv_max_vps;
1609 c->ebx = cpu->hyperv_limits[0];
1610 c->ecx = cpu->hyperv_limits[1];
1611 c->edx = cpu->hyperv_limits[2];
1612
1613 if (nested_eax) {
1614 uint32_t function;
1615
1616 /* Create zeroed 0x40000006..0x40000009 leaves */
1617 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1618 function < HV_CPUID_NESTED_FEATURES; function++) {
1619 c = &cpuid_ent[cpuid_i++];
1620 c->function = function;
1621 }
1622
1623 c = &cpuid_ent[cpuid_i++];
1624 c->function = HV_CPUID_NESTED_FEATURES;
1625 c->eax = nested_eax;
1626 }
1627
1628 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1629 c = &cpuid_ent[cpuid_i++];
1630 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1631 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1632 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1633 memcpy(signature, "Microsoft VS", 12);
1634 c->eax = 0;
1635 c->ebx = signature[0];
1636 c->ecx = signature[1];
1637 c->edx = signature[2];
1638
1639 c = &cpuid_ent[cpuid_i++];
1640 c->function = HV_CPUID_SYNDBG_INTERFACE;
1641 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1642 c->eax = signature[0];
1643 c->ebx = 0;
1644 c->ecx = 0;
1645 c->edx = 0;
1646
1647 c = &cpuid_ent[cpuid_i++];
1648 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1649 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1650 c->ebx = 0;
1651 c->ecx = 0;
1652 c->edx = 0;
1653 }
1654
1655 return cpuid_i;
1656 }
1657
1658 static Error *hv_passthrough_mig_blocker;
1659 static Error *hv_no_nonarch_cs_mig_blocker;
1660
1661 /* Checks that the exposed eVMCS version range is supported by KVM */
evmcs_version_supported(uint16_t evmcs_version,uint16_t supported_evmcs_version)1662 static bool evmcs_version_supported(uint16_t evmcs_version,
1663 uint16_t supported_evmcs_version)
1664 {
1665 uint8_t min_version = evmcs_version & 0xff;
1666 uint8_t max_version = evmcs_version >> 8;
1667 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1668 uint8_t max_supported_version = supported_evmcs_version >> 8;
1669
1670 return (min_version >= min_supported_version) &&
1671 (max_version <= max_supported_version);
1672 }
1673
hyperv_init_vcpu(X86CPU * cpu)1674 static int hyperv_init_vcpu(X86CPU *cpu)
1675 {
1676 CPUState *cs = CPU(cpu);
1677 Error *local_err = NULL;
1678 int ret;
1679
1680 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1681 error_setg(&hv_passthrough_mig_blocker,
1682 "'hv-passthrough' CPU flag prevents migration, use explicit"
1683 " set of hv-* flags instead");
1684 ret = migrate_add_blocker(&hv_passthrough_mig_blocker, &local_err);
1685 if (ret < 0) {
1686 error_report_err(local_err);
1687 return ret;
1688 }
1689 }
1690
1691 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1692 hv_no_nonarch_cs_mig_blocker == NULL) {
1693 error_setg(&hv_no_nonarch_cs_mig_blocker,
1694 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1695 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1696 " make sure SMT is disabled and/or that vCPUs are properly"
1697 " pinned)");
1698 ret = migrate_add_blocker(&hv_no_nonarch_cs_mig_blocker, &local_err);
1699 if (ret < 0) {
1700 error_report_err(local_err);
1701 return ret;
1702 }
1703 }
1704
1705 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1706 /*
1707 * the kernel doesn't support setting vp_index; assert that its value
1708 * is in sync
1709 */
1710 uint64_t value;
1711
1712 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
1713 if (ret < 0) {
1714 return ret;
1715 }
1716
1717 if (value != hyperv_vp_index(CPU(cpu))) {
1718 error_report("kernel's vp_index != QEMU's vp_index");
1719 return -ENXIO;
1720 }
1721 }
1722
1723 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1724 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1725 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1726 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1727 if (ret < 0) {
1728 error_report("failed to turn on HyperV SynIC in KVM: %s",
1729 strerror(-ret));
1730 return ret;
1731 }
1732
1733 if (!cpu->hyperv_synic_kvm_only) {
1734 ret = hyperv_x86_synic_add(cpu);
1735 if (ret < 0) {
1736 error_report("failed to create HyperV SynIC: %s",
1737 strerror(-ret));
1738 return ret;
1739 }
1740 }
1741 }
1742
1743 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1744 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1745 uint16_t supported_evmcs_version;
1746
1747 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1748 (uintptr_t)&supported_evmcs_version);
1749
1750 /*
1751 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1752 * option sets. Note: we hardcode the maximum supported eVMCS version
1753 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1754 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1755 * to be added.
1756 */
1757 if (ret < 0) {
1758 error_report("Hyper-V %s is not supported by kernel",
1759 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1760 return ret;
1761 }
1762
1763 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1764 error_report("eVMCS version range [%d..%d] is not supported by "
1765 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1766 evmcs_version >> 8, supported_evmcs_version & 0xff,
1767 supported_evmcs_version >> 8);
1768 return -ENOTSUP;
1769 }
1770 }
1771
1772 if (cpu->hyperv_enforce_cpuid) {
1773 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1774 if (ret < 0) {
1775 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1776 strerror(-ret));
1777 return ret;
1778 }
1779 }
1780
1781 /* Skip SynIC and VP_INDEX since they are hard deps already */
1782 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER) &&
1783 hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1784 hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1785 hyperv_x86_set_vmbus_recommended_features_enabled();
1786 }
1787
1788 return 0;
1789 }
1790
1791 static Error *invtsc_mig_blocker;
1792
kvm_init_xsave(CPUX86State * env)1793 static void kvm_init_xsave(CPUX86State *env)
1794 {
1795 if (has_xsave2) {
1796 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1797 } else {
1798 env->xsave_buf_len = sizeof(struct kvm_xsave);
1799 }
1800
1801 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1802 memset(env->xsave_buf, 0, env->xsave_buf_len);
1803 /*
1804 * The allocated storage must be large enough for all of the
1805 * possible XSAVE state components.
1806 */
1807 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1808 env->xsave_buf_len);
1809 }
1810
kvm_init_nested_state(CPUX86State * env)1811 static void kvm_init_nested_state(CPUX86State *env)
1812 {
1813 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1814 uint32_t size;
1815
1816 if (!env->nested_state) {
1817 return;
1818 }
1819
1820 size = env->nested_state->size;
1821
1822 memset(env->nested_state, 0, size);
1823 env->nested_state->size = size;
1824
1825 if (cpu_has_vmx(env)) {
1826 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1827 vmx_hdr = &env->nested_state->hdr.vmx;
1828 vmx_hdr->vmxon_pa = -1ull;
1829 vmx_hdr->vmcs12_pa = -1ull;
1830 } else if (cpu_has_svm(env)) {
1831 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1832 }
1833 }
1834
kvm_x86_build_cpuid(CPUX86State * env,struct kvm_cpuid_entry2 * entries,uint32_t cpuid_i)1835 uint32_t kvm_x86_build_cpuid(CPUX86State *env, struct kvm_cpuid_entry2 *entries,
1836 uint32_t cpuid_i)
1837 {
1838 uint32_t limit, i, j;
1839 uint32_t unused;
1840 struct kvm_cpuid_entry2 *c;
1841
1842 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1843
1844 for (i = 0; i <= limit; i++) {
1845 j = 0;
1846 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1847 goto full;
1848 }
1849 c = &entries[cpuid_i++];
1850 switch (i) {
1851 case 2: {
1852 /* Keep reading function 2 till all the input is received */
1853 int times;
1854
1855 c->function = i;
1856 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1857 times = c->eax & 0xff;
1858 if (times > 1) {
1859 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1860 KVM_CPUID_FLAG_STATE_READ_NEXT;
1861 }
1862
1863 for (j = 1; j < times; ++j) {
1864 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1865 goto full;
1866 }
1867 c = &entries[cpuid_i++];
1868 c->function = i;
1869 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1870 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1871 }
1872 break;
1873 }
1874 case 0x1f:
1875 if (!x86_has_cpuid_0x1f(env_archcpu(env))) {
1876 cpuid_i--;
1877 break;
1878 }
1879 /* fallthrough */
1880 case 4:
1881 case 0xb:
1882 case 0xd:
1883 for (j = 0; ; j++) {
1884 c->function = i;
1885 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1886 c->index = j;
1887 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1888
1889 if (i == 4 && c->eax == 0) {
1890 break;
1891 }
1892 if (i == 0xb && !(c->ecx & 0xff00)) {
1893 break;
1894 }
1895 if (i == 0x1f && !(c->ecx & 0xff00)) {
1896 break;
1897 }
1898 if (i == 0xd && c->eax == 0) {
1899 if (j < 63) {
1900 continue;
1901 } else {
1902 cpuid_i--;
1903 break;
1904 }
1905 }
1906 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1907 goto full;
1908 }
1909 c = &entries[cpuid_i++];
1910 }
1911 break;
1912 case 0x12:
1913 for (j = 0; ; j++) {
1914 c->function = i;
1915 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1916 c->index = j;
1917 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1918
1919 if (j > 1 && (c->eax & 0xf) != 1) {
1920 break;
1921 }
1922
1923 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1924 goto full;
1925 }
1926 c = &entries[cpuid_i++];
1927 }
1928 break;
1929 case 0x7:
1930 case 0x14:
1931 case 0x1d:
1932 case 0x1e:
1933 case 0x24: {
1934 uint32_t times;
1935
1936 c->function = i;
1937 c->index = 0;
1938 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1939 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1940 times = c->eax;
1941
1942 for (j = 1; j <= times; ++j) {
1943 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1944 goto full;
1945 }
1946 c = &entries[cpuid_i++];
1947 c->function = i;
1948 c->index = j;
1949 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1950 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1951 }
1952 break;
1953 }
1954 default:
1955 c->function = i;
1956 c->flags = 0;
1957 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1958 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1959 /*
1960 * KVM already returns all zeroes if a CPUID entry is missing,
1961 * so we can omit it and avoid hitting KVM's 80-entry limit.
1962 */
1963 cpuid_i--;
1964 }
1965 break;
1966 }
1967 }
1968
1969 if (limit >= 0x0a) {
1970 uint32_t eax, edx;
1971
1972 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1973
1974 has_architectural_pmu_version = eax & 0xff;
1975 if (has_architectural_pmu_version > 0) {
1976 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1977
1978 /* Shouldn't be more than 32, since that's the number of bits
1979 * available in EBX to tell us _which_ counters are available.
1980 * Play it safe.
1981 */
1982 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1983 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1984 }
1985
1986 if (has_architectural_pmu_version > 1) {
1987 num_architectural_pmu_fixed_counters = edx & 0x1f;
1988
1989 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1990 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1991 }
1992 }
1993 }
1994 }
1995
1996 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1997
1998 for (i = 0x80000000; i <= limit; i++) {
1999 j = 0;
2000 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2001 goto full;
2002 }
2003 c = &entries[cpuid_i++];
2004
2005 switch (i) {
2006 case 0x8000001d:
2007 /* Query for all AMD cache information leaves */
2008 for (j = 0; ; j++) {
2009 c->function = i;
2010 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2011 c->index = j;
2012 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2013
2014 if (c->eax == 0) {
2015 break;
2016 }
2017 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2018 goto full;
2019 }
2020 c = &entries[cpuid_i++];
2021 }
2022 break;
2023 default:
2024 c->function = i;
2025 c->flags = 0;
2026 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2027 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2028 /*
2029 * KVM already returns all zeroes if a CPUID entry is missing,
2030 * so we can omit it and avoid hitting KVM's 80-entry limit.
2031 */
2032 cpuid_i--;
2033 }
2034 break;
2035 }
2036 }
2037
2038 /* Call Centaur's CPUID instructions they are supported. */
2039 if (env->cpuid_xlevel2 > 0) {
2040 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2041
2042 for (i = 0xC0000000; i <= limit; i++) {
2043 j = 0;
2044 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2045 goto full;
2046 }
2047 c = &entries[cpuid_i++];
2048
2049 c->function = i;
2050 c->flags = 0;
2051 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2052 }
2053 }
2054
2055 return cpuid_i;
2056
2057 full:
2058 fprintf(stderr, "cpuid_data is full, no space for "
2059 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2060 abort();
2061 }
2062
kvm_arch_pre_create_vcpu(CPUState * cpu,Error ** errp)2063 int kvm_arch_pre_create_vcpu(CPUState *cpu, Error **errp)
2064 {
2065 if (is_tdx_vm()) {
2066 return tdx_pre_create_vcpu(cpu, errp);
2067 }
2068
2069 return 0;
2070 }
2071
kvm_arch_init_vcpu(CPUState * cs)2072 int kvm_arch_init_vcpu(CPUState *cs)
2073 {
2074 struct {
2075 struct kvm_cpuid2 cpuid;
2076 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
2077 } cpuid_data;
2078 /*
2079 * The kernel defines these structs with padding fields so there
2080 * should be no extra padding in our cpuid_data struct.
2081 */
2082 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
2083 sizeof(struct kvm_cpuid2) +
2084 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
2085
2086 X86CPU *cpu = X86_CPU(cs);
2087 CPUX86State *env = &cpu->env;
2088 uint32_t cpuid_i;
2089 struct kvm_cpuid_entry2 *c;
2090 uint32_t signature[3];
2091 int kvm_base = KVM_CPUID_SIGNATURE;
2092 int max_nested_state_len;
2093 int r;
2094 Error *local_err = NULL;
2095
2096 if (current_machine->cgs) {
2097 r = x86_confidential_guest_check_features(
2098 X86_CONFIDENTIAL_GUEST(current_machine->cgs), cs);
2099 if (r < 0) {
2100 return r;
2101 }
2102 }
2103
2104 memset(&cpuid_data, 0, sizeof(cpuid_data));
2105
2106 cpuid_i = 0;
2107
2108 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
2109
2110 r = kvm_arch_set_tsc_khz(cs);
2111 if (r < 0) {
2112 return r;
2113 }
2114
2115 /* vcpu's TSC frequency is either specified by user, or following
2116 * the value used by KVM if the former is not present. In the
2117 * latter case, we query it from KVM and record in env->tsc_khz,
2118 * so that vcpu's TSC frequency can be migrated later via this field.
2119 */
2120 if (!env->tsc_khz) {
2121 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
2122 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
2123 -ENOTSUP;
2124 if (r > 0) {
2125 env->tsc_khz = r;
2126 }
2127 }
2128
2129 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
2130
2131 /*
2132 * kvm_hyperv_expand_features() is called here for the second time in case
2133 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
2134 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
2135 * check which Hyper-V enlightenments are supported and which are not, we
2136 * can still proceed and check/expand Hyper-V enlightenments here so legacy
2137 * behavior is preserved.
2138 */
2139 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
2140 error_report_err(local_err);
2141 return -ENOSYS;
2142 }
2143
2144 if (hyperv_enabled(cpu)) {
2145 r = hyperv_init_vcpu(cpu);
2146 if (r) {
2147 return r;
2148 }
2149
2150 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
2151 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
2152 has_msr_hv_hypercall = true;
2153 }
2154
2155 if (cs->kvm_state->xen_version) {
2156 #ifdef CONFIG_XEN_EMU
2157 struct kvm_cpuid_entry2 *xen_max_leaf;
2158
2159 memcpy(signature, "XenVMMXenVMM", 12);
2160
2161 xen_max_leaf = c = &cpuid_data.entries[cpuid_i++];
2162 c->function = kvm_base + XEN_CPUID_SIGNATURE;
2163 c->eax = kvm_base + XEN_CPUID_TIME;
2164 c->ebx = signature[0];
2165 c->ecx = signature[1];
2166 c->edx = signature[2];
2167
2168 c = &cpuid_data.entries[cpuid_i++];
2169 c->function = kvm_base + XEN_CPUID_VENDOR;
2170 c->eax = cs->kvm_state->xen_version;
2171 c->ebx = 0;
2172 c->ecx = 0;
2173 c->edx = 0;
2174
2175 c = &cpuid_data.entries[cpuid_i++];
2176 c->function = kvm_base + XEN_CPUID_HVM_MSR;
2177 /* Number of hypercall-transfer pages */
2178 c->eax = 1;
2179 /* Hypercall MSR base address */
2180 if (hyperv_enabled(cpu)) {
2181 c->ebx = XEN_HYPERCALL_MSR_HYPERV;
2182 kvm_xen_init(cs->kvm_state, c->ebx);
2183 } else {
2184 c->ebx = XEN_HYPERCALL_MSR;
2185 }
2186 c->ecx = 0;
2187 c->edx = 0;
2188
2189 c = &cpuid_data.entries[cpuid_i++];
2190 c->function = kvm_base + XEN_CPUID_TIME;
2191 c->eax = ((!!tsc_is_stable_and_known(env) << 1) |
2192 (!!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP) << 2));
2193 /* default=0 (emulate if necessary) */
2194 c->ebx = 0;
2195 /* guest tsc frequency */
2196 c->ecx = env->user_tsc_khz;
2197 /* guest tsc incarnation (migration count) */
2198 c->edx = 0;
2199
2200 c = &cpuid_data.entries[cpuid_i++];
2201 c->function = kvm_base + XEN_CPUID_HVM;
2202 xen_max_leaf->eax = kvm_base + XEN_CPUID_HVM;
2203 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 5)) {
2204 c->function = kvm_base + XEN_CPUID_HVM;
2205
2206 if (cpu->xen_vapic) {
2207 c->eax |= XEN_HVM_CPUID_APIC_ACCESS_VIRT;
2208 c->eax |= XEN_HVM_CPUID_X2APIC_VIRT;
2209 }
2210
2211 c->eax |= XEN_HVM_CPUID_IOMMU_MAPPINGS;
2212
2213 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 6)) {
2214 c->eax |= XEN_HVM_CPUID_VCPU_ID_PRESENT;
2215 c->ebx = cs->cpu_index;
2216 }
2217
2218 if (cs->kvm_state->xen_version >= XEN_VERSION(4, 17)) {
2219 c->eax |= XEN_HVM_CPUID_UPCALL_VECTOR;
2220 }
2221 }
2222
2223 r = kvm_xen_init_vcpu(cs);
2224 if (r) {
2225 return r;
2226 }
2227
2228 kvm_base += 0x100;
2229 #else /* CONFIG_XEN_EMU */
2230 /* This should never happen as kvm_arch_init() would have died first. */
2231 fprintf(stderr, "Cannot enable Xen CPUID without Xen support\n");
2232 abort();
2233 #endif
2234 } else if (cpu->expose_kvm) {
2235 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
2236 c = &cpuid_data.entries[cpuid_i++];
2237 c->function = KVM_CPUID_SIGNATURE | kvm_base;
2238 c->eax = KVM_CPUID_FEATURES | kvm_base;
2239 c->ebx = signature[0];
2240 c->ecx = signature[1];
2241 c->edx = signature[2];
2242
2243 c = &cpuid_data.entries[cpuid_i++];
2244 c->function = KVM_CPUID_FEATURES | kvm_base;
2245 c->eax = env->features[FEAT_KVM];
2246 c->edx = env->features[FEAT_KVM_HINTS];
2247 }
2248
2249 if (cpu->kvm_pv_enforce_cpuid) {
2250 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
2251 if (r < 0) {
2252 fprintf(stderr,
2253 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
2254 strerror(-r));
2255 abort();
2256 }
2257 }
2258
2259 cpuid_i = kvm_x86_build_cpuid(env, cpuid_data.entries, cpuid_i);
2260 cpuid_data.cpuid.nent = cpuid_i;
2261
2262 if (((env->cpuid_version >> 8)&0xF) >= 6
2263 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2264 (CPUID_MCE | CPUID_MCA)) {
2265 uint64_t mcg_cap, unsupported_caps;
2266 int banks;
2267 int ret;
2268
2269 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
2270 if (ret < 0) {
2271 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2272 return ret;
2273 }
2274
2275 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
2276 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2277 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
2278 return -ENOTSUP;
2279 }
2280
2281 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2282 if (unsupported_caps) {
2283 if (unsupported_caps & MCG_LMCE_P) {
2284 error_report("kvm: LMCE not supported");
2285 return -ENOTSUP;
2286 }
2287 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2288 unsupported_caps);
2289 }
2290
2291 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2292 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
2293 if (ret < 0) {
2294 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2295 return ret;
2296 }
2297 }
2298
2299 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
2300
2301 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2302 if (c) {
2303 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2304 !!(c->ecx & CPUID_EXT_SMX);
2305 }
2306
2307 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2308 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2309 has_msr_feature_control = true;
2310 }
2311
2312 if (env->mcg_cap & MCG_LMCE_P) {
2313 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2314 }
2315
2316 if (!env->user_tsc_khz) {
2317 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2318 invtsc_mig_blocker == NULL) {
2319 error_setg(&invtsc_mig_blocker,
2320 "State blocked by non-migratable CPU device"
2321 " (invtsc flag)");
2322 r = migrate_add_blocker(&invtsc_mig_blocker, &local_err);
2323 if (r < 0) {
2324 error_report_err(local_err);
2325 return r;
2326 }
2327 }
2328 }
2329
2330 if (cpu->vmware_cpuid_freq
2331 /* Guests depend on 0x40000000 to detect this feature, so only expose
2332 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2333 && cpu->expose_kvm
2334 && kvm_base == KVM_CPUID_SIGNATURE
2335 /* TSC clock must be stable and known for this feature. */
2336 && tsc_is_stable_and_known(env)) {
2337
2338 c = &cpuid_data.entries[cpuid_i++];
2339 c->function = KVM_CPUID_SIGNATURE | 0x10;
2340 c->eax = env->tsc_khz;
2341 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
2342 c->ecx = c->edx = 0;
2343
2344 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2345 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2346 }
2347
2348 cpuid_data.cpuid.nent = cpuid_i;
2349
2350 cpuid_data.cpuid.padding = 0;
2351 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2352 if (r) {
2353 goto fail;
2354 }
2355 kvm_init_xsave(env);
2356
2357 max_nested_state_len = kvm_max_nested_state_length();
2358 if (max_nested_state_len > 0) {
2359 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
2360
2361 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
2362 env->nested_state = g_malloc0(max_nested_state_len);
2363 env->nested_state->size = max_nested_state_len;
2364
2365 kvm_init_nested_state(env);
2366 }
2367 }
2368
2369 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
2370
2371 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2372 has_msr_tsc_aux = false;
2373 }
2374
2375 kvm_init_msrs(cpu);
2376
2377 return 0;
2378
2379 fail:
2380 migrate_del_blocker(&invtsc_mig_blocker);
2381
2382 return r;
2383 }
2384
kvm_arch_destroy_vcpu(CPUState * cs)2385 int kvm_arch_destroy_vcpu(CPUState *cs)
2386 {
2387 X86CPU *cpu = X86_CPU(cs);
2388 CPUX86State *env = &cpu->env;
2389
2390 g_free(env->xsave_buf);
2391
2392 g_free(cpu->kvm_msr_buf);
2393 cpu->kvm_msr_buf = NULL;
2394
2395 g_free(env->nested_state);
2396 env->nested_state = NULL;
2397
2398 qemu_del_vm_change_state_handler(cpu->vmsentry);
2399
2400 return 0;
2401 }
2402
kvm_arch_reset_vcpu(X86CPU * cpu)2403 void kvm_arch_reset_vcpu(X86CPU *cpu)
2404 {
2405 CPUX86State *env = &cpu->env;
2406
2407 env->xcr0 = 1;
2408 if (kvm_irqchip_in_kernel()) {
2409 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
2410 KVM_MP_STATE_UNINITIALIZED;
2411 } else {
2412 env->mp_state = KVM_MP_STATE_RUNNABLE;
2413 }
2414
2415 /* enabled by default */
2416 env->poll_control_msr = 1;
2417
2418 kvm_init_nested_state(env);
2419
2420 sev_es_set_reset_vector(CPU(cpu));
2421 }
2422
kvm_arch_after_reset_vcpu(X86CPU * cpu)2423 void kvm_arch_after_reset_vcpu(X86CPU *cpu)
2424 {
2425 CPUX86State *env = &cpu->env;
2426 int i;
2427
2428 /*
2429 * Reset SynIC after all other devices have been reset to let them remove
2430 * their SINT routes first.
2431 */
2432 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2433 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2434 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2435 }
2436
2437 hyperv_x86_synic_reset(cpu);
2438 }
2439 }
2440
kvm_arch_reset_parked_vcpu(unsigned long vcpu_id,int kvm_fd)2441 void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd)
2442 {
2443 g_autofree struct kvm_msrs *msrs = NULL;
2444
2445 msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0]));
2446 msrs->entries[0].index = MSR_IA32_TSC;
2447 msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */
2448 msrs->nmsrs++;
2449
2450 if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) {
2451 warn_report("parked vCPU %lu TSC reset failed: %d",
2452 vcpu_id, errno);
2453 }
2454 }
2455
kvm_arch_do_init_vcpu(X86CPU * cpu)2456 void kvm_arch_do_init_vcpu(X86CPU *cpu)
2457 {
2458 CPUX86State *env = &cpu->env;
2459
2460 /* APs get directly into wait-for-SIPI state. */
2461 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2462 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2463 }
2464 }
2465
kvm_get_supported_feature_msrs(KVMState * s)2466 static int kvm_get_supported_feature_msrs(KVMState *s)
2467 {
2468 int ret = 0;
2469
2470 if (kvm_feature_msrs != NULL) {
2471 return 0;
2472 }
2473
2474 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2475 return 0;
2476 }
2477
2478 struct kvm_msr_list msr_list;
2479
2480 msr_list.nmsrs = 0;
2481 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2482 if (ret < 0 && ret != -E2BIG) {
2483 error_report("Fetch KVM feature MSR list failed: %s",
2484 strerror(-ret));
2485 return ret;
2486 }
2487
2488 assert(msr_list.nmsrs > 0);
2489 kvm_feature_msrs = g_malloc0(sizeof(msr_list) +
2490 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2491
2492 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2493 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2494
2495 if (ret < 0) {
2496 error_report("Fetch KVM feature MSR list failed: %s",
2497 strerror(-ret));
2498 g_free(kvm_feature_msrs);
2499 kvm_feature_msrs = NULL;
2500 return ret;
2501 }
2502
2503 return 0;
2504 }
2505
kvm_get_supported_msrs(KVMState * s)2506 static int kvm_get_supported_msrs(KVMState *s)
2507 {
2508 int ret = 0;
2509 struct kvm_msr_list msr_list, *kvm_msr_list;
2510
2511 /*
2512 * Obtain MSR list from KVM. These are the MSRs that we must
2513 * save/restore.
2514 */
2515 msr_list.nmsrs = 0;
2516 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2517 if (ret < 0 && ret != -E2BIG) {
2518 return ret;
2519 }
2520 /*
2521 * Old kernel modules had a bug and could write beyond the provided
2522 * memory. Allocate at least a safe amount of 1K.
2523 */
2524 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2525 msr_list.nmsrs *
2526 sizeof(msr_list.indices[0])));
2527
2528 kvm_msr_list->nmsrs = msr_list.nmsrs;
2529 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2530 if (ret >= 0) {
2531 int i;
2532
2533 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2534 switch (kvm_msr_list->indices[i]) {
2535 case MSR_STAR:
2536 has_msr_star = true;
2537 break;
2538 case MSR_VM_HSAVE_PA:
2539 has_msr_hsave_pa = true;
2540 break;
2541 case MSR_TSC_AUX:
2542 has_msr_tsc_aux = true;
2543 break;
2544 case MSR_TSC_ADJUST:
2545 has_msr_tsc_adjust = true;
2546 break;
2547 case MSR_IA32_TSCDEADLINE:
2548 has_msr_tsc_deadline = true;
2549 break;
2550 case MSR_IA32_SMBASE:
2551 has_msr_smbase = true;
2552 break;
2553 case MSR_SMI_COUNT:
2554 has_msr_smi_count = true;
2555 break;
2556 case MSR_IA32_MISC_ENABLE:
2557 has_msr_misc_enable = true;
2558 break;
2559 case MSR_IA32_BNDCFGS:
2560 has_msr_bndcfgs = true;
2561 break;
2562 case MSR_IA32_XSS:
2563 has_msr_xss = true;
2564 break;
2565 case MSR_IA32_UMWAIT_CONTROL:
2566 has_msr_umwait = true;
2567 break;
2568 case HV_X64_MSR_CRASH_CTL:
2569 has_msr_hv_crash = true;
2570 break;
2571 case HV_X64_MSR_RESET:
2572 has_msr_hv_reset = true;
2573 break;
2574 case HV_X64_MSR_VP_INDEX:
2575 has_msr_hv_vpindex = true;
2576 break;
2577 case HV_X64_MSR_VP_RUNTIME:
2578 has_msr_hv_runtime = true;
2579 break;
2580 case HV_X64_MSR_SCONTROL:
2581 has_msr_hv_synic = true;
2582 break;
2583 case HV_X64_MSR_STIMER0_CONFIG:
2584 has_msr_hv_stimer = true;
2585 break;
2586 case HV_X64_MSR_TSC_FREQUENCY:
2587 has_msr_hv_frequencies = true;
2588 break;
2589 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2590 has_msr_hv_reenlightenment = true;
2591 break;
2592 case HV_X64_MSR_SYNDBG_OPTIONS:
2593 has_msr_hv_syndbg_options = true;
2594 break;
2595 case MSR_IA32_SPEC_CTRL:
2596 has_msr_spec_ctrl = true;
2597 break;
2598 case MSR_AMD64_TSC_RATIO:
2599 has_tsc_scale_msr = true;
2600 break;
2601 case MSR_IA32_TSX_CTRL:
2602 has_msr_tsx_ctrl = true;
2603 break;
2604 case MSR_VIRT_SSBD:
2605 has_msr_virt_ssbd = true;
2606 break;
2607 case MSR_IA32_ARCH_CAPABILITIES:
2608 has_msr_arch_capabs = true;
2609 break;
2610 case MSR_IA32_CORE_CAPABILITY:
2611 has_msr_core_capabs = true;
2612 break;
2613 case MSR_IA32_PERF_CAPABILITIES:
2614 has_msr_perf_capabs = true;
2615 break;
2616 case MSR_IA32_VMX_VMFUNC:
2617 has_msr_vmx_vmfunc = true;
2618 break;
2619 case MSR_IA32_UCODE_REV:
2620 has_msr_ucode_rev = true;
2621 break;
2622 case MSR_IA32_VMX_PROCBASED_CTLS2:
2623 has_msr_vmx_procbased_ctls2 = true;
2624 break;
2625 case MSR_IA32_PKRS:
2626 has_msr_pkrs = true;
2627 break;
2628 case MSR_K7_HWCR:
2629 has_msr_hwcr = true;
2630 }
2631 }
2632 }
2633
2634 g_free(kvm_msr_list);
2635
2636 return ret;
2637 }
2638
kvm_rdmsr_core_thread_count(X86CPU * cpu,uint32_t msr,uint64_t * val)2639 static bool kvm_rdmsr_core_thread_count(X86CPU *cpu,
2640 uint32_t msr,
2641 uint64_t *val)
2642 {
2643 *val = cpu_x86_get_msr_core_thread_count(cpu);
2644
2645 return true;
2646 }
2647
kvm_rdmsr_rapl_power_unit(X86CPU * cpu,uint32_t msr,uint64_t * val)2648 static bool kvm_rdmsr_rapl_power_unit(X86CPU *cpu,
2649 uint32_t msr,
2650 uint64_t *val)
2651 {
2652
2653 CPUState *cs = CPU(cpu);
2654
2655 *val = cs->kvm_state->msr_energy.msr_unit;
2656
2657 return true;
2658 }
2659
kvm_rdmsr_pkg_power_limit(X86CPU * cpu,uint32_t msr,uint64_t * val)2660 static bool kvm_rdmsr_pkg_power_limit(X86CPU *cpu,
2661 uint32_t msr,
2662 uint64_t *val)
2663 {
2664
2665 CPUState *cs = CPU(cpu);
2666
2667 *val = cs->kvm_state->msr_energy.msr_limit;
2668
2669 return true;
2670 }
2671
kvm_rdmsr_pkg_power_info(X86CPU * cpu,uint32_t msr,uint64_t * val)2672 static bool kvm_rdmsr_pkg_power_info(X86CPU *cpu,
2673 uint32_t msr,
2674 uint64_t *val)
2675 {
2676
2677 CPUState *cs = CPU(cpu);
2678
2679 *val = cs->kvm_state->msr_energy.msr_info;
2680
2681 return true;
2682 }
2683
kvm_rdmsr_pkg_energy_status(X86CPU * cpu,uint32_t msr,uint64_t * val)2684 static bool kvm_rdmsr_pkg_energy_status(X86CPU *cpu,
2685 uint32_t msr,
2686 uint64_t *val)
2687 {
2688
2689 CPUState *cs = CPU(cpu);
2690 *val = cs->kvm_state->msr_energy.msr_value[cs->cpu_index];
2691
2692 return true;
2693 }
2694
2695 static Notifier smram_machine_done;
2696 static KVMMemoryListener smram_listener;
2697 static AddressSpace smram_address_space;
2698 static MemoryRegion smram_as_root;
2699 static MemoryRegion smram_as_mem;
2700
register_smram_listener(Notifier * n,void * unused)2701 static void register_smram_listener(Notifier *n, void *unused)
2702 {
2703 MemoryRegion *smram =
2704 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2705
2706 /* Outer container... */
2707 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2708 memory_region_set_enabled(&smram_as_root, true);
2709
2710 /* ... with two regions inside: normal system memory with low
2711 * priority, and...
2712 */
2713 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2714 get_system_memory(), 0, ~0ull);
2715 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2716 memory_region_set_enabled(&smram_as_mem, true);
2717
2718 if (smram) {
2719 /* ... SMRAM with higher priority */
2720 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2721 memory_region_set_enabled(smram, true);
2722 }
2723
2724 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2725 kvm_memory_listener_register(kvm_state, &smram_listener,
2726 &smram_address_space, 1, "kvm-smram");
2727 }
2728
kvm_msr_energy_thread(void * data)2729 static void *kvm_msr_energy_thread(void *data)
2730 {
2731 KVMState *s = data;
2732 struct KVMMsrEnergy *vmsr = &s->msr_energy;
2733
2734 g_autofree vmsr_package_energy_stat *pkg_stat = NULL;
2735 g_autofree vmsr_thread_stat *thd_stat = NULL;
2736 g_autofree CPUState *cpu = NULL;
2737 g_autofree unsigned int *vpkgs_energy_stat = NULL;
2738 unsigned int num_threads = 0;
2739
2740 X86CPUTopoIDs topo_ids;
2741
2742 rcu_register_thread();
2743
2744 /* Allocate memory for each package energy status */
2745 pkg_stat = g_new0(vmsr_package_energy_stat, vmsr->host_topo.maxpkgs);
2746
2747 /* Allocate memory for thread stats */
2748 thd_stat = g_new0(vmsr_thread_stat, 1);
2749
2750 /* Allocate memory for holding virtual package energy counter */
2751 vpkgs_energy_stat = g_new0(unsigned int, vmsr->guest_vsockets);
2752
2753 /* Populate the max tick of each packages */
2754 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2755 /*
2756 * Max numbers of ticks per package
2757 * Time in second * Number of ticks/second * Number of cores/package
2758 * ex: 100 ticks/second/CPU, 12 CPUs per Package gives 1200 ticks max
2759 */
2760 vmsr->host_topo.maxticks[i] = (MSR_ENERGY_THREAD_SLEEP_US / 1000000)
2761 * sysconf(_SC_CLK_TCK)
2762 * vmsr->host_topo.pkg_cpu_count[i];
2763 }
2764
2765 while (true) {
2766 /* Get all qemu threads id */
2767 g_autofree pid_t *thread_ids
2768 = vmsr_get_thread_ids(vmsr->pid, &num_threads);
2769
2770 if (thread_ids == NULL) {
2771 goto clean;
2772 }
2773
2774 thd_stat = g_renew(vmsr_thread_stat, thd_stat, num_threads);
2775 /* Unlike g_new0, g_renew0 function doesn't exist yet... */
2776 memset(thd_stat, 0, num_threads * sizeof(vmsr_thread_stat));
2777
2778 /* Populate all the thread stats */
2779 for (int i = 0; i < num_threads; i++) {
2780 thd_stat[i].utime = g_new0(unsigned long long, 2);
2781 thd_stat[i].stime = g_new0(unsigned long long, 2);
2782 thd_stat[i].thread_id = thread_ids[i];
2783 vmsr_read_thread_stat(vmsr->pid,
2784 thd_stat[i].thread_id,
2785 &thd_stat[i].utime[0],
2786 &thd_stat[i].stime[0],
2787 &thd_stat[i].cpu_id);
2788 thd_stat[i].pkg_id =
2789 vmsr_get_physical_package_id(thd_stat[i].cpu_id);
2790 }
2791
2792 /* Retrieve all packages power plane energy counter */
2793 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2794 for (int j = 0; j < num_threads; j++) {
2795 /*
2796 * Use the first thread we found that ran on the CPU
2797 * of the package to read the packages energy counter
2798 */
2799 if (thd_stat[j].pkg_id == i) {
2800 pkg_stat[i].e_start =
2801 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2802 thd_stat[j].cpu_id,
2803 thd_stat[j].thread_id,
2804 s->msr_energy.sioc);
2805 break;
2806 }
2807 }
2808 }
2809
2810 /* Sleep a short period while the other threads are working */
2811 usleep(MSR_ENERGY_THREAD_SLEEP_US);
2812
2813 /*
2814 * Retrieve all packages power plane energy counter
2815 * Calculate the delta of all packages
2816 */
2817 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2818 for (int j = 0; j < num_threads; j++) {
2819 /*
2820 * Use the first thread we found that ran on the CPU
2821 * of the package to read the packages energy counter
2822 */
2823 if (thd_stat[j].pkg_id == i) {
2824 pkg_stat[i].e_end =
2825 vmsr_read_msr(MSR_PKG_ENERGY_STATUS,
2826 thd_stat[j].cpu_id,
2827 thd_stat[j].thread_id,
2828 s->msr_energy.sioc);
2829 /*
2830 * Prevent the case we have migrate the VM
2831 * during the sleep period or any other cases
2832 * were energy counter might be lower after
2833 * the sleep period.
2834 */
2835 if (pkg_stat[i].e_end > pkg_stat[i].e_start) {
2836 pkg_stat[i].e_delta =
2837 pkg_stat[i].e_end - pkg_stat[i].e_start;
2838 } else {
2839 pkg_stat[i].e_delta = 0;
2840 }
2841 break;
2842 }
2843 }
2844 }
2845
2846 /* Delta of ticks spend by each thread between the sample */
2847 for (int i = 0; i < num_threads; i++) {
2848 vmsr_read_thread_stat(vmsr->pid,
2849 thd_stat[i].thread_id,
2850 &thd_stat[i].utime[1],
2851 &thd_stat[i].stime[1],
2852 &thd_stat[i].cpu_id);
2853
2854 if (vmsr->pid < 0) {
2855 /*
2856 * We don't count the dead thread
2857 * i.e threads that existed before the sleep
2858 * and not anymore
2859 */
2860 thd_stat[i].delta_ticks = 0;
2861 } else {
2862 vmsr_delta_ticks(thd_stat, i);
2863 }
2864 }
2865
2866 /*
2867 * Identify the vcpu threads
2868 * Calculate the number of vcpu per package
2869 */
2870 CPU_FOREACH(cpu) {
2871 for (int i = 0; i < num_threads; i++) {
2872 if (cpu->thread_id == thd_stat[i].thread_id) {
2873 thd_stat[i].is_vcpu = true;
2874 thd_stat[i].vcpu_id = cpu->cpu_index;
2875 pkg_stat[thd_stat[i].pkg_id].nb_vcpu++;
2876 thd_stat[i].acpi_id = kvm_arch_vcpu_id(cpu);
2877 break;
2878 }
2879 }
2880 }
2881
2882 /* Retrieve the virtual package number of each vCPU */
2883 for (int i = 0; i < vmsr->guest_cpu_list->len; i++) {
2884 for (int j = 0; j < num_threads; j++) {
2885 if ((thd_stat[j].acpi_id ==
2886 vmsr->guest_cpu_list->cpus[i].arch_id)
2887 && (thd_stat[j].is_vcpu == true)) {
2888 x86_topo_ids_from_apicid(thd_stat[j].acpi_id,
2889 &vmsr->guest_topo_info, &topo_ids);
2890 thd_stat[j].vpkg_id = topo_ids.pkg_id;
2891 }
2892 }
2893 }
2894
2895 /* Calculate the total energy of all non-vCPU thread */
2896 for (int i = 0; i < num_threads; i++) {
2897 if ((thd_stat[i].is_vcpu != true) &&
2898 (thd_stat[i].delta_ticks > 0)) {
2899 double temp;
2900 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2901 thd_stat[i].delta_ticks,
2902 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2903 pkg_stat[thd_stat[i].pkg_id].e_ratio
2904 += (uint64_t)lround(temp);
2905 }
2906 }
2907
2908 /* Calculate the ratio per non-vCPU thread of each package */
2909 for (int i = 0; i < vmsr->host_topo.maxpkgs; i++) {
2910 if (pkg_stat[i].nb_vcpu > 0) {
2911 pkg_stat[i].e_ratio = pkg_stat[i].e_ratio / pkg_stat[i].nb_vcpu;
2912 }
2913 }
2914
2915 /*
2916 * Calculate the energy for each Package:
2917 * Energy Package = sum of each vCPU energy that belongs to the package
2918 */
2919 for (int i = 0; i < num_threads; i++) {
2920 if ((thd_stat[i].is_vcpu == true) && \
2921 (thd_stat[i].delta_ticks > 0)) {
2922 double temp;
2923 temp = vmsr_get_ratio(pkg_stat[thd_stat[i].pkg_id].e_delta,
2924 thd_stat[i].delta_ticks,
2925 vmsr->host_topo.maxticks[thd_stat[i].pkg_id]);
2926 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2927 (uint64_t)lround(temp);
2928 vpkgs_energy_stat[thd_stat[i].vpkg_id] +=
2929 pkg_stat[thd_stat[i].pkg_id].e_ratio;
2930 }
2931 }
2932
2933 /*
2934 * Finally populate the vmsr register of each vCPU with the total
2935 * package value to emulate the real hardware where each CPU return the
2936 * value of the package it belongs.
2937 */
2938 for (int i = 0; i < num_threads; i++) {
2939 if ((thd_stat[i].is_vcpu == true) && \
2940 (thd_stat[i].delta_ticks > 0)) {
2941 vmsr->msr_value[thd_stat[i].vcpu_id] = \
2942 vpkgs_energy_stat[thd_stat[i].vpkg_id];
2943 }
2944 }
2945
2946 /* Freeing memory before zeroing the pointer */
2947 for (int i = 0; i < num_threads; i++) {
2948 g_free(thd_stat[i].utime);
2949 g_free(thd_stat[i].stime);
2950 }
2951 }
2952
2953 clean:
2954 rcu_unregister_thread();
2955 return NULL;
2956 }
2957
kvm_msr_energy_thread_init(KVMState * s,MachineState * ms)2958 static int kvm_msr_energy_thread_init(KVMState *s, MachineState *ms)
2959 {
2960 MachineClass *mc = MACHINE_GET_CLASS(ms);
2961 struct KVMMsrEnergy *r = &s->msr_energy;
2962
2963 /*
2964 * Sanity check
2965 * 1. Host cpu must be Intel cpu
2966 * 2. RAPL must be enabled on the Host
2967 */
2968 if (!is_host_cpu_intel()) {
2969 error_report("The RAPL feature can only be enabled on hosts "
2970 "with Intel CPU models");
2971 return -1;
2972 }
2973
2974 if (!is_rapl_enabled()) {
2975 return -1;
2976 }
2977
2978 /* Retrieve the virtual topology */
2979 vmsr_init_topo_info(&r->guest_topo_info, ms);
2980
2981 /* Retrieve the number of vcpu */
2982 r->guest_vcpus = ms->smp.cpus;
2983
2984 /* Retrieve the number of virtual sockets */
2985 r->guest_vsockets = ms->smp.sockets;
2986
2987 /* Allocate register memory (MSR_PKG_STATUS) for each vcpu */
2988 r->msr_value = g_new0(uint64_t, r->guest_vcpus);
2989
2990 /* Retrieve the CPUArchIDlist */
2991 r->guest_cpu_list = mc->possible_cpu_arch_ids(ms);
2992
2993 /* Max number of cpus on the Host */
2994 r->host_topo.maxcpus = vmsr_get_maxcpus();
2995 if (r->host_topo.maxcpus == 0) {
2996 error_report("host max cpus = 0");
2997 return -1;
2998 }
2999
3000 /* Max number of packages on the host */
3001 r->host_topo.maxpkgs = vmsr_get_max_physical_package(r->host_topo.maxcpus);
3002 if (r->host_topo.maxpkgs == 0) {
3003 error_report("host max pkgs = 0");
3004 return -1;
3005 }
3006
3007 /* Allocate memory for each package on the host */
3008 r->host_topo.pkg_cpu_count = g_new0(unsigned int, r->host_topo.maxpkgs);
3009 r->host_topo.maxticks = g_new0(unsigned int, r->host_topo.maxpkgs);
3010
3011 vmsr_count_cpus_per_package(r->host_topo.pkg_cpu_count,
3012 r->host_topo.maxpkgs);
3013 for (int i = 0; i < r->host_topo.maxpkgs; i++) {
3014 if (r->host_topo.pkg_cpu_count[i] == 0) {
3015 error_report("cpu per packages = 0 on package_%d", i);
3016 return -1;
3017 }
3018 }
3019
3020 /* Get QEMU PID*/
3021 r->pid = getpid();
3022
3023 /* Compute the socket path if necessary */
3024 if (s->msr_energy.socket_path == NULL) {
3025 s->msr_energy.socket_path = vmsr_compute_default_paths();
3026 }
3027
3028 /* Open socket with vmsr helper */
3029 s->msr_energy.sioc = vmsr_open_socket(s->msr_energy.socket_path);
3030
3031 if (s->msr_energy.sioc == NULL) {
3032 error_report("vmsr socket opening failed");
3033 return -1;
3034 }
3035
3036 /* Those MSR values should not change */
3037 r->msr_unit = vmsr_read_msr(MSR_RAPL_POWER_UNIT, 0, r->pid,
3038 s->msr_energy.sioc);
3039 r->msr_limit = vmsr_read_msr(MSR_PKG_POWER_LIMIT, 0, r->pid,
3040 s->msr_energy.sioc);
3041 r->msr_info = vmsr_read_msr(MSR_PKG_POWER_INFO, 0, r->pid,
3042 s->msr_energy.sioc);
3043 if (r->msr_unit == 0 || r->msr_limit == 0 || r->msr_info == 0) {
3044 error_report("can't read any virtual msr");
3045 return -1;
3046 }
3047
3048 qemu_thread_create(&r->msr_thr, "kvm-msr",
3049 kvm_msr_energy_thread,
3050 s, QEMU_THREAD_JOINABLE);
3051 return 0;
3052 }
3053
kvm_arch_get_default_type(MachineState * ms)3054 int kvm_arch_get_default_type(MachineState *ms)
3055 {
3056 return 0;
3057 }
3058
kvm_vm_enable_exception_payload(KVMState * s)3059 static int kvm_vm_enable_exception_payload(KVMState *s)
3060 {
3061 int ret = 0;
3062 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
3063 if (has_exception_payload) {
3064 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
3065 if (ret < 0) {
3066 error_report("kvm: Failed to enable exception payload cap: %s",
3067 strerror(-ret));
3068 }
3069 }
3070
3071 return ret;
3072 }
3073
kvm_vm_enable_triple_fault_event(KVMState * s)3074 static int kvm_vm_enable_triple_fault_event(KVMState *s)
3075 {
3076 int ret = 0;
3077 has_triple_fault_event = \
3078 kvm_check_extension(s,
3079 KVM_CAP_X86_TRIPLE_FAULT_EVENT);
3080 if (has_triple_fault_event) {
3081 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
3082 if (ret < 0) {
3083 error_report("kvm: Failed to enable triple fault event cap: %s",
3084 strerror(-ret));
3085 }
3086 }
3087 return ret;
3088 }
3089
kvm_vm_set_identity_map_addr(KVMState * s,uint64_t identity_base)3090 static int kvm_vm_set_identity_map_addr(KVMState *s, uint64_t identity_base)
3091 {
3092 return kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
3093 }
3094
kvm_vm_set_nr_mmu_pages(KVMState * s)3095 static int kvm_vm_set_nr_mmu_pages(KVMState *s)
3096 {
3097 uint64_t shadow_mem;
3098 int ret = 0;
3099 shadow_mem = object_property_get_int(OBJECT(s),
3100 "kvm-shadow-mem",
3101 &error_abort);
3102 if (shadow_mem != -1) {
3103 shadow_mem /= 4096;
3104 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
3105 }
3106 return ret;
3107 }
3108
kvm_vm_set_tss_addr(KVMState * s,uint64_t tss_base)3109 static int kvm_vm_set_tss_addr(KVMState *s, uint64_t tss_base)
3110 {
3111 return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, tss_base);
3112 }
3113
kvm_vm_enable_disable_exits(KVMState * s)3114 static int kvm_vm_enable_disable_exits(KVMState *s)
3115 {
3116 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
3117
3118 if (disable_exits) {
3119 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
3120 KVM_X86_DISABLE_EXITS_HLT |
3121 KVM_X86_DISABLE_EXITS_PAUSE |
3122 KVM_X86_DISABLE_EXITS_CSTATE);
3123 }
3124
3125 return kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
3126 disable_exits);
3127 }
3128
kvm_vm_enable_bus_lock_exit(KVMState * s)3129 static int kvm_vm_enable_bus_lock_exit(KVMState *s)
3130 {
3131 int ret = 0;
3132 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
3133 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
3134 error_report("kvm: bus lock detection unsupported");
3135 return -ENOTSUP;
3136 }
3137 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
3138 KVM_BUS_LOCK_DETECTION_EXIT);
3139 if (ret < 0) {
3140 error_report("kvm: Failed to enable bus lock detection cap: %s",
3141 strerror(-ret));
3142 }
3143
3144 return ret;
3145 }
3146
kvm_vm_enable_notify_vmexit(KVMState * s)3147 static int kvm_vm_enable_notify_vmexit(KVMState *s)
3148 {
3149 int ret = 0;
3150 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE) {
3151 uint64_t notify_window_flags =
3152 ((uint64_t)s->notify_window << 32) |
3153 KVM_X86_NOTIFY_VMEXIT_ENABLED |
3154 KVM_X86_NOTIFY_VMEXIT_USER;
3155 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
3156 notify_window_flags);
3157 if (ret < 0) {
3158 error_report("kvm: Failed to enable notify vmexit cap: %s",
3159 strerror(-ret));
3160 }
3161 }
3162 return ret;
3163 }
3164
kvm_vm_enable_userspace_msr(KVMState * s)3165 static int kvm_vm_enable_userspace_msr(KVMState *s)
3166 {
3167 int ret;
3168
3169 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_USER_SPACE_MSR, 0,
3170 KVM_MSR_EXIT_REASON_FILTER);
3171 if (ret < 0) {
3172 error_report("Could not enable user space MSRs: %s",
3173 strerror(-ret));
3174 exit(1);
3175 }
3176
3177 ret = kvm_filter_msr(s, MSR_CORE_THREAD_COUNT,
3178 kvm_rdmsr_core_thread_count, NULL);
3179 if (ret < 0) {
3180 error_report("Could not install MSR_CORE_THREAD_COUNT handler: %s",
3181 strerror(-ret));
3182 exit(1);
3183 }
3184
3185 return 0;
3186 }
3187
kvm_vm_enable_energy_msrs(KVMState * s)3188 static int kvm_vm_enable_energy_msrs(KVMState *s)
3189 {
3190 int ret;
3191
3192 if (s->msr_energy.enable == true) {
3193 ret = kvm_filter_msr(s, MSR_RAPL_POWER_UNIT,
3194 kvm_rdmsr_rapl_power_unit, NULL);
3195 if (ret < 0) {
3196 error_report("Could not install MSR_RAPL_POWER_UNIT handler: %s",
3197 strerror(-ret));
3198 return ret;
3199 }
3200
3201 ret = kvm_filter_msr(s, MSR_PKG_POWER_LIMIT,
3202 kvm_rdmsr_pkg_power_limit, NULL);
3203 if (ret < 0) {
3204 error_report("Could not install MSR_PKG_POWER_LIMIT handler: %s",
3205 strerror(-ret));
3206 return ret;
3207 }
3208
3209 ret = kvm_filter_msr(s, MSR_PKG_POWER_INFO,
3210 kvm_rdmsr_pkg_power_info, NULL);
3211 if (ret < 0) {
3212 error_report("Could not install MSR_PKG_POWER_INFO handler: %s",
3213 strerror(-ret));
3214 return ret;
3215 }
3216 ret = kvm_filter_msr(s, MSR_PKG_ENERGY_STATUS,
3217 kvm_rdmsr_pkg_energy_status, NULL);
3218 if (ret < 0) {
3219 error_report("Could not install MSR_PKG_ENERGY_STATUS handler: %s",
3220 strerror(-ret));
3221 return ret;
3222 }
3223 }
3224 return 0;
3225 }
3226
kvm_arch_init(MachineState * ms,KVMState * s)3227 int kvm_arch_init(MachineState *ms, KVMState *s)
3228 {
3229 int ret;
3230 struct utsname utsname;
3231 Error *local_err = NULL;
3232
3233 /*
3234 * Initialize confidential guest (SEV/TDX) context, if required
3235 */
3236 if (ms->cgs) {
3237 ret = confidential_guest_kvm_init(ms->cgs, &local_err);
3238 if (ret < 0) {
3239 error_report_err(local_err);
3240 return ret;
3241 }
3242 }
3243
3244 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
3245 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
3246
3247 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
3248
3249 ret = kvm_vm_enable_exception_payload(s);
3250 if (ret < 0) {
3251 return ret;
3252 }
3253
3254 ret = kvm_vm_enable_triple_fault_event(s);
3255 if (ret < 0) {
3256 return ret;
3257 }
3258
3259 if (s->xen_version) {
3260 #ifdef CONFIG_XEN_EMU
3261 if (!object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE)) {
3262 error_report("kvm: Xen support only available in PC machine");
3263 return -ENOTSUP;
3264 }
3265 /* hyperv_enabled() doesn't work yet. */
3266 uint32_t msr = XEN_HYPERCALL_MSR;
3267 ret = kvm_xen_init(s, msr);
3268 if (ret < 0) {
3269 return ret;
3270 }
3271 #else
3272 error_report("kvm: Xen support not enabled in qemu");
3273 return -ENOTSUP;
3274 #endif
3275 }
3276
3277 ret = kvm_get_supported_msrs(s);
3278 if (ret < 0) {
3279 return ret;
3280 }
3281
3282 ret = kvm_get_supported_feature_msrs(s);
3283 if (ret < 0) {
3284 return ret;
3285 }
3286
3287 uname(&utsname);
3288 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
3289
3290 ret = kvm_vm_set_identity_map_addr(s, KVM_IDENTITY_BASE);
3291 if (ret < 0) {
3292 return ret;
3293 }
3294
3295 /* Set TSS base one page after EPT identity map. */
3296 ret = kvm_vm_set_tss_addr(s, KVM_IDENTITY_BASE + 0x1000);
3297 if (ret < 0) {
3298 return ret;
3299 }
3300
3301 /* Tell fw_cfg to notify the BIOS to reserve the range. */
3302 e820_add_entry(KVM_IDENTITY_BASE, 0x4000, E820_RESERVED);
3303
3304 ret = kvm_vm_set_nr_mmu_pages(s);
3305 if (ret < 0) {
3306 return ret;
3307 }
3308
3309 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
3310 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
3311 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
3312 smram_machine_done.notify = register_smram_listener;
3313 qemu_add_machine_init_done_notifier(&smram_machine_done);
3314 }
3315
3316 if (enable_cpu_pm) {
3317 ret = kvm_vm_enable_disable_exits(s);
3318 if (ret < 0) {
3319 error_report("kvm: guest stopping CPU not supported: %s",
3320 strerror(-ret));
3321 return ret;
3322 }
3323 }
3324
3325 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
3326 X86MachineState *x86ms = X86_MACHINE(ms);
3327
3328 if (x86ms->bus_lock_ratelimit > 0) {
3329 ret = kvm_vm_enable_bus_lock_exit(s);
3330 if (ret < 0) {
3331 return ret;
3332 }
3333 ratelimit_init(&bus_lock_ratelimit_ctrl);
3334 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
3335 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
3336 }
3337 }
3338
3339 if (kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
3340 ret = kvm_vm_enable_notify_vmexit(s);
3341 if (ret < 0) {
3342 return ret;
3343 }
3344 }
3345
3346 if (kvm_vm_check_extension(s, KVM_CAP_X86_USER_SPACE_MSR)) {
3347 ret = kvm_vm_enable_userspace_msr(s);
3348 if (ret < 0) {
3349 return ret;
3350 }
3351
3352 if (s->msr_energy.enable == true) {
3353 ret = kvm_vm_enable_energy_msrs(s);
3354 if (ret < 0) {
3355 return ret;
3356 }
3357
3358 ret = kvm_msr_energy_thread_init(s, ms);
3359 if (ret < 0) {
3360 error_report("kvm : error RAPL feature requirement not met");
3361 return ret;
3362 }
3363 }
3364 }
3365
3366 return 0;
3367 }
3368
set_v8086_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3369 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3370 {
3371 lhs->selector = rhs->selector;
3372 lhs->base = rhs->base;
3373 lhs->limit = rhs->limit;
3374 lhs->type = 3;
3375 lhs->present = 1;
3376 lhs->dpl = 3;
3377 lhs->db = 0;
3378 lhs->s = 1;
3379 lhs->l = 0;
3380 lhs->g = 0;
3381 lhs->avl = 0;
3382 lhs->unusable = 0;
3383 }
3384
set_seg(struct kvm_segment * lhs,const SegmentCache * rhs)3385 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
3386 {
3387 unsigned flags = rhs->flags;
3388 lhs->selector = rhs->selector;
3389 lhs->base = rhs->base;
3390 lhs->limit = rhs->limit;
3391 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
3392 lhs->present = (flags & DESC_P_MASK) != 0;
3393 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
3394 lhs->db = (flags >> DESC_B_SHIFT) & 1;
3395 lhs->s = (flags & DESC_S_MASK) != 0;
3396 lhs->l = (flags >> DESC_L_SHIFT) & 1;
3397 lhs->g = (flags & DESC_G_MASK) != 0;
3398 lhs->avl = (flags & DESC_AVL_MASK) != 0;
3399 lhs->unusable = !lhs->present;
3400 lhs->padding = 0;
3401 }
3402
get_seg(SegmentCache * lhs,const struct kvm_segment * rhs)3403 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
3404 {
3405 lhs->selector = rhs->selector;
3406 lhs->base = rhs->base;
3407 lhs->limit = rhs->limit;
3408 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
3409 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
3410 (rhs->dpl << DESC_DPL_SHIFT) |
3411 (rhs->db << DESC_B_SHIFT) |
3412 (rhs->s * DESC_S_MASK) |
3413 (rhs->l << DESC_L_SHIFT) |
3414 (rhs->g * DESC_G_MASK) |
3415 (rhs->avl * DESC_AVL_MASK);
3416 }
3417
kvm_getput_reg(__u64 * kvm_reg,target_ulong * qemu_reg,int set)3418 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
3419 {
3420 if (set) {
3421 *kvm_reg = *qemu_reg;
3422 } else {
3423 *qemu_reg = *kvm_reg;
3424 }
3425 }
3426
kvm_getput_regs(X86CPU * cpu,int set)3427 static int kvm_getput_regs(X86CPU *cpu, int set)
3428 {
3429 CPUX86State *env = &cpu->env;
3430 struct kvm_regs regs;
3431 int ret = 0;
3432
3433 if (!set) {
3434 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s);
3435 if (ret < 0) {
3436 return ret;
3437 }
3438 }
3439
3440 kvm_getput_reg(®s.rax, &env->regs[R_EAX], set);
3441 kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set);
3442 kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set);
3443 kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set);
3444 kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set);
3445 kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set);
3446 kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set);
3447 kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set);
3448 #ifdef TARGET_X86_64
3449 kvm_getput_reg(®s.r8, &env->regs[8], set);
3450 kvm_getput_reg(®s.r9, &env->regs[9], set);
3451 kvm_getput_reg(®s.r10, &env->regs[10], set);
3452 kvm_getput_reg(®s.r11, &env->regs[11], set);
3453 kvm_getput_reg(®s.r12, &env->regs[12], set);
3454 kvm_getput_reg(®s.r13, &env->regs[13], set);
3455 kvm_getput_reg(®s.r14, &env->regs[14], set);
3456 kvm_getput_reg(®s.r15, &env->regs[15], set);
3457 #endif
3458
3459 kvm_getput_reg(®s.rflags, &env->eflags, set);
3460 kvm_getput_reg(®s.rip, &env->eip, set);
3461
3462 if (set) {
3463 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s);
3464 }
3465
3466 return ret;
3467 }
3468
kvm_put_xsave(X86CPU * cpu)3469 static int kvm_put_xsave(X86CPU *cpu)
3470 {
3471 CPUX86State *env = &cpu->env;
3472 void *xsave = env->xsave_buf;
3473
3474 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
3475
3476 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
3477 }
3478
kvm_put_xcrs(X86CPU * cpu)3479 static int kvm_put_xcrs(X86CPU *cpu)
3480 {
3481 CPUX86State *env = &cpu->env;
3482 struct kvm_xcrs xcrs = {};
3483
3484 if (!has_xcrs) {
3485 return 0;
3486 }
3487
3488 xcrs.nr_xcrs = 1;
3489 xcrs.flags = 0;
3490 xcrs.xcrs[0].xcr = 0;
3491 xcrs.xcrs[0].value = env->xcr0;
3492 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
3493 }
3494
kvm_put_sregs(X86CPU * cpu)3495 static int kvm_put_sregs(X86CPU *cpu)
3496 {
3497 CPUX86State *env = &cpu->env;
3498 struct kvm_sregs sregs;
3499
3500 /*
3501 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
3502 * always followed by KVM_SET_VCPU_EVENTS.
3503 */
3504 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
3505
3506 if ((env->eflags & VM_MASK)) {
3507 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3508 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3509 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3510 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3511 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3512 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3513 } else {
3514 set_seg(&sregs.cs, &env->segs[R_CS]);
3515 set_seg(&sregs.ds, &env->segs[R_DS]);
3516 set_seg(&sregs.es, &env->segs[R_ES]);
3517 set_seg(&sregs.fs, &env->segs[R_FS]);
3518 set_seg(&sregs.gs, &env->segs[R_GS]);
3519 set_seg(&sregs.ss, &env->segs[R_SS]);
3520 }
3521
3522 set_seg(&sregs.tr, &env->tr);
3523 set_seg(&sregs.ldt, &env->ldt);
3524
3525 sregs.idt.limit = env->idt.limit;
3526 sregs.idt.base = env->idt.base;
3527 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3528 sregs.gdt.limit = env->gdt.limit;
3529 sregs.gdt.base = env->gdt.base;
3530 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3531
3532 sregs.cr0 = env->cr[0];
3533 sregs.cr2 = env->cr[2];
3534 sregs.cr3 = env->cr[3];
3535 sregs.cr4 = env->cr[4];
3536
3537 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3538 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3539
3540 sregs.efer = env->efer;
3541
3542 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
3543 }
3544
kvm_put_sregs2(X86CPU * cpu)3545 static int kvm_put_sregs2(X86CPU *cpu)
3546 {
3547 CPUX86State *env = &cpu->env;
3548 struct kvm_sregs2 sregs;
3549 int i;
3550
3551 sregs.flags = 0;
3552
3553 if ((env->eflags & VM_MASK)) {
3554 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
3555 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
3556 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
3557 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
3558 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
3559 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
3560 } else {
3561 set_seg(&sregs.cs, &env->segs[R_CS]);
3562 set_seg(&sregs.ds, &env->segs[R_DS]);
3563 set_seg(&sregs.es, &env->segs[R_ES]);
3564 set_seg(&sregs.fs, &env->segs[R_FS]);
3565 set_seg(&sregs.gs, &env->segs[R_GS]);
3566 set_seg(&sregs.ss, &env->segs[R_SS]);
3567 }
3568
3569 set_seg(&sregs.tr, &env->tr);
3570 set_seg(&sregs.ldt, &env->ldt);
3571
3572 sregs.idt.limit = env->idt.limit;
3573 sregs.idt.base = env->idt.base;
3574 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
3575 sregs.gdt.limit = env->gdt.limit;
3576 sregs.gdt.base = env->gdt.base;
3577 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
3578
3579 sregs.cr0 = env->cr[0];
3580 sregs.cr2 = env->cr[2];
3581 sregs.cr3 = env->cr[3];
3582 sregs.cr4 = env->cr[4];
3583
3584 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
3585 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
3586
3587 sregs.efer = env->efer;
3588
3589 if (env->pdptrs_valid) {
3590 for (i = 0; i < 4; i++) {
3591 sregs.pdptrs[i] = env->pdptrs[i];
3592 }
3593 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
3594 }
3595
3596 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
3597 }
3598
3599
kvm_msr_buf_reset(X86CPU * cpu)3600 static void kvm_msr_buf_reset(X86CPU *cpu)
3601 {
3602 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
3603 }
3604
kvm_msr_entry_add(X86CPU * cpu,uint32_t index,uint64_t value)3605 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
3606 {
3607 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
3608 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
3609 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
3610
3611 assert((void *)(entry + 1) <= limit);
3612
3613 entry->index = index;
3614 entry->reserved = 0;
3615 entry->data = value;
3616 msrs->nmsrs++;
3617 }
3618
kvm_put_one_msr(X86CPU * cpu,int index,uint64_t value)3619 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
3620 {
3621 kvm_msr_buf_reset(cpu);
3622 kvm_msr_entry_add(cpu, index, value);
3623
3624 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3625 }
3626
kvm_get_one_msr(X86CPU * cpu,int index,uint64_t * value)3627 static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
3628 {
3629 int ret;
3630 struct {
3631 struct kvm_msrs info;
3632 struct kvm_msr_entry entries[1];
3633 } msr_data = {
3634 .info.nmsrs = 1,
3635 .entries[0].index = index,
3636 };
3637
3638 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
3639 if (ret < 0) {
3640 return ret;
3641 }
3642 assert(ret == 1);
3643 *value = msr_data.entries[0].data;
3644 return ret;
3645 }
kvm_put_apicbase(X86CPU * cpu,uint64_t value)3646 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
3647 {
3648 int ret;
3649
3650 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
3651 assert(ret == 1);
3652 }
3653
kvm_put_tscdeadline_msr(X86CPU * cpu)3654 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
3655 {
3656 CPUX86State *env = &cpu->env;
3657 int ret;
3658
3659 if (!has_msr_tsc_deadline) {
3660 return 0;
3661 }
3662
3663 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
3664 if (ret < 0) {
3665 return ret;
3666 }
3667
3668 assert(ret == 1);
3669 return 0;
3670 }
3671
3672 /*
3673 * Provide a separate write service for the feature control MSR in order to
3674 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
3675 * before writing any other state because forcibly leaving nested mode
3676 * invalidates the VCPU state.
3677 */
kvm_put_msr_feature_control(X86CPU * cpu)3678 static int kvm_put_msr_feature_control(X86CPU *cpu)
3679 {
3680 int ret;
3681
3682 if (!has_msr_feature_control) {
3683 return 0;
3684 }
3685
3686 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
3687 cpu->env.msr_ia32_feature_control);
3688 if (ret < 0) {
3689 return ret;
3690 }
3691
3692 assert(ret == 1);
3693 return 0;
3694 }
3695
make_vmx_msr_value(uint32_t index,uint32_t features)3696 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
3697 {
3698 uint32_t default1, can_be_one, can_be_zero;
3699 uint32_t must_be_one;
3700
3701 switch (index) {
3702 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3703 default1 = 0x00000016;
3704 break;
3705 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3706 default1 = 0x0401e172;
3707 break;
3708 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3709 default1 = 0x000011ff;
3710 break;
3711 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3712 default1 = 0x00036dff;
3713 break;
3714 case MSR_IA32_VMX_PROCBASED_CTLS2:
3715 default1 = 0;
3716 break;
3717 default:
3718 abort();
3719 }
3720
3721 /* If a feature bit is set, the control can be either set or clear.
3722 * Otherwise the value is limited to either 0 or 1 by default1.
3723 */
3724 can_be_one = features | default1;
3725 can_be_zero = features | ~default1;
3726 must_be_one = ~can_be_zero;
3727
3728 /*
3729 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3730 * Bit 32:63 -> 1 if the control bit can be one.
3731 */
3732 return must_be_one | (((uint64_t)can_be_one) << 32);
3733 }
3734
kvm_msr_entry_add_vmx(X86CPU * cpu,FeatureWordArray f)3735 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3736 {
3737 uint64_t kvm_vmx_basic =
3738 kvm_arch_get_supported_msr_feature(kvm_state,
3739 MSR_IA32_VMX_BASIC);
3740
3741 if (!kvm_vmx_basic) {
3742 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3743 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3744 */
3745 return;
3746 }
3747
3748 uint64_t kvm_vmx_misc =
3749 kvm_arch_get_supported_msr_feature(kvm_state,
3750 MSR_IA32_VMX_MISC);
3751 uint64_t kvm_vmx_ept_vpid =
3752 kvm_arch_get_supported_msr_feature(kvm_state,
3753 MSR_IA32_VMX_EPT_VPID_CAP);
3754
3755 /*
3756 * If the guest is 64-bit, a value of 1 is allowed for the host address
3757 * space size vmexit control.
3758 */
3759 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3760 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3761
3762 /*
3763 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3764 * not change them for backwards compatibility.
3765 */
3766 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3767 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3768 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3769 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3770
3771 /*
3772 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3773 * change in the future but are always zero for now, clear them to be
3774 * future proof. Bits 32-63 in theory could change, though KVM does
3775 * not support dual-monitor treatment and probably never will; mask
3776 * them out as well.
3777 */
3778 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3779 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3780 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3781
3782 /*
3783 * EPT memory types should not change either, so we do not bother
3784 * adding features for them.
3785 */
3786 uint64_t fixed_vmx_ept_mask =
3787 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3788 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3789 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3790
3791 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3792 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3793 f[FEAT_VMX_PROCBASED_CTLS]));
3794 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3795 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3796 f[FEAT_VMX_PINBASED_CTLS]));
3797 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3798 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3799 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3800 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3801 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3802 f[FEAT_VMX_ENTRY_CTLS]));
3803 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3804 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3805 f[FEAT_VMX_SECONDARY_CTLS]));
3806 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3807 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3808 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3809 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3810 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3811 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3812 if (has_msr_vmx_vmfunc) {
3813 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3814 }
3815
3816 /*
3817 * Just to be safe, write these with constant values. The CRn_FIXED1
3818 * MSRs are generated by KVM based on the vCPU's CPUID.
3819 */
3820 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3821 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3822 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3823 CR4_VMXE_MASK);
3824
3825 if (f[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3826 /* FRED injected-event data (0x2052). */
3827 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x52);
3828 } else if (f[FEAT_VMX_EXIT_CTLS] &
3829 VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS) {
3830 /* Secondary VM-exit controls (0x2044). */
3831 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x44);
3832 } else if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3833 /* TSC multiplier (0x2032). */
3834 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3835 } else {
3836 /* Preemption timer (0x482E). */
3837 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3838 }
3839 }
3840
kvm_msr_entry_add_perf(X86CPU * cpu,FeatureWordArray f)3841 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3842 {
3843 uint64_t kvm_perf_cap =
3844 kvm_arch_get_supported_msr_feature(kvm_state,
3845 MSR_IA32_PERF_CAPABILITIES);
3846
3847 if (kvm_perf_cap) {
3848 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3849 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3850 }
3851 }
3852
kvm_buf_set_msrs(X86CPU * cpu)3853 static int kvm_buf_set_msrs(X86CPU *cpu)
3854 {
3855 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3856 if (ret < 0) {
3857 return ret;
3858 }
3859
3860 if (ret < cpu->kvm_msr_buf->nmsrs) {
3861 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3862 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3863 (uint32_t)e->index, (uint64_t)e->data);
3864 }
3865
3866 assert(ret == cpu->kvm_msr_buf->nmsrs);
3867 return 0;
3868 }
3869
kvm_init_msrs(X86CPU * cpu)3870 static void kvm_init_msrs(X86CPU *cpu)
3871 {
3872 CPUX86State *env = &cpu->env;
3873
3874 kvm_msr_buf_reset(cpu);
3875
3876 if (!is_tdx_vm()) {
3877 if (has_msr_arch_capabs) {
3878 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3879 env->features[FEAT_ARCH_CAPABILITIES]);
3880 }
3881
3882 if (has_msr_core_capabs) {
3883 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3884 env->features[FEAT_CORE_CAPABILITY]);
3885 }
3886
3887 if (has_msr_perf_capabs && cpu->enable_pmu) {
3888 kvm_msr_entry_add_perf(cpu, env->features);
3889 }
3890
3891 /*
3892 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3893 * all kernels with MSR features should have them.
3894 */
3895 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3896 kvm_msr_entry_add_vmx(cpu, env->features);
3897 }
3898 }
3899
3900 if (has_msr_ucode_rev) {
3901 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3902 }
3903 assert(kvm_buf_set_msrs(cpu) == 0);
3904 }
3905
kvm_put_msrs(X86CPU * cpu,int level)3906 static int kvm_put_msrs(X86CPU *cpu, int level)
3907 {
3908 CPUX86State *env = &cpu->env;
3909 int i;
3910
3911 kvm_msr_buf_reset(cpu);
3912
3913 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3914 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3915 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3916 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
3917 if (has_msr_star) {
3918 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
3919 }
3920 if (has_msr_hsave_pa) {
3921 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
3922 }
3923 if (has_msr_tsc_aux) {
3924 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
3925 }
3926 if (has_msr_tsc_adjust) {
3927 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
3928 }
3929 if (has_msr_misc_enable) {
3930 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
3931 env->msr_ia32_misc_enable);
3932 }
3933 if (has_msr_smbase) {
3934 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
3935 }
3936 if (has_msr_smi_count) {
3937 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3938 }
3939 if (has_msr_pkrs) {
3940 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3941 }
3942 if (has_msr_bndcfgs) {
3943 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
3944 }
3945 if (has_msr_xss) {
3946 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
3947 }
3948 if (has_msr_umwait) {
3949 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3950 }
3951 if (has_msr_spec_ctrl) {
3952 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3953 }
3954 if (has_tsc_scale_msr) {
3955 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3956 }
3957
3958 if (has_msr_tsx_ctrl) {
3959 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3960 }
3961 if (has_msr_virt_ssbd) {
3962 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3963 }
3964 if (has_msr_hwcr) {
3965 kvm_msr_entry_add(cpu, MSR_K7_HWCR, env->msr_hwcr);
3966 }
3967
3968 #ifdef TARGET_X86_64
3969 if (lm_capable_kernel) {
3970 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3971 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3972 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3973 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
3974 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
3975 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, env->fred_rsp0);
3976 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, env->fred_rsp1);
3977 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, env->fred_rsp2);
3978 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, env->fred_rsp3);
3979 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, env->fred_stklvls);
3980 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, env->fred_ssp1);
3981 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2);
3982 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3);
3983 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config);
3984 }
3985 }
3986 #endif
3987
3988 /*
3989 * The following MSRs have side effects on the guest or are too heavy
3990 * for normal writeback. Limit them to reset or full state updates.
3991 */
3992 if (level >= KVM_PUT_RESET_STATE) {
3993 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3994 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
3995 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3996 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
3997 }
3998 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
3999 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
4000 }
4001 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4002 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
4003 }
4004 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4005 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
4006 }
4007 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4008 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
4009 }
4010
4011 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4012 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
4013 }
4014
4015 if (has_architectural_pmu_version > 0) {
4016 if (has_architectural_pmu_version > 1) {
4017 /* Stop the counter. */
4018 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4019 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4020 }
4021
4022 /* Set the counter values. */
4023 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4024 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
4025 env->msr_fixed_counters[i]);
4026 }
4027 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4028 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
4029 env->msr_gp_counters[i]);
4030 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
4031 env->msr_gp_evtsel[i]);
4032 }
4033 if (has_architectural_pmu_version > 1) {
4034 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
4035 env->msr_global_status);
4036 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
4037 env->msr_global_ovf_ctrl);
4038
4039 /* Now start the PMU. */
4040 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
4041 env->msr_fixed_ctr_ctrl);
4042 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
4043 env->msr_global_ctrl);
4044 }
4045 }
4046 /*
4047 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
4048 * only sync them to KVM on the first cpu
4049 */
4050 if (current_cpu == first_cpu) {
4051 if (has_msr_hv_hypercall) {
4052 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
4053 env->msr_hv_guest_os_id);
4054 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
4055 env->msr_hv_hypercall);
4056 }
4057 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4058 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
4059 env->msr_hv_tsc);
4060 }
4061 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4062 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
4063 env->msr_hv_reenlightenment_control);
4064 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
4065 env->msr_hv_tsc_emulation_control);
4066 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
4067 env->msr_hv_tsc_emulation_status);
4068 }
4069 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
4070 has_msr_hv_syndbg_options) {
4071 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
4072 hyperv_syndbg_query_options());
4073 }
4074 }
4075 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4076 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
4077 env->msr_hv_vapic);
4078 }
4079 if (has_msr_hv_crash) {
4080 int j;
4081
4082 for (j = 0; j < HV_CRASH_PARAMS; j++)
4083 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
4084 env->msr_hv_crash_params[j]);
4085
4086 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
4087 }
4088 if (has_msr_hv_runtime) {
4089 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
4090 }
4091 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
4092 && hv_vpindex_settable) {
4093 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
4094 hyperv_vp_index(CPU(cpu)));
4095 }
4096 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4097 int j;
4098
4099 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
4100
4101 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
4102 env->msr_hv_synic_control);
4103 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
4104 env->msr_hv_synic_evt_page);
4105 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
4106 env->msr_hv_synic_msg_page);
4107
4108 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
4109 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
4110 env->msr_hv_synic_sint[j]);
4111 }
4112 }
4113 if (has_msr_hv_stimer) {
4114 int j;
4115
4116 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
4117 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
4118 env->msr_hv_stimer_config[j]);
4119 }
4120
4121 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
4122 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
4123 env->msr_hv_stimer_count[j]);
4124 }
4125 }
4126 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4127 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
4128
4129 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
4130 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
4131 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
4132 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
4133 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
4134 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
4135 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
4136 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
4137 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
4138 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
4139 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
4140 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
4141 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4142 /* The CPU GPs if we write to a bit above the physical limit of
4143 * the host CPU (and KVM emulates that)
4144 */
4145 uint64_t mask = env->mtrr_var[i].mask;
4146 mask &= phys_mask;
4147
4148 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
4149 env->mtrr_var[i].base);
4150 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
4151 }
4152 }
4153 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4154 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
4155 0x14, 1, R_EAX) & 0x7;
4156
4157 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
4158 env->msr_rtit_ctrl);
4159 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
4160 env->msr_rtit_status);
4161 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
4162 env->msr_rtit_output_base);
4163 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
4164 env->msr_rtit_output_mask);
4165 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
4166 env->msr_rtit_cr3_match);
4167 for (i = 0; i < addr_num; i++) {
4168 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
4169 env->msr_rtit_addrs[i]);
4170 }
4171 }
4172
4173 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4174 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
4175 env->msr_ia32_sgxlepubkeyhash[0]);
4176 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
4177 env->msr_ia32_sgxlepubkeyhash[1]);
4178 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
4179 env->msr_ia32_sgxlepubkeyhash[2]);
4180 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
4181 env->msr_ia32_sgxlepubkeyhash[3]);
4182 }
4183
4184 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4185 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
4186 env->msr_xfd);
4187 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
4188 env->msr_xfd_err);
4189 }
4190
4191 if (kvm_enabled() && cpu->enable_pmu &&
4192 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4193 uint64_t depth;
4194 int ret;
4195
4196 /*
4197 * Only migrate Arch LBR states when the host Arch LBR depth
4198 * equals that of source guest's, this is to avoid mismatch
4199 * of guest/host config for the msr hence avoid unexpected
4200 * misbehavior.
4201 */
4202 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4203
4204 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
4205 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
4206 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
4207
4208 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4209 if (!env->lbr_records[i].from) {
4210 continue;
4211 }
4212 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
4213 env->lbr_records[i].from);
4214 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
4215 env->lbr_records[i].to);
4216 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
4217 env->lbr_records[i].info);
4218 }
4219 }
4220 }
4221
4222 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
4223 * kvm_put_msr_feature_control. */
4224 }
4225
4226 if (env->mcg_cap) {
4227 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
4228 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
4229 if (has_msr_mcg_ext_ctl) {
4230 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
4231 }
4232 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4233 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
4234 }
4235 }
4236
4237 return kvm_buf_set_msrs(cpu);
4238 }
4239
4240
kvm_get_xsave(X86CPU * cpu)4241 static int kvm_get_xsave(X86CPU *cpu)
4242 {
4243 CPUX86State *env = &cpu->env;
4244 void *xsave = env->xsave_buf;
4245 unsigned long type;
4246 int ret;
4247
4248 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
4249 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
4250 if (ret < 0) {
4251 return ret;
4252 }
4253 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
4254
4255 return 0;
4256 }
4257
kvm_get_xcrs(X86CPU * cpu)4258 static int kvm_get_xcrs(X86CPU *cpu)
4259 {
4260 CPUX86State *env = &cpu->env;
4261 int i, ret;
4262 struct kvm_xcrs xcrs;
4263
4264 if (!has_xcrs) {
4265 return 0;
4266 }
4267
4268 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
4269 if (ret < 0) {
4270 return ret;
4271 }
4272
4273 for (i = 0; i < xcrs.nr_xcrs; i++) {
4274 /* Only support xcr0 now */
4275 if (xcrs.xcrs[i].xcr == 0) {
4276 env->xcr0 = xcrs.xcrs[i].value;
4277 break;
4278 }
4279 }
4280 return 0;
4281 }
4282
kvm_get_sregs(X86CPU * cpu)4283 static int kvm_get_sregs(X86CPU *cpu)
4284 {
4285 CPUX86State *env = &cpu->env;
4286 struct kvm_sregs sregs;
4287 int ret;
4288
4289 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
4290 if (ret < 0) {
4291 return ret;
4292 }
4293
4294 /*
4295 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
4296 * always preceded by KVM_GET_VCPU_EVENTS.
4297 */
4298
4299 get_seg(&env->segs[R_CS], &sregs.cs);
4300 get_seg(&env->segs[R_DS], &sregs.ds);
4301 get_seg(&env->segs[R_ES], &sregs.es);
4302 get_seg(&env->segs[R_FS], &sregs.fs);
4303 get_seg(&env->segs[R_GS], &sregs.gs);
4304 get_seg(&env->segs[R_SS], &sregs.ss);
4305
4306 get_seg(&env->tr, &sregs.tr);
4307 get_seg(&env->ldt, &sregs.ldt);
4308
4309 env->idt.limit = sregs.idt.limit;
4310 env->idt.base = sregs.idt.base;
4311 env->gdt.limit = sregs.gdt.limit;
4312 env->gdt.base = sregs.gdt.base;
4313
4314 env->cr[0] = sregs.cr0;
4315 env->cr[2] = sregs.cr2;
4316 env->cr[3] = sregs.cr3;
4317 env->cr[4] = sregs.cr4;
4318
4319 env->efer = sregs.efer;
4320 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4321 env->cr[0] & CR0_PG_MASK) {
4322 env->efer |= MSR_EFER_LMA;
4323 }
4324
4325 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4326 x86_update_hflags(env);
4327
4328 return 0;
4329 }
4330
kvm_get_sregs2(X86CPU * cpu)4331 static int kvm_get_sregs2(X86CPU *cpu)
4332 {
4333 CPUX86State *env = &cpu->env;
4334 struct kvm_sregs2 sregs;
4335 int i, ret;
4336
4337 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
4338 if (ret < 0) {
4339 return ret;
4340 }
4341
4342 get_seg(&env->segs[R_CS], &sregs.cs);
4343 get_seg(&env->segs[R_DS], &sregs.ds);
4344 get_seg(&env->segs[R_ES], &sregs.es);
4345 get_seg(&env->segs[R_FS], &sregs.fs);
4346 get_seg(&env->segs[R_GS], &sregs.gs);
4347 get_seg(&env->segs[R_SS], &sregs.ss);
4348
4349 get_seg(&env->tr, &sregs.tr);
4350 get_seg(&env->ldt, &sregs.ldt);
4351
4352 env->idt.limit = sregs.idt.limit;
4353 env->idt.base = sregs.idt.base;
4354 env->gdt.limit = sregs.gdt.limit;
4355 env->gdt.base = sregs.gdt.base;
4356
4357 env->cr[0] = sregs.cr0;
4358 env->cr[2] = sregs.cr2;
4359 env->cr[3] = sregs.cr3;
4360 env->cr[4] = sregs.cr4;
4361
4362 env->efer = sregs.efer;
4363 if (sev_es_enabled() && env->efer & MSR_EFER_LME &&
4364 env->cr[0] & CR0_PG_MASK) {
4365 env->efer |= MSR_EFER_LMA;
4366 }
4367
4368 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
4369
4370 if (env->pdptrs_valid) {
4371 for (i = 0; i < 4; i++) {
4372 env->pdptrs[i] = sregs.pdptrs[i];
4373 }
4374 }
4375
4376 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
4377 x86_update_hflags(env);
4378
4379 return 0;
4380 }
4381
kvm_get_msrs(X86CPU * cpu)4382 static int kvm_get_msrs(X86CPU *cpu)
4383 {
4384 CPUX86State *env = &cpu->env;
4385 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
4386 int ret, i;
4387 uint64_t mtrr_top_bits;
4388
4389 kvm_msr_buf_reset(cpu);
4390
4391 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
4392 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
4393 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
4394 kvm_msr_entry_add(cpu, MSR_PAT, 0);
4395 if (has_msr_star) {
4396 kvm_msr_entry_add(cpu, MSR_STAR, 0);
4397 }
4398 if (has_msr_hsave_pa) {
4399 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
4400 }
4401 if (has_msr_tsc_aux) {
4402 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
4403 }
4404 if (has_msr_tsc_adjust) {
4405 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
4406 }
4407 if (has_msr_tsc_deadline) {
4408 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
4409 }
4410 if (has_msr_misc_enable) {
4411 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
4412 }
4413 if (has_msr_smbase) {
4414 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
4415 }
4416 if (has_msr_smi_count) {
4417 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
4418 }
4419 if (has_msr_feature_control) {
4420 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
4421 }
4422 if (has_msr_pkrs) {
4423 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
4424 }
4425 if (has_msr_bndcfgs) {
4426 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
4427 }
4428 if (has_msr_xss) {
4429 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
4430 }
4431 if (has_msr_umwait) {
4432 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
4433 }
4434 if (has_msr_spec_ctrl) {
4435 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
4436 }
4437 if (has_tsc_scale_msr) {
4438 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
4439 }
4440
4441 if (has_msr_tsx_ctrl) {
4442 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
4443 }
4444 if (has_msr_virt_ssbd) {
4445 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
4446 }
4447 if (!env->tsc_valid) {
4448 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
4449 env->tsc_valid = !runstate_is_running();
4450 }
4451 if (has_msr_hwcr) {
4452 kvm_msr_entry_add(cpu, MSR_K7_HWCR, 0);
4453 }
4454
4455 #ifdef TARGET_X86_64
4456 if (lm_capable_kernel) {
4457 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
4458 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
4459 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
4460 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
4461 if (env->features[FEAT_7_1_EAX] & CPUID_7_1_EAX_FRED) {
4462 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP0, 0);
4463 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP1, 0);
4464 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP2, 0);
4465 kvm_msr_entry_add(cpu, MSR_IA32_FRED_RSP3, 0);
4466 kvm_msr_entry_add(cpu, MSR_IA32_FRED_STKLVLS, 0);
4467 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP1, 0);
4468 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0);
4469 kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0);
4470 kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0);
4471 }
4472 }
4473 #endif
4474 if (env->features[FEAT_KVM] & (CPUID_KVM_CLOCK | CPUID_KVM_CLOCK2)) {
4475 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
4476 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
4477 }
4478 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF_INT) {
4479 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
4480 }
4481 if (env->features[FEAT_KVM] & CPUID_KVM_ASYNCPF) {
4482 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
4483 }
4484 if (env->features[FEAT_KVM] & CPUID_KVM_PV_EOI) {
4485 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
4486 }
4487 if (env->features[FEAT_KVM] & CPUID_KVM_STEAL_TIME) {
4488 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
4489 }
4490 if (env->features[FEAT_KVM] & CPUID_KVM_POLL_CONTROL) {
4491 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
4492 }
4493 if (has_architectural_pmu_version > 0) {
4494 if (has_architectural_pmu_version > 1) {
4495 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
4496 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
4497 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
4498 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
4499 }
4500 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
4501 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
4502 }
4503 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
4504 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
4505 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
4506 }
4507 }
4508
4509 if (env->mcg_cap) {
4510 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
4511 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
4512 if (has_msr_mcg_ext_ctl) {
4513 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
4514 }
4515 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
4516 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
4517 }
4518 }
4519
4520 if (has_msr_hv_hypercall) {
4521 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
4522 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
4523 }
4524 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
4525 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
4526 }
4527 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
4528 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
4529 }
4530 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
4531 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
4532 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
4533 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
4534 }
4535 if (has_msr_hv_syndbg_options) {
4536 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
4537 }
4538 if (has_msr_hv_crash) {
4539 int j;
4540
4541 for (j = 0; j < HV_CRASH_PARAMS; j++) {
4542 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
4543 }
4544 }
4545 if (has_msr_hv_runtime) {
4546 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
4547 }
4548 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
4549 uint32_t msr;
4550
4551 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
4552 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
4553 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
4554 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
4555 kvm_msr_entry_add(cpu, msr, 0);
4556 }
4557 }
4558 if (has_msr_hv_stimer) {
4559 uint32_t msr;
4560
4561 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
4562 msr++) {
4563 kvm_msr_entry_add(cpu, msr, 0);
4564 }
4565 }
4566 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
4567 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
4568 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
4569 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
4570 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
4571 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
4572 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
4573 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
4574 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
4575 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
4576 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
4577 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
4578 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
4579 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
4580 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
4581 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
4582 }
4583 }
4584
4585 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
4586 int addr_num =
4587 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
4588
4589 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
4590 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
4591 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
4592 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
4593 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
4594 for (i = 0; i < addr_num; i++) {
4595 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
4596 }
4597 }
4598
4599 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
4600 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
4601 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
4602 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
4603 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
4604 }
4605
4606 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
4607 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
4608 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
4609 }
4610
4611 if (kvm_enabled() && cpu->enable_pmu &&
4612 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
4613 uint64_t depth;
4614
4615 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
4616 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
4617 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
4618 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
4619
4620 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
4621 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
4622 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
4623 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
4624 }
4625 }
4626 }
4627
4628 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
4629 if (ret < 0) {
4630 return ret;
4631 }
4632
4633 if (ret < cpu->kvm_msr_buf->nmsrs) {
4634 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
4635 error_report("error: failed to get MSR 0x%" PRIx32,
4636 (uint32_t)e->index);
4637 }
4638
4639 assert(ret == cpu->kvm_msr_buf->nmsrs);
4640 /*
4641 * MTRR masks: Each mask consists of 5 parts
4642 * a 10..0: must be zero
4643 * b 11 : valid bit
4644 * c n-1.12: actual mask bits
4645 * d 51..n: reserved must be zero
4646 * e 63.52: reserved must be zero
4647 *
4648 * 'n' is the number of physical bits supported by the CPU and is
4649 * apparently always <= 52. We know our 'n' but don't know what
4650 * the destinations 'n' is; it might be smaller, in which case
4651 * it masks (c) on loading. It might be larger, in which case
4652 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
4653 * we're migrating to.
4654 */
4655
4656 if (cpu->fill_mtrr_mask) {
4657 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
4658 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
4659 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
4660 } else {
4661 mtrr_top_bits = 0;
4662 }
4663
4664 for (i = 0; i < ret; i++) {
4665 uint32_t index = msrs[i].index;
4666 switch (index) {
4667 case MSR_IA32_SYSENTER_CS:
4668 env->sysenter_cs = msrs[i].data;
4669 break;
4670 case MSR_IA32_SYSENTER_ESP:
4671 env->sysenter_esp = msrs[i].data;
4672 break;
4673 case MSR_IA32_SYSENTER_EIP:
4674 env->sysenter_eip = msrs[i].data;
4675 break;
4676 case MSR_PAT:
4677 env->pat = msrs[i].data;
4678 break;
4679 case MSR_STAR:
4680 env->star = msrs[i].data;
4681 break;
4682 #ifdef TARGET_X86_64
4683 case MSR_CSTAR:
4684 env->cstar = msrs[i].data;
4685 break;
4686 case MSR_KERNELGSBASE:
4687 env->kernelgsbase = msrs[i].data;
4688 break;
4689 case MSR_FMASK:
4690 env->fmask = msrs[i].data;
4691 break;
4692 case MSR_LSTAR:
4693 env->lstar = msrs[i].data;
4694 break;
4695 case MSR_IA32_FRED_RSP0:
4696 env->fred_rsp0 = msrs[i].data;
4697 break;
4698 case MSR_IA32_FRED_RSP1:
4699 env->fred_rsp1 = msrs[i].data;
4700 break;
4701 case MSR_IA32_FRED_RSP2:
4702 env->fred_rsp2 = msrs[i].data;
4703 break;
4704 case MSR_IA32_FRED_RSP3:
4705 env->fred_rsp3 = msrs[i].data;
4706 break;
4707 case MSR_IA32_FRED_STKLVLS:
4708 env->fred_stklvls = msrs[i].data;
4709 break;
4710 case MSR_IA32_FRED_SSP1:
4711 env->fred_ssp1 = msrs[i].data;
4712 break;
4713 case MSR_IA32_FRED_SSP2:
4714 env->fred_ssp2 = msrs[i].data;
4715 break;
4716 case MSR_IA32_FRED_SSP3:
4717 env->fred_ssp3 = msrs[i].data;
4718 break;
4719 case MSR_IA32_FRED_CONFIG:
4720 env->fred_config = msrs[i].data;
4721 break;
4722 #endif
4723 case MSR_IA32_TSC:
4724 env->tsc = msrs[i].data;
4725 break;
4726 case MSR_TSC_AUX:
4727 env->tsc_aux = msrs[i].data;
4728 break;
4729 case MSR_TSC_ADJUST:
4730 env->tsc_adjust = msrs[i].data;
4731 break;
4732 case MSR_IA32_TSCDEADLINE:
4733 env->tsc_deadline = msrs[i].data;
4734 break;
4735 case MSR_VM_HSAVE_PA:
4736 env->vm_hsave = msrs[i].data;
4737 break;
4738 case MSR_KVM_SYSTEM_TIME:
4739 env->system_time_msr = msrs[i].data;
4740 break;
4741 case MSR_KVM_WALL_CLOCK:
4742 env->wall_clock_msr = msrs[i].data;
4743 break;
4744 case MSR_MCG_STATUS:
4745 env->mcg_status = msrs[i].data;
4746 break;
4747 case MSR_MCG_CTL:
4748 env->mcg_ctl = msrs[i].data;
4749 break;
4750 case MSR_MCG_EXT_CTL:
4751 env->mcg_ext_ctl = msrs[i].data;
4752 break;
4753 case MSR_IA32_MISC_ENABLE:
4754 env->msr_ia32_misc_enable = msrs[i].data;
4755 break;
4756 case MSR_IA32_SMBASE:
4757 env->smbase = msrs[i].data;
4758 break;
4759 case MSR_SMI_COUNT:
4760 env->msr_smi_count = msrs[i].data;
4761 break;
4762 case MSR_IA32_FEATURE_CONTROL:
4763 env->msr_ia32_feature_control = msrs[i].data;
4764 break;
4765 case MSR_IA32_BNDCFGS:
4766 env->msr_bndcfgs = msrs[i].data;
4767 break;
4768 case MSR_IA32_XSS:
4769 env->xss = msrs[i].data;
4770 break;
4771 case MSR_IA32_UMWAIT_CONTROL:
4772 env->umwait = msrs[i].data;
4773 break;
4774 case MSR_IA32_PKRS:
4775 env->pkrs = msrs[i].data;
4776 break;
4777 default:
4778 if (msrs[i].index >= MSR_MC0_CTL &&
4779 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4780 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
4781 }
4782 break;
4783 case MSR_KVM_ASYNC_PF_EN:
4784 env->async_pf_en_msr = msrs[i].data;
4785 break;
4786 case MSR_KVM_ASYNC_PF_INT:
4787 env->async_pf_int_msr = msrs[i].data;
4788 break;
4789 case MSR_KVM_PV_EOI_EN:
4790 env->pv_eoi_en_msr = msrs[i].data;
4791 break;
4792 case MSR_KVM_STEAL_TIME:
4793 env->steal_time_msr = msrs[i].data;
4794 break;
4795 case MSR_KVM_POLL_CONTROL: {
4796 env->poll_control_msr = msrs[i].data;
4797 break;
4798 }
4799 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4800 env->msr_fixed_ctr_ctrl = msrs[i].data;
4801 break;
4802 case MSR_CORE_PERF_GLOBAL_CTRL:
4803 env->msr_global_ctrl = msrs[i].data;
4804 break;
4805 case MSR_CORE_PERF_GLOBAL_STATUS:
4806 env->msr_global_status = msrs[i].data;
4807 break;
4808 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4809 env->msr_global_ovf_ctrl = msrs[i].data;
4810 break;
4811 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4812 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4813 break;
4814 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4815 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4816 break;
4817 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4818 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4819 break;
4820 case HV_X64_MSR_HYPERCALL:
4821 env->msr_hv_hypercall = msrs[i].data;
4822 break;
4823 case HV_X64_MSR_GUEST_OS_ID:
4824 env->msr_hv_guest_os_id = msrs[i].data;
4825 break;
4826 case HV_X64_MSR_APIC_ASSIST_PAGE:
4827 env->msr_hv_vapic = msrs[i].data;
4828 break;
4829 case HV_X64_MSR_REFERENCE_TSC:
4830 env->msr_hv_tsc = msrs[i].data;
4831 break;
4832 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4833 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4834 break;
4835 case HV_X64_MSR_VP_RUNTIME:
4836 env->msr_hv_runtime = msrs[i].data;
4837 break;
4838 case HV_X64_MSR_SCONTROL:
4839 env->msr_hv_synic_control = msrs[i].data;
4840 break;
4841 case HV_X64_MSR_SIEFP:
4842 env->msr_hv_synic_evt_page = msrs[i].data;
4843 break;
4844 case HV_X64_MSR_SIMP:
4845 env->msr_hv_synic_msg_page = msrs[i].data;
4846 break;
4847 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4848 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
4849 break;
4850 case HV_X64_MSR_STIMER0_CONFIG:
4851 case HV_X64_MSR_STIMER1_CONFIG:
4852 case HV_X64_MSR_STIMER2_CONFIG:
4853 case HV_X64_MSR_STIMER3_CONFIG:
4854 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4855 msrs[i].data;
4856 break;
4857 case HV_X64_MSR_STIMER0_COUNT:
4858 case HV_X64_MSR_STIMER1_COUNT:
4859 case HV_X64_MSR_STIMER2_COUNT:
4860 case HV_X64_MSR_STIMER3_COUNT:
4861 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4862 msrs[i].data;
4863 break;
4864 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4865 env->msr_hv_reenlightenment_control = msrs[i].data;
4866 break;
4867 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4868 env->msr_hv_tsc_emulation_control = msrs[i].data;
4869 break;
4870 case HV_X64_MSR_TSC_EMULATION_STATUS:
4871 env->msr_hv_tsc_emulation_status = msrs[i].data;
4872 break;
4873 case HV_X64_MSR_SYNDBG_OPTIONS:
4874 env->msr_hv_syndbg_options = msrs[i].data;
4875 break;
4876 case MSR_MTRRdefType:
4877 env->mtrr_deftype = msrs[i].data;
4878 break;
4879 case MSR_MTRRfix64K_00000:
4880 env->mtrr_fixed[0] = msrs[i].data;
4881 break;
4882 case MSR_MTRRfix16K_80000:
4883 env->mtrr_fixed[1] = msrs[i].data;
4884 break;
4885 case MSR_MTRRfix16K_A0000:
4886 env->mtrr_fixed[2] = msrs[i].data;
4887 break;
4888 case MSR_MTRRfix4K_C0000:
4889 env->mtrr_fixed[3] = msrs[i].data;
4890 break;
4891 case MSR_MTRRfix4K_C8000:
4892 env->mtrr_fixed[4] = msrs[i].data;
4893 break;
4894 case MSR_MTRRfix4K_D0000:
4895 env->mtrr_fixed[5] = msrs[i].data;
4896 break;
4897 case MSR_MTRRfix4K_D8000:
4898 env->mtrr_fixed[6] = msrs[i].data;
4899 break;
4900 case MSR_MTRRfix4K_E0000:
4901 env->mtrr_fixed[7] = msrs[i].data;
4902 break;
4903 case MSR_MTRRfix4K_E8000:
4904 env->mtrr_fixed[8] = msrs[i].data;
4905 break;
4906 case MSR_MTRRfix4K_F0000:
4907 env->mtrr_fixed[9] = msrs[i].data;
4908 break;
4909 case MSR_MTRRfix4K_F8000:
4910 env->mtrr_fixed[10] = msrs[i].data;
4911 break;
4912 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4913 if (index & 1) {
4914 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4915 mtrr_top_bits;
4916 } else {
4917 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4918 }
4919 break;
4920 case MSR_IA32_SPEC_CTRL:
4921 env->spec_ctrl = msrs[i].data;
4922 break;
4923 case MSR_AMD64_TSC_RATIO:
4924 env->amd_tsc_scale_msr = msrs[i].data;
4925 break;
4926 case MSR_IA32_TSX_CTRL:
4927 env->tsx_ctrl = msrs[i].data;
4928 break;
4929 case MSR_VIRT_SSBD:
4930 env->virt_ssbd = msrs[i].data;
4931 break;
4932 case MSR_IA32_RTIT_CTL:
4933 env->msr_rtit_ctrl = msrs[i].data;
4934 break;
4935 case MSR_IA32_RTIT_STATUS:
4936 env->msr_rtit_status = msrs[i].data;
4937 break;
4938 case MSR_IA32_RTIT_OUTPUT_BASE:
4939 env->msr_rtit_output_base = msrs[i].data;
4940 break;
4941 case MSR_IA32_RTIT_OUTPUT_MASK:
4942 env->msr_rtit_output_mask = msrs[i].data;
4943 break;
4944 case MSR_IA32_RTIT_CR3_MATCH:
4945 env->msr_rtit_cr3_match = msrs[i].data;
4946 break;
4947 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4948 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4949 break;
4950 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4951 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4952 msrs[i].data;
4953 break;
4954 case MSR_IA32_XFD:
4955 env->msr_xfd = msrs[i].data;
4956 break;
4957 case MSR_IA32_XFD_ERR:
4958 env->msr_xfd_err = msrs[i].data;
4959 break;
4960 case MSR_ARCH_LBR_CTL:
4961 env->msr_lbr_ctl = msrs[i].data;
4962 break;
4963 case MSR_ARCH_LBR_DEPTH:
4964 env->msr_lbr_depth = msrs[i].data;
4965 break;
4966 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4967 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4968 break;
4969 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4970 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4971 break;
4972 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4973 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4974 break;
4975 case MSR_K7_HWCR:
4976 env->msr_hwcr = msrs[i].data;
4977 break;
4978 }
4979 }
4980
4981 return 0;
4982 }
4983
kvm_put_mp_state(X86CPU * cpu)4984 static int kvm_put_mp_state(X86CPU *cpu)
4985 {
4986 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
4987
4988 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
4989 }
4990
kvm_get_mp_state(X86CPU * cpu)4991 static int kvm_get_mp_state(X86CPU *cpu)
4992 {
4993 CPUState *cs = CPU(cpu);
4994 CPUX86State *env = &cpu->env;
4995 struct kvm_mp_state mp_state;
4996 int ret;
4997
4998 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
4999 if (ret < 0) {
5000 return ret;
5001 }
5002 env->mp_state = mp_state.mp_state;
5003 if (kvm_irqchip_in_kernel()) {
5004 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
5005 }
5006 return 0;
5007 }
5008
kvm_get_apic(X86CPU * cpu)5009 static int kvm_get_apic(X86CPU *cpu)
5010 {
5011 DeviceState *apic = cpu->apic_state;
5012 struct kvm_lapic_state kapic;
5013 int ret;
5014
5015 if (apic && kvm_irqchip_in_kernel()) {
5016 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
5017 if (ret < 0) {
5018 return ret;
5019 }
5020
5021 kvm_get_apic_state(apic, &kapic);
5022 }
5023 return 0;
5024 }
5025
kvm_put_vcpu_events(X86CPU * cpu,int level)5026 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
5027 {
5028 CPUState *cs = CPU(cpu);
5029 CPUX86State *env = &cpu->env;
5030 struct kvm_vcpu_events events = {};
5031
5032 events.flags = 0;
5033
5034 if (has_exception_payload) {
5035 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5036 events.exception.pending = env->exception_pending;
5037 events.exception_has_payload = env->exception_has_payload;
5038 events.exception_payload = env->exception_payload;
5039 }
5040 events.exception.nr = env->exception_nr;
5041 events.exception.injected = env->exception_injected;
5042 events.exception.has_error_code = env->has_error_code;
5043 events.exception.error_code = env->error_code;
5044
5045 events.interrupt.injected = (env->interrupt_injected >= 0);
5046 events.interrupt.nr = env->interrupt_injected;
5047 events.interrupt.soft = env->soft_interrupt;
5048
5049 events.nmi.injected = env->nmi_injected;
5050 events.nmi.pending = env->nmi_pending;
5051 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
5052
5053 events.sipi_vector = env->sipi_vector;
5054
5055 if (has_msr_smbase) {
5056 events.flags |= KVM_VCPUEVENT_VALID_SMM;
5057 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
5058 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
5059 if (kvm_irqchip_in_kernel()) {
5060 /* As soon as these are moved to the kernel, remove them
5061 * from cs->interrupt_request.
5062 */
5063 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
5064 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
5065 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
5066 } else {
5067 /* Keep these in cs->interrupt_request. */
5068 events.smi.pending = 0;
5069 events.smi.latched_init = 0;
5070 }
5071 }
5072
5073 if (level >= KVM_PUT_RESET_STATE) {
5074 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
5075 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
5076 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
5077 }
5078 }
5079
5080 if (has_triple_fault_event) {
5081 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5082 events.triple_fault.pending = env->triple_fault_pending;
5083 }
5084
5085 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
5086 }
5087
kvm_get_vcpu_events(X86CPU * cpu)5088 static int kvm_get_vcpu_events(X86CPU *cpu)
5089 {
5090 CPUX86State *env = &cpu->env;
5091 struct kvm_vcpu_events events;
5092 int ret;
5093
5094 memset(&events, 0, sizeof(events));
5095 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
5096 if (ret < 0) {
5097 return ret;
5098 }
5099
5100 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5101 env->exception_pending = events.exception.pending;
5102 env->exception_has_payload = events.exception_has_payload;
5103 env->exception_payload = events.exception_payload;
5104 } else {
5105 env->exception_pending = 0;
5106 env->exception_has_payload = false;
5107 }
5108 env->exception_injected = events.exception.injected;
5109 env->exception_nr =
5110 (env->exception_pending || env->exception_injected) ?
5111 events.exception.nr : -1;
5112 env->has_error_code = events.exception.has_error_code;
5113 env->error_code = events.exception.error_code;
5114
5115 env->interrupt_injected =
5116 events.interrupt.injected ? events.interrupt.nr : -1;
5117 env->soft_interrupt = events.interrupt.soft;
5118
5119 env->nmi_injected = events.nmi.injected;
5120 env->nmi_pending = events.nmi.pending;
5121 if (events.nmi.masked) {
5122 env->hflags2 |= HF2_NMI_MASK;
5123 } else {
5124 env->hflags2 &= ~HF2_NMI_MASK;
5125 }
5126
5127 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
5128 if (events.smi.smm) {
5129 env->hflags |= HF_SMM_MASK;
5130 } else {
5131 env->hflags &= ~HF_SMM_MASK;
5132 }
5133 if (events.smi.pending) {
5134 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5135 } else {
5136 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
5137 }
5138 if (events.smi.smm_inside_nmi) {
5139 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
5140 } else {
5141 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
5142 }
5143 if (events.smi.latched_init) {
5144 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5145 } else {
5146 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
5147 }
5148 }
5149
5150 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5151 env->triple_fault_pending = events.triple_fault.pending;
5152 }
5153
5154 env->sipi_vector = events.sipi_vector;
5155
5156 return 0;
5157 }
5158
kvm_put_debugregs(X86CPU * cpu)5159 static int kvm_put_debugregs(X86CPU *cpu)
5160 {
5161 CPUX86State *env = &cpu->env;
5162 struct kvm_debugregs dbgregs;
5163 int i;
5164
5165 memset(&dbgregs, 0, sizeof(dbgregs));
5166 for (i = 0; i < 4; i++) {
5167 dbgregs.db[i] = env->dr[i];
5168 }
5169 dbgregs.dr6 = env->dr[6];
5170 dbgregs.dr7 = env->dr[7];
5171 dbgregs.flags = 0;
5172
5173 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
5174 }
5175
kvm_get_debugregs(X86CPU * cpu)5176 static int kvm_get_debugregs(X86CPU *cpu)
5177 {
5178 CPUX86State *env = &cpu->env;
5179 struct kvm_debugregs dbgregs;
5180 int i, ret;
5181
5182 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
5183 if (ret < 0) {
5184 return ret;
5185 }
5186 for (i = 0; i < 4; i++) {
5187 env->dr[i] = dbgregs.db[i];
5188 }
5189 env->dr[4] = env->dr[6] = dbgregs.dr6;
5190 env->dr[5] = env->dr[7] = dbgregs.dr7;
5191
5192 return 0;
5193 }
5194
kvm_put_nested_state(X86CPU * cpu)5195 static int kvm_put_nested_state(X86CPU *cpu)
5196 {
5197 CPUX86State *env = &cpu->env;
5198 int max_nested_state_len = kvm_max_nested_state_length();
5199
5200 if (!env->nested_state) {
5201 return 0;
5202 }
5203
5204 /*
5205 * Copy flags that are affected by reset from env->hflags and env->hflags2.
5206 */
5207 if (env->hflags & HF_GUEST_MASK) {
5208 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
5209 } else {
5210 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
5211 }
5212
5213 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
5214 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
5215 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
5216 } else {
5217 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
5218 }
5219
5220 assert(env->nested_state->size <= max_nested_state_len);
5221 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
5222 }
5223
kvm_get_nested_state(X86CPU * cpu)5224 static int kvm_get_nested_state(X86CPU *cpu)
5225 {
5226 CPUX86State *env = &cpu->env;
5227 int max_nested_state_len = kvm_max_nested_state_length();
5228 int ret;
5229
5230 if (!env->nested_state) {
5231 return 0;
5232 }
5233
5234 /*
5235 * It is possible that migration restored a smaller size into
5236 * nested_state->hdr.size than what our kernel support.
5237 * We preserve migration origin nested_state->hdr.size for
5238 * call to KVM_SET_NESTED_STATE but wish that our next call
5239 * to KVM_GET_NESTED_STATE will use max size our kernel support.
5240 */
5241 env->nested_state->size = max_nested_state_len;
5242
5243 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
5244 if (ret < 0) {
5245 return ret;
5246 }
5247
5248 /*
5249 * Copy flags that are affected by reset to env->hflags and env->hflags2.
5250 */
5251 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
5252 env->hflags |= HF_GUEST_MASK;
5253 } else {
5254 env->hflags &= ~HF_GUEST_MASK;
5255 }
5256
5257 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
5258 if (cpu_has_svm(env)) {
5259 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
5260 env->hflags2 |= HF2_GIF_MASK;
5261 } else {
5262 env->hflags2 &= ~HF2_GIF_MASK;
5263 }
5264 }
5265
5266 return ret;
5267 }
5268
kvm_arch_put_registers(CPUState * cpu,int level,Error ** errp)5269 int kvm_arch_put_registers(CPUState *cpu, int level, Error **errp)
5270 {
5271 X86CPU *x86_cpu = X86_CPU(cpu);
5272 int ret;
5273
5274 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
5275
5276 /*
5277 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
5278 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
5279 * precede kvm_put_nested_state() when 'real' nested state is set.
5280 */
5281 if (level >= KVM_PUT_RESET_STATE) {
5282 ret = kvm_put_msr_feature_control(x86_cpu);
5283 if (ret < 0) {
5284 error_setg_errno(errp, -ret, "Failed to set feature control MSR");
5285 return ret;
5286 }
5287 }
5288
5289 /* must be before kvm_put_nested_state so that EFER.SVME is set */
5290 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
5291 if (ret < 0) {
5292 error_setg_errno(errp, -ret, "Failed to set special registers");
5293 return ret;
5294 }
5295
5296 if (level >= KVM_PUT_RESET_STATE) {
5297 ret = kvm_put_nested_state(x86_cpu);
5298 if (ret < 0) {
5299 error_setg_errno(errp, -ret, "Failed to set nested state");
5300 return ret;
5301 }
5302 }
5303
5304 if (level == KVM_PUT_FULL_STATE) {
5305 /* We don't check for kvm_arch_set_tsc_khz() errors here,
5306 * because TSC frequency mismatch shouldn't abort migration,
5307 * unless the user explicitly asked for a more strict TSC
5308 * setting (e.g. using an explicit "tsc-freq" option).
5309 */
5310 kvm_arch_set_tsc_khz(cpu);
5311 }
5312
5313 #ifdef CONFIG_XEN_EMU
5314 if (xen_mode == XEN_EMULATE && level == KVM_PUT_FULL_STATE) {
5315 ret = kvm_put_xen_state(cpu);
5316 if (ret < 0) {
5317 error_setg_errno(errp, -ret, "Failed to set Xen state");
5318 return ret;
5319 }
5320 }
5321 #endif
5322
5323 ret = kvm_getput_regs(x86_cpu, 1);
5324 if (ret < 0) {
5325 error_setg_errno(errp, -ret, "Failed to set general purpose registers");
5326 return ret;
5327 }
5328 ret = kvm_put_xsave(x86_cpu);
5329 if (ret < 0) {
5330 error_setg_errno(errp, -ret, "Failed to set XSAVE");
5331 return ret;
5332 }
5333 ret = kvm_put_xcrs(x86_cpu);
5334 if (ret < 0) {
5335 error_setg_errno(errp, -ret, "Failed to set XCRs");
5336 return ret;
5337 }
5338 ret = kvm_put_msrs(x86_cpu, level);
5339 if (ret < 0) {
5340 error_setg_errno(errp, -ret, "Failed to set MSRs");
5341 return ret;
5342 }
5343 ret = kvm_put_vcpu_events(x86_cpu, level);
5344 if (ret < 0) {
5345 error_setg_errno(errp, -ret, "Failed to set vCPU events");
5346 return ret;
5347 }
5348 if (level >= KVM_PUT_RESET_STATE) {
5349 ret = kvm_put_mp_state(x86_cpu);
5350 if (ret < 0) {
5351 error_setg_errno(errp, -ret, "Failed to set MP state");
5352 return ret;
5353 }
5354 }
5355
5356 ret = kvm_put_tscdeadline_msr(x86_cpu);
5357 if (ret < 0) {
5358 error_setg_errno(errp, -ret, "Failed to set TSC deadline MSR");
5359 return ret;
5360 }
5361 ret = kvm_put_debugregs(x86_cpu);
5362 if (ret < 0) {
5363 error_setg_errno(errp, -ret, "Failed to set debug registers");
5364 return ret;
5365 }
5366 return 0;
5367 }
5368
kvm_arch_get_registers(CPUState * cs,Error ** errp)5369 int kvm_arch_get_registers(CPUState *cs, Error **errp)
5370 {
5371 X86CPU *cpu = X86_CPU(cs);
5372 int ret;
5373
5374 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
5375
5376 ret = kvm_get_vcpu_events(cpu);
5377 if (ret < 0) {
5378 error_setg_errno(errp, -ret, "Failed to get vCPU events");
5379 goto out;
5380 }
5381 /*
5382 * KVM_GET_MPSTATE can modify CS and RIP, call it before
5383 * KVM_GET_REGS and KVM_GET_SREGS.
5384 */
5385 ret = kvm_get_mp_state(cpu);
5386 if (ret < 0) {
5387 error_setg_errno(errp, -ret, "Failed to get MP state");
5388 goto out;
5389 }
5390 ret = kvm_getput_regs(cpu, 0);
5391 if (ret < 0) {
5392 error_setg_errno(errp, -ret, "Failed to get general purpose registers");
5393 goto out;
5394 }
5395 ret = kvm_get_xsave(cpu);
5396 if (ret < 0) {
5397 error_setg_errno(errp, -ret, "Failed to get XSAVE");
5398 goto out;
5399 }
5400 ret = kvm_get_xcrs(cpu);
5401 if (ret < 0) {
5402 error_setg_errno(errp, -ret, "Failed to get XCRs");
5403 goto out;
5404 }
5405 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
5406 if (ret < 0) {
5407 error_setg_errno(errp, -ret, "Failed to get special registers");
5408 goto out;
5409 }
5410 ret = kvm_get_msrs(cpu);
5411 if (ret < 0) {
5412 error_setg_errno(errp, -ret, "Failed to get MSRs");
5413 goto out;
5414 }
5415 ret = kvm_get_apic(cpu);
5416 if (ret < 0) {
5417 error_setg_errno(errp, -ret, "Failed to get APIC");
5418 goto out;
5419 }
5420 ret = kvm_get_debugregs(cpu);
5421 if (ret < 0) {
5422 error_setg_errno(errp, -ret, "Failed to get debug registers");
5423 goto out;
5424 }
5425 ret = kvm_get_nested_state(cpu);
5426 if (ret < 0) {
5427 error_setg_errno(errp, -ret, "Failed to get nested state");
5428 goto out;
5429 }
5430 #ifdef CONFIG_XEN_EMU
5431 if (xen_mode == XEN_EMULATE) {
5432 ret = kvm_get_xen_state(cs);
5433 if (ret < 0) {
5434 error_setg_errno(errp, -ret, "Failed to get Xen state");
5435 goto out;
5436 }
5437 }
5438 #endif
5439 ret = 0;
5440 out:
5441 cpu_sync_bndcs_hflags(&cpu->env);
5442 return ret;
5443 }
5444
kvm_arch_pre_run(CPUState * cpu,struct kvm_run * run)5445 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
5446 {
5447 X86CPU *x86_cpu = X86_CPU(cpu);
5448 CPUX86State *env = &x86_cpu->env;
5449 int ret;
5450
5451 /* Inject NMI */
5452 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
5453 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
5454 bql_lock();
5455 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
5456 bql_unlock();
5457 DPRINTF("injected NMI\n");
5458 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
5459 if (ret < 0) {
5460 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
5461 strerror(-ret));
5462 }
5463 }
5464 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
5465 bql_lock();
5466 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
5467 bql_unlock();
5468 DPRINTF("injected SMI\n");
5469 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
5470 if (ret < 0) {
5471 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
5472 strerror(-ret));
5473 }
5474 }
5475 }
5476
5477 if (!kvm_pic_in_kernel()) {
5478 bql_lock();
5479 }
5480
5481 /* Force the VCPU out of its inner loop to process any INIT requests
5482 * or (for userspace APIC, but it is cheap to combine the checks here)
5483 * pending TPR access reports.
5484 */
5485 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
5486 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
5487 !(env->hflags & HF_SMM_MASK)) {
5488 cpu->exit_request = 1;
5489 }
5490 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
5491 cpu->exit_request = 1;
5492 }
5493 }
5494
5495 if (!kvm_pic_in_kernel()) {
5496 /* Try to inject an interrupt if the guest can accept it */
5497 if (run->ready_for_interrupt_injection &&
5498 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
5499 (env->eflags & IF_MASK)) {
5500 int irq;
5501
5502 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
5503 irq = cpu_get_pic_interrupt(env);
5504 if (irq >= 0) {
5505 struct kvm_interrupt intr;
5506
5507 intr.irq = irq;
5508 DPRINTF("injected interrupt %d\n", irq);
5509 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
5510 if (ret < 0) {
5511 fprintf(stderr,
5512 "KVM: injection failed, interrupt lost (%s)\n",
5513 strerror(-ret));
5514 }
5515 }
5516 }
5517
5518 /* If we have an interrupt but the guest is not ready to receive an
5519 * interrupt, request an interrupt window exit. This will
5520 * cause a return to userspace as soon as the guest is ready to
5521 * receive interrupts. */
5522 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
5523 run->request_interrupt_window = 1;
5524 } else {
5525 run->request_interrupt_window = 0;
5526 }
5527
5528 DPRINTF("setting tpr\n");
5529 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
5530
5531 bql_unlock();
5532 }
5533 }
5534
kvm_rate_limit_on_bus_lock(void)5535 static void kvm_rate_limit_on_bus_lock(void)
5536 {
5537 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
5538
5539 if (delay_ns) {
5540 g_usleep(delay_ns / SCALE_US);
5541 }
5542 }
5543
kvm_arch_post_run(CPUState * cpu,struct kvm_run * run)5544 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
5545 {
5546 X86CPU *x86_cpu = X86_CPU(cpu);
5547 CPUX86State *env = &x86_cpu->env;
5548
5549 if (run->flags & KVM_RUN_X86_SMM) {
5550 env->hflags |= HF_SMM_MASK;
5551 } else {
5552 env->hflags &= ~HF_SMM_MASK;
5553 }
5554 if (run->if_flag) {
5555 env->eflags |= IF_MASK;
5556 } else {
5557 env->eflags &= ~IF_MASK;
5558 }
5559 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
5560 kvm_rate_limit_on_bus_lock();
5561 }
5562
5563 #ifdef CONFIG_XEN_EMU
5564 /*
5565 * If the callback is asserted as a GSI (or PCI INTx) then check if
5566 * vcpu_info->evtchn_upcall_pending has been cleared, and deassert
5567 * the callback IRQ if so. Ideally we could hook into the PIC/IOAPIC
5568 * EOI and only resample then, exactly how the VFIO eventfd pairs
5569 * are designed to work for level triggered interrupts.
5570 */
5571 if (x86_cpu->env.xen_callback_asserted) {
5572 kvm_xen_maybe_deassert_callback(cpu);
5573 }
5574 #endif
5575
5576 /* We need to protect the apic state against concurrent accesses from
5577 * different threads in case the userspace irqchip is used. */
5578 if (!kvm_irqchip_in_kernel()) {
5579 bql_lock();
5580 }
5581 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
5582 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
5583 if (!kvm_irqchip_in_kernel()) {
5584 bql_unlock();
5585 }
5586 return cpu_get_mem_attrs(env);
5587 }
5588
kvm_arch_process_async_events(CPUState * cs)5589 int kvm_arch_process_async_events(CPUState *cs)
5590 {
5591 X86CPU *cpu = X86_CPU(cs);
5592 CPUX86State *env = &cpu->env;
5593
5594 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
5595 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
5596 assert(env->mcg_cap);
5597
5598 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
5599
5600 kvm_cpu_synchronize_state(cs);
5601
5602 if (env->exception_nr == EXCP08_DBLE) {
5603 /* this means triple fault */
5604 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
5605 cs->exit_request = 1;
5606 return 0;
5607 }
5608 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
5609 env->has_error_code = 0;
5610
5611 cs->halted = 0;
5612 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
5613 env->mp_state = KVM_MP_STATE_RUNNABLE;
5614 }
5615 }
5616
5617 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
5618 !(env->hflags & HF_SMM_MASK)) {
5619 kvm_cpu_synchronize_state(cs);
5620 do_cpu_init(cpu);
5621 }
5622
5623 if (kvm_irqchip_in_kernel()) {
5624 return 0;
5625 }
5626
5627 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
5628 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
5629 apic_poll_irq(cpu->apic_state);
5630 }
5631 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5632 (env->eflags & IF_MASK)) ||
5633 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5634 cs->halted = 0;
5635 }
5636 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
5637 kvm_cpu_synchronize_state(cs);
5638 do_cpu_sipi(cpu);
5639 }
5640 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
5641 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
5642 kvm_cpu_synchronize_state(cs);
5643 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
5644 env->tpr_access_type);
5645 }
5646
5647 return cs->halted;
5648 }
5649
kvm_handle_halt(X86CPU * cpu)5650 static int kvm_handle_halt(X86CPU *cpu)
5651 {
5652 CPUState *cs = CPU(cpu);
5653 CPUX86State *env = &cpu->env;
5654
5655 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
5656 (env->eflags & IF_MASK)) &&
5657 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
5658 cs->halted = 1;
5659 return EXCP_HLT;
5660 }
5661
5662 return 0;
5663 }
5664
kvm_handle_tpr_access(X86CPU * cpu)5665 static int kvm_handle_tpr_access(X86CPU *cpu)
5666 {
5667 CPUState *cs = CPU(cpu);
5668 struct kvm_run *run = cs->kvm_run;
5669
5670 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
5671 run->tpr_access.is_write ? TPR_ACCESS_WRITE
5672 : TPR_ACCESS_READ);
5673 return 1;
5674 }
5675
kvm_arch_insert_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5676 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5677 {
5678 static const uint8_t int3 = 0xcc;
5679
5680 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
5681 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
5682 return -EINVAL;
5683 }
5684 return 0;
5685 }
5686
kvm_arch_remove_sw_breakpoint(CPUState * cs,struct kvm_sw_breakpoint * bp)5687 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
5688 {
5689 uint8_t int3;
5690
5691 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
5692 return -EINVAL;
5693 }
5694 if (int3 != 0xcc) {
5695 return 0;
5696 }
5697 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
5698 return -EINVAL;
5699 }
5700 return 0;
5701 }
5702
5703 static struct {
5704 target_ulong addr;
5705 int len;
5706 int type;
5707 } hw_breakpoint[4];
5708
5709 static int nb_hw_breakpoint;
5710
find_hw_breakpoint(target_ulong addr,int len,int type)5711 static int find_hw_breakpoint(target_ulong addr, int len, int type)
5712 {
5713 int n;
5714
5715 for (n = 0; n < nb_hw_breakpoint; n++) {
5716 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
5717 (hw_breakpoint[n].len == len || len == -1)) {
5718 return n;
5719 }
5720 }
5721 return -1;
5722 }
5723
kvm_arch_insert_hw_breakpoint(vaddr addr,vaddr len,int type)5724 int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
5725 {
5726 switch (type) {
5727 case GDB_BREAKPOINT_HW:
5728 len = 1;
5729 break;
5730 case GDB_WATCHPOINT_WRITE:
5731 case GDB_WATCHPOINT_ACCESS:
5732 switch (len) {
5733 case 1:
5734 break;
5735 case 2:
5736 case 4:
5737 case 8:
5738 if (addr & (len - 1)) {
5739 return -EINVAL;
5740 }
5741 break;
5742 default:
5743 return -EINVAL;
5744 }
5745 break;
5746 default:
5747 return -ENOSYS;
5748 }
5749
5750 if (nb_hw_breakpoint == 4) {
5751 return -ENOBUFS;
5752 }
5753 if (find_hw_breakpoint(addr, len, type) >= 0) {
5754 return -EEXIST;
5755 }
5756 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5757 hw_breakpoint[nb_hw_breakpoint].len = len;
5758 hw_breakpoint[nb_hw_breakpoint].type = type;
5759 nb_hw_breakpoint++;
5760
5761 return 0;
5762 }
5763
kvm_arch_remove_hw_breakpoint(vaddr addr,vaddr len,int type)5764 int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
5765 {
5766 int n;
5767
5768 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
5769 if (n < 0) {
5770 return -ENOENT;
5771 }
5772 nb_hw_breakpoint--;
5773 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5774
5775 return 0;
5776 }
5777
kvm_arch_remove_all_hw_breakpoints(void)5778 void kvm_arch_remove_all_hw_breakpoints(void)
5779 {
5780 nb_hw_breakpoint = 0;
5781 }
5782
5783 static CPUWatchpoint hw_watchpoint;
5784
kvm_handle_debug(X86CPU * cpu,struct kvm_debug_exit_arch * arch_info)5785 static int kvm_handle_debug(X86CPU *cpu,
5786 struct kvm_debug_exit_arch *arch_info)
5787 {
5788 CPUState *cs = CPU(cpu);
5789 CPUX86State *env = &cpu->env;
5790 int ret = 0;
5791 int n;
5792
5793 if (arch_info->exception == EXCP01_DB) {
5794 if (arch_info->dr6 & DR6_BS) {
5795 if (cs->singlestep_enabled) {
5796 ret = EXCP_DEBUG;
5797 }
5798 } else {
5799 for (n = 0; n < 4; n++) {
5800 if (arch_info->dr6 & (1 << n)) {
5801 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5802 case 0x0:
5803 ret = EXCP_DEBUG;
5804 break;
5805 case 0x1:
5806 ret = EXCP_DEBUG;
5807 cs->watchpoint_hit = &hw_watchpoint;
5808 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5809 hw_watchpoint.flags = BP_MEM_WRITE;
5810 break;
5811 case 0x3:
5812 ret = EXCP_DEBUG;
5813 cs->watchpoint_hit = &hw_watchpoint;
5814 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5815 hw_watchpoint.flags = BP_MEM_ACCESS;
5816 break;
5817 }
5818 }
5819 }
5820 }
5821 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
5822 ret = EXCP_DEBUG;
5823 }
5824 if (ret == 0) {
5825 cpu_synchronize_state(cs);
5826 assert(env->exception_nr == -1);
5827
5828 /* pass to guest */
5829 kvm_queue_exception(env, arch_info->exception,
5830 arch_info->exception == EXCP01_DB,
5831 arch_info->dr6);
5832 env->has_error_code = 0;
5833 }
5834
5835 return ret;
5836 }
5837
kvm_arch_update_guest_debug(CPUState * cpu,struct kvm_guest_debug * dbg)5838 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
5839 {
5840 const uint8_t type_code[] = {
5841 [GDB_BREAKPOINT_HW] = 0x0,
5842 [GDB_WATCHPOINT_WRITE] = 0x1,
5843 [GDB_WATCHPOINT_ACCESS] = 0x3
5844 };
5845 const uint8_t len_code[] = {
5846 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5847 };
5848 int n;
5849
5850 if (kvm_sw_breakpoints_active(cpu)) {
5851 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
5852 }
5853 if (nb_hw_breakpoint > 0) {
5854 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5855 dbg->arch.debugreg[7] = 0x0600;
5856 for (n = 0; n < nb_hw_breakpoint; n++) {
5857 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5858 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5859 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
5860 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
5861 }
5862 }
5863 }
5864
kvm_install_msr_filters(KVMState * s)5865 static int kvm_install_msr_filters(KVMState *s)
5866 {
5867 uint64_t zero = 0;
5868 struct kvm_msr_filter filter = {
5869 .flags = KVM_MSR_FILTER_DEFAULT_ALLOW,
5870 };
5871 int i, j = 0;
5872
5873 QEMU_BUILD_BUG_ON(ARRAY_SIZE(msr_handlers) != ARRAY_SIZE(filter.ranges));
5874 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5875 KVMMSRHandlers *handler = &msr_handlers[i];
5876 if (handler->msr) {
5877 struct kvm_msr_filter_range *range = &filter.ranges[j++];
5878
5879 *range = (struct kvm_msr_filter_range) {
5880 .flags = 0,
5881 .nmsrs = 1,
5882 .base = handler->msr,
5883 .bitmap = (__u8 *)&zero,
5884 };
5885
5886 if (handler->rdmsr) {
5887 range->flags |= KVM_MSR_FILTER_READ;
5888 }
5889
5890 if (handler->wrmsr) {
5891 range->flags |= KVM_MSR_FILTER_WRITE;
5892 }
5893 }
5894 }
5895
5896 return kvm_vm_ioctl(s, KVM_X86_SET_MSR_FILTER, &filter);
5897 }
5898
kvm_filter_msr(KVMState * s,uint32_t msr,QEMURDMSRHandler * rdmsr,QEMUWRMSRHandler * wrmsr)5899 static int kvm_filter_msr(KVMState *s, uint32_t msr, QEMURDMSRHandler *rdmsr,
5900 QEMUWRMSRHandler *wrmsr)
5901 {
5902 int i, ret;
5903
5904 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5905 if (!msr_handlers[i].msr) {
5906 msr_handlers[i] = (KVMMSRHandlers) {
5907 .msr = msr,
5908 .rdmsr = rdmsr,
5909 .wrmsr = wrmsr,
5910 };
5911
5912 ret = kvm_install_msr_filters(s);
5913 if (ret) {
5914 msr_handlers[i] = (KVMMSRHandlers) { };
5915 return ret;
5916 }
5917
5918 return 0;
5919 }
5920 }
5921
5922 return -EINVAL;
5923 }
5924
kvm_handle_rdmsr(X86CPU * cpu,struct kvm_run * run)5925 static int kvm_handle_rdmsr(X86CPU *cpu, struct kvm_run *run)
5926 {
5927 int i;
5928 bool r;
5929
5930 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5931 KVMMSRHandlers *handler = &msr_handlers[i];
5932 if (run->msr.index == handler->msr) {
5933 if (handler->rdmsr) {
5934 r = handler->rdmsr(cpu, handler->msr,
5935 (uint64_t *)&run->msr.data);
5936 run->msr.error = r ? 0 : 1;
5937 return 0;
5938 }
5939 }
5940 }
5941
5942 g_assert_not_reached();
5943 }
5944
kvm_handle_wrmsr(X86CPU * cpu,struct kvm_run * run)5945 static int kvm_handle_wrmsr(X86CPU *cpu, struct kvm_run *run)
5946 {
5947 int i;
5948 bool r;
5949
5950 for (i = 0; i < ARRAY_SIZE(msr_handlers); i++) {
5951 KVMMSRHandlers *handler = &msr_handlers[i];
5952 if (run->msr.index == handler->msr) {
5953 if (handler->wrmsr) {
5954 r = handler->wrmsr(cpu, handler->msr, run->msr.data);
5955 run->msr.error = r ? 0 : 1;
5956 return 0;
5957 }
5958 }
5959 }
5960
5961 g_assert_not_reached();
5962 }
5963
5964 static bool has_sgx_provisioning;
5965
__kvm_enable_sgx_provisioning(KVMState * s)5966 static bool __kvm_enable_sgx_provisioning(KVMState *s)
5967 {
5968 int fd, ret;
5969
5970 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5971 return false;
5972 }
5973
5974 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5975 if (fd < 0) {
5976 return false;
5977 }
5978
5979 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5980 if (ret) {
5981 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5982 exit(1);
5983 }
5984 close(fd);
5985 return true;
5986 }
5987
kvm_enable_sgx_provisioning(KVMState * s)5988 bool kvm_enable_sgx_provisioning(KVMState *s)
5989 {
5990 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5991 }
5992
host_supports_vmx(void)5993 static bool host_supports_vmx(void)
5994 {
5995 uint32_t ecx, unused;
5996
5997 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
5998 return ecx & CPUID_EXT_VMX;
5999 }
6000
6001 /*
6002 * Currently the handling here only supports use of KVM_HC_MAP_GPA_RANGE
6003 * to service guest-initiated memory attribute update requests so that
6004 * KVM_SET_MEMORY_ATTRIBUTES can update whether or not a page should be
6005 * backed by the private memory pool provided by guest_memfd, and as such
6006 * is only applicable to guest_memfd-backed guests (e.g. SNP/TDX).
6007 *
6008 * Other other use-cases for KVM_HC_MAP_GPA_RANGE, such as for SEV live
6009 * migration, are not implemented here currently.
6010 *
6011 * For the guest_memfd use-case, these exits will generally be synthesized
6012 * by KVM based on platform-specific hypercalls, like GHCB requests in the
6013 * case of SEV-SNP, and not issued directly within the guest though the
6014 * KVM_HC_MAP_GPA_RANGE hypercall. So in this case, KVM_HC_MAP_GPA_RANGE is
6015 * not actually advertised to guests via the KVM CPUID feature bit, as
6016 * opposed to SEV live migration where it would be. Since it is unlikely the
6017 * SEV live migration use-case would be useful for guest-memfd backed guests,
6018 * because private/shared page tracking is already provided through other
6019 * means, these 2 use-cases should be treated as being mutually-exclusive.
6020 */
kvm_handle_hc_map_gpa_range(X86CPU * cpu,struct kvm_run * run)6021 static int kvm_handle_hc_map_gpa_range(X86CPU *cpu, struct kvm_run *run)
6022 {
6023 struct kvm_pre_fault_memory mem;
6024 uint64_t gpa, size, attributes;
6025 int ret;
6026
6027 if (!machine_require_guest_memfd(current_machine))
6028 return -EINVAL;
6029
6030 gpa = run->hypercall.args[0];
6031 size = run->hypercall.args[1] * TARGET_PAGE_SIZE;
6032 attributes = run->hypercall.args[2];
6033
6034 trace_kvm_hc_map_gpa_range(gpa, size, attributes, run->hypercall.flags);
6035
6036 ret = kvm_convert_memory(gpa, size, attributes & KVM_MAP_GPA_RANGE_ENCRYPTED);
6037 if (ret || !kvm_pre_fault_memory_supported) {
6038 return ret;
6039 }
6040
6041 /*
6042 * Opportunistically pre-fault memory in. Failures are ignored so that any
6043 * errors in faulting in the memory will get captured in KVM page fault
6044 * path when the guest first accesses the page.
6045 */
6046 memset(&mem, 0, sizeof(mem));
6047 mem.gpa = gpa;
6048 mem.size = size;
6049 while (mem.size) {
6050 if (kvm_vcpu_ioctl(CPU(cpu), KVM_PRE_FAULT_MEMORY, &mem)) {
6051 break;
6052 }
6053 }
6054
6055 return 0;
6056 }
6057
kvm_handle_hypercall(X86CPU * cpu,struct kvm_run * run)6058 static int kvm_handle_hypercall(X86CPU *cpu, struct kvm_run *run)
6059 {
6060 if (run->hypercall.nr == KVM_HC_MAP_GPA_RANGE)
6061 return kvm_handle_hc_map_gpa_range(cpu, run);
6062
6063 return -EINVAL;
6064 }
6065
6066 #define VMX_INVALID_GUEST_STATE 0x80000021
6067
kvm_arch_handle_exit(CPUState * cs,struct kvm_run * run)6068 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
6069 {
6070 X86CPU *cpu = X86_CPU(cs);
6071 uint64_t code;
6072 int ret;
6073 bool ctx_invalid;
6074 KVMState *state;
6075
6076 switch (run->exit_reason) {
6077 case KVM_EXIT_HLT:
6078 DPRINTF("handle_hlt\n");
6079 bql_lock();
6080 ret = kvm_handle_halt(cpu);
6081 bql_unlock();
6082 break;
6083 case KVM_EXIT_SET_TPR:
6084 ret = 0;
6085 break;
6086 case KVM_EXIT_TPR_ACCESS:
6087 bql_lock();
6088 ret = kvm_handle_tpr_access(cpu);
6089 bql_unlock();
6090 break;
6091 case KVM_EXIT_FAIL_ENTRY:
6092 code = run->fail_entry.hardware_entry_failure_reason;
6093 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
6094 code);
6095 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
6096 fprintf(stderr,
6097 "\nIf you're running a guest on an Intel machine without "
6098 "unrestricted mode\n"
6099 "support, the failure can be most likely due to the guest "
6100 "entering an invalid\n"
6101 "state for Intel VT. For example, the guest maybe running "
6102 "in big real mode\n"
6103 "which is not supported on less recent Intel processors."
6104 "\n\n");
6105 }
6106 ret = -1;
6107 break;
6108 case KVM_EXIT_EXCEPTION:
6109 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
6110 run->ex.exception, run->ex.error_code);
6111 ret = -1;
6112 break;
6113 case KVM_EXIT_DEBUG:
6114 DPRINTF("kvm_exit_debug\n");
6115 bql_lock();
6116 ret = kvm_handle_debug(cpu, &run->debug.arch);
6117 bql_unlock();
6118 break;
6119 case KVM_EXIT_HYPERV:
6120 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
6121 break;
6122 case KVM_EXIT_IOAPIC_EOI:
6123 ioapic_eoi_broadcast(run->eoi.vector);
6124 ret = 0;
6125 break;
6126 case KVM_EXIT_X86_BUS_LOCK:
6127 /* already handled in kvm_arch_post_run */
6128 ret = 0;
6129 break;
6130 case KVM_EXIT_NOTIFY:
6131 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
6132 state = KVM_STATE(current_accel());
6133 if (ctx_invalid ||
6134 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
6135 warn_report("KVM internal error: Encountered a notify exit "
6136 "with invalid context in guest.");
6137 ret = -1;
6138 } else {
6139 warn_report_once("KVM: Encountered a notify exit with valid "
6140 "context in guest. "
6141 "The guest could be misbehaving.");
6142 ret = 0;
6143 }
6144 break;
6145 case KVM_EXIT_X86_RDMSR:
6146 /* We only enable MSR filtering, any other exit is bogus */
6147 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6148 ret = kvm_handle_rdmsr(cpu, run);
6149 break;
6150 case KVM_EXIT_X86_WRMSR:
6151 /* We only enable MSR filtering, any other exit is bogus */
6152 assert(run->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
6153 ret = kvm_handle_wrmsr(cpu, run);
6154 break;
6155 #ifdef CONFIG_XEN_EMU
6156 case KVM_EXIT_XEN:
6157 ret = kvm_xen_handle_exit(cpu, &run->xen);
6158 break;
6159 #endif
6160 case KVM_EXIT_HYPERCALL:
6161 ret = kvm_handle_hypercall(cpu, run);
6162 break;
6163 case KVM_EXIT_SYSTEM_EVENT:
6164 switch (run->system_event.type) {
6165 case KVM_SYSTEM_EVENT_TDX_FATAL:
6166 ret = tdx_handle_report_fatal_error(cpu, run);
6167 break;
6168 default:
6169 ret = -1;
6170 break;
6171 }
6172 break;
6173 default:
6174 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
6175 ret = -1;
6176 break;
6177 }
6178
6179 return ret;
6180 }
6181
kvm_arch_stop_on_emulation_error(CPUState * cs)6182 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
6183 {
6184 X86CPU *cpu = X86_CPU(cs);
6185 CPUX86State *env = &cpu->env;
6186
6187 kvm_cpu_synchronize_state(cs);
6188 return !(env->cr[0] & CR0_PE_MASK) ||
6189 ((env->segs[R_CS].selector & 3) != 3);
6190 }
6191
kvm_arch_init_irq_routing(KVMState * s)6192 void kvm_arch_init_irq_routing(KVMState *s)
6193 {
6194 /* We know at this point that we're using the in-kernel
6195 * irqchip, so we can use irqfds, and on x86 we know
6196 * we can use msi via irqfd and GSI routing.
6197 */
6198 kvm_msi_via_irqfd_allowed = true;
6199 kvm_gsi_routing_allowed = true;
6200
6201 if (kvm_irqchip_is_split()) {
6202 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
6203 int i;
6204
6205 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
6206 MSI routes for signaling interrupts to the local apics. */
6207 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
6208 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
6209 error_report("Could not enable split IRQ mode.");
6210 exit(1);
6211 }
6212 }
6213 kvm_irqchip_commit_route_changes(&c);
6214 }
6215 }
6216
kvm_arch_irqchip_create(KVMState * s)6217 int kvm_arch_irqchip_create(KVMState *s)
6218 {
6219 int ret;
6220 if (kvm_kernel_irqchip_split()) {
6221 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
6222 if (ret) {
6223 error_report("Could not enable split irqchip mode: %s",
6224 strerror(-ret));
6225 exit(1);
6226 } else {
6227 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
6228 kvm_split_irqchip = true;
6229 return 1;
6230 }
6231 } else {
6232 return 0;
6233 }
6234 }
6235
kvm_swizzle_msi_ext_dest_id(uint64_t address)6236 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
6237 {
6238 CPUX86State *env;
6239 uint64_t ext_id;
6240
6241 if (!first_cpu) {
6242 return address;
6243 }
6244 env = &X86_CPU(first_cpu)->env;
6245 if (!(env->features[FEAT_KVM] & CPUID_KVM_MSI_EXT_DEST_ID)) {
6246 return address;
6247 }
6248
6249 /*
6250 * If the remappable format bit is set, or the upper bits are
6251 * already set in address_hi, or the low extended bits aren't
6252 * there anyway, do nothing.
6253 */
6254 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
6255 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
6256 return address;
6257 }
6258
6259 address &= ~ext_id;
6260 address |= ext_id << 35;
6261 return address;
6262 }
6263
kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry * route,uint64_t address,uint32_t data,PCIDevice * dev)6264 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
6265 uint64_t address, uint32_t data, PCIDevice *dev)
6266 {
6267 X86IOMMUState *iommu = x86_iommu_get_default();
6268
6269 if (iommu) {
6270 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
6271
6272 if (class->int_remap) {
6273 int ret;
6274 MSIMessage src, dst;
6275
6276 src.address = route->u.msi.address_hi;
6277 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
6278 src.address |= route->u.msi.address_lo;
6279 src.data = route->u.msi.data;
6280
6281 ret = class->int_remap(iommu, &src, &dst, dev ? \
6282 pci_requester_id(dev) : \
6283 X86_IOMMU_SID_INVALID);
6284 if (ret) {
6285 trace_kvm_x86_fixup_msi_error(route->gsi);
6286 return 1;
6287 }
6288
6289 /*
6290 * Handled untranslated compatibility format interrupt with
6291 * extended destination ID in the low bits 11-5. */
6292 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
6293
6294 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
6295 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
6296 route->u.msi.data = dst.data;
6297 return 0;
6298 }
6299 }
6300
6301 #ifdef CONFIG_XEN_EMU
6302 if (xen_mode == XEN_EMULATE) {
6303 int handled = xen_evtchn_translate_pirq_msi(route, address, data);
6304
6305 /*
6306 * If it was a PIRQ and successfully routed (handled == 0) or it was
6307 * an error (handled < 0), return. If it wasn't a PIRQ, keep going.
6308 */
6309 if (handled <= 0) {
6310 return handled;
6311 }
6312 }
6313 #endif
6314
6315 address = kvm_swizzle_msi_ext_dest_id(address);
6316 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
6317 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
6318 return 0;
6319 }
6320
6321 typedef struct MSIRouteEntry MSIRouteEntry;
6322
6323 struct MSIRouteEntry {
6324 PCIDevice *dev; /* Device pointer */
6325 int vector; /* MSI/MSIX vector index */
6326 int virq; /* Virtual IRQ index */
6327 QLIST_ENTRY(MSIRouteEntry) list;
6328 };
6329
6330 /* List of used GSI routes */
6331 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
6332 QLIST_HEAD_INITIALIZER(msi_route_list);
6333
kvm_update_msi_routes_all(void * private,bool global,uint32_t index,uint32_t mask)6334 void kvm_update_msi_routes_all(void *private, bool global,
6335 uint32_t index, uint32_t mask)
6336 {
6337 int cnt = 0, vector;
6338 MSIRouteEntry *entry;
6339 MSIMessage msg;
6340 PCIDevice *dev;
6341
6342 /* TODO: explicit route update */
6343 QLIST_FOREACH(entry, &msi_route_list, list) {
6344 cnt++;
6345 vector = entry->vector;
6346 dev = entry->dev;
6347 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
6348 msg = msix_get_message(dev, vector);
6349 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
6350 msg = msi_get_message(dev, vector);
6351 } else {
6352 /*
6353 * Either MSI/MSIX is disabled for the device, or the
6354 * specific message was masked out. Skip this one.
6355 */
6356 continue;
6357 }
6358 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
6359 }
6360 kvm_irqchip_commit_routes(kvm_state);
6361 trace_kvm_x86_update_msi_routes(cnt);
6362 }
6363
kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry * route,int vector,PCIDevice * dev)6364 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
6365 int vector, PCIDevice *dev)
6366 {
6367 static bool notify_list_inited = false;
6368 MSIRouteEntry *entry;
6369
6370 if (!dev) {
6371 /* These are (possibly) IOAPIC routes only used for split
6372 * kernel irqchip mode, while what we are housekeeping are
6373 * PCI devices only. */
6374 return 0;
6375 }
6376
6377 entry = g_new0(MSIRouteEntry, 1);
6378 entry->dev = dev;
6379 entry->vector = vector;
6380 entry->virq = route->gsi;
6381 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
6382
6383 trace_kvm_x86_add_msi_route(route->gsi);
6384
6385 if (!notify_list_inited) {
6386 /* For the first time we do add route, add ourselves into
6387 * IOMMU's IEC notify list if needed. */
6388 X86IOMMUState *iommu = x86_iommu_get_default();
6389 if (iommu) {
6390 x86_iommu_iec_register_notifier(iommu,
6391 kvm_update_msi_routes_all,
6392 NULL);
6393 }
6394 notify_list_inited = true;
6395 }
6396 return 0;
6397 }
6398
kvm_arch_release_virq_post(int virq)6399 int kvm_arch_release_virq_post(int virq)
6400 {
6401 MSIRouteEntry *entry, *next;
6402 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
6403 if (entry->virq == virq) {
6404 trace_kvm_x86_remove_msi_route(virq);
6405 QLIST_REMOVE(entry, list);
6406 g_free(entry);
6407 break;
6408 }
6409 }
6410 return 0;
6411 }
6412
kvm_arch_msi_data_to_gsi(uint32_t data)6413 int kvm_arch_msi_data_to_gsi(uint32_t data)
6414 {
6415 abort();
6416 }
6417
kvm_has_waitpkg(void)6418 bool kvm_has_waitpkg(void)
6419 {
6420 return has_msr_umwait;
6421 }
6422
6423 #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
6424
kvm_request_xsave_components(X86CPU * cpu,uint64_t mask)6425 void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
6426 {
6427 KVMState *s = kvm_state;
6428 uint64_t supported;
6429
6430 mask &= XSTATE_DYNAMIC_MASK;
6431 if (!mask) {
6432 return;
6433 }
6434 /*
6435 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
6436 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
6437 * about them already because they are not supported features.
6438 */
6439 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
6440 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
6441 mask &= supported;
6442
6443 while (mask) {
6444 int bit = ctz64(mask);
6445 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
6446 if (rc) {
6447 /*
6448 * Older kernel version (<5.17) do not support
6449 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
6450 * any dynamic feature from kvm_arch_get_supported_cpuid.
6451 */
6452 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
6453 "for feature bit %d", bit);
6454 }
6455 mask &= ~BIT_ULL(bit);
6456 }
6457 }
6458
kvm_arch_get_notify_vmexit(Object * obj,Error ** errp)6459 static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
6460 {
6461 KVMState *s = KVM_STATE(obj);
6462 return s->notify_vmexit;
6463 }
6464
kvm_arch_set_notify_vmexit(Object * obj,int value,Error ** errp)6465 static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
6466 {
6467 KVMState *s = KVM_STATE(obj);
6468
6469 if (s->fd != -1) {
6470 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6471 return;
6472 }
6473
6474 s->notify_vmexit = value;
6475 }
6476
kvm_arch_get_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6477 static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
6478 const char *name, void *opaque,
6479 Error **errp)
6480 {
6481 KVMState *s = KVM_STATE(obj);
6482 uint32_t value = s->notify_window;
6483
6484 visit_type_uint32(v, name, &value, errp);
6485 }
6486
kvm_arch_set_notify_window(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6487 static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
6488 const char *name, void *opaque,
6489 Error **errp)
6490 {
6491 KVMState *s = KVM_STATE(obj);
6492 uint32_t value;
6493
6494 if (s->fd != -1) {
6495 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
6496 return;
6497 }
6498
6499 if (!visit_type_uint32(v, name, &value, errp)) {
6500 return;
6501 }
6502
6503 s->notify_window = value;
6504 }
6505
kvm_arch_get_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6506 static void kvm_arch_get_xen_version(Object *obj, Visitor *v,
6507 const char *name, void *opaque,
6508 Error **errp)
6509 {
6510 KVMState *s = KVM_STATE(obj);
6511 uint32_t value = s->xen_version;
6512
6513 visit_type_uint32(v, name, &value, errp);
6514 }
6515
kvm_arch_set_xen_version(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6516 static void kvm_arch_set_xen_version(Object *obj, Visitor *v,
6517 const char *name, void *opaque,
6518 Error **errp)
6519 {
6520 KVMState *s = KVM_STATE(obj);
6521 Error *error = NULL;
6522 uint32_t value;
6523
6524 visit_type_uint32(v, name, &value, &error);
6525 if (error) {
6526 error_propagate(errp, error);
6527 return;
6528 }
6529
6530 s->xen_version = value;
6531 if (value && xen_mode == XEN_DISABLED) {
6532 xen_mode = XEN_EMULATE;
6533 }
6534 }
6535
kvm_arch_get_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6536 static void kvm_arch_get_xen_gnttab_max_frames(Object *obj, Visitor *v,
6537 const char *name, void *opaque,
6538 Error **errp)
6539 {
6540 KVMState *s = KVM_STATE(obj);
6541 uint16_t value = s->xen_gnttab_max_frames;
6542
6543 visit_type_uint16(v, name, &value, errp);
6544 }
6545
kvm_arch_set_xen_gnttab_max_frames(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6546 static void kvm_arch_set_xen_gnttab_max_frames(Object *obj, Visitor *v,
6547 const char *name, void *opaque,
6548 Error **errp)
6549 {
6550 KVMState *s = KVM_STATE(obj);
6551 Error *error = NULL;
6552 uint16_t value;
6553
6554 visit_type_uint16(v, name, &value, &error);
6555 if (error) {
6556 error_propagate(errp, error);
6557 return;
6558 }
6559
6560 s->xen_gnttab_max_frames = value;
6561 }
6562
kvm_arch_get_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6563 static void kvm_arch_get_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6564 const char *name, void *opaque,
6565 Error **errp)
6566 {
6567 KVMState *s = KVM_STATE(obj);
6568 uint16_t value = s->xen_evtchn_max_pirq;
6569
6570 visit_type_uint16(v, name, &value, errp);
6571 }
6572
kvm_arch_set_xen_evtchn_max_pirq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)6573 static void kvm_arch_set_xen_evtchn_max_pirq(Object *obj, Visitor *v,
6574 const char *name, void *opaque,
6575 Error **errp)
6576 {
6577 KVMState *s = KVM_STATE(obj);
6578 Error *error = NULL;
6579 uint16_t value;
6580
6581 visit_type_uint16(v, name, &value, &error);
6582 if (error) {
6583 error_propagate(errp, error);
6584 return;
6585 }
6586
6587 s->xen_evtchn_max_pirq = value;
6588 }
6589
kvm_arch_accel_class_init(ObjectClass * oc)6590 void kvm_arch_accel_class_init(ObjectClass *oc)
6591 {
6592 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
6593 &NotifyVmexitOption_lookup,
6594 kvm_arch_get_notify_vmexit,
6595 kvm_arch_set_notify_vmexit);
6596 object_class_property_set_description(oc, "notify-vmexit",
6597 "Enable notify VM exit");
6598
6599 object_class_property_add(oc, "notify-window", "uint32",
6600 kvm_arch_get_notify_window,
6601 kvm_arch_set_notify_window,
6602 NULL, NULL);
6603 object_class_property_set_description(oc, "notify-window",
6604 "Clock cycles without an event window "
6605 "after which a notification VM exit occurs");
6606
6607 object_class_property_add(oc, "xen-version", "uint32",
6608 kvm_arch_get_xen_version,
6609 kvm_arch_set_xen_version,
6610 NULL, NULL);
6611 object_class_property_set_description(oc, "xen-version",
6612 "Xen version to be emulated "
6613 "(in XENVER_version form "
6614 "e.g. 0x4000a for 4.10)");
6615
6616 object_class_property_add(oc, "xen-gnttab-max-frames", "uint16",
6617 kvm_arch_get_xen_gnttab_max_frames,
6618 kvm_arch_set_xen_gnttab_max_frames,
6619 NULL, NULL);
6620 object_class_property_set_description(oc, "xen-gnttab-max-frames",
6621 "Maximum number of grant table frames");
6622
6623 object_class_property_add(oc, "xen-evtchn-max-pirq", "uint16",
6624 kvm_arch_get_xen_evtchn_max_pirq,
6625 kvm_arch_set_xen_evtchn_max_pirq,
6626 NULL, NULL);
6627 object_class_property_set_description(oc, "xen-evtchn-max-pirq",
6628 "Maximum number of Xen PIRQs");
6629 }
6630
kvm_set_max_apic_id(uint32_t max_apic_id)6631 void kvm_set_max_apic_id(uint32_t max_apic_id)
6632 {
6633 kvm_vm_enable_cap(kvm_state, KVM_CAP_MAX_VCPU_ID, 0, max_apic_id);
6634 }
6635