1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2021 Google LLC
4 * Author: Fuad Tabba <tabba@google.com>
5 */
6
7 #include <linux/irqchip/arm-gic-v3.h>
8
9 #include <asm/kvm_asm.h>
10 #include <asm/kvm_mmu.h>
11
12 #include <hyp/adjust_pc.h>
13
14 #include <nvhe/pkvm.h>
15
16 #include "../../sys_regs.h"
17
18 /*
19 * Copies of the host's CPU features registers holding sanitized values at hyp.
20 */
21 u64 id_aa64pfr0_el1_sys_val;
22 u64 id_aa64pfr1_el1_sys_val;
23 u64 id_aa64isar0_el1_sys_val;
24 u64 id_aa64isar1_el1_sys_val;
25 u64 id_aa64isar2_el1_sys_val;
26 u64 id_aa64mmfr0_el1_sys_val;
27 u64 id_aa64mmfr1_el1_sys_val;
28 u64 id_aa64mmfr2_el1_sys_val;
29 u64 id_aa64smfr0_el1_sys_val;
30
31 struct pvm_ftr_bits {
32 bool sign;
33 u8 shift;
34 u8 width;
35 u8 max_val;
36 bool (*vm_supported)(const struct kvm *kvm);
37 };
38
39 #define __MAX_FEAT_FUNC(id, fld, max, func, sgn) \
40 { \
41 .sign = sgn, \
42 .shift = id##_##fld##_SHIFT, \
43 .width = id##_##fld##_WIDTH, \
44 .max_val = id##_##fld##_##max, \
45 .vm_supported = func, \
46 }
47
48 #define MAX_FEAT_FUNC(id, fld, max, func) \
49 __MAX_FEAT_FUNC(id, fld, max, func, id##_##fld##_SIGNED)
50
51 #define MAX_FEAT(id, fld, max) \
52 MAX_FEAT_FUNC(id, fld, max, NULL)
53
54 #define MAX_FEAT_ENUM(id, fld, max) \
55 __MAX_FEAT_FUNC(id, fld, max, NULL, false)
56
57 #define FEAT_END { .width = 0, }
58
vm_has_ptrauth(const struct kvm * kvm)59 static bool vm_has_ptrauth(const struct kvm *kvm)
60 {
61 if (!IS_ENABLED(CONFIG_ARM64_PTR_AUTH))
62 return false;
63
64 return (cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||
65 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&
66 kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_PTRAUTH_GENERIC);
67 }
68
vm_has_sve(const struct kvm * kvm)69 static bool vm_has_sve(const struct kvm *kvm)
70 {
71 return system_supports_sve() && kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_SVE);
72 }
73
74 /*
75 * Definitions for features to be allowed or restricted for protected guests.
76 *
77 * Each field in the masks represents the highest supported value for the
78 * feature. If a feature field is not present, it is not supported. Moreover,
79 * these are used to generate the guest's view of the feature registers.
80 *
81 * The approach for protected VMs is to at least support features that are:
82 * - Needed by common Linux distributions (e.g., floating point)
83 * - Trivial to support, e.g., supporting the feature does not introduce or
84 * require tracking of additional state in KVM
85 * - Cannot be trapped or prevent the guest from using anyway
86 */
87
88 static const struct pvm_ftr_bits pvmid_aa64pfr0[] = {
89 MAX_FEAT(ID_AA64PFR0_EL1, EL0, IMP),
90 MAX_FEAT(ID_AA64PFR0_EL1, EL1, IMP),
91 MAX_FEAT(ID_AA64PFR0_EL1, EL2, IMP),
92 MAX_FEAT(ID_AA64PFR0_EL1, EL3, IMP),
93 MAX_FEAT(ID_AA64PFR0_EL1, FP, FP16),
94 MAX_FEAT(ID_AA64PFR0_EL1, AdvSIMD, FP16),
95 MAX_FEAT(ID_AA64PFR0_EL1, GIC, IMP),
96 MAX_FEAT_FUNC(ID_AA64PFR0_EL1, SVE, IMP, vm_has_sve),
97 MAX_FEAT(ID_AA64PFR0_EL1, RAS, IMP),
98 MAX_FEAT(ID_AA64PFR0_EL1, DIT, IMP),
99 MAX_FEAT(ID_AA64PFR0_EL1, CSV2, IMP),
100 MAX_FEAT(ID_AA64PFR0_EL1, CSV3, IMP),
101 FEAT_END
102 };
103
104 static const struct pvm_ftr_bits pvmid_aa64pfr1[] = {
105 MAX_FEAT(ID_AA64PFR1_EL1, BT, IMP),
106 MAX_FEAT(ID_AA64PFR1_EL1, SSBS, SSBS2),
107 MAX_FEAT_ENUM(ID_AA64PFR1_EL1, MTE_frac, NI),
108 FEAT_END
109 };
110
111 static const struct pvm_ftr_bits pvmid_aa64mmfr0[] = {
112 MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40),
113 MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16),
114 MAX_FEAT(ID_AA64MMFR0_EL1, BIGEND, IMP),
115 MAX_FEAT(ID_AA64MMFR0_EL1, SNSMEM, IMP),
116 MAX_FEAT(ID_AA64MMFR0_EL1, BIGENDEL0, IMP),
117 MAX_FEAT(ID_AA64MMFR0_EL1, EXS, IMP),
118 FEAT_END
119 };
120
121 static const struct pvm_ftr_bits pvmid_aa64mmfr1[] = {
122 MAX_FEAT(ID_AA64MMFR1_EL1, HAFDBS, DBM),
123 MAX_FEAT_ENUM(ID_AA64MMFR1_EL1, VMIDBits, 16),
124 MAX_FEAT(ID_AA64MMFR1_EL1, HPDS, HPDS2),
125 MAX_FEAT(ID_AA64MMFR1_EL1, PAN, PAN3),
126 MAX_FEAT(ID_AA64MMFR1_EL1, SpecSEI, IMP),
127 MAX_FEAT(ID_AA64MMFR1_EL1, ETS, IMP),
128 MAX_FEAT(ID_AA64MMFR1_EL1, CMOW, IMP),
129 FEAT_END
130 };
131
132 static const struct pvm_ftr_bits pvmid_aa64mmfr2[] = {
133 MAX_FEAT(ID_AA64MMFR2_EL1, CnP, IMP),
134 MAX_FEAT(ID_AA64MMFR2_EL1, UAO, IMP),
135 MAX_FEAT(ID_AA64MMFR2_EL1, IESB, IMP),
136 MAX_FEAT(ID_AA64MMFR2_EL1, AT, IMP),
137 MAX_FEAT(ID_AA64MMFR2_EL1, IDS, IMP),
138 MAX_FEAT(ID_AA64MMFR2_EL1, TTL, IMP),
139 MAX_FEAT(ID_AA64MMFR2_EL1, BBM, 2),
140 MAX_FEAT(ID_AA64MMFR2_EL1, E0PD, IMP),
141 FEAT_END
142 };
143
144 static const struct pvm_ftr_bits pvmid_aa64isar1[] = {
145 MAX_FEAT(ID_AA64ISAR1_EL1, DPB, DPB2),
146 MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, APA, PAuth, vm_has_ptrauth),
147 MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, API, PAuth, vm_has_ptrauth),
148 MAX_FEAT(ID_AA64ISAR1_EL1, JSCVT, IMP),
149 MAX_FEAT(ID_AA64ISAR1_EL1, FCMA, IMP),
150 MAX_FEAT(ID_AA64ISAR1_EL1, LRCPC, LRCPC3),
151 MAX_FEAT(ID_AA64ISAR1_EL1, GPA, IMP),
152 MAX_FEAT(ID_AA64ISAR1_EL1, GPI, IMP),
153 MAX_FEAT(ID_AA64ISAR1_EL1, FRINTTS, IMP),
154 MAX_FEAT(ID_AA64ISAR1_EL1, SB, IMP),
155 MAX_FEAT(ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX),
156 MAX_FEAT(ID_AA64ISAR1_EL1, BF16, EBF16),
157 MAX_FEAT(ID_AA64ISAR1_EL1, DGH, IMP),
158 MAX_FEAT(ID_AA64ISAR1_EL1, I8MM, IMP),
159 FEAT_END
160 };
161
162 static const struct pvm_ftr_bits pvmid_aa64isar2[] = {
163 MAX_FEAT_FUNC(ID_AA64ISAR2_EL1, GPA3, IMP, vm_has_ptrauth),
164 MAX_FEAT_FUNC(ID_AA64ISAR2_EL1, APA3, PAuth, vm_has_ptrauth),
165 MAX_FEAT(ID_AA64ISAR2_EL1, ATS1A, IMP),
166 FEAT_END
167 };
168
169 /*
170 * None of the features in ID_AA64DFR0_EL1 nor ID_AA64MMFR4_EL1 are supported.
171 * However, both have Not-Implemented values that are non-zero. Define them
172 * so they can be used when getting the value of these registers.
173 */
174 #define ID_AA64DFR0_EL1_NONZERO_NI \
175 ( \
176 SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI) | \
177 SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, MTPMU, NI) \
178 )
179
180 #define ID_AA64MMFR4_EL1_NONZERO_NI \
181 SYS_FIELD_PREP_ENUM(ID_AA64MMFR4_EL1, E2H0, NI)
182
183 /*
184 * Returns the value of the feature registers based on the system register
185 * value, the vcpu support for the revelant features, and the additional
186 * restrictions for protected VMs.
187 */
get_restricted_features(const struct kvm_vcpu * vcpu,u64 sys_reg_val,const struct pvm_ftr_bits restrictions[])188 static u64 get_restricted_features(const struct kvm_vcpu *vcpu,
189 u64 sys_reg_val,
190 const struct pvm_ftr_bits restrictions[])
191 {
192 u64 val = 0UL;
193 int i;
194
195 for (i = 0; restrictions[i].width != 0; i++) {
196 bool (*vm_supported)(const struct kvm *) = restrictions[i].vm_supported;
197 bool sign = restrictions[i].sign;
198 int shift = restrictions[i].shift;
199 int width = restrictions[i].width;
200 u64 min_signed = (1UL << width) - 1UL;
201 u64 sign_bit = 1UL << (width - 1);
202 u64 mask = GENMASK_ULL(width + shift - 1, shift);
203 u64 sys_val = (sys_reg_val & mask) >> shift;
204 u64 pvm_max = restrictions[i].max_val;
205
206 if (vm_supported && !vm_supported(vcpu->kvm))
207 val |= (sign ? min_signed : 0) << shift;
208 else if (sign && (sys_val >= sign_bit || pvm_max >= sign_bit))
209 val |= max(sys_val, pvm_max) << shift;
210 else
211 val |= min(sys_val, pvm_max) << shift;
212 }
213
214 return val;
215 }
216
pvm_calc_id_reg(const struct kvm_vcpu * vcpu,u32 id)217 static u64 pvm_calc_id_reg(const struct kvm_vcpu *vcpu, u32 id)
218 {
219 switch (id) {
220 case SYS_ID_AA64PFR0_EL1:
221 return get_restricted_features(vcpu, id_aa64pfr0_el1_sys_val, pvmid_aa64pfr0);
222 case SYS_ID_AA64PFR1_EL1:
223 return get_restricted_features(vcpu, id_aa64pfr1_el1_sys_val, pvmid_aa64pfr1);
224 case SYS_ID_AA64ISAR0_EL1:
225 return id_aa64isar0_el1_sys_val;
226 case SYS_ID_AA64ISAR1_EL1:
227 return get_restricted_features(vcpu, id_aa64isar1_el1_sys_val, pvmid_aa64isar1);
228 case SYS_ID_AA64ISAR2_EL1:
229 return get_restricted_features(vcpu, id_aa64isar2_el1_sys_val, pvmid_aa64isar2);
230 case SYS_ID_AA64MMFR0_EL1:
231 return get_restricted_features(vcpu, id_aa64mmfr0_el1_sys_val, pvmid_aa64mmfr0);
232 case SYS_ID_AA64MMFR1_EL1:
233 return get_restricted_features(vcpu, id_aa64mmfr1_el1_sys_val, pvmid_aa64mmfr1);
234 case SYS_ID_AA64MMFR2_EL1:
235 return get_restricted_features(vcpu, id_aa64mmfr2_el1_sys_val, pvmid_aa64mmfr2);
236 case SYS_ID_AA64DFR0_EL1:
237 return ID_AA64DFR0_EL1_NONZERO_NI;
238 case SYS_ID_AA64MMFR4_EL1:
239 return ID_AA64MMFR4_EL1_NONZERO_NI;
240 default:
241 /* Unhandled ID register, RAZ */
242 return 0;
243 }
244 }
245
inject_sync64(struct kvm_vcpu * vcpu,u64 esr)246 static void inject_sync64(struct kvm_vcpu *vcpu, u64 esr)
247 {
248 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
249 *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR);
250
251 /*
252 * Make sure we have the latest update to VBAR_EL1, as pKVM
253 * handles traps very early, before sysregs are resync'ed
254 */
255 __vcpu_assign_sys_reg(vcpu, VBAR_EL1, read_sysreg_el1(SYS_VBAR));
256
257 kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
258
259 __kvm_adjust_pc(vcpu);
260
261 write_sysreg_el1(esr, SYS_ESR);
262 write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR);
263 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
264 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
265 }
266
267 /*
268 * Inject an unknown/undefined exception to an AArch64 guest while most of its
269 * sysregs are live.
270 */
inject_undef64(struct kvm_vcpu * vcpu)271 static void inject_undef64(struct kvm_vcpu *vcpu)
272 {
273 inject_sync64(vcpu, (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT));
274 }
275
read_id_reg(const struct kvm_vcpu * vcpu,struct sys_reg_desc const * r)276 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
277 struct sys_reg_desc const *r)
278 {
279 struct kvm *kvm = vcpu->kvm;
280 u32 reg = reg_to_encoding(r);
281
282 if (WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)))
283 return 0;
284
285 if (reg >= sys_reg(3, 0, 0, 1, 0) && reg <= sys_reg(3, 0, 0, 7, 7))
286 return kvm->arch.id_regs[IDREG_IDX(reg)];
287
288 return 0;
289 }
290
291 /* Handler to RAZ/WI sysregs */
pvm_access_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)292 static bool pvm_access_raz_wi(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
293 const struct sys_reg_desc *r)
294 {
295 if (!p->is_write)
296 p->regval = 0;
297
298 return true;
299 }
300
301 /*
302 * Accessor for AArch32 feature id registers.
303 *
304 * The value of these registers is "unknown" according to the spec if AArch32
305 * isn't supported.
306 */
pvm_access_id_aarch32(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)307 static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu,
308 struct sys_reg_params *p,
309 const struct sys_reg_desc *r)
310 {
311 if (p->is_write) {
312 inject_undef64(vcpu);
313 return false;
314 }
315
316 return pvm_access_raz_wi(vcpu, p, r);
317 }
318
319 /*
320 * Accessor for AArch64 feature id registers.
321 *
322 * If access is allowed, set the regval to the protected VM's view of the
323 * register and return true.
324 * Otherwise, inject an undefined exception and return false.
325 */
pvm_access_id_aarch64(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)326 static bool pvm_access_id_aarch64(struct kvm_vcpu *vcpu,
327 struct sys_reg_params *p,
328 const struct sys_reg_desc *r)
329 {
330 if (p->is_write) {
331 inject_undef64(vcpu);
332 return false;
333 }
334
335 p->regval = read_id_reg(vcpu, r);
336 return true;
337 }
338
pvm_gic_read_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)339 static bool pvm_gic_read_sre(struct kvm_vcpu *vcpu,
340 struct sys_reg_params *p,
341 const struct sys_reg_desc *r)
342 {
343 /* pVMs only support GICv3. 'nuf said. */
344 if (!p->is_write)
345 p->regval = ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE;
346
347 return true;
348 }
349
pvm_idst_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)350 static bool pvm_idst_access(struct kvm_vcpu *vcpu,
351 struct sys_reg_params *p,
352 const struct sys_reg_desc *r)
353 {
354 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, IMP))
355 inject_sync64(vcpu, kvm_vcpu_get_esr(vcpu));
356 else
357 inject_undef64(vcpu);
358
359 return false;
360 }
361
362 /* Mark the specified system register as an AArch32 feature id register. */
363 #define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 }
364
365 /* Mark the specified system register as an AArch64 feature id register. */
366 #define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 }
367
368 /*
369 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
370 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
371 * (1 <= crm < 8, 0 <= Op2 < 8).
372 */
373 #define ID_UNALLOCATED(crm, op2) { \
374 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
375 .access = pvm_access_id_aarch64, \
376 }
377
378 /* Mark the specified system register as Read-As-Zero/Write-Ignored */
379 #define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi }
380
381 /* Mark the specified system register as not being handled in hyp. */
382 #define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL }
383
384 /*
385 * Architected system registers.
386 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
387 *
388 * NOTE: Anything not explicitly listed here is *restricted by default*, i.e.,
389 * it will lead to injecting an exception into the guest.
390 */
391 static const struct sys_reg_desc pvm_sys_reg_descs[] = {
392 /* Cache maintenance by set/way operations are restricted. */
393
394 /* Debug and Trace Registers are restricted. */
395
396 /* Group 1 ID registers */
397 HOST_HANDLED(SYS_REVIDR_EL1),
398
399 /* AArch64 mappings of the AArch32 ID registers */
400 /* CRm=1 */
401 AARCH32(SYS_ID_PFR0_EL1),
402 AARCH32(SYS_ID_PFR1_EL1),
403 AARCH32(SYS_ID_DFR0_EL1),
404 AARCH32(SYS_ID_AFR0_EL1),
405 AARCH32(SYS_ID_MMFR0_EL1),
406 AARCH32(SYS_ID_MMFR1_EL1),
407 AARCH32(SYS_ID_MMFR2_EL1),
408 AARCH32(SYS_ID_MMFR3_EL1),
409
410 /* CRm=2 */
411 AARCH32(SYS_ID_ISAR0_EL1),
412 AARCH32(SYS_ID_ISAR1_EL1),
413 AARCH32(SYS_ID_ISAR2_EL1),
414 AARCH32(SYS_ID_ISAR3_EL1),
415 AARCH32(SYS_ID_ISAR4_EL1),
416 AARCH32(SYS_ID_ISAR5_EL1),
417 AARCH32(SYS_ID_MMFR4_EL1),
418 AARCH32(SYS_ID_ISAR6_EL1),
419
420 /* CRm=3 */
421 AARCH32(SYS_MVFR0_EL1),
422 AARCH32(SYS_MVFR1_EL1),
423 AARCH32(SYS_MVFR2_EL1),
424 ID_UNALLOCATED(3,3),
425 AARCH32(SYS_ID_PFR2_EL1),
426 AARCH32(SYS_ID_DFR1_EL1),
427 AARCH32(SYS_ID_MMFR5_EL1),
428 ID_UNALLOCATED(3,7),
429
430 /* AArch64 ID registers */
431 /* CRm=4 */
432 AARCH64(SYS_ID_AA64PFR0_EL1),
433 AARCH64(SYS_ID_AA64PFR1_EL1),
434 ID_UNALLOCATED(4,2),
435 ID_UNALLOCATED(4,3),
436 AARCH64(SYS_ID_AA64ZFR0_EL1),
437 ID_UNALLOCATED(4,5),
438 ID_UNALLOCATED(4,6),
439 ID_UNALLOCATED(4,7),
440 AARCH64(SYS_ID_AA64DFR0_EL1),
441 AARCH64(SYS_ID_AA64DFR1_EL1),
442 ID_UNALLOCATED(5,2),
443 ID_UNALLOCATED(5,3),
444 AARCH64(SYS_ID_AA64AFR0_EL1),
445 AARCH64(SYS_ID_AA64AFR1_EL1),
446 ID_UNALLOCATED(5,6),
447 ID_UNALLOCATED(5,7),
448 AARCH64(SYS_ID_AA64ISAR0_EL1),
449 AARCH64(SYS_ID_AA64ISAR1_EL1),
450 AARCH64(SYS_ID_AA64ISAR2_EL1),
451 ID_UNALLOCATED(6,3),
452 ID_UNALLOCATED(6,4),
453 ID_UNALLOCATED(6,5),
454 ID_UNALLOCATED(6,6),
455 ID_UNALLOCATED(6,7),
456 AARCH64(SYS_ID_AA64MMFR0_EL1),
457 AARCH64(SYS_ID_AA64MMFR1_EL1),
458 AARCH64(SYS_ID_AA64MMFR2_EL1),
459 ID_UNALLOCATED(7,3),
460 ID_UNALLOCATED(7,4),
461 ID_UNALLOCATED(7,5),
462 ID_UNALLOCATED(7,6),
463 ID_UNALLOCATED(7,7),
464
465 /* Scalable Vector Registers are restricted. */
466
467 HOST_HANDLED(SYS_ICC_PMR_EL1),
468
469 RAZ_WI(SYS_ERRIDR_EL1),
470 RAZ_WI(SYS_ERRSELR_EL1),
471 RAZ_WI(SYS_ERXFR_EL1),
472 RAZ_WI(SYS_ERXCTLR_EL1),
473 RAZ_WI(SYS_ERXSTATUS_EL1),
474 RAZ_WI(SYS_ERXADDR_EL1),
475 RAZ_WI(SYS_ERXMISC0_EL1),
476 RAZ_WI(SYS_ERXMISC1_EL1),
477
478 /* Performance Monitoring Registers are restricted. */
479
480 /* Limited Ordering Regions Registers are restricted. */
481
482 HOST_HANDLED(SYS_ICC_DIR_EL1),
483 HOST_HANDLED(SYS_ICC_RPR_EL1),
484 HOST_HANDLED(SYS_ICC_SGI1R_EL1),
485 HOST_HANDLED(SYS_ICC_ASGI1R_EL1),
486 HOST_HANDLED(SYS_ICC_SGI0R_EL1),
487 HOST_HANDLED(SYS_ICC_CTLR_EL1),
488 { SYS_DESC(SYS_ICC_SRE_EL1), .access = pvm_gic_read_sre, },
489
490 HOST_HANDLED(SYS_CCSIDR_EL1),
491 HOST_HANDLED(SYS_CLIDR_EL1),
492 { SYS_DESC(SYS_CCSIDR2_EL1), .access = pvm_idst_access },
493 { SYS_DESC(SYS_GMID_EL1), .access = pvm_idst_access },
494 { SYS_DESC(SYS_SMIDR_EL1), .access = pvm_idst_access },
495 HOST_HANDLED(SYS_AIDR_EL1),
496 HOST_HANDLED(SYS_CSSELR_EL1),
497 HOST_HANDLED(SYS_CTR_EL0),
498
499 /* Performance Monitoring Registers are restricted. */
500
501 /* Activity Monitoring Registers are restricted. */
502
503 HOST_HANDLED(SYS_CNTP_TVAL_EL0),
504 HOST_HANDLED(SYS_CNTP_CTL_EL0),
505 HOST_HANDLED(SYS_CNTP_CVAL_EL0),
506
507 /* Performance Monitoring Registers are restricted. */
508 };
509
510 /*
511 * Initializes feature registers for protected vms.
512 */
kvm_init_pvm_id_regs(struct kvm_vcpu * vcpu)513 void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu)
514 {
515 struct kvm *kvm = vcpu->kvm;
516 struct kvm_arch *ka = &kvm->arch;
517 u32 r;
518
519 hyp_assert_lock_held(&vm_table_lock);
520
521 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
522 return;
523
524 /*
525 * Initialize only AArch64 id registers since AArch32 isn't supported
526 * for protected VMs.
527 */
528 for (r = sys_reg(3, 0, 0, 4, 0); r <= sys_reg(3, 0, 0, 7, 7); r += sys_reg(0, 0, 0, 0, 1))
529 ka->id_regs[IDREG_IDX(r)] = pvm_calc_id_reg(vcpu, r);
530
531 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
532 }
533
534 /*
535 * Checks that the sysreg table is unique and in-order.
536 *
537 * Returns 0 if the table is consistent, or 1 otherwise.
538 */
kvm_check_pvm_sysreg_table(void)539 int kvm_check_pvm_sysreg_table(void)
540 {
541 unsigned int i;
542
543 for (i = 1; i < ARRAY_SIZE(pvm_sys_reg_descs); i++) {
544 if (cmp_sys_reg(&pvm_sys_reg_descs[i-1], &pvm_sys_reg_descs[i]) >= 0)
545 return 1;
546 }
547
548 return 0;
549 }
550
551 /*
552 * Handler for protected VM MSR, MRS or System instruction execution.
553 *
554 * Returns true if the hypervisor has handled the exit, and control should go
555 * back to the guest, or false if it hasn't, to be handled by the host.
556 */
kvm_handle_pvm_sysreg(struct kvm_vcpu * vcpu,u64 * exit_code)557 bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
558 {
559 const struct sys_reg_desc *r;
560 struct sys_reg_params params;
561 unsigned long esr = kvm_vcpu_get_esr(vcpu);
562 int Rt = kvm_vcpu_sys_get_rt(vcpu);
563
564 params = esr_sys64_to_params(esr);
565 params.regval = vcpu_get_reg(vcpu, Rt);
566
567 r = find_reg(¶ms, pvm_sys_reg_descs, ARRAY_SIZE(pvm_sys_reg_descs));
568
569 /* Undefined (RESTRICTED). */
570 if (r == NULL) {
571 inject_undef64(vcpu);
572 return true;
573 }
574
575 /* Handled by the host (HOST_HANDLED) */
576 if (r->access == NULL)
577 return false;
578
579 /* Handled by hyp: skip instruction if instructed to do so. */
580 if (r->access(vcpu, ¶ms, r))
581 __kvm_skip_instr(vcpu);
582
583 if (!params.is_write)
584 vcpu_set_reg(vcpu, Rt, params.regval);
585
586 return true;
587 }
588
589 /*
590 * Handler for protected VM restricted exceptions.
591 *
592 * Inject an undefined exception into the guest and return true to indicate that
593 * the hypervisor has handled the exit, and control should go back to the guest.
594 */
kvm_handle_pvm_restricted(struct kvm_vcpu * vcpu,u64 * exit_code)595 bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code)
596 {
597 inject_undef64(vcpu);
598 return true;
599 }
600