1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip KSZ8XXX series switch driver
4 *
5 * It supports the following switches:
6 * - KSZ8463
7 * - KSZ8863, KSZ8873 aka KSZ88X3
8 * - KSZ8895, KSZ8864 aka KSZ8895 family
9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX
10 * Note that it does NOT support:
11 * - KSZ8563, KSZ8567 - see KSZ9477 driver
12 *
13 * Copyright (C) 2017 Microchip Technology Inc.
14 * Tristram Ha <Tristram.Ha@microchip.com>
15 */
16
17 #include <linux/bitfield.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/gpio.h>
21 #include <linux/if_vlan.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_data/microchip-ksz.h>
25 #include <linux/phy.h>
26 #include <linux/etherdevice.h>
27 #include <linux/if_bridge.h>
28 #include <linux/micrel_phy.h>
29 #include <net/dsa.h>
30 #include <net/switchdev.h>
31 #include <linux/phylink.h>
32
33 #include "ksz_common.h"
34 #include "ksz8_reg.h"
35 #include "ksz8.h"
36
ksz_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)37 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
38 {
39 ksz_rmw8(dev, addr, bits, set ? bits : 0);
40 }
41
ksz_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)42 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
43 bool set)
44 {
45 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits,
46 set ? bits : 0);
47 }
48
49 /**
50 * ksz8_ind_write8 - EEE/ACL/PME indirect register write
51 * @dev: The device structure.
52 * @table: Function & table select, register 110.
53 * @addr: Indirect access control, register 111.
54 * @data: The data to be written.
55 *
56 * This function performs an indirect register write for EEE, ACL or
57 * PME switch functionalities. Both 8-bit registers 110 and 111 are
58 * written at once with ksz_write16, using the serial multiple write
59 * functionality.
60 *
61 * Return: 0 on success, or an error code on failure.
62 */
ksz8_ind_write8(struct ksz_device * dev,u8 table,u16 addr,u8 data)63 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
64 {
65 const u16 *regs;
66 u16 ctrl_addr;
67 int ret = 0;
68
69 regs = dev->info->regs;
70
71 mutex_lock(&dev->alu_mutex);
72
73 ctrl_addr = IND_ACC_TABLE(table) | addr;
74 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
75 if (!ret)
76 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
77
78 mutex_unlock(&dev->alu_mutex);
79
80 return ret;
81 }
82
83 /**
84 * ksz8_ind_read8 - EEE/ACL/PME indirect register read
85 * @dev: The device structure.
86 * @table: Function & table select, register 110.
87 * @addr: Indirect access control, register 111.
88 * @val: The value read.
89 *
90 * This function performs an indirect register read for EEE, ACL or
91 * PME switch functionalities. Both 8-bit registers 110 and 111 are
92 * written at once with ksz_write16, using the serial multiple write
93 * functionality.
94 *
95 * Return: 0 on success, or an error code on failure.
96 */
ksz8_ind_read8(struct ksz_device * dev,u8 table,u16 addr,u8 * val)97 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val)
98 {
99 const u16 *regs;
100 u16 ctrl_addr;
101 int ret = 0;
102
103 regs = dev->info->regs;
104
105 mutex_lock(&dev->alu_mutex);
106
107 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
108 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
109 if (!ret)
110 ret = ksz_read8(dev, regs[REG_IND_BYTE], val);
111
112 mutex_unlock(&dev->alu_mutex);
113
114 return ret;
115 }
116
ksz8_pme_write8(struct ksz_device * dev,u32 reg,u8 value)117 int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value)
118 {
119 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value);
120 }
121
ksz8_pme_pread8(struct ksz_device * dev,int port,int offset,u8 * data)122 int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data)
123 {
124 u8 table = (u8)(offset >> 8 | (port + 1));
125
126 return ksz8_ind_read8(dev, table, (u8)(offset), data);
127 }
128
ksz8_pme_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)129 int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data)
130 {
131 u8 table = (u8)(offset >> 8 | (port + 1));
132
133 return ksz8_ind_write8(dev, table, (u8)(offset), data);
134 }
135
ksz8_reset_switch(struct ksz_device * dev)136 int ksz8_reset_switch(struct ksz_device *dev)
137 {
138 if (ksz_is_ksz88x3(dev)) {
139 /* reset switch */
140 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
141 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
142 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
143 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
144 } else if (ksz_is_ksz8463(dev)) {
145 ksz_cfg(dev, KSZ8463_REG_SW_RESET,
146 KSZ8463_GLOBAL_SOFTWARE_RESET, true);
147 ksz_cfg(dev, KSZ8463_REG_SW_RESET,
148 KSZ8463_GLOBAL_SOFTWARE_RESET, false);
149 } else {
150 /* reset switch */
151 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
152 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
153 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
154 }
155
156 return 0;
157 }
158
ksz8863_change_mtu(struct ksz_device * dev,int frame_size)159 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size)
160 {
161 u8 ctrl2 = 0;
162
163 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE)
164 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE;
165 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
166 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE;
167
168 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE |
169 KSZ8863_HUGE_PACKET_ENABLE, ctrl2);
170 }
171
ksz8795_change_mtu(struct ksz_device * dev,int frame_size)172 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size)
173 {
174 u8 ctrl1 = 0, ctrl2 = 0;
175 int ret;
176
177 if (frame_size > KSZ8_LEGAL_PACKET_SIZE)
178 ctrl2 |= SW_LEGAL_PACKET_DISABLE;
179 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
180 ctrl1 |= SW_HUGE_PACKET;
181
182 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1);
183 if (ret)
184 return ret;
185
186 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2);
187 }
188
ksz8_change_mtu(struct ksz_device * dev,int port,int mtu)189 int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu)
190 {
191 u16 frame_size;
192
193 if (!dsa_is_cpu_port(dev->ds, port))
194 return 0;
195
196 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
197
198 switch (dev->chip_id) {
199 case KSZ8795_CHIP_ID:
200 case KSZ8794_CHIP_ID:
201 case KSZ8765_CHIP_ID:
202 return ksz8795_change_mtu(dev, frame_size);
203 case KSZ8463_CHIP_ID:
204 case KSZ88X3_CHIP_ID:
205 case KSZ8864_CHIP_ID:
206 case KSZ8895_CHIP_ID:
207 return ksz8863_change_mtu(dev, frame_size);
208 }
209
210 return -EOPNOTSUPP;
211 }
212
ksz8_port_queue_split(struct ksz_device * dev,int port,int queues)213 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues)
214 {
215 u8 mask_4q, mask_2q;
216 u8 reg_4q, reg_2q;
217 u8 data_4q = 0;
218 u8 data_2q = 0;
219 int ret;
220
221 if (ksz_is_ksz88x3(dev)) {
222 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN;
223 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN;
224 reg_4q = REG_PORT_CTRL_0;
225 reg_2q = REG_PORT_CTRL_2;
226
227 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ)
228 * enabled by default. Enable it for KSZ8873 family switches
229 * too. Default value for KSZ8873 family is strict priority,
230 * which should be enabled by using TC_SETUP_QDISC_ETS, not
231 * by default.
232 */
233 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE,
234 WEIGHTED_FAIR_QUEUE_ENABLE);
235 if (ret)
236 return ret;
237 } else if (ksz_is_ksz8463(dev)) {
238 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN;
239 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN;
240 reg_4q = P1CR1;
241 reg_2q = P1CR1 + 1;
242 } else {
243 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN;
244 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN;
245 reg_4q = REG_PORT_CTRL_13;
246 reg_2q = REG_PORT_CTRL_0;
247
248 /* TODO: this is legacy from initial KSZ8795 driver, should be
249 * moved to appropriate place in the future.
250 */
251 ret = ksz_rmw8(dev, REG_SW_CTRL_19,
252 SW_OUT_RATE_LIMIT_QUEUE_BASED,
253 SW_OUT_RATE_LIMIT_QUEUE_BASED);
254 if (ret)
255 return ret;
256 }
257
258 if (queues == 4)
259 data_4q = mask_4q;
260 else if (queues == 2)
261 data_2q = mask_2q;
262
263 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q);
264 if (ret)
265 return ret;
266
267 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q);
268 }
269
ksz8_all_queues_split(struct ksz_device * dev,int queues)270 int ksz8_all_queues_split(struct ksz_device *dev, int queues)
271 {
272 struct dsa_switch *ds = dev->ds;
273 const struct dsa_port *dp;
274
275 dsa_switch_for_each_port(dp, ds) {
276 int ret = ksz8_port_queue_split(dev, dp->index, queues);
277
278 if (ret)
279 return ret;
280 }
281
282 return 0;
283 }
284
ksz8_r_mib_cnt(struct ksz_device * dev,int port,u16 addr,u64 * cnt)285 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
286 {
287 const u32 *masks;
288 const u16 *regs;
289 u16 ctrl_addr;
290 u32 data;
291 u8 check;
292 int loop;
293
294 masks = dev->info->masks;
295 regs = dev->info->regs;
296
297 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
298 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
299
300 mutex_lock(&dev->alu_mutex);
301 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
302
303 /* It is almost guaranteed to always read the valid bit because of
304 * slow SPI speed.
305 */
306 for (loop = 2; loop > 0; loop--) {
307 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
308
309 if (check & masks[MIB_COUNTER_VALID]) {
310 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
311 if (check & masks[MIB_COUNTER_OVERFLOW])
312 *cnt += MIB_COUNTER_VALUE + 1;
313 *cnt += data & MIB_COUNTER_VALUE;
314 break;
315 }
316 }
317 mutex_unlock(&dev->alu_mutex);
318 }
319
ksz8795_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)320 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
321 u64 *dropped, u64 *cnt)
322 {
323 const u32 *masks;
324 const u16 *regs;
325 u16 ctrl_addr;
326 u32 data;
327 u8 check;
328 int loop;
329
330 masks = dev->info->masks;
331 regs = dev->info->regs;
332
333 addr -= dev->info->reg_mib_cnt;
334 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
335 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
336 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
337
338 mutex_lock(&dev->alu_mutex);
339 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
340
341 /* It is almost guaranteed to always read the valid bit because of
342 * slow SPI speed.
343 */
344 for (loop = 2; loop > 0; loop--) {
345 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
346
347 if (check & masks[MIB_COUNTER_VALID]) {
348 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
349 if (addr < 2) {
350 u64 total;
351
352 total = check & MIB_TOTAL_BYTES_H;
353 total <<= 32;
354 *cnt += total;
355 *cnt += data;
356 if (check & masks[MIB_COUNTER_OVERFLOW]) {
357 total = MIB_TOTAL_BYTES_H + 1;
358 total <<= 32;
359 *cnt += total;
360 }
361 } else {
362 if (check & masks[MIB_COUNTER_OVERFLOW])
363 *cnt += MIB_PACKET_DROPPED + 1;
364 *cnt += data & MIB_PACKET_DROPPED;
365 }
366 break;
367 }
368 }
369 mutex_unlock(&dev->alu_mutex);
370 }
371
ksz8863_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)372 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
373 u64 *dropped, u64 *cnt)
374 {
375 u32 *last = (u32 *)dropped;
376 const u16 *regs;
377 u16 ctrl_addr;
378 u32 data;
379 u32 cur;
380
381 regs = dev->info->regs;
382
383 addr -= dev->info->reg_mib_cnt;
384 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
385 KSZ8863_MIB_PACKET_DROPPED_RX_0;
386 if (ksz_is_8895_family(dev) &&
387 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0)
388 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0;
389 ctrl_addr += port;
390 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
391
392 mutex_lock(&dev->alu_mutex);
393 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
394 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
395 mutex_unlock(&dev->alu_mutex);
396
397 data &= MIB_PACKET_DROPPED;
398 cur = last[addr];
399 if (data != cur) {
400 last[addr] = data;
401 if (data < cur)
402 data += MIB_PACKET_DROPPED + 1;
403 data -= cur;
404 *cnt += data;
405 }
406 }
407
ksz8_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)408 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
409 u64 *dropped, u64 *cnt)
410 {
411 if (is_ksz88xx(dev))
412 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
413 else
414 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
415 }
416
ksz8_freeze_mib(struct ksz_device * dev,int port,bool freeze)417 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
418 {
419 if (is_ksz88xx(dev))
420 return;
421
422 /* enable the port for flush/freeze function */
423 if (freeze)
424 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
425 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
426
427 /* disable the port after freeze is done */
428 if (!freeze)
429 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
430 }
431
ksz8_port_init_cnt(struct ksz_device * dev,int port)432 void ksz8_port_init_cnt(struct ksz_device *dev, int port)
433 {
434 struct ksz_port_mib *mib = &dev->ports[port].mib;
435 u64 *dropped;
436
437 /* For KSZ8795 family. */
438 if (ksz_is_ksz87xx(dev)) {
439 /* flush all enabled port MIB counters */
440 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
441 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
442 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
443 }
444
445 mib->cnt_ptr = 0;
446
447 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
448 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
449 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
450 &mib->counters[mib->cnt_ptr]);
451 ++mib->cnt_ptr;
452 }
453
454 /* last one in storage */
455 dropped = &mib->counters[dev->info->mib_cnt];
456
457 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
458 while (mib->cnt_ptr < dev->info->mib_cnt) {
459 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
460 dropped, &mib->counters[mib->cnt_ptr]);
461 ++mib->cnt_ptr;
462 }
463 }
464
ksz8_r_table(struct ksz_device * dev,int table,u16 addr,u64 * data)465 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
466 {
467 const u16 *regs;
468 u16 ctrl_addr;
469 int ret;
470
471 regs = dev->info->regs;
472
473 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
474
475 mutex_lock(&dev->alu_mutex);
476 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
477 if (ret)
478 goto unlock_alu;
479
480 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data);
481 unlock_alu:
482 mutex_unlock(&dev->alu_mutex);
483
484 return ret;
485 }
486
ksz8_w_table(struct ksz_device * dev,int table,u16 addr,u64 data)487 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
488 {
489 const u16 *regs;
490 u16 ctrl_addr;
491 int ret;
492
493 regs = dev->info->regs;
494
495 ctrl_addr = IND_ACC_TABLE(table) | addr;
496
497 mutex_lock(&dev->alu_mutex);
498 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data);
499 if (ret)
500 goto unlock_alu;
501
502 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
503 unlock_alu:
504 mutex_unlock(&dev->alu_mutex);
505
506 return ret;
507 }
508
ksz8_valid_dyn_entry(struct ksz_device * dev,u8 * data)509 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
510 {
511 int timeout = 100;
512 const u32 *masks;
513 const u16 *regs;
514 int ret;
515
516 masks = dev->info->masks;
517 regs = dev->info->regs;
518
519 do {
520 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
521 if (ret)
522 return ret;
523
524 timeout--;
525 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
526
527 /* Entry is not ready for accessing. */
528 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY])
529 return -ETIMEDOUT;
530
531 /* Entry is ready for accessing. */
532 return ksz_read8(dev, regs[REG_IND_DATA_8], data);
533 }
534
ksz8_r_dyn_mac_table(struct ksz_device * dev,u16 addr,u8 * mac_addr,u8 * fid,u8 * src_port,u16 * entries)535 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
536 u8 *fid, u8 *src_port, u16 *entries)
537 {
538 u32 data_hi, data_lo;
539 const u8 *shifts;
540 const u32 *masks;
541 const u16 *regs;
542 u16 ctrl_addr;
543 u64 buf = 0;
544 u8 data;
545 int cnt;
546 int ret;
547
548 shifts = dev->info->shifts;
549 masks = dev->info->masks;
550 regs = dev->info->regs;
551
552 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
553
554 mutex_lock(&dev->alu_mutex);
555 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
556 if (ret)
557 goto unlock_alu;
558
559 ret = ksz8_valid_dyn_entry(dev, &data);
560 if (ret)
561 goto unlock_alu;
562
563 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) {
564 *entries = 0;
565 goto unlock_alu;
566 }
567
568 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
569 if (ret)
570 goto unlock_alu;
571
572 data_hi = (u32)(buf >> 32);
573 data_lo = (u32)buf;
574
575 /* Check out how many valid entry in the table. */
576 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
577 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
578 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
579 shifts[DYNAMIC_MAC_ENTRIES];
580 *entries = cnt + 1;
581
582 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
583 shifts[DYNAMIC_MAC_FID];
584 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
585 shifts[DYNAMIC_MAC_SRC_PORT];
586
587 mac_addr[5] = (u8)data_lo;
588 mac_addr[4] = (u8)(data_lo >> 8);
589 mac_addr[3] = (u8)(data_lo >> 16);
590 mac_addr[2] = (u8)(data_lo >> 24);
591
592 mac_addr[1] = (u8)data_hi;
593 mac_addr[0] = (u8)(data_hi >> 8);
594
595 unlock_alu:
596 mutex_unlock(&dev->alu_mutex);
597
598 return ret;
599 }
600
ksz8_r_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu,bool * valid)601 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
602 struct alu_struct *alu, bool *valid)
603 {
604 u32 data_hi, data_lo;
605 const u8 *shifts;
606 const u32 *masks;
607 u64 data;
608 int ret;
609
610 shifts = dev->info->shifts;
611 masks = dev->info->masks;
612
613 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
614 if (ret)
615 return ret;
616
617 data_hi = data >> 32;
618 data_lo = (u32)data;
619
620 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] |
621 masks[STATIC_MAC_TABLE_OVERRIDE]))) {
622 *valid = false;
623 return 0;
624 }
625
626 alu->mac[5] = (u8)data_lo;
627 alu->mac[4] = (u8)(data_lo >> 8);
628 alu->mac[3] = (u8)(data_lo >> 16);
629 alu->mac[2] = (u8)(data_lo >> 24);
630 alu->mac[1] = (u8)data_hi;
631 alu->mac[0] = (u8)(data_hi >> 8);
632 alu->port_forward =
633 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
634 shifts[STATIC_MAC_FWD_PORTS];
635 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
636
637 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and
638 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the
639 * static MAC table compared to doing write.
640 */
641 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
642 data_hi >>= 1;
643 alu->is_static = true;
644 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
645 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
646 shifts[STATIC_MAC_FID];
647
648 *valid = true;
649
650 return 0;
651 }
652
ksz8_w_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu)653 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
654 struct alu_struct *alu)
655 {
656 u32 data_hi, data_lo;
657 const u8 *shifts;
658 const u32 *masks;
659 u64 data;
660
661 shifts = dev->info->shifts;
662 masks = dev->info->masks;
663
664 data_lo = ((u32)alu->mac[2] << 24) |
665 ((u32)alu->mac[3] << 16) |
666 ((u32)alu->mac[4] << 8) | alu->mac[5];
667 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
668 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
669
670 if (alu->is_override)
671 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
672 if (alu->is_use_fid) {
673 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
674 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
675 }
676 if (alu->is_static)
677 data_hi |= masks[STATIC_MAC_TABLE_VALID];
678 else
679 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
680
681 data = (u64)data_hi << 32 | data_lo;
682
683 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
684 }
685
ksz8_from_vlan(struct ksz_device * dev,u32 vlan,u8 * fid,u8 * member,u8 * valid)686 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
687 u8 *member, u8 *valid)
688 {
689 const u8 *shifts;
690 const u32 *masks;
691
692 shifts = dev->info->shifts;
693 masks = dev->info->masks;
694
695 *fid = vlan & masks[VLAN_TABLE_FID];
696 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
697 shifts[VLAN_TABLE_MEMBERSHIP_S];
698 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
699 }
700
ksz8_to_vlan(struct ksz_device * dev,u8 fid,u8 member,u8 valid,u16 * vlan)701 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
702 u16 *vlan)
703 {
704 const u8 *shifts;
705 const u32 *masks;
706
707 shifts = dev->info->shifts;
708 masks = dev->info->masks;
709
710 *vlan = fid;
711 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
712 if (valid)
713 *vlan |= masks[VLAN_TABLE_VALID];
714 }
715
ksz8_r_vlan_entries(struct ksz_device * dev,u16 addr)716 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
717 {
718 const u8 *shifts;
719 u64 data;
720 int i;
721
722 shifts = dev->info->shifts;
723
724 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
725 addr *= 4;
726 for (i = 0; i < 4; i++) {
727 dev->vlan_cache[addr + i].table[0] = (u16)data;
728 data >>= shifts[VLAN_TABLE];
729 }
730 }
731
ksz8_r_vlan_table(struct ksz_device * dev,u16 vid,u16 * vlan)732 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
733 {
734 int index;
735 u16 *data;
736 u16 addr;
737 u64 buf;
738
739 data = (u16 *)&buf;
740 addr = vid / 4;
741 index = vid & 3;
742 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
743 *vlan = data[index];
744 }
745
ksz8_w_vlan_table(struct ksz_device * dev,u16 vid,u16 vlan)746 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
747 {
748 int index;
749 u16 *data;
750 u16 addr;
751 u64 buf;
752
753 data = (u16 *)&buf;
754 addr = vid / 4;
755 index = vid & 3;
756 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
757 data[index] = vlan;
758 dev->vlan_cache[vid].table[0] = vlan;
759 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
760 }
761
762 /**
763 * ksz879x_get_loopback - KSZ879x specific function to get loopback
764 * configuration status for a specific port
765 * @dev: Pointer to the device structure
766 * @port: Port number to query
767 * @val: Pointer to store the result
768 *
769 * This function reads the SMI registers to determine whether loopback mode
770 * is enabled for a specific port.
771 *
772 * Return: 0 on success, error code on failure.
773 */
ksz879x_get_loopback(struct ksz_device * dev,u16 port,u16 * val)774 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port,
775 u16 *val)
776 {
777 u8 stat3;
778 int ret;
779
780 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3);
781 if (ret)
782 return ret;
783
784 if (stat3 & PORT_PHY_LOOPBACK)
785 *val |= BMCR_LOOPBACK;
786
787 return 0;
788 }
789
790 /**
791 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for
792 * a specific port
793 * @dev: Pointer to the device structure.
794 * @port: Port number to modify.
795 * @val: Value indicating whether to enable or disable loopback mode.
796 *
797 * This function translates loopback bit of the BMCR register into the
798 * corresponding hardware register bit value and writes it to the SMI interface.
799 *
800 * Return: 0 on success, error code on failure.
801 */
ksz879x_set_loopback(struct ksz_device * dev,u16 port,u16 val)802 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val)
803 {
804 u8 stat3 = 0;
805
806 if (val & BMCR_LOOPBACK)
807 stat3 |= PORT_PHY_LOOPBACK;
808
809 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK,
810 stat3);
811 }
812
813 /**
814 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
815 * Control register (Reg. 31).
816 * @dev: The KSZ device instance.
817 * @port: The port number to be read.
818 * @val: The value read from the SMI interface.
819 *
820 * This function reads the SMI interface and translates the hardware register
821 * bit values into their corresponding control settings for a MIIM PHY Control
822 * register.
823 *
824 * Return: 0 on success, error code on failure.
825 */
ksz8_r_phy_ctrl(struct ksz_device * dev,int port,u16 * val)826 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val)
827 {
828 const u16 *regs = dev->info->regs;
829 u8 reg_val;
830 int ret;
831
832 *val = 0;
833
834 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val);
835 if (ret < 0)
836 return ret;
837
838 if (reg_val & PORT_MDIX_STATUS)
839 *val |= KSZ886X_CTRL_MDIX_STAT;
840
841 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val);
842 if (ret < 0)
843 return ret;
844
845 if (reg_val & PORT_FORCE_LINK)
846 *val |= KSZ886X_CTRL_FORCE_LINK;
847
848 if (reg_val & PORT_POWER_SAVING)
849 *val |= KSZ886X_CTRL_PWRSAVE;
850
851 if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
852 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK;
853
854 return 0;
855 }
856
857 /**
858 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY
859 * Basic mode control register (Reg. 0).
860 * @dev: The KSZ device instance.
861 * @port: The port number to be read.
862 * @val: The value read from the SMI interface.
863 *
864 * This function reads the SMI interface and translates the hardware register
865 * bit values into their corresponding control settings for a MIIM PHY Basic
866 * mode control register.
867 *
868 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
869 * -------------------------------------------------------------------
870 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
871 * ----------------------------+-----------------------------+----------------
872 * Bit 15 - Soft Reset | 0xF/4 | Not supported
873 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY)
874 * Bit 13 - Force 100 | 0xC/6 = 0xC/6
875 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7
876 * Bit 11 - Power Down | 0xD/3 = 0xD/3
877 * Bit 10 - PHY Isolate | 0xF/5 | Not supported
878 * Bit 9 - Restart AN | 0xD/5 = 0xD/5
879 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5
880 * Bit 7 - Collision Test/Res. | Not supported | Not supported
881 * Bit 6 - Reserved | Not supported | Not supported
882 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7
883 * Bit 4 - Force MDI | 0xD/1 = 0xD/1
884 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2
885 * Bit 2 - Disable Far-End F. | ???? | 0xD/4
886 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6
887 * Bit 0 - Disable LED | 0xD/7 = 0xD/7
888 * -------------------------------------------------------------------
889 *
890 * Return: 0 on success, error code on failure.
891 */
ksz8_r_phy_bmcr(struct ksz_device * dev,u16 port,u16 * val)892 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val)
893 {
894 const u16 *regs = dev->info->regs;
895 u8 restart, speed, ctrl;
896 int ret;
897
898 *val = 0;
899
900 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart);
901 if (ret)
902 return ret;
903
904 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed);
905 if (ret)
906 return ret;
907
908 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl);
909 if (ret)
910 return ret;
911
912 if (ctrl & PORT_FORCE_100_MBIT)
913 *val |= BMCR_SPEED100;
914
915 if (ksz_is_ksz88x3(dev)) {
916 if (restart & KSZ8873_PORT_PHY_LOOPBACK)
917 *val |= BMCR_LOOPBACK;
918
919 if ((ctrl & PORT_AUTO_NEG_ENABLE))
920 *val |= BMCR_ANENABLE;
921 } else {
922 ret = ksz879x_get_loopback(dev, port, val);
923 if (ret)
924 return ret;
925
926 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
927 *val |= BMCR_ANENABLE;
928 }
929
930 if (restart & PORT_POWER_DOWN)
931 *val |= BMCR_PDOWN;
932
933 if (restart & PORT_AUTO_NEG_RESTART)
934 *val |= BMCR_ANRESTART;
935
936 if (ctrl & PORT_FORCE_FULL_DUPLEX)
937 *val |= BMCR_FULLDPLX;
938
939 if (speed & PORT_HP_MDIX)
940 *val |= KSZ886X_BMCR_HP_MDIX;
941
942 if (restart & PORT_FORCE_MDIX)
943 *val |= KSZ886X_BMCR_FORCE_MDI;
944
945 if (restart & PORT_AUTO_MDIX_DISABLE)
946 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
947
948 if (restart & PORT_TX_DISABLE)
949 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT;
950
951 if (restart & PORT_LED_OFF)
952 *val |= KSZ886X_BMCR_DISABLE_LED;
953
954 return 0;
955 }
956
ksz8_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)957 int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
958 {
959 u8 ctrl, link, val1, val2;
960 int processed = true;
961 const u16 *regs;
962 u16 data = 0;
963 u16 p = phy;
964 int ret;
965
966 regs = dev->info->regs;
967
968 switch (reg) {
969 case MII_BMCR:
970 ret = ksz8_r_phy_bmcr(dev, p, &data);
971 if (ret)
972 return ret;
973 break;
974 case MII_BMSR:
975 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
976 if (ret)
977 return ret;
978
979 data = BMSR_100FULL |
980 BMSR_100HALF |
981 BMSR_10FULL |
982 BMSR_10HALF |
983 BMSR_ANEGCAPABLE;
984 if (link & PORT_AUTO_NEG_COMPLETE)
985 data |= BMSR_ANEGCOMPLETE;
986 if (link & PORT_STAT_LINK_GOOD)
987 data |= BMSR_LSTATUS;
988 break;
989 case MII_PHYSID1:
990 data = KSZ8795_ID_HI;
991 break;
992 case MII_PHYSID2:
993 if (ksz_is_ksz88x3(dev))
994 data = KSZ8863_ID_LO;
995 else
996 data = KSZ8795_ID_LO;
997 break;
998 case MII_ADVERTISE:
999 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
1000 if (ret)
1001 return ret;
1002
1003 data = ADVERTISE_CSMA;
1004 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
1005 data |= ADVERTISE_PAUSE_CAP;
1006 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
1007 data |= ADVERTISE_100FULL;
1008 if (ctrl & PORT_AUTO_NEG_100BTX)
1009 data |= ADVERTISE_100HALF;
1010 if (ctrl & PORT_AUTO_NEG_10BT_FD)
1011 data |= ADVERTISE_10FULL;
1012 if (ctrl & PORT_AUTO_NEG_10BT)
1013 data |= ADVERTISE_10HALF;
1014 break;
1015 case MII_LPA:
1016 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
1017 if (ret)
1018 return ret;
1019
1020 data = LPA_SLCT;
1021 if (link & PORT_REMOTE_SYM_PAUSE)
1022 data |= LPA_PAUSE_CAP;
1023 if (link & PORT_REMOTE_100BTX_FD)
1024 data |= LPA_100FULL;
1025 if (link & PORT_REMOTE_100BTX)
1026 data |= LPA_100HALF;
1027 if (link & PORT_REMOTE_10BT_FD)
1028 data |= LPA_10FULL;
1029 if (link & PORT_REMOTE_10BT)
1030 data |= LPA_10HALF;
1031 if (data & ~LPA_SLCT)
1032 data |= LPA_LPACK;
1033 break;
1034 case PHY_REG_LINK_MD:
1035 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
1036 if (ret)
1037 return ret;
1038
1039 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
1040 if (ret)
1041 return ret;
1042
1043 if (val1 & PORT_START_CABLE_DIAG)
1044 data |= PHY_START_CABLE_DIAG;
1045
1046 if (val1 & PORT_CABLE_10M_SHORT)
1047 data |= PHY_CABLE_10M_SHORT;
1048
1049 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
1050 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
1051
1052 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
1053 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
1054 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
1055 break;
1056 case PHY_REG_PHY_CTRL:
1057 ret = ksz8_r_phy_ctrl(dev, p, &data);
1058 if (ret)
1059 return ret;
1060
1061 break;
1062 default:
1063 processed = false;
1064 break;
1065 }
1066 if (processed)
1067 *val = data;
1068
1069 return 0;
1070 }
1071
1072 /**
1073 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
1074 * Control register (Reg. 31).
1075 * @dev: The KSZ device instance.
1076 * @port: The port number to be configured.
1077 * @val: The register value to be written.
1078 *
1079 * This function translates control settings from a MIIM PHY Control register
1080 * into their corresponding hardware register bit values for the SMI
1081 * interface.
1082 *
1083 * Return: 0 on success, error code on failure.
1084 */
ksz8_w_phy_ctrl(struct ksz_device * dev,int port,u16 val)1085 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val)
1086 {
1087 u8 reg_val = 0;
1088 int ret;
1089
1090 if (val & KSZ886X_CTRL_FORCE_LINK)
1091 reg_val |= PORT_FORCE_LINK;
1092
1093 if (val & KSZ886X_CTRL_PWRSAVE)
1094 reg_val |= PORT_POWER_SAVING;
1095
1096 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK)
1097 reg_val |= PORT_PHY_REMOTE_LOOPBACK;
1098
1099 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK |
1100 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);
1101 return ret;
1102 }
1103
1104 /**
1105 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY
1106 * Basic mode control register (Reg. 0).
1107 * @dev: The KSZ device instance.
1108 * @port: The port number to be configured.
1109 * @val: The register value to be written.
1110 *
1111 * This function translates control settings from a MIIM PHY Basic mode control
1112 * register into their corresponding hardware register bit values for the SMI
1113 * interface.
1114 *
1115 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
1116 * -------------------------------------------------------------------
1117 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
1118 * ----------------------------+-----------------------------+----------------
1119 * Bit 15 - Soft Reset | 0xF/4 | Not supported
1120 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY)
1121 * Bit 13 - Force 100 | 0xC/6 = 0xC/6
1122 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7
1123 * Bit 11 - Power Down | 0xD/3 = 0xD/3
1124 * Bit 10 - PHY Isolate | 0xF/5 | Not supported
1125 * Bit 9 - Restart AN | 0xD/5 = 0xD/5
1126 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5
1127 * Bit 7 - Collision Test/Res. | Not supported | Not supported
1128 * Bit 6 - Reserved | Not supported | Not supported
1129 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7
1130 * Bit 4 - Force MDI | 0xD/1 = 0xD/1
1131 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2
1132 * Bit 2 - Disable Far-End F. | ???? | 0xD/4
1133 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6
1134 * Bit 0 - Disable LED | 0xD/7 = 0xD/7
1135 * -------------------------------------------------------------------
1136 *
1137 * Return: 0 on success, error code on failure.
1138 */
ksz8_w_phy_bmcr(struct ksz_device * dev,u16 port,u16 val)1139 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val)
1140 {
1141 u8 restart, speed, ctrl, restart_mask;
1142 const u16 *regs = dev->info->regs;
1143 int ret;
1144
1145 /* Do not support PHY reset function. */
1146 if (val & BMCR_RESET)
1147 return 0;
1148
1149 speed = 0;
1150 if (val & KSZ886X_BMCR_HP_MDIX)
1151 speed |= PORT_HP_MDIX;
1152
1153 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed);
1154 if (ret)
1155 return ret;
1156
1157 ctrl = 0;
1158 if (ksz_is_ksz88x3(dev)) {
1159 if ((val & BMCR_ANENABLE))
1160 ctrl |= PORT_AUTO_NEG_ENABLE;
1161 } else {
1162 if (!(val & BMCR_ANENABLE))
1163 ctrl |= PORT_AUTO_NEG_DISABLE;
1164
1165 /* Fiber port does not support auto-negotiation. */
1166 if (dev->ports[port].fiber)
1167 ctrl |= PORT_AUTO_NEG_DISABLE;
1168 }
1169
1170 if (val & BMCR_SPEED100)
1171 ctrl |= PORT_FORCE_100_MBIT;
1172
1173 if (val & BMCR_FULLDPLX)
1174 ctrl |= PORT_FORCE_FULL_DUPLEX;
1175
1176 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT |
1177 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same
1178 * bits
1179 */
1180 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl);
1181 if (ret)
1182 return ret;
1183
1184 restart = 0;
1185 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART |
1186 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX;
1187
1188 if (val & KSZ886X_BMCR_DISABLE_LED)
1189 restart |= PORT_LED_OFF;
1190
1191 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
1192 restart |= PORT_TX_DISABLE;
1193
1194 if (val & BMCR_ANRESTART)
1195 restart |= PORT_AUTO_NEG_RESTART;
1196
1197 if (val & BMCR_PDOWN)
1198 restart |= PORT_POWER_DOWN;
1199
1200 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
1201 restart |= PORT_AUTO_MDIX_DISABLE;
1202
1203 if (val & KSZ886X_BMCR_FORCE_MDI)
1204 restart |= PORT_FORCE_MDIX;
1205
1206 if (ksz_is_ksz88x3(dev)) {
1207 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK;
1208
1209 if (val & BMCR_LOOPBACK)
1210 restart |= KSZ8873_PORT_PHY_LOOPBACK;
1211 } else {
1212 ret = ksz879x_set_loopback(dev, port, val);
1213 if (ret)
1214 return ret;
1215 }
1216
1217 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask,
1218 restart);
1219 }
1220
ksz8_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)1221 int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
1222 {
1223 const u16 *regs;
1224 u8 ctrl, data;
1225 u16 p = phy;
1226 int ret;
1227
1228 regs = dev->info->regs;
1229
1230 switch (reg) {
1231 case MII_BMCR:
1232 ret = ksz8_w_phy_bmcr(dev, p, val);
1233 if (ret)
1234 return ret;
1235 break;
1236 case MII_ADVERTISE:
1237 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
1238 if (ret)
1239 return ret;
1240
1241 data = ctrl;
1242 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
1243 PORT_AUTO_NEG_100BTX_FD |
1244 PORT_AUTO_NEG_100BTX |
1245 PORT_AUTO_NEG_10BT_FD |
1246 PORT_AUTO_NEG_10BT);
1247 if (val & ADVERTISE_PAUSE_CAP)
1248 data |= PORT_AUTO_NEG_SYM_PAUSE;
1249 if (val & ADVERTISE_100FULL)
1250 data |= PORT_AUTO_NEG_100BTX_FD;
1251 if (val & ADVERTISE_100HALF)
1252 data |= PORT_AUTO_NEG_100BTX;
1253 if (val & ADVERTISE_10FULL)
1254 data |= PORT_AUTO_NEG_10BT_FD;
1255 if (val & ADVERTISE_10HALF)
1256 data |= PORT_AUTO_NEG_10BT;
1257
1258 if (data != ctrl) {
1259 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
1260 if (ret)
1261 return ret;
1262 }
1263 break;
1264 case PHY_REG_LINK_MD:
1265 if (val & PHY_START_CABLE_DIAG)
1266 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
1267 break;
1268
1269 case PHY_REG_PHY_CTRL:
1270 ret = ksz8_w_phy_ctrl(dev, p, val);
1271 if (ret)
1272 return ret;
1273 break;
1274 default:
1275 break;
1276 }
1277
1278 return 0;
1279 }
1280
ksz8_cfg_port_member(struct ksz_device * dev,int port,u8 member)1281 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1282 {
1283 int offset = P_MIRROR_CTRL;
1284 u8 data;
1285
1286 if (ksz_is_ksz8463(dev))
1287 offset = P1CR2;
1288 ksz_pread8(dev, port, offset, &data);
1289 data &= ~dev->port_mask;
1290 data |= (member & dev->port_mask);
1291 ksz_pwrite8(dev, port, offset, data);
1292 }
1293
ksz8_flush_dyn_mac_table(struct ksz_device * dev,int port)1294 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1295 {
1296 u8 learn[DSA_MAX_PORTS];
1297 int first, index, cnt;
1298 const u16 *regs;
1299 int reg = S_FLUSH_TABLE_CTRL;
1300 int mask = SW_FLUSH_DYN_MAC_TABLE;
1301
1302 regs = dev->info->regs;
1303
1304 if ((uint)port < dev->info->port_cnt) {
1305 first = port;
1306 cnt = port + 1;
1307 } else {
1308 /* Flush all ports. */
1309 first = 0;
1310 cnt = dev->info->port_cnt;
1311 }
1312 for (index = first; index < cnt; index++) {
1313 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
1314 if (!(learn[index] & PORT_LEARN_DISABLE))
1315 ksz_pwrite8(dev, index, regs[P_STP_CTRL],
1316 learn[index] | PORT_LEARN_DISABLE);
1317 }
1318 if (ksz_is_ksz8463(dev)) {
1319 reg = KSZ8463_FLUSH_TABLE_CTRL;
1320 mask = KSZ8463_FLUSH_DYN_MAC_TABLE;
1321 }
1322 ksz_cfg(dev, reg, mask, true);
1323 for (index = first; index < cnt; index++) {
1324 if (!(learn[index] & PORT_LEARN_DISABLE))
1325 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
1326 }
1327 }
1328
ksz8_fdb_dump(struct ksz_device * dev,int port,dsa_fdb_dump_cb_t * cb,void * data)1329 int ksz8_fdb_dump(struct ksz_device *dev, int port,
1330 dsa_fdb_dump_cb_t *cb, void *data)
1331 {
1332 u8 mac[ETH_ALEN];
1333 u8 src_port, fid;
1334 u16 entries = 0;
1335 int ret, i;
1336
1337 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) {
1338 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port,
1339 &entries);
1340 if (ret)
1341 return ret;
1342
1343 if (i >= entries)
1344 return 0;
1345
1346 if (port == src_port) {
1347 ret = cb(mac, fid, false, data);
1348 if (ret)
1349 return ret;
1350 }
1351 }
1352
1353 return 0;
1354 }
1355
ksz8_add_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1356 static int ksz8_add_sta_mac(struct ksz_device *dev, int port,
1357 const unsigned char *addr, u16 vid)
1358 {
1359 struct alu_struct alu;
1360 int index, ret;
1361 int empty = 0;
1362
1363 alu.port_forward = 0;
1364 for (index = 0; index < dev->info->num_statics; index++) {
1365 bool valid;
1366
1367 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1368 if (ret)
1369 return ret;
1370 if (!valid) {
1371 /* Remember the first empty entry. */
1372 if (!empty)
1373 empty = index + 1;
1374 continue;
1375 }
1376
1377 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1378 break;
1379 }
1380
1381 /* no available entry */
1382 if (index == dev->info->num_statics && !empty)
1383 return -ENOSPC;
1384
1385 /* add entry */
1386 if (index == dev->info->num_statics) {
1387 index = empty - 1;
1388 memset(&alu, 0, sizeof(alu));
1389 memcpy(alu.mac, addr, ETH_ALEN);
1390 alu.is_static = true;
1391 }
1392 alu.port_forward |= BIT(port);
1393 if (vid) {
1394 alu.is_use_fid = true;
1395
1396 /* Need a way to map VID to FID. */
1397 alu.fid = vid;
1398 }
1399
1400 return ksz8_w_sta_mac_table(dev, index, &alu);
1401 }
1402
ksz8_del_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1403 static int ksz8_del_sta_mac(struct ksz_device *dev, int port,
1404 const unsigned char *addr, u16 vid)
1405 {
1406 struct alu_struct alu;
1407 int index, ret;
1408
1409 for (index = 0; index < dev->info->num_statics; index++) {
1410 bool valid;
1411
1412 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1413 if (ret)
1414 return ret;
1415 if (!valid)
1416 continue;
1417
1418 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1419 break;
1420 }
1421
1422 /* no available entry */
1423 if (index == dev->info->num_statics)
1424 return 0;
1425
1426 /* clear port */
1427 alu.port_forward &= ~BIT(port);
1428 if (!alu.port_forward)
1429 alu.is_static = false;
1430
1431 return ksz8_w_sta_mac_table(dev, index, &alu);
1432 }
1433
ksz8_mdb_add(struct ksz_device * dev,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1434 int ksz8_mdb_add(struct ksz_device *dev, int port,
1435 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1436 {
1437 return ksz8_add_sta_mac(dev, port, mdb->addr, mdb->vid);
1438 }
1439
ksz8_mdb_del(struct ksz_device * dev,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1440 int ksz8_mdb_del(struct ksz_device *dev, int port,
1441 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1442 {
1443 return ksz8_del_sta_mac(dev, port, mdb->addr, mdb->vid);
1444 }
1445
ksz8_fdb_add(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1446 int ksz8_fdb_add(struct ksz_device *dev, int port, const unsigned char *addr,
1447 u16 vid, struct dsa_db db)
1448 {
1449 return ksz8_add_sta_mac(dev, port, addr, vid);
1450 }
1451
ksz8_fdb_del(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1452 int ksz8_fdb_del(struct ksz_device *dev, int port, const unsigned char *addr,
1453 u16 vid, struct dsa_db db)
1454 {
1455 return ksz8_del_sta_mac(dev, port, addr, vid);
1456 }
1457
ksz8_port_vlan_filtering(struct ksz_device * dev,int port,bool flag,struct netlink_ext_ack * extack)1458 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag,
1459 struct netlink_ext_ack *extack)
1460 {
1461 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
1462 return -ENOTSUPP;
1463
1464 /* Discard packets with VID not enabled on the switch */
1465 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1466
1467 /* Discard packets with VID not enabled on the ingress port */
1468 for (port = 0; port < dev->phy_port_cnt; ++port)
1469 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1470 flag);
1471
1472 return 0;
1473 }
1474
ksz8_port_enable_pvid(struct ksz_device * dev,int port,bool state)1475 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1476 {
1477 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) {
1478 int reg = REG_SW_INSERT_SRC_PVID;
1479
1480 if (ksz_is_ksz8463(dev))
1481 reg = KSZ8463_REG_SW_CTRL_9;
1482 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state);
1483 } else {
1484 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1485 }
1486 }
1487
ksz8_port_vlan_add(struct ksz_device * dev,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1488 int ksz8_port_vlan_add(struct ksz_device *dev, int port,
1489 const struct switchdev_obj_port_vlan *vlan,
1490 struct netlink_ext_ack *extack)
1491 {
1492 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1493 struct ksz_port *p = &dev->ports[port];
1494 u16 data, new_pvid = 0;
1495 u8 fid, member, valid;
1496
1497 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
1498 return -ENOTSUPP;
1499
1500 /* If a VLAN is added with untagged flag different from the
1501 * port's Remove Tag flag, we need to change the latter.
1502 * Ignore VID 0, which is always untagged.
1503 * Ignore CPU port, which will always be tagged.
1504 */
1505 if (untagged != p->remove_tag && vlan->vid != 0 &&
1506 port != dev->cpu_port) {
1507 unsigned int vid;
1508
1509 /* Reject attempts to add a VLAN that requires the
1510 * Remove Tag flag to be changed, unless there are no
1511 * other VLANs currently configured.
1512 */
1513 for (vid = 1; vid < dev->info->num_vlans; ++vid) {
1514 /* Skip the VID we are going to add or reconfigure */
1515 if (vid == vlan->vid)
1516 continue;
1517
1518 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1519 &fid, &member, &valid);
1520 if (valid && (member & BIT(port)))
1521 return -EINVAL;
1522 }
1523
1524 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1525 p->remove_tag = untagged;
1526 }
1527
1528 ksz8_r_vlan_table(dev, vlan->vid, &data);
1529 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1530
1531 /* First time to setup the VLAN entry. */
1532 if (!valid) {
1533 /* Need to find a way to map VID to FID. */
1534 fid = 1;
1535 valid = 1;
1536 }
1537 member |= BIT(port);
1538
1539 ksz8_to_vlan(dev, fid, member, valid, &data);
1540 ksz8_w_vlan_table(dev, vlan->vid, data);
1541
1542 /* change PVID */
1543 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1544 new_pvid = vlan->vid;
1545
1546 if (new_pvid) {
1547 u16 vid;
1548
1549 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1550 vid &= ~VLAN_VID_MASK;
1551 vid |= new_pvid;
1552 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1553
1554 ksz8_port_enable_pvid(dev, port, true);
1555 }
1556
1557 return 0;
1558 }
1559
ksz8_port_vlan_del(struct ksz_device * dev,int port,const struct switchdev_obj_port_vlan * vlan)1560 int ksz8_port_vlan_del(struct ksz_device *dev, int port,
1561 const struct switchdev_obj_port_vlan *vlan)
1562 {
1563 u16 data, pvid;
1564 u8 fid, member, valid;
1565
1566 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
1567 return -ENOTSUPP;
1568
1569 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1570 pvid = pvid & 0xFFF;
1571
1572 ksz8_r_vlan_table(dev, vlan->vid, &data);
1573 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1574
1575 member &= ~BIT(port);
1576
1577 /* Invalidate the entry if no more member. */
1578 if (!member) {
1579 fid = 0;
1580 valid = 0;
1581 }
1582
1583 ksz8_to_vlan(dev, fid, member, valid, &data);
1584 ksz8_w_vlan_table(dev, vlan->vid, data);
1585
1586 if (pvid == vlan->vid)
1587 ksz8_port_enable_pvid(dev, port, false);
1588
1589 return 0;
1590 }
1591
ksz8_port_mirror_add(struct ksz_device * dev,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)1592 int ksz8_port_mirror_add(struct ksz_device *dev, int port,
1593 struct dsa_mall_mirror_tc_entry *mirror,
1594 bool ingress, struct netlink_ext_ack *extack)
1595 {
1596 int offset = P_MIRROR_CTRL;
1597
1598 if (ksz_is_ksz8463(dev))
1599 offset = P1CR2;
1600 if (ingress) {
1601 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true);
1602 dev->mirror_rx |= BIT(port);
1603 } else {
1604 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true);
1605 dev->mirror_tx |= BIT(port);
1606 }
1607
1608 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false);
1609
1610 /* configure mirror port */
1611 if (dev->mirror_rx || dev->mirror_tx)
1612 ksz_port_cfg(dev, mirror->to_local_port, offset,
1613 PORT_MIRROR_SNIFFER, true);
1614
1615 return 0;
1616 }
1617
ksz8_port_mirror_del(struct ksz_device * dev,int port,struct dsa_mall_mirror_tc_entry * mirror)1618 void ksz8_port_mirror_del(struct ksz_device *dev, int port,
1619 struct dsa_mall_mirror_tc_entry *mirror)
1620 {
1621 int offset = P_MIRROR_CTRL;
1622 u8 data;
1623
1624 if (ksz_is_ksz8463(dev))
1625 offset = P1CR2;
1626 if (mirror->ingress) {
1627 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false);
1628 dev->mirror_rx &= ~BIT(port);
1629 } else {
1630 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false);
1631 dev->mirror_tx &= ~BIT(port);
1632 }
1633
1634 ksz_pread8(dev, port, offset, &data);
1635
1636 if (!dev->mirror_rx && !dev->mirror_tx)
1637 ksz_port_cfg(dev, mirror->to_local_port, offset,
1638 PORT_MIRROR_SNIFFER, false);
1639 }
1640
ksz8795_cpu_interface_select(struct ksz_device * dev,int port)1641 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1642 {
1643 struct ksz_port *p = &dev->ports[port];
1644
1645 if (!ksz_is_ksz87xx(dev))
1646 return;
1647
1648 if (!p->interface && dev->compat_interface) {
1649 dev_warn(dev->dev,
1650 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1651 "Please update your device tree.\n",
1652 port);
1653 p->interface = dev->compat_interface;
1654 }
1655 }
1656
ksz8_port_setup(struct ksz_device * dev,int port,bool cpu_port)1657 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1658 {
1659 const u16 *regs = dev->info->regs;
1660 struct dsa_switch *ds = dev->ds;
1661 const u32 *masks;
1662 int offset;
1663 u8 member;
1664
1665 masks = dev->info->masks;
1666
1667 /* enable broadcast storm limit */
1668 offset = P_BCAST_STORM_CTRL;
1669 if (ksz_is_ksz8463(dev))
1670 offset = P1CR1;
1671 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true);
1672
1673 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues);
1674
1675 /* replace priority */
1676 offset = P_802_1P_CTRL;
1677 if (ksz_is_ksz8463(dev))
1678 offset = P1CR2;
1679 ksz_port_cfg(dev, port, offset,
1680 masks[PORT_802_1P_REMAPPING], false);
1681
1682 if (cpu_port)
1683 member = dsa_user_ports(ds);
1684 else
1685 member = BIT(dsa_upstream_port(ds, port));
1686
1687 ksz8_cfg_port_member(dev, port, member);
1688
1689 /* Disable all WoL options by default. Otherwise
1690 * ksz_switch_macaddr_get/put logic will not work properly.
1691 * CPU port 4 has no WoL functionality.
1692 */
1693 if (ksz_is_ksz87xx(dev) && !cpu_port)
1694 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0);
1695 }
1696
ksz88x3_config_rmii_clk(struct ksz_device * dev)1697 static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
1698 {
1699 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
1700 bool rmii_clk_internal;
1701
1702 if (!ksz_is_ksz88x3(dev))
1703 return;
1704
1705 rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
1706 "microchip,rmii-clk-internal");
1707
1708 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
1709 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
1710 }
1711
ksz8_config_cpu_port(struct dsa_switch * ds)1712 void ksz8_config_cpu_port(struct dsa_switch *ds)
1713 {
1714 struct ksz_device *dev = ds->priv;
1715 struct ksz_port *p;
1716 const u32 *masks;
1717 const u16 *regs;
1718 u8 remote;
1719 u8 fiber_ports = 0;
1720 int i;
1721
1722 masks = dev->info->masks;
1723 regs = dev->info->regs;
1724
1725 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1726
1727 ksz8_port_setup(dev, dev->cpu_port, true);
1728
1729 ksz8795_cpu_interface_select(dev, dev->cpu_port);
1730 ksz88x3_config_rmii_clk(dev);
1731
1732 for (i = 0; i < dev->phy_port_cnt; i++) {
1733 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1734 }
1735 for (i = 0; i < dev->phy_port_cnt; i++) {
1736 p = &dev->ports[i];
1737
1738 /* For KSZ8795 family. */
1739 if (ksz_is_ksz87xx(dev)) {
1740 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1741 if (remote & KSZ8_PORT_FIBER_MODE)
1742 p->fiber = 1;
1743 }
1744 if (p->fiber)
1745 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1746 PORT_FORCE_FLOW_CTRL, true);
1747 else
1748 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1749 PORT_FORCE_FLOW_CTRL, false);
1750 if (p->fiber)
1751 fiber_ports |= (1 << i);
1752 }
1753 if (ksz_is_ksz8463(dev)) {
1754 /* Setup fiber ports. */
1755 if (fiber_ports) {
1756 fiber_ports &= 3;
1757 regmap_update_bits(ksz_regmap_16(dev),
1758 KSZ8463_REG_CFG_CTRL,
1759 fiber_ports << PORT_COPPER_MODE_S,
1760 0);
1761 regmap_update_bits(ksz_regmap_16(dev),
1762 KSZ8463_REG_DSP_CTRL_6,
1763 COPPER_RECEIVE_ADJUSTMENT, 0);
1764 }
1765
1766 /* Turn off PTP function as the switch's proprietary way of
1767 * handling timestamp is not supported in current Linux PTP
1768 * stack implementation.
1769 */
1770 regmap_update_bits(ksz_regmap_16(dev),
1771 KSZ8463_PTP_MSG_CONF1,
1772 PTP_ENABLE, 0);
1773 regmap_update_bits(ksz_regmap_16(dev),
1774 KSZ8463_PTP_CLK_CTRL,
1775 PTP_CLK_ENABLE, 0);
1776 }
1777 }
1778
1779 /**
1780 * ksz8_phy_port_link_up - Configures ports with integrated PHYs
1781 * @dev: The KSZ device instance.
1782 * @port: The port number to configure.
1783 * @duplex: The desired duplex mode.
1784 * @tx_pause: If true, enables transmit pause.
1785 * @rx_pause: If true, enables receive pause.
1786 *
1787 * Description:
1788 * The function configures flow control settings for a given port based on the
1789 * desired settings and current duplex mode.
1790 *
1791 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the
1792 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)
1793 * determines how flow control is handled on the port:
1794 * "1 = will always enable full-duplex flow control on the port, regardless
1795 * of AN result.
1796 * 0 = full-duplex flow control is enabled based on AN result."
1797 *
1798 * This means that the flow control behavior depends on the state of this bit:
1799 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and
1800 * force flow control on the port.
1801 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable
1802 * flow control based on the AN results.
1803 *
1804 * However, there is a potential limitation in this configuration. It is
1805 * currently not possible to force disable flow control on a port if we still
1806 * advertise pause support. While such a configuration is not currently
1807 * supported by Linux, and may not make practical sense, it's important to be
1808 * aware of this limitation when working with the KSZ8873 and similar devices.
1809 */
ksz8_phy_port_link_up(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)1810 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,
1811 bool tx_pause, bool rx_pause)
1812 {
1813 const u16 *regs = dev->info->regs;
1814 u8 sctrl = 0;
1815
1816 /* The KSZ8795 switch differs from the KSZ8873 by supporting
1817 * asymmetric pause control. However, since a single bit is used to
1818 * control both RX and TX pause, we can't enforce asymmetric pause
1819 * control - both TX and RX pause will be either enabled or disabled
1820 * together.
1821 *
1822 * If auto-negotiation is enabled, we usually allow the flow control to
1823 * be determined by the auto-negotiation process based on the
1824 * capabilities of both link partners. However, for KSZ8873, the
1825 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,
1826 * ignoring the auto-negotiation result. Thus, even in auto-negotiation
1827 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is
1828 * properly cleared.
1829 *
1830 * In the absence of pause auto-negotiation, we will enforce symmetric
1831 * pause control for both variants of switches - KSZ8873 and KSZ8795.
1832 *
1833 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL
1834 * 1 1 x 0
1835 * 0 1 x 0 (flow control probably disabled)
1836 * x 0 1 1 (flow control force enabled)
1837 * 1 0 0 0 (flow control still depends on
1838 * aneg result due to hardware)
1839 * 0 0 0 0 (flow control probably disabled)
1840 */
1841 if (dev->ports[port].manual_flow && tx_pause)
1842 sctrl |= PORT_FORCE_FLOW_CTRL;
1843
1844 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);
1845 }
1846
1847 /**
1848 * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
1849 * @dev: The KSZ device instance.
1850 * @speed: The desired link speed.
1851 * @duplex: The desired duplex mode.
1852 * @tx_pause: If true, enables transmit pause.
1853 * @rx_pause: If true, enables receive pause.
1854 *
1855 * Description:
1856 * The function configures flow control and speed settings for the CPU
1857 * port of the switch based on the desired settings, current duplex mode, and
1858 * speed.
1859 */
ksz8_cpu_port_link_up(struct ksz_device * dev,int speed,int duplex,bool tx_pause,bool rx_pause)1860 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
1861 bool tx_pause, bool rx_pause)
1862 {
1863 const u16 *regs = dev->info->regs;
1864 u8 ctrl = 0;
1865
1866 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
1867 * at least on KSZ8873. They can have different values depending on your
1868 * board setup.
1869 */
1870 if (tx_pause || rx_pause)
1871 ctrl |= SW_FLOW_CTRL;
1872
1873 if (duplex == DUPLEX_HALF)
1874 ctrl |= SW_HALF_DUPLEX;
1875
1876 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
1877 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
1878 */
1879 if (speed == SPEED_10)
1880 ctrl |= SW_10_MBIT;
1881
1882 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |
1883 SW_10_MBIT, ctrl);
1884 }
1885
ksz8_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1886 void ksz8_phylink_mac_link_up(struct phylink_config *config,
1887 struct phy_device *phydev, unsigned int mode,
1888 phy_interface_t interface, int speed, int duplex,
1889 bool tx_pause, bool rx_pause)
1890 {
1891 struct dsa_port *dp = dsa_phylink_to_port(config);
1892 struct ksz_device *dev = dp->ds->priv;
1893 int port = dp->index;
1894
1895 /* If the port is the CPU port, apply special handling. Only the CPU
1896 * port is configured via global registers.
1897 */
1898 if (dev->cpu_port == port)
1899 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
1900 else if (dev->info->internal_phy[port])
1901 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);
1902 }
1903
ksz8_handle_global_errata(struct dsa_switch * ds)1904 static int ksz8_handle_global_errata(struct dsa_switch *ds)
1905 {
1906 struct ksz_device *dev = ds->priv;
1907 int ret = 0;
1908
1909 /* KSZ87xx Errata DS80000687C.
1910 * Module 2: Link drops with some EEE link partners.
1911 * An issue with the EEE next page exchange between the
1912 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
1913 * the link dropping.
1914 */
1915 if (dev->info->ksz87xx_eee_link_erratum)
1916 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
1917
1918 return ret;
1919 }
1920
ksz8_enable_stp_addr(struct ksz_device * dev)1921 int ksz8_enable_stp_addr(struct ksz_device *dev)
1922 {
1923 struct alu_struct alu;
1924
1925 /* Setup STP address for STP operation. */
1926 memset(&alu, 0, sizeof(alu));
1927 ether_addr_copy(alu.mac, eth_stp_addr);
1928 alu.is_static = true;
1929 alu.is_override = true;
1930 alu.port_forward = dev->info->cpu_ports;
1931
1932 return ksz8_w_sta_mac_table(dev, 0, &alu);
1933 }
1934
ksz8_setup(struct dsa_switch * ds)1935 int ksz8_setup(struct dsa_switch *ds)
1936 {
1937 struct ksz_device *dev = ds->priv;
1938 const u16 *regs = dev->info->regs;
1939 int i, ret = 0;
1940
1941 ds->mtu_enforcement_ingress = true;
1942
1943 /* We rely on software untagging on the CPU port, so that we
1944 * can support both tagged and untagged VLANs
1945 */
1946 ds->untag_bridge_pvid = true;
1947
1948 /* VLAN filtering is partly controlled by the global VLAN
1949 * Enable flag
1950 */
1951 ds->vlan_filtering_is_global = true;
1952
1953 /* Enable automatic fast aging when link changed detected. */
1954 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1955
1956 /* Enable aggressive back off algorithm in half duplex mode. */
1957 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1958 if (ret)
1959 return ret;
1960
1961 /*
1962 * Make sure unicast VLAN boundary is set as default and
1963 * enable no excessive collision drop.
1964 */
1965 ret = ksz_rmw8(dev, REG_SW_CTRL_2,
1966 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1967 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1968 if (ret)
1969 return ret;
1970
1971 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1972
1973 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1974
1975 if (!ksz_is_ksz88x3(dev) && !ksz_is_ksz8463(dev))
1976 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1977
1978 for (i = 0; i < (dev->info->num_vlans / 4); i++)
1979 ksz8_r_vlan_entries(dev, i);
1980
1981 /* Make sure PME (WoL) is not enabled. If requested, it will
1982 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs
1983 * do not like PME events changes before shutdown. PME only
1984 * available on KSZ87xx family.
1985 */
1986 if (ksz_is_ksz87xx(dev)) {
1987 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0);
1988 if (!ret)
1989 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0);
1990 }
1991
1992 if (!ret)
1993 return ksz8_handle_global_errata(ds);
1994 else
1995 return ret;
1996 }
1997
ksz8_get_caps(struct ksz_device * dev,int port,struct phylink_config * config)1998 void ksz8_get_caps(struct ksz_device *dev, int port,
1999 struct phylink_config *config)
2000 {
2001 config->mac_capabilities = MAC_10 | MAC_100;
2002
2003 /* Silicon Errata Sheet (DS80000830A):
2004 * "Port 1 does not respond to received flow control PAUSE frames"
2005 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
2006 * switches.
2007 */
2008 if (!ksz_is_ksz88x3(dev) || port)
2009 config->mac_capabilities |= MAC_SYM_PAUSE;
2010
2011 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
2012 if (!ksz_is_ksz88x3(dev))
2013 config->mac_capabilities |= MAC_ASYM_PAUSE;
2014 }
2015
ksz8_get_port_addr(int port,int offset)2016 u32 ksz8_get_port_addr(int port, int offset)
2017 {
2018 return PORT_CTRL_ADDR(port, offset);
2019 }
2020
ksz8463_get_port_addr(int port,int offset)2021 u32 ksz8463_get_port_addr(int port, int offset)
2022 {
2023 return offset + 0x18 * port;
2024 }
2025
ksz8463_get_phy_addr(u16 phy,u16 reg,u16 offset)2026 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset)
2027 {
2028 return offset + reg * 2 + phy * (P2MBCR - P1MBCR);
2029 }
2030
ksz8463_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)2031 int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
2032 {
2033 u16 sw_reg = 0;
2034 u16 data = 0;
2035 int ret;
2036
2037 if (phy > 1)
2038 return -ENOSPC;
2039 switch (reg) {
2040 case MII_PHYSID1:
2041 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR);
2042 break;
2043 case MII_PHYSID2:
2044 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR);
2045 break;
2046 case MII_BMCR:
2047 case MII_BMSR:
2048 case MII_ADVERTISE:
2049 case MII_LPA:
2050 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR);
2051 break;
2052 case MII_TPISTATUS:
2053 /* This register holds the PHY interrupt status for simulated
2054 * Micrel KSZ PHY.
2055 */
2056 data = 0x0505;
2057 break;
2058 default:
2059 break;
2060 }
2061 if (sw_reg) {
2062 ret = ksz_read16(dev, sw_reg, &data);
2063 if (ret)
2064 return ret;
2065 }
2066 *val = data;
2067
2068 return 0;
2069 }
2070
ksz8463_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)2071 int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
2072 {
2073 u16 sw_reg = 0;
2074 int ret;
2075
2076 if (phy > 1)
2077 return -ENOSPC;
2078
2079 /* No write to fiber port. */
2080 if (dev->ports[phy].fiber)
2081 return 0;
2082 switch (reg) {
2083 case MII_BMCR:
2084 case MII_ADVERTISE:
2085 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR);
2086 break;
2087 default:
2088 break;
2089 }
2090 if (sw_reg) {
2091 ret = ksz_write16(dev, sw_reg, val);
2092 if (ret)
2093 return ret;
2094 }
2095
2096 return 0;
2097 }
2098
ksz8_switch_init(struct ksz_device * dev)2099 int ksz8_switch_init(struct ksz_device *dev)
2100 {
2101 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
2102 dev->phy_port_cnt = dev->info->port_cnt - 1;
2103 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
2104
2105 return 0;
2106 }
2107
ksz8_switch_exit(struct ksz_device * dev)2108 void ksz8_switch_exit(struct ksz_device *dev)
2109 {
2110 ksz8_reset_switch(dev);
2111 }
2112
2113 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
2114 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
2115 MODULE_LICENSE("GPL");
2116