1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/bsearch.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include "kfd_priv.h"
28 #include "kfd_device_queue_manager.h"
29 #include "kfd_pm4_headers_vi.h"
30 #include "kfd_pm4_headers_aldebaran.h"
31 #include "cwsr_trap_handler.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_svm.h"
35 #include "kfd_migrate.h"
36 #include "amdgpu.h"
37 #include "amdgpu_xcp.h"
38
39 #define MQD_SIZE_ALIGNED 768
40
41 /*
42 * kfd_locked is used to lock the kfd driver during suspend or reset
43 * once locked, kfd driver will stop any further GPU execution.
44 * create process (open) will return -EAGAIN.
45 */
46 static int kfd_locked;
47
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50 #endif
51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd;
60
61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
62 unsigned int chunk_size);
63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
64
65 static int kfd_resume(struct kfd_node *kfd);
66
kfd_device_info_set_sdma_info(struct kfd_dev * kfd)67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
68 {
69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0);
70
71 switch (sdma_version) {
72 case IP_VERSION(4, 0, 0):/* VEGA10 */
73 case IP_VERSION(4, 0, 1):/* VEGA12 */
74 case IP_VERSION(4, 1, 0):/* RAVEN */
75 case IP_VERSION(4, 1, 1):/* RAVEN */
76 case IP_VERSION(4, 1, 2):/* RENOIR */
77 case IP_VERSION(5, 2, 1):/* VANGOGH */
78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
81 kfd->device_info.num_sdma_queues_per_engine = 2;
82 break;
83 case IP_VERSION(4, 2, 0):/* VEGA20 */
84 case IP_VERSION(4, 2, 2):/* ARCTURUS */
85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */
86 case IP_VERSION(4, 4, 2):
87 case IP_VERSION(4, 4, 5):
88 case IP_VERSION(4, 4, 4):
89 case IP_VERSION(5, 0, 0):/* NAVI10 */
90 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
91 case IP_VERSION(5, 0, 2):/* NAVI14 */
92 case IP_VERSION(5, 0, 5):/* NAVI12 */
93 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
94 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
95 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
96 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
97 case IP_VERSION(6, 0, 0):
98 case IP_VERSION(6, 0, 1):
99 case IP_VERSION(6, 0, 2):
100 case IP_VERSION(6, 0, 3):
101 case IP_VERSION(6, 1, 0):
102 case IP_VERSION(6, 1, 1):
103 case IP_VERSION(6, 1, 2):
104 case IP_VERSION(6, 1, 3):
105 case IP_VERSION(7, 0, 0):
106 case IP_VERSION(7, 0, 1):
107 kfd->device_info.num_sdma_queues_per_engine = 8;
108 break;
109 default:
110 dev_warn(kfd_device,
111 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
112 sdma_version);
113 kfd->device_info.num_sdma_queues_per_engine = 8;
114 }
115
116 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
117
118 switch (sdma_version) {
119 case IP_VERSION(6, 0, 0):
120 case IP_VERSION(6, 0, 1):
121 case IP_VERSION(6, 0, 2):
122 case IP_VERSION(6, 0, 3):
123 case IP_VERSION(6, 1, 0):
124 case IP_VERSION(6, 1, 1):
125 case IP_VERSION(6, 1, 2):
126 case IP_VERSION(6, 1, 3):
127 case IP_VERSION(7, 0, 0):
128 case IP_VERSION(7, 0, 1):
129 /* Reserve 1 for paging and 1 for gfx */
130 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
131 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
132 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
133 kfd->adev->sdma.num_instances *
134 kfd->device_info.num_reserved_sdma_queues_per_engine);
135 break;
136 default:
137 break;
138 }
139 }
140
kfd_device_info_set_event_interrupt_class(struct kfd_dev * kfd)141 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
142 {
143 uint32_t gc_version = KFD_GC_VERSION(kfd);
144
145 switch (gc_version) {
146 case IP_VERSION(9, 0, 1): /* VEGA10 */
147 case IP_VERSION(9, 1, 0): /* RAVEN */
148 case IP_VERSION(9, 2, 1): /* VEGA12 */
149 case IP_VERSION(9, 2, 2): /* RAVEN */
150 case IP_VERSION(9, 3, 0): /* RENOIR */
151 case IP_VERSION(9, 4, 0): /* VEGA20 */
152 case IP_VERSION(9, 4, 1): /* ARCTURUS */
153 case IP_VERSION(9, 4, 2): /* ALDEBARAN */
154 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
155 break;
156 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
157 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */
158 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */
159 kfd->device_info.event_interrupt_class =
160 &event_interrupt_class_v9_4_3;
161 break;
162 case IP_VERSION(10, 3, 1): /* VANGOGH */
163 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
164 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
165 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
166 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
167 case IP_VERSION(10, 1, 4):
168 case IP_VERSION(10, 1, 10): /* NAVI10 */
169 case IP_VERSION(10, 1, 2): /* NAVI12 */
170 case IP_VERSION(10, 1, 1): /* NAVI14 */
171 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
172 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
173 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
174 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
175 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
176 break;
177 case IP_VERSION(11, 0, 0):
178 case IP_VERSION(11, 0, 1):
179 case IP_VERSION(11, 0, 2):
180 case IP_VERSION(11, 0, 3):
181 case IP_VERSION(11, 0, 4):
182 case IP_VERSION(11, 5, 0):
183 case IP_VERSION(11, 5, 1):
184 case IP_VERSION(11, 5, 2):
185 case IP_VERSION(11, 5, 3):
186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
187 break;
188 case IP_VERSION(12, 0, 0):
189 case IP_VERSION(12, 0, 1):
190 /* GFX12_TODO: Change to v12 version. */
191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
192 break;
193 default:
194 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
195 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
196 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
197 }
198 }
199
kfd_device_info_init(struct kfd_dev * kfd,bool vf,uint32_t gfx_target_version)200 static void kfd_device_info_init(struct kfd_dev *kfd,
201 bool vf, uint32_t gfx_target_version)
202 {
203 uint32_t gc_version = KFD_GC_VERSION(kfd);
204 uint32_t asic_type = kfd->adev->asic_type;
205
206 kfd->device_info.max_pasid_bits = 16;
207 kfd->device_info.max_no_of_hqd = 24;
208 kfd->device_info.num_of_watch_points = 4;
209 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
210 kfd->device_info.gfx_target_version = gfx_target_version;
211
212 if (KFD_IS_SOC15(kfd)) {
213 kfd->device_info.doorbell_size = 8;
214 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
215 kfd->device_info.supports_cwsr = true;
216
217 kfd_device_info_set_sdma_info(kfd);
218
219 kfd_device_info_set_event_interrupt_class(kfd);
220
221 if (gc_version < IP_VERSION(11, 0, 0)) {
222 /* Navi2x+, Navi1x+ */
223 if (gc_version == IP_VERSION(10, 3, 6))
224 kfd->device_info.no_atomic_fw_version = 14;
225 else if (gc_version == IP_VERSION(10, 3, 7))
226 kfd->device_info.no_atomic_fw_version = 3;
227 else if (gc_version >= IP_VERSION(10, 3, 0))
228 kfd->device_info.no_atomic_fw_version = 92;
229 else if (gc_version >= IP_VERSION(10, 1, 1))
230 kfd->device_info.no_atomic_fw_version = 145;
231
232 /* Navi1x+ */
233 if (gc_version >= IP_VERSION(10, 1, 1))
234 kfd->device_info.needs_pci_atomics = true;
235 } else if (gc_version < IP_VERSION(12, 0, 0)) {
236 /*
237 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
238 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
239 * PCIe atomics support.
240 */
241 kfd->device_info.needs_pci_atomics = true;
242 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
243 } else if (gc_version < IP_VERSION(13, 0, 0)) {
244 kfd->device_info.needs_pci_atomics = true;
245 kfd->device_info.no_atomic_fw_version = 2090;
246 } else {
247 kfd->device_info.needs_pci_atomics = true;
248 }
249 } else {
250 kfd->device_info.doorbell_size = 4;
251 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
252 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
253 kfd->device_info.num_sdma_queues_per_engine = 2;
254
255 if (asic_type != CHIP_KAVERI &&
256 asic_type != CHIP_HAWAII &&
257 asic_type != CHIP_TONGA)
258 kfd->device_info.supports_cwsr = true;
259
260 if (asic_type != CHIP_HAWAII && !vf)
261 kfd->device_info.needs_pci_atomics = true;
262 }
263 }
264
kgd2kfd_probe(struct amdgpu_device * adev,bool vf)265 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
266 {
267 struct kfd_dev *kfd = NULL;
268 const struct kfd2kgd_calls *f2g = NULL;
269 uint32_t gfx_target_version = 0;
270
271 switch (adev->asic_type) {
272 #ifdef CONFIG_DRM_AMDGPU_CIK
273 case CHIP_KAVERI:
274 gfx_target_version = 70000;
275 if (!vf)
276 f2g = &gfx_v7_kfd2kgd;
277 break;
278 #endif
279 case CHIP_CARRIZO:
280 gfx_target_version = 80001;
281 if (!vf)
282 f2g = &gfx_v8_kfd2kgd;
283 break;
284 #ifdef CONFIG_DRM_AMDGPU_CIK
285 case CHIP_HAWAII:
286 gfx_target_version = 70001;
287 if (!amdgpu_exp_hw_support)
288 pr_info(
289 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
290 );
291 else if (!vf)
292 f2g = &gfx_v7_kfd2kgd;
293 break;
294 #endif
295 case CHIP_TONGA:
296 gfx_target_version = 80002;
297 if (!vf)
298 f2g = &gfx_v8_kfd2kgd;
299 break;
300 case CHIP_FIJI:
301 case CHIP_POLARIS10:
302 gfx_target_version = 80003;
303 f2g = &gfx_v8_kfd2kgd;
304 break;
305 case CHIP_POLARIS11:
306 case CHIP_POLARIS12:
307 case CHIP_VEGAM:
308 gfx_target_version = 80003;
309 if (!vf)
310 f2g = &gfx_v8_kfd2kgd;
311 break;
312 default:
313 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
314 /* Vega 10 */
315 case IP_VERSION(9, 0, 1):
316 gfx_target_version = 90000;
317 f2g = &gfx_v9_kfd2kgd;
318 break;
319 /* Raven */
320 case IP_VERSION(9, 1, 0):
321 case IP_VERSION(9, 2, 2):
322 gfx_target_version = 90002;
323 if (!vf)
324 f2g = &gfx_v9_kfd2kgd;
325 break;
326 /* Vega12 */
327 case IP_VERSION(9, 2, 1):
328 gfx_target_version = 90004;
329 if (!vf)
330 f2g = &gfx_v9_kfd2kgd;
331 break;
332 /* Renoir */
333 case IP_VERSION(9, 3, 0):
334 gfx_target_version = 90012;
335 if (!vf)
336 f2g = &gfx_v9_kfd2kgd;
337 break;
338 /* Vega20 */
339 case IP_VERSION(9, 4, 0):
340 gfx_target_version = 90006;
341 if (!vf)
342 f2g = &gfx_v9_kfd2kgd;
343 break;
344 /* Arcturus */
345 case IP_VERSION(9, 4, 1):
346 gfx_target_version = 90008;
347 f2g = &arcturus_kfd2kgd;
348 break;
349 /* Aldebaran */
350 case IP_VERSION(9, 4, 2):
351 gfx_target_version = 90010;
352 f2g = &aldebaran_kfd2kgd;
353 break;
354 case IP_VERSION(9, 4, 3):
355 case IP_VERSION(9, 4, 4):
356 gfx_target_version = 90402;
357 f2g = &gc_9_4_3_kfd2kgd;
358 break;
359 case IP_VERSION(9, 5, 0):
360 gfx_target_version = 90500;
361 f2g = &gc_9_4_3_kfd2kgd;
362 break;
363 /* Navi10 */
364 case IP_VERSION(10, 1, 10):
365 gfx_target_version = 100100;
366 if (!vf)
367 f2g = &gfx_v10_kfd2kgd;
368 break;
369 /* Navi12 */
370 case IP_VERSION(10, 1, 2):
371 gfx_target_version = 100101;
372 f2g = &gfx_v10_kfd2kgd;
373 break;
374 /* Navi14 */
375 case IP_VERSION(10, 1, 1):
376 gfx_target_version = 100102;
377 if (!vf)
378 f2g = &gfx_v10_kfd2kgd;
379 break;
380 /* Cyan Skillfish */
381 case IP_VERSION(10, 1, 3):
382 case IP_VERSION(10, 1, 4):
383 gfx_target_version = 100103;
384 if (!vf)
385 f2g = &gfx_v10_kfd2kgd;
386 break;
387 /* Sienna Cichlid */
388 case IP_VERSION(10, 3, 0):
389 gfx_target_version = 100300;
390 f2g = &gfx_v10_3_kfd2kgd;
391 break;
392 /* Navy Flounder */
393 case IP_VERSION(10, 3, 2):
394 gfx_target_version = 100301;
395 f2g = &gfx_v10_3_kfd2kgd;
396 break;
397 /* Van Gogh */
398 case IP_VERSION(10, 3, 1):
399 gfx_target_version = 100303;
400 if (!vf)
401 f2g = &gfx_v10_3_kfd2kgd;
402 break;
403 /* Dimgrey Cavefish */
404 case IP_VERSION(10, 3, 4):
405 gfx_target_version = 100302;
406 f2g = &gfx_v10_3_kfd2kgd;
407 break;
408 /* Beige Goby */
409 case IP_VERSION(10, 3, 5):
410 gfx_target_version = 100304;
411 f2g = &gfx_v10_3_kfd2kgd;
412 break;
413 /* Yellow Carp */
414 case IP_VERSION(10, 3, 3):
415 gfx_target_version = 100305;
416 if (!vf)
417 f2g = &gfx_v10_3_kfd2kgd;
418 break;
419 case IP_VERSION(10, 3, 6):
420 case IP_VERSION(10, 3, 7):
421 gfx_target_version = 100306;
422 if (!vf)
423 f2g = &gfx_v10_3_kfd2kgd;
424 break;
425 case IP_VERSION(11, 0, 0):
426 gfx_target_version = 110000;
427 f2g = &gfx_v11_kfd2kgd;
428 break;
429 case IP_VERSION(11, 0, 1):
430 case IP_VERSION(11, 0, 4):
431 gfx_target_version = 110003;
432 f2g = &gfx_v11_kfd2kgd;
433 break;
434 case IP_VERSION(11, 0, 2):
435 gfx_target_version = 110002;
436 f2g = &gfx_v11_kfd2kgd;
437 break;
438 case IP_VERSION(11, 0, 3):
439 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
440 gfx_target_version = 110001;
441 f2g = &gfx_v11_kfd2kgd;
442 break;
443 case IP_VERSION(11, 5, 0):
444 gfx_target_version = 110500;
445 f2g = &gfx_v11_kfd2kgd;
446 break;
447 case IP_VERSION(11, 5, 1):
448 gfx_target_version = 110501;
449 f2g = &gfx_v11_kfd2kgd;
450 break;
451 case IP_VERSION(11, 5, 2):
452 gfx_target_version = 110502;
453 f2g = &gfx_v11_kfd2kgd;
454 break;
455 case IP_VERSION(11, 5, 3):
456 gfx_target_version = 110503;
457 f2g = &gfx_v11_kfd2kgd;
458 break;
459 case IP_VERSION(12, 0, 0):
460 gfx_target_version = 120000;
461 f2g = &gfx_v12_kfd2kgd;
462 break;
463 case IP_VERSION(12, 0, 1):
464 gfx_target_version = 120001;
465 f2g = &gfx_v12_kfd2kgd;
466 break;
467 default:
468 break;
469 }
470 break;
471 }
472
473 if (!f2g) {
474 if (amdgpu_ip_version(adev, GC_HWIP, 0))
475 dev_info(kfd_device,
476 "GC IP %06x %s not supported in kfd\n",
477 amdgpu_ip_version(adev, GC_HWIP, 0),
478 vf ? "VF" : "");
479 else
480 dev_info(kfd_device, "%s %s not supported in kfd\n",
481 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
482 return NULL;
483 }
484
485 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
486 if (!kfd)
487 return NULL;
488
489 kfd->adev = adev;
490 kfd_device_info_init(kfd, vf, gfx_target_version);
491 kfd->init_complete = false;
492 kfd->kfd2kgd = f2g;
493 atomic_set(&kfd->compute_profile, 0);
494
495 mutex_init(&kfd->doorbell_mutex);
496
497 ida_init(&kfd->doorbell_ida);
498
499 return kfd;
500 }
501
kfd_cwsr_init(struct kfd_dev * kfd)502 static void kfd_cwsr_init(struct kfd_dev *kfd)
503 {
504 if (cwsr_enable && kfd->device_info.supports_cwsr) {
505 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
506 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex)
507 > KFD_CWSR_TMA_OFFSET);
508 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
509 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
510 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
511 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex)
512 > KFD_CWSR_TMA_OFFSET);
513 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
514 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
515 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
516 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex)
517 > KFD_CWSR_TMA_OFFSET);
518 kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
519 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
520 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
521 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) {
522 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex)
523 > KFD_CWSR_TMA_OFFSET);
524 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
525 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
526 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) {
527 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE);
528 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex;
529 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex);
530 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
531 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex)
532 > KFD_CWSR_TMA_OFFSET);
533 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
534 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
535 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
536 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex)
537 > KFD_CWSR_TMA_OFFSET);
538 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
539 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
540 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
541 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex)
542 > KFD_CWSR_TMA_OFFSET);
543 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
544 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
545 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) {
546 /* The gfx11 cwsr trap handler must fit inside a single
547 page. */
548 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
549 kfd->cwsr_isa = cwsr_trap_gfx11_hex;
550 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
551 } else {
552 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex)
553 > KFD_CWSR_TMA_OFFSET);
554 kfd->cwsr_isa = cwsr_trap_gfx12_hex;
555 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex);
556 }
557
558 kfd->cwsr_enabled = true;
559 }
560 }
561
kfd_gws_init(struct kfd_node * node)562 static int kfd_gws_init(struct kfd_node *node)
563 {
564 int ret = 0;
565 struct kfd_dev *kfd = node->kfd;
566 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
567
568 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
569 return 0;
570
571 if (hws_gws_support || (KFD_IS_SOC15(node) &&
572 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
573 && kfd->mec2_fw_version >= 0x81b3) ||
574 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
575 && kfd->mec2_fw_version >= 0x1b3) ||
576 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
577 && kfd->mec2_fw_version >= 0x30) ||
578 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
579 && kfd->mec2_fw_version >= 0x28) ||
580 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) ||
581 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) ||
582 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) ||
583 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
584 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
585 && kfd->mec2_fw_version >= 0x6b) ||
586 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
587 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
588 && mes_rev >= 68) ||
589 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) {
590 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))
591 node->adev->gds.gws_size = 64;
592 ret = amdgpu_amdkfd_alloc_gws(node->adev,
593 node->adev->gds.gws_size, &node->gws);
594 }
595
596 return ret;
597 }
598
kfd_smi_init(struct kfd_node * dev)599 static void kfd_smi_init(struct kfd_node *dev)
600 {
601 INIT_LIST_HEAD(&dev->smi_clients);
602 spin_lock_init(&dev->smi_lock);
603 }
604
kfd_init_node(struct kfd_node * node)605 static int kfd_init_node(struct kfd_node *node)
606 {
607 int err = -1;
608
609 if (kfd_interrupt_init(node)) {
610 dev_err(kfd_device, "Error initializing interrupts\n");
611 goto kfd_interrupt_error;
612 }
613
614 node->dqm = device_queue_manager_init(node);
615 if (!node->dqm) {
616 dev_err(kfd_device, "Error initializing queue manager\n");
617 goto device_queue_manager_error;
618 }
619
620 if (kfd_gws_init(node)) {
621 dev_err(kfd_device, "Could not allocate %d gws\n",
622 node->adev->gds.gws_size);
623 goto gws_error;
624 }
625
626 if (kfd_resume(node))
627 goto kfd_resume_error;
628
629 if (kfd_topology_add_device(node)) {
630 dev_err(kfd_device, "Error adding device to topology\n");
631 goto kfd_topology_add_device_error;
632 }
633
634 kfd_smi_init(node);
635
636 return 0;
637
638 kfd_topology_add_device_error:
639 kfd_resume_error:
640 gws_error:
641 device_queue_manager_uninit(node->dqm);
642 device_queue_manager_error:
643 kfd_interrupt_exit(node);
644 kfd_interrupt_error:
645 if (node->gws)
646 amdgpu_amdkfd_free_gws(node->adev, node->gws);
647
648 /* Cleanup the node memory here */
649 kfree(node);
650 return err;
651 }
652
kfd_cleanup_nodes(struct kfd_dev * kfd,unsigned int num_nodes)653 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
654 {
655 struct kfd_node *knode;
656 unsigned int i;
657
658 /*
659 * flush_work ensures that there are no outstanding
660 * work-queue items that will access interrupt_ring. New work items
661 * can't be created because we stopped interrupt handling above.
662 */
663 flush_workqueue(kfd->ih_wq);
664 destroy_workqueue(kfd->ih_wq);
665
666 for (i = 0; i < num_nodes; i++) {
667 knode = kfd->nodes[i];
668 device_queue_manager_uninit(knode->dqm);
669 kfd_interrupt_exit(knode);
670 kfd_topology_remove_device(knode);
671 if (knode->gws)
672 amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
673 kfree(knode);
674 kfd->nodes[i] = NULL;
675 }
676 }
677
kfd_setup_interrupt_bitmap(struct kfd_node * node,unsigned int kfd_node_idx)678 static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
679 unsigned int kfd_node_idx)
680 {
681 struct amdgpu_device *adev = node->adev;
682 uint32_t xcc_mask = node->xcc_mask;
683 uint32_t xcc, mapped_xcc;
684 /*
685 * Interrupt bitmap is setup for processing interrupts from
686 * different XCDs and AIDs.
687 * Interrupt bitmap is defined as follows:
688 * 1. Bits 0-15 - correspond to the NodeId field.
689 * Each bit corresponds to NodeId number. For example, if
690 * a KFD node has interrupt bitmap set to 0x7, then this
691 * KFD node will process interrupts with NodeId = 0, 1 and 2
692 * in the IH cookie.
693 * 2. Bits 16-31 - unused.
694 *
695 * Please note that the kfd_node_idx argument passed to this
696 * function is not related to NodeId field received in the
697 * IH cookie.
698 *
699 * In CPX mode, a KFD node will process an interrupt if:
700 * - the Node Id matches the corresponding bit set in
701 * Bits 0-15.
702 * - AND VMID reported in the interrupt lies within the
703 * VMID range of the node.
704 */
705 for_each_inst(xcc, xcc_mask) {
706 mapped_xcc = GET_INST(GC, xcc);
707 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
708 }
709 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
710 node->interrupt_bitmap);
711 }
712
kgd2kfd_device_init(struct kfd_dev * kfd,const struct kgd2kfd_shared_resources * gpu_resources)713 bool kgd2kfd_device_init(struct kfd_dev *kfd,
714 const struct kgd2kfd_shared_resources *gpu_resources)
715 {
716 unsigned int size, map_process_packet_size, i;
717 struct kfd_node *node;
718 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
719 unsigned int max_proc_per_quantum;
720 int partition_mode;
721 int xcp_idx;
722
723 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
724 KGD_ENGINE_MEC1);
725 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
726 KGD_ENGINE_MEC2);
727 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
728 KGD_ENGINE_SDMA1);
729 kfd->shared_resources = *gpu_resources;
730
731 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
732
733 if (kfd->num_nodes == 0) {
734 dev_err(kfd_device,
735 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
736 kfd->adev->gfx.num_xcc_per_xcp);
737 goto out;
738 }
739
740 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
741 * 32 and 64-bit requests are possible and must be
742 * supported.
743 */
744 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
745 if (!kfd->pci_atomic_requested &&
746 kfd->device_info.needs_pci_atomics &&
747 (!kfd->device_info.no_atomic_fw_version ||
748 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
749 dev_info(kfd_device,
750 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
751 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
752 kfd->mec_fw_version,
753 kfd->device_info.no_atomic_fw_version);
754 return false;
755 }
756
757 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
758 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
759 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
760
761 /* For multi-partition capable GPUs, we need special handling for VMIDs
762 * depending on partition mode.
763 * In CPX mode, the VMID range needs to be shared between XCDs.
764 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
765 * divide them equally, we change starting VMID to 4 and not use
766 * VMID 3.
767 * If the VMID range changes for multi-partition capable GPUs, then
768 * this code MUST be revisited.
769 */
770 if (kfd->adev->xcp_mgr) {
771 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
772 AMDGPU_XCP_FL_LOCKED);
773 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
774 kfd->num_nodes != 1) {
775 vmid_num_kfd /= 2;
776 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
777 }
778 }
779
780 /* Verify module parameters regarding mapped process number*/
781 if (hws_max_conc_proc >= 0)
782 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
783 else
784 max_proc_per_quantum = vmid_num_kfd;
785
786 /* calculate max size of mqds needed for queues */
787 size = max_num_of_queues_per_device *
788 kfd->device_info.mqd_size_aligned;
789
790 /*
791 * calculate max size of runlist packet.
792 * There can be only 2 packets at once
793 */
794 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
795 sizeof(struct pm4_mes_map_process_aldebaran) :
796 sizeof(struct pm4_mes_map_process);
797 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
798 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
799 + sizeof(struct pm4_mes_runlist)) * 2;
800
801 /* Add size of HIQ & DIQ */
802 size += KFD_KERNEL_QUEUE_SIZE * 2;
803
804 /* add another 512KB for all other allocations on gart (HPD, fences) */
805 size += 512 * 1024;
806
807 if (amdgpu_amdkfd_alloc_gtt_mem(
808 kfd->adev, size, &kfd->gtt_mem,
809 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
810 false)) {
811 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
812 goto alloc_gtt_mem_failure;
813 }
814
815 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
816
817 /* Initialize GTT sa with 512 byte chunk size */
818 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
819 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
820 goto kfd_gtt_sa_init_error;
821 }
822
823 if (kfd_doorbell_init(kfd)) {
824 dev_err(kfd_device,
825 "Error initializing doorbell aperture\n");
826 goto kfd_doorbell_error;
827 }
828
829 if (amdgpu_use_xgmi_p2p)
830 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
831
832 /*
833 * For multi-partition capable GPUs, the KFD abstracts all partitions
834 * within a socket as xGMI connected in the topology so assign a unique
835 * hive id per device based on the pci device location if device is in
836 * PCIe mode.
837 */
838 if (!kfd->hive_id && kfd->num_nodes > 1)
839 kfd->hive_id = pci_dev_id(kfd->adev->pdev);
840
841 kfd->noretry = kfd->adev->gmc.noretry;
842
843 kfd_cwsr_init(kfd);
844
845 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
846 kfd->num_nodes);
847
848 /* Allocate the KFD nodes */
849 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
850 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
851 if (!node)
852 goto node_alloc_error;
853
854 node->node_id = i;
855 node->adev = kfd->adev;
856 node->kfd = kfd;
857 node->kfd2kgd = kfd->kfd2kgd;
858 node->vm_info.vmid_num_kfd = vmid_num_kfd;
859 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
860 /* TODO : Check if error handling is needed */
861 if (node->xcp) {
862 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
863 &node->xcc_mask);
864 ++xcp_idx;
865 } else {
866 node->xcc_mask =
867 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
868 }
869
870 if (node->xcp) {
871 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
872 node->node_id, node->xcp->mem_id,
873 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
874 }
875
876 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
877 kfd->num_nodes != 1) {
878 /* For multi-partition capable GPUs and CPX mode, first
879 * XCD gets VMID range 4-9 and second XCD gets VMID
880 * range 10-15.
881 */
882
883 node->vm_info.first_vmid_kfd = (i%2 == 0) ?
884 first_vmid_kfd :
885 first_vmid_kfd+vmid_num_kfd;
886 node->vm_info.last_vmid_kfd = (i%2 == 0) ?
887 last_vmid_kfd-vmid_num_kfd :
888 last_vmid_kfd;
889 node->compute_vmid_bitmap =
890 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
891 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
892 } else {
893 node->vm_info.first_vmid_kfd = first_vmid_kfd;
894 node->vm_info.last_vmid_kfd = last_vmid_kfd;
895 node->compute_vmid_bitmap =
896 gpu_resources->compute_vmid_bitmap;
897 }
898 node->max_proc_per_quantum = max_proc_per_quantum;
899 atomic_set(&node->sram_ecc_flag, 0);
900
901 amdgpu_amdkfd_get_local_mem_info(kfd->adev,
902 &node->local_mem_info, node->xcp);
903
904 if (kfd->adev->xcp_mgr)
905 kfd_setup_interrupt_bitmap(node, i);
906
907 /* Initialize the KFD node */
908 if (kfd_init_node(node)) {
909 dev_err(kfd_device, "Error initializing KFD node\n");
910 goto node_init_error;
911 }
912
913 spin_lock_init(&node->watch_points_lock);
914
915 kfd->nodes[i] = node;
916 }
917
918 svm_range_set_max_pages(kfd->adev);
919
920 kfd->init_complete = true;
921 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
922 kfd->adev->pdev->device);
923
924 pr_debug("Starting kfd with the following scheduling policy %d\n",
925 node->dqm->sched_policy);
926
927 goto out;
928
929 node_init_error:
930 node_alloc_error:
931 kfd_cleanup_nodes(kfd, i);
932 kfd_doorbell_fini(kfd);
933 kfd_doorbell_error:
934 kfd_gtt_sa_fini(kfd);
935 kfd_gtt_sa_init_error:
936 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
937 alloc_gtt_mem_failure:
938 dev_err(kfd_device,
939 "device %x:%x NOT added due to errors\n",
940 kfd->adev->pdev->vendor, kfd->adev->pdev->device);
941 out:
942 return kfd->init_complete;
943 }
944
kgd2kfd_device_exit(struct kfd_dev * kfd)945 void kgd2kfd_device_exit(struct kfd_dev *kfd)
946 {
947 if (kfd->init_complete) {
948 /* Cleanup KFD nodes */
949 kfd_cleanup_nodes(kfd, kfd->num_nodes);
950 /* Cleanup common/shared resources */
951 kfd_doorbell_fini(kfd);
952 ida_destroy(&kfd->doorbell_ida);
953 kfd_gtt_sa_fini(kfd);
954 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
955 }
956
957 kfree(kfd);
958 }
959
kgd2kfd_pre_reset(struct kfd_dev * kfd,struct amdgpu_reset_context * reset_context)960 int kgd2kfd_pre_reset(struct kfd_dev *kfd,
961 struct amdgpu_reset_context *reset_context)
962 {
963 struct kfd_node *node;
964 int i;
965
966 if (!kfd->init_complete)
967 return 0;
968
969 for (i = 0; i < kfd->num_nodes; i++) {
970 node = kfd->nodes[i];
971 kfd_smi_event_update_gpu_reset(node, false, reset_context);
972 }
973
974 kgd2kfd_suspend(kfd, true);
975
976 for (i = 0; i < kfd->num_nodes; i++)
977 kfd_signal_reset_event(kfd->nodes[i]);
978
979 return 0;
980 }
981
982 /*
983 * Fix me. KFD won't be able to resume existing process for now.
984 * We will keep all existing process in a evicted state and
985 * wait the process to be terminated.
986 */
987
kgd2kfd_post_reset(struct kfd_dev * kfd)988 int kgd2kfd_post_reset(struct kfd_dev *kfd)
989 {
990 int ret;
991 struct kfd_node *node;
992 int i;
993
994 if (!kfd->init_complete)
995 return 0;
996
997 for (i = 0; i < kfd->num_nodes; i++) {
998 ret = kfd_resume(kfd->nodes[i]);
999 if (ret)
1000 return ret;
1001 }
1002
1003 mutex_lock(&kfd_processes_mutex);
1004 --kfd_locked;
1005 mutex_unlock(&kfd_processes_mutex);
1006
1007 for (i = 0; i < kfd->num_nodes; i++) {
1008 node = kfd->nodes[i];
1009 atomic_set(&node->sram_ecc_flag, 0);
1010 kfd_smi_event_update_gpu_reset(node, true, NULL);
1011 }
1012
1013 return 0;
1014 }
1015
kfd_is_locked(struct kfd_dev * kfd)1016 bool kfd_is_locked(struct kfd_dev *kfd)
1017 {
1018 uint8_t id = 0;
1019 struct kfd_node *dev;
1020
1021 lockdep_assert_held(&kfd_processes_mutex);
1022
1023 /* check reset/suspend lock */
1024 if (kfd_locked > 0)
1025 return true;
1026
1027 if (kfd)
1028 return kfd->kfd_dev_lock > 0;
1029
1030 /* check lock on all cgroup accessible devices */
1031 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) {
1032 if (!dev || kfd_devcgroup_check_permission(dev))
1033 continue;
1034
1035 if (dev->kfd->kfd_dev_lock > 0)
1036 return true;
1037 }
1038
1039 return false;
1040 }
1041
kgd2kfd_suspend(struct kfd_dev * kfd,bool suspend_proc)1042 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc)
1043 {
1044 struct kfd_node *node;
1045 int i;
1046
1047 if (!kfd->init_complete)
1048 return;
1049
1050 if (suspend_proc)
1051 kgd2kfd_suspend_process(kfd);
1052
1053 for (i = 0; i < kfd->num_nodes; i++) {
1054 node = kfd->nodes[i];
1055 node->dqm->ops.stop(node->dqm);
1056 }
1057 }
1058
kgd2kfd_resume(struct kfd_dev * kfd,bool resume_proc)1059 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc)
1060 {
1061 int ret, i;
1062
1063 if (!kfd->init_complete)
1064 return 0;
1065
1066 for (i = 0; i < kfd->num_nodes; i++) {
1067 ret = kfd_resume(kfd->nodes[i]);
1068 if (ret)
1069 return ret;
1070 }
1071
1072 if (resume_proc)
1073 ret = kgd2kfd_resume_process(kfd);
1074
1075 return ret;
1076 }
1077
kgd2kfd_suspend_process(struct kfd_dev * kfd)1078 void kgd2kfd_suspend_process(struct kfd_dev *kfd)
1079 {
1080 if (!kfd->init_complete)
1081 return;
1082
1083 mutex_lock(&kfd_processes_mutex);
1084 /* For first KFD device suspend all the KFD processes */
1085 if (++kfd_locked == 1)
1086 kfd_suspend_all_processes();
1087 mutex_unlock(&kfd_processes_mutex);
1088 }
1089
kgd2kfd_resume_process(struct kfd_dev * kfd)1090 int kgd2kfd_resume_process(struct kfd_dev *kfd)
1091 {
1092 int ret = 0;
1093
1094 if (!kfd->init_complete)
1095 return 0;
1096
1097 mutex_lock(&kfd_processes_mutex);
1098 if (--kfd_locked == 0)
1099 ret = kfd_resume_all_processes();
1100 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error");
1101 mutex_unlock(&kfd_processes_mutex);
1102
1103 return ret;
1104 }
1105
kfd_resume(struct kfd_node * node)1106 static int kfd_resume(struct kfd_node *node)
1107 {
1108 int err = 0;
1109
1110 err = node->dqm->ops.start(node->dqm);
1111 if (err)
1112 dev_err(kfd_device,
1113 "Error starting queue manager for device %x:%x\n",
1114 node->adev->pdev->vendor, node->adev->pdev->device);
1115
1116 return err;
1117 }
1118
1119 /* This is called directly from KGD at ISR. */
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)1120 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1121 {
1122 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1123 bool is_patched = false;
1124 unsigned long flags;
1125 struct kfd_node *node;
1126
1127 if (!kfd->init_complete)
1128 return;
1129
1130 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1131 dev_err_once(kfd_device, "Ring entry too small\n");
1132 return;
1133 }
1134
1135 for (i = 0; i < kfd->num_nodes; i++) {
1136 node = kfd->nodes[i];
1137 spin_lock_irqsave(&node->interrupt_lock, flags);
1138
1139 if (node->interrupts_active
1140 && interrupt_is_wanted(node, ih_ring_entry,
1141 patched_ihre, &is_patched)
1142 && enqueue_ih_ring_entry(node,
1143 is_patched ? patched_ihre : ih_ring_entry)) {
1144 queue_work(node->kfd->ih_wq, &node->interrupt_work);
1145 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1146 return;
1147 }
1148 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1149 }
1150
1151 }
1152
kgd2kfd_quiesce_mm(struct mm_struct * mm,uint32_t trigger)1153 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1154 {
1155 struct kfd_process *p;
1156 int r;
1157
1158 /* Because we are called from arbitrary context (workqueue) as opposed
1159 * to process context, kfd_process could attempt to exit while we are
1160 * running so the lookup function increments the process ref count.
1161 */
1162 p = kfd_lookup_process_by_mm(mm);
1163 if (!p)
1164 return -ESRCH;
1165
1166 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1167 r = kfd_process_evict_queues(p, trigger);
1168
1169 kfd_unref_process(p);
1170 return r;
1171 }
1172
kgd2kfd_resume_mm(struct mm_struct * mm)1173 int kgd2kfd_resume_mm(struct mm_struct *mm)
1174 {
1175 struct kfd_process *p;
1176 int r;
1177
1178 /* Because we are called from arbitrary context (workqueue) as opposed
1179 * to process context, kfd_process could attempt to exit while we are
1180 * running so the lookup function increments the process ref count.
1181 */
1182 p = kfd_lookup_process_by_mm(mm);
1183 if (!p)
1184 return -ESRCH;
1185
1186 r = kfd_process_restore_queues(p);
1187
1188 kfd_unref_process(p);
1189 return r;
1190 }
1191
1192 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1193 * prepare for safe eviction of KFD BOs that belong to the specified
1194 * process.
1195 *
1196 * @mm: mm_struct that identifies the specified KFD process
1197 * @fence: eviction fence attached to KFD process BOs
1198 *
1199 */
kgd2kfd_schedule_evict_and_restore_process(struct mm_struct * mm,struct dma_fence * fence)1200 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1201 struct dma_fence *fence)
1202 {
1203 struct kfd_process *p;
1204 unsigned long active_time;
1205 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1206
1207 if (!fence)
1208 return -EINVAL;
1209
1210 if (dma_fence_is_signaled(fence))
1211 return 0;
1212
1213 p = kfd_lookup_process_by_mm(mm);
1214 if (!p)
1215 return -ENODEV;
1216
1217 if (fence->seqno == p->last_eviction_seqno)
1218 goto out;
1219
1220 p->last_eviction_seqno = fence->seqno;
1221
1222 /* Avoid KFD process starvation. Wait for at least
1223 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1224 */
1225 active_time = get_jiffies_64() - p->last_restore_timestamp;
1226 if (delay_jiffies > active_time)
1227 delay_jiffies -= active_time;
1228 else
1229 delay_jiffies = 0;
1230
1231 /* During process initialization eviction_work.dwork is initialized
1232 * to kfd_evict_bo_worker
1233 */
1234 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1235 p->lead_thread->pid, delay_jiffies);
1236 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1237 out:
1238 kfd_unref_process(p);
1239 return 0;
1240 }
1241
kfd_gtt_sa_init(struct kfd_dev * kfd,unsigned int buf_size,unsigned int chunk_size)1242 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1243 unsigned int chunk_size)
1244 {
1245 if (WARN_ON(buf_size < chunk_size))
1246 return -EINVAL;
1247 if (WARN_ON(buf_size == 0))
1248 return -EINVAL;
1249 if (WARN_ON(chunk_size == 0))
1250 return -EINVAL;
1251
1252 kfd->gtt_sa_chunk_size = chunk_size;
1253 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1254
1255 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1256 GFP_KERNEL);
1257 if (!kfd->gtt_sa_bitmap)
1258 return -ENOMEM;
1259
1260 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1261 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1262
1263 mutex_init(&kfd->gtt_sa_lock);
1264
1265 return 0;
1266 }
1267
kfd_gtt_sa_fini(struct kfd_dev * kfd)1268 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1269 {
1270 mutex_destroy(&kfd->gtt_sa_lock);
1271 bitmap_free(kfd->gtt_sa_bitmap);
1272 }
1273
kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,unsigned int bit_num,unsigned int chunk_size)1274 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1275 unsigned int bit_num,
1276 unsigned int chunk_size)
1277 {
1278 return start_addr + bit_num * chunk_size;
1279 }
1280
kfd_gtt_sa_calc_cpu_addr(void * start_addr,unsigned int bit_num,unsigned int chunk_size)1281 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1282 unsigned int bit_num,
1283 unsigned int chunk_size)
1284 {
1285 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1286 }
1287
kfd_gtt_sa_allocate(struct kfd_node * node,unsigned int size,struct kfd_mem_obj ** mem_obj)1288 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1289 struct kfd_mem_obj **mem_obj)
1290 {
1291 unsigned int found, start_search, cur_size;
1292 struct kfd_dev *kfd = node->kfd;
1293
1294 if (size == 0)
1295 return -EINVAL;
1296
1297 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1298 return -ENOMEM;
1299
1300 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1301 if (!(*mem_obj))
1302 return -ENOMEM;
1303
1304 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1305
1306 start_search = 0;
1307
1308 mutex_lock(&kfd->gtt_sa_lock);
1309
1310 kfd_gtt_restart_search:
1311 /* Find the first chunk that is free */
1312 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1313 kfd->gtt_sa_num_of_chunks,
1314 start_search);
1315
1316 pr_debug("Found = %d\n", found);
1317
1318 /* If there wasn't any free chunk, bail out */
1319 if (found == kfd->gtt_sa_num_of_chunks)
1320 goto kfd_gtt_no_free_chunk;
1321
1322 /* Update fields of mem_obj */
1323 (*mem_obj)->range_start = found;
1324 (*mem_obj)->range_end = found;
1325 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1326 kfd->gtt_start_gpu_addr,
1327 found,
1328 kfd->gtt_sa_chunk_size);
1329 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1330 kfd->gtt_start_cpu_ptr,
1331 found,
1332 kfd->gtt_sa_chunk_size);
1333
1334 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1335 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1336
1337 /* If we need only one chunk, mark it as allocated and get out */
1338 if (size <= kfd->gtt_sa_chunk_size) {
1339 pr_debug("Single bit\n");
1340 __set_bit(found, kfd->gtt_sa_bitmap);
1341 goto kfd_gtt_out;
1342 }
1343
1344 /* Otherwise, try to see if we have enough contiguous chunks */
1345 cur_size = size - kfd->gtt_sa_chunk_size;
1346 do {
1347 (*mem_obj)->range_end =
1348 find_next_zero_bit(kfd->gtt_sa_bitmap,
1349 kfd->gtt_sa_num_of_chunks, ++found);
1350 /*
1351 * If next free chunk is not contiguous than we need to
1352 * restart our search from the last free chunk we found (which
1353 * wasn't contiguous to the previous ones
1354 */
1355 if ((*mem_obj)->range_end != found) {
1356 start_search = found;
1357 goto kfd_gtt_restart_search;
1358 }
1359
1360 /*
1361 * If we reached end of buffer, bail out with error
1362 */
1363 if (found == kfd->gtt_sa_num_of_chunks)
1364 goto kfd_gtt_no_free_chunk;
1365
1366 /* Check if we don't need another chunk */
1367 if (cur_size <= kfd->gtt_sa_chunk_size)
1368 cur_size = 0;
1369 else
1370 cur_size -= kfd->gtt_sa_chunk_size;
1371
1372 } while (cur_size > 0);
1373
1374 pr_debug("range_start = %d, range_end = %d\n",
1375 (*mem_obj)->range_start, (*mem_obj)->range_end);
1376
1377 /* Mark the chunks as allocated */
1378 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1379 (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1380
1381 kfd_gtt_out:
1382 mutex_unlock(&kfd->gtt_sa_lock);
1383 return 0;
1384
1385 kfd_gtt_no_free_chunk:
1386 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1387 mutex_unlock(&kfd->gtt_sa_lock);
1388 kfree(*mem_obj);
1389 return -ENOMEM;
1390 }
1391
kfd_gtt_sa_free(struct kfd_node * node,struct kfd_mem_obj * mem_obj)1392 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1393 {
1394 struct kfd_dev *kfd = node->kfd;
1395
1396 /* Act like kfree when trying to free a NULL object */
1397 if (!mem_obj)
1398 return 0;
1399
1400 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1401 mem_obj, mem_obj->range_start, mem_obj->range_end);
1402
1403 mutex_lock(&kfd->gtt_sa_lock);
1404
1405 /* Mark the chunks as free */
1406 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1407 mem_obj->range_end - mem_obj->range_start + 1);
1408
1409 mutex_unlock(&kfd->gtt_sa_lock);
1410
1411 kfree(mem_obj);
1412 return 0;
1413 }
1414
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)1415 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1416 {
1417 /*
1418 * TODO: Currently update SRAM ECC flag for first node.
1419 * This needs to be updated later when we can
1420 * identify SRAM ECC error on other nodes also.
1421 */
1422 if (kfd)
1423 atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1424 }
1425
kfd_inc_compute_active(struct kfd_node * node)1426 void kfd_inc_compute_active(struct kfd_node *node)
1427 {
1428 if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1429 amdgpu_amdkfd_set_compute_idle(node->adev, false);
1430 }
1431
kfd_dec_compute_active(struct kfd_node * node)1432 void kfd_dec_compute_active(struct kfd_node *node)
1433 {
1434 int count = atomic_dec_return(&node->kfd->compute_profile);
1435
1436 if (count == 0)
1437 amdgpu_amdkfd_set_compute_idle(node->adev, true);
1438 WARN_ONCE(count < 0, "Compute profile ref. count error");
1439 }
1440
kfd_compute_active(struct kfd_node * node)1441 static bool kfd_compute_active(struct kfd_node *node)
1442 {
1443 if (atomic_read(&node->kfd->compute_profile))
1444 return true;
1445 return false;
1446 }
1447
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint64_t throttle_bitmask)1448 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1449 {
1450 /*
1451 * TODO: For now, raise the throttling event only on first node.
1452 * This will need to change after we are able to determine
1453 * which node raised the throttling event.
1454 */
1455 if (kfd && kfd->init_complete)
1456 kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1457 throttle_bitmask);
1458 }
1459
1460 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1461 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1462 * When the device has more than two engines, we reserve two for PCIe to enable
1463 * full-duplex and the rest are used as XGMI.
1464 */
kfd_get_num_sdma_engines(struct kfd_node * node)1465 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1466 {
1467 /* If XGMI is not supported, all SDMA engines are PCIe */
1468 if (!node->adev->gmc.xgmi.supported)
1469 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1470
1471 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1472 }
1473
kfd_get_num_xgmi_sdma_engines(struct kfd_node * node)1474 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1475 {
1476 /* After reserved for PCIe, the rest of engines are XGMI */
1477 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1478 kfd_get_num_sdma_engines(node);
1479 }
1480
kgd2kfd_check_and_lock_kfd(struct kfd_dev * kfd)1481 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd)
1482 {
1483 struct kfd_process *p;
1484 int r = 0, temp, idx;
1485
1486 mutex_lock(&kfd_processes_mutex);
1487
1488 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd))
1489 goto out;
1490
1491 /* fail under system reset/resume or kfd device is partition switching. */
1492 if (kfd_is_locked(kfd)) {
1493 r = -EBUSY;
1494 goto out;
1495 }
1496
1497 /*
1498 * ensure all running processes are cgroup excluded from device before mode switch.
1499 * i.e. no pdd was created on the process socket.
1500 */
1501 idx = srcu_read_lock(&kfd_processes_srcu);
1502 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) {
1503 int i;
1504
1505 for (i = 0; i < p->n_pdds; i++) {
1506 if (p->pdds[i]->dev->kfd != kfd)
1507 continue;
1508
1509 r = -EBUSY;
1510 goto proc_check_unlock;
1511 }
1512 }
1513
1514 proc_check_unlock:
1515 srcu_read_unlock(&kfd_processes_srcu, idx);
1516 out:
1517 if (!r)
1518 ++kfd->kfd_dev_lock;
1519 mutex_unlock(&kfd_processes_mutex);
1520
1521 return r;
1522 }
1523
kgd2kfd_unlock_kfd(struct kfd_dev * kfd)1524 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd)
1525 {
1526 mutex_lock(&kfd_processes_mutex);
1527 --kfd->kfd_dev_lock;
1528 mutex_unlock(&kfd_processes_mutex);
1529 }
1530
kgd2kfd_start_sched(struct kfd_dev * kfd,uint32_t node_id)1531 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)
1532 {
1533 struct kfd_node *node;
1534 int ret;
1535
1536 if (!kfd->init_complete)
1537 return 0;
1538
1539 if (node_id >= kfd->num_nodes) {
1540 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1541 node_id, kfd->num_nodes - 1);
1542 return -EINVAL;
1543 }
1544 node = kfd->nodes[node_id];
1545
1546 ret = node->dqm->ops.unhalt(node->dqm);
1547 if (ret)
1548 dev_err(kfd_device, "Error in starting scheduler\n");
1549
1550 return ret;
1551 }
1552
kgd2kfd_stop_sched(struct kfd_dev * kfd,uint32_t node_id)1553 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)
1554 {
1555 struct kfd_node *node;
1556
1557 if (!kfd->init_complete)
1558 return 0;
1559
1560 if (node_id >= kfd->num_nodes) {
1561 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1562 node_id, kfd->num_nodes - 1);
1563 return -EINVAL;
1564 }
1565
1566 node = kfd->nodes[node_id];
1567 return node->dqm->ops.halt(node->dqm);
1568 }
1569
kgd2kfd_compute_active(struct kfd_dev * kfd,uint32_t node_id)1570 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)
1571 {
1572 struct kfd_node *node;
1573
1574 if (!kfd->init_complete)
1575 return false;
1576
1577 if (node_id >= kfd->num_nodes) {
1578 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1579 node_id, kfd->num_nodes - 1);
1580 return false;
1581 }
1582
1583 node = kfd->nodes[node_id];
1584
1585 return kfd_compute_active(node);
1586 }
1587
1588 /**
1589 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9
1590 * @adev: amdgpu device
1591 * @entry: vm fault interrupt vector
1592 * @retry_fault: if this is retry fault
1593 *
1594 * retry fault -
1595 * with CAM enabled, adev primary ring
1596 * | gmc_v9_0_process_interrupt()
1597 * adev soft_ring
1598 * | gmc_v9_0_process_interrupt() worker failed to recover page fault
1599 * KFD node ih_fifo
1600 * | KFD interrupt_wq worker
1601 * kfd_signal_vm_fault_event
1602 *
1603 * without CAM, adev primary ring1
1604 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault
1605 * KFD node ih_fifo
1606 * | KFD interrupt_wq worker
1607 * kfd_signal_vm_fault_event
1608 *
1609 * no-retry fault -
1610 * adev primary ring
1611 * | gmc_v9_0_process_interrupt()
1612 * KFD node ih_fifo
1613 * | KFD interrupt_wq worker
1614 * kfd_signal_vm_fault_event
1615 *
1616 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault
1617 * of same process, don't copy interrupt to KFD node ih_fifo.
1618 * With gdb debugger enabled, need convert the retry fault to no-retry fault for
1619 * debugger, cannot use the fast path.
1620 *
1621 * Return:
1622 * true - use the fast path to handle this fault
1623 * false - use normal path to handle it
1624 */
kgd2kfd_vmfault_fast_path(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry,bool retry_fault)1625 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry,
1626 bool retry_fault)
1627 {
1628 struct kfd_process *p;
1629 u32 cam_index;
1630
1631 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) {
1632 p = kfd_lookup_process_by_pasid(entry->pasid, NULL);
1633 if (!p)
1634 return true;
1635
1636 if (p->gpu_page_fault && !p->debug_trap_enabled) {
1637 if (retry_fault && adev->irq.retry_cam_enabled) {
1638 cam_index = entry->src_data[2] & 0x3ff;
1639 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
1640 }
1641
1642 kfd_unref_process(p);
1643 return true;
1644 }
1645
1646 /*
1647 * This is the first page fault, set flag and then signal user space
1648 */
1649 p->gpu_page_fault = true;
1650 kfd_unref_process(p);
1651 }
1652 return false;
1653 }
1654
1655 #if defined(CONFIG_DEBUG_FS)
1656
1657 /* This function will send a package to HIQ to hang the HWS
1658 * which will trigger a GPU reset and bring the HWS back to normal state
1659 */
kfd_debugfs_hang_hws(struct kfd_node * dev)1660 int kfd_debugfs_hang_hws(struct kfd_node *dev)
1661 {
1662 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1663 pr_err("HWS is not enabled");
1664 return -EINVAL;
1665 }
1666
1667 if (dev->kfd->shared_resources.enable_mes) {
1668 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n");
1669 return -EINVAL;
1670 }
1671
1672 return dqm_debugfs_hang_hws(dev->dqm);
1673 }
1674
1675 #endif
1676