1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/iopoll.h>
7 #include <linux/sched.h>
8
9 #include "ixgbe.h"
10 #include "ixgbe_phy.h"
11
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28 /**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)35 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36 {
37 s32 status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43 }
44
45 /**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)52 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53 {
54 s32 status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61 }
62
63 /**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71 {
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76 }
77
78 /**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)88 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90 {
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return IXGBE_ERR_SWFW_SYNC;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142 fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return IXGBE_ERR_I2C;
154 }
155
156 /**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)166 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168 {
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 1;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return IXGBE_ERR_SWFW_SYNC;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207 fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return IXGBE_ERR_I2C;
219 }
220
221 /**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229 {
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255 }
256
257 /**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)263 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264 {
265 u32 phy_addr;
266 u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = (hw->phy.nw_mng_if_sel &
280 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
281 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
282 if (ixgbe_probe_phy(hw, phy_addr))
283 return 0;
284 else
285 return IXGBE_ERR_PHY_ADDR_INVALID;
286 }
287
288 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
289 if (ixgbe_probe_phy(hw, phy_addr)) {
290 status = 0;
291 break;
292 }
293 }
294
295 /* Certain media types do not have a phy so an address will not
296 * be found and the code will take this path. Caller has to
297 * decide if it is an error or not.
298 */
299 if (status)
300 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
301
302 return status;
303 }
304
305 /**
306 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
307 * @hw: pointer to the hardware structure
308 *
309 * This function checks the MMNGC.MNG_VETO bit to see if there are
310 * any constraints on link from manageability. For MAC's that don't
311 * have this bit just return false since the link can not be blocked
312 * via this method.
313 **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)314 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
315 {
316 u32 mmngc;
317
318 /* If we don't have this bit, it can't be blocking */
319 if (hw->mac.type == ixgbe_mac_82598EB)
320 return false;
321
322 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
323 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
324 hw_dbg(hw, "MNG_VETO bit detected.\n");
325 return true;
326 }
327
328 return false;
329 }
330
331 /**
332 * ixgbe_get_phy_id - Get the phy type
333 * @hw: pointer to hardware structure
334 *
335 **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)336 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
337 {
338 s32 status;
339 u16 phy_id_high = 0;
340 u16 phy_id_low = 0;
341
342 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
343 &phy_id_high);
344
345 if (!status) {
346 hw->phy.id = (u32)(phy_id_high << 16);
347 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
348 &phy_id_low);
349 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
350 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
351 }
352 return status;
353 }
354
355 /**
356 * ixgbe_get_phy_type_from_id - Get the phy type
357 * @phy_id: hardware phy id
358 *
359 **/
ixgbe_get_phy_type_from_id(u32 phy_id)360 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
361 {
362 enum ixgbe_phy_type phy_type;
363
364 switch (phy_id) {
365 case TN1010_PHY_ID:
366 phy_type = ixgbe_phy_tn;
367 break;
368 case X550_PHY_ID2:
369 case X550_PHY_ID3:
370 case X540_PHY_ID:
371 phy_type = ixgbe_phy_aq;
372 break;
373 case QT2022_PHY_ID:
374 phy_type = ixgbe_phy_qt;
375 break;
376 case ATH_PHY_ID:
377 phy_type = ixgbe_phy_nl;
378 break;
379 case X557_PHY_ID:
380 case X557_PHY_ID2:
381 phy_type = ixgbe_phy_x550em_ext_t;
382 break;
383 default:
384 phy_type = ixgbe_phy_unknown;
385 break;
386 }
387
388 return phy_type;
389 }
390
391 /**
392 * ixgbe_reset_phy_generic - Performs a PHY reset
393 * @hw: pointer to hardware structure
394 **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)395 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
396 {
397 u32 i;
398 u16 ctrl = 0;
399 s32 status = 0;
400
401 if (hw->phy.type == ixgbe_phy_unknown)
402 status = ixgbe_identify_phy_generic(hw);
403
404 if (status != 0 || hw->phy.type == ixgbe_phy_none)
405 return status;
406
407 /* Don't reset PHY if it's shut down due to overtemp. */
408 if (!hw->phy.reset_if_overtemp &&
409 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
410 return 0;
411
412 /* Blocked by MNG FW so bail */
413 if (ixgbe_check_reset_blocked(hw))
414 return 0;
415
416 /*
417 * Perform soft PHY reset to the PHY_XS.
418 * This will cause a soft reset to the PHY
419 */
420 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
421 MDIO_MMD_PHYXS,
422 MDIO_CTRL1_RESET);
423
424 /*
425 * Poll for reset bit to self-clear indicating reset is complete.
426 * Some PHYs could take up to 3 seconds to complete and need about
427 * 1.7 usec delay after the reset is complete.
428 */
429 for (i = 0; i < 30; i++) {
430 msleep(100);
431 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
432 status = hw->phy.ops.read_reg(hw,
433 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
434 MDIO_MMD_PMAPMD, &ctrl);
435 if (status)
436 return status;
437
438 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
439 udelay(2);
440 break;
441 }
442 } else {
443 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
444 MDIO_MMD_PHYXS, &ctrl);
445 if (status)
446 return status;
447
448 if (!(ctrl & MDIO_CTRL1_RESET)) {
449 udelay(2);
450 break;
451 }
452 }
453 }
454
455 if (ctrl & MDIO_CTRL1_RESET) {
456 hw_dbg(hw, "PHY reset polling failed to complete.\n");
457 return IXGBE_ERR_RESET_FAILED;
458 }
459
460 return 0;
461 }
462
463 /**
464 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
465 * the SWFW lock
466 * @hw: pointer to hardware structure
467 * @reg_addr: 32 bit address of PHY register to read
468 * @device_type: 5 bit device type
469 * @phy_data: Pointer to read data from PHY register
470 **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)471 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
472 u16 *phy_data)
473 {
474 u32 i, data, command;
475
476 /* Setup and write the address cycle command */
477 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
478 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
479 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
480 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
481
482 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
483
484 /* Check every 10 usec to see if the address cycle completed.
485 * The MDI Command bit will clear when the operation is
486 * complete
487 */
488 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
489 udelay(10);
490
491 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
492 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
493 break;
494 }
495
496
497 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
498 hw_dbg(hw, "PHY address command did not complete.\n");
499 return IXGBE_ERR_PHY;
500 }
501
502 /* Address cycle complete, setup and write the read
503 * command
504 */
505 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
506 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
507 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
508 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
509
510 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
511
512 /* Check every 10 usec to see if the address cycle
513 * completed. The MDI Command bit will clear when the
514 * operation is complete
515 */
516 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
517 udelay(10);
518
519 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
520 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
521 break;
522 }
523
524 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
525 hw_dbg(hw, "PHY read command didn't complete\n");
526 return IXGBE_ERR_PHY;
527 }
528
529 /* Read operation is complete. Get the data
530 * from MSRWD
531 */
532 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
533 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
534 *phy_data = (u16)(data);
535
536 return 0;
537 }
538
539 /**
540 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
541 * using the SWFW lock - this function is needed in most cases
542 * @hw: pointer to hardware structure
543 * @reg_addr: 32 bit address of PHY register to read
544 * @device_type: 5 bit device type
545 * @phy_data: Pointer to read data from PHY register
546 **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)547 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
548 u32 device_type, u16 *phy_data)
549 {
550 s32 status;
551 u32 gssr = hw->phy.phy_semaphore_mask;
552
553 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
554 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
555 phy_data);
556 hw->mac.ops.release_swfw_sync(hw, gssr);
557 } else {
558 return IXGBE_ERR_SWFW_SYNC;
559 }
560
561 return status;
562 }
563
564 /**
565 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
566 * without SWFW lock
567 * @hw: pointer to hardware structure
568 * @reg_addr: 32 bit PHY register to write
569 * @device_type: 5 bit device type
570 * @phy_data: Data to write to the PHY register
571 **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)572 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
573 u32 device_type, u16 phy_data)
574 {
575 u32 i, command;
576
577 /* Put the data in the MDI single read and write data register*/
578 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
579
580 /* Setup and write the address cycle command */
581 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
582 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
583 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
584 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
585
586 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
587
588 /*
589 * Check every 10 usec to see if the address cycle completed.
590 * The MDI Command bit will clear when the operation is
591 * complete
592 */
593 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
594 udelay(10);
595
596 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
597 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
598 break;
599 }
600
601 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
602 hw_dbg(hw, "PHY address cmd didn't complete\n");
603 return IXGBE_ERR_PHY;
604 }
605
606 /*
607 * Address cycle complete, setup and write the write
608 * command
609 */
610 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
611 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
612 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
613 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
614
615 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
616
617 /* Check every 10 usec to see if the address cycle
618 * completed. The MDI Command bit will clear when the
619 * operation is complete
620 */
621 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
622 udelay(10);
623
624 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
625 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
626 break;
627 }
628
629 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
630 hw_dbg(hw, "PHY write cmd didn't complete\n");
631 return IXGBE_ERR_PHY;
632 }
633
634 return 0;
635 }
636
637 /**
638 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
639 * using SWFW lock- this function is needed in most cases
640 * @hw: pointer to hardware structure
641 * @reg_addr: 32 bit PHY register to write
642 * @device_type: 5 bit device type
643 * @phy_data: Data to write to the PHY register
644 **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)645 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
646 u32 device_type, u16 phy_data)
647 {
648 s32 status;
649 u32 gssr = hw->phy.phy_semaphore_mask;
650
651 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
652 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
653 phy_data);
654 hw->mac.ops.release_swfw_sync(hw, gssr);
655 } else {
656 return IXGBE_ERR_SWFW_SYNC;
657 }
658
659 return status;
660 }
661
662 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
663
664 /**
665 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
666 * @hw: pointer to hardware structure
667 * @cmd: command register value to write
668 **/
ixgbe_msca_cmd(struct ixgbe_hw * hw,u32 cmd)669 static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
670 {
671 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
672
673 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
674 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
675 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
676 }
677
678 /**
679 * ixgbe_mii_bus_read_generic - Read a clause 22/45 register with gssr flags
680 * @hw: pointer to hardware structure
681 * @addr: address
682 * @regnum: register number
683 * @gssr: semaphore flags to acquire
684 **/
ixgbe_mii_bus_read_generic(struct ixgbe_hw * hw,int addr,int regnum,u32 gssr)685 static s32 ixgbe_mii_bus_read_generic(struct ixgbe_hw *hw, int addr,
686 int regnum, u32 gssr)
687 {
688 u32 hwaddr, cmd;
689 s32 data;
690
691 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
692 return -EBUSY;
693
694 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
695 if (regnum & MII_ADDR_C45) {
696 hwaddr |= regnum & GENMASK(21, 0);
697 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
698 } else {
699 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
700 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
701 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
702 }
703
704 data = ixgbe_msca_cmd(hw, cmd);
705 if (data < 0)
706 goto mii_bus_read_done;
707
708 /* For a clause 45 access the address cycle just completed, we still
709 * need to do the read command, otherwise just get the data
710 */
711 if (!(regnum & MII_ADDR_C45))
712 goto do_mii_bus_read;
713
714 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
715 data = ixgbe_msca_cmd(hw, cmd);
716 if (data < 0)
717 goto mii_bus_read_done;
718
719 do_mii_bus_read:
720 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
721 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
722
723 mii_bus_read_done:
724 hw->mac.ops.release_swfw_sync(hw, gssr);
725 return data;
726 }
727
728 /**
729 * ixgbe_mii_bus_write_generic - Write a clause 22/45 register with gssr flags
730 * @hw: pointer to hardware structure
731 * @addr: address
732 * @regnum: register number
733 * @val: value to write
734 * @gssr: semaphore flags to acquire
735 **/
ixgbe_mii_bus_write_generic(struct ixgbe_hw * hw,int addr,int regnum,u16 val,u32 gssr)736 static s32 ixgbe_mii_bus_write_generic(struct ixgbe_hw *hw, int addr,
737 int regnum, u16 val, u32 gssr)
738 {
739 u32 hwaddr, cmd;
740 s32 err;
741
742 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
743 return -EBUSY;
744
745 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
746
747 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
748 if (regnum & MII_ADDR_C45) {
749 hwaddr |= regnum & GENMASK(21, 0);
750 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
751 } else {
752 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
753 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
754 IXGBE_MSCA_MDI_COMMAND;
755 }
756
757 /* For clause 45 this is an address cycle, for clause 22 this is the
758 * entire transaction
759 */
760 err = ixgbe_msca_cmd(hw, cmd);
761 if (err < 0 || !(regnum & MII_ADDR_C45))
762 goto mii_bus_write_done;
763
764 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
765 err = ixgbe_msca_cmd(hw, cmd);
766
767 mii_bus_write_done:
768 hw->mac.ops.release_swfw_sync(hw, gssr);
769 return err;
770 }
771
772 /**
773 * ixgbe_mii_bus_read - Read a clause 22/45 register
774 * @bus: pointer to mii_bus structure which points to our driver private
775 * @addr: address
776 * @regnum: register number
777 **/
ixgbe_mii_bus_read(struct mii_bus * bus,int addr,int regnum)778 static s32 ixgbe_mii_bus_read(struct mii_bus *bus, int addr, int regnum)
779 {
780 struct ixgbe_adapter *adapter = bus->priv;
781 struct ixgbe_hw *hw = &adapter->hw;
782 u32 gssr = hw->phy.phy_semaphore_mask;
783
784 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
785 }
786
787 /**
788 * ixgbe_mii_bus_write - Write a clause 22/45 register
789 * @bus: pointer to mii_bus structure which points to our driver private
790 * @addr: address
791 * @regnum: register number
792 * @val: value to write
793 **/
ixgbe_mii_bus_write(struct mii_bus * bus,int addr,int regnum,u16 val)794 static s32 ixgbe_mii_bus_write(struct mii_bus *bus, int addr, int regnum,
795 u16 val)
796 {
797 struct ixgbe_adapter *adapter = bus->priv;
798 struct ixgbe_hw *hw = &adapter->hw;
799 u32 gssr = hw->phy.phy_semaphore_mask;
800
801 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
802 }
803
804 /**
805 * ixgbe_x550em_a_mii_bus_read - Read a clause 22/45 register on x550em_a
806 * @bus: pointer to mii_bus structure which points to our driver private
807 * @addr: address
808 * @regnum: register number
809 **/
ixgbe_x550em_a_mii_bus_read(struct mii_bus * bus,int addr,int regnum)810 static s32 ixgbe_x550em_a_mii_bus_read(struct mii_bus *bus, int addr,
811 int regnum)
812 {
813 struct ixgbe_adapter *adapter = bus->priv;
814 struct ixgbe_hw *hw = &adapter->hw;
815 u32 gssr = hw->phy.phy_semaphore_mask;
816
817 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
818 return ixgbe_mii_bus_read_generic(hw, addr, regnum, gssr);
819 }
820
821 /**
822 * ixgbe_x550em_a_mii_bus_write - Write a clause 22/45 register on x550em_a
823 * @bus: pointer to mii_bus structure which points to our driver private
824 * @addr: address
825 * @regnum: register number
826 * @val: value to write
827 **/
ixgbe_x550em_a_mii_bus_write(struct mii_bus * bus,int addr,int regnum,u16 val)828 static s32 ixgbe_x550em_a_mii_bus_write(struct mii_bus *bus, int addr,
829 int regnum, u16 val)
830 {
831 struct ixgbe_adapter *adapter = bus->priv;
832 struct ixgbe_hw *hw = &adapter->hw;
833 u32 gssr = hw->phy.phy_semaphore_mask;
834
835 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
836 return ixgbe_mii_bus_write_generic(hw, addr, regnum, val, gssr);
837 }
838
839 /**
840 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
841 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
842 *
843 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
844 * on domain 0, bus 0, devfn = 'devfn'
845 **/
ixgbe_get_first_secondary_devfn(unsigned int devfn)846 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
847 {
848 struct pci_dev *rp_pdev;
849 int bus;
850
851 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
852 if (rp_pdev && rp_pdev->subordinate) {
853 bus = rp_pdev->subordinate->number;
854 return pci_get_domain_bus_and_slot(0, bus, 0);
855 }
856
857 return NULL;
858 }
859
860 /**
861 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
862 * @hw: pointer to hardware structure
863 *
864 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
865 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
866 * but we only want to register one MDIO bus.
867 **/
ixgbe_x550em_a_has_mii(struct ixgbe_hw * hw)868 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
869 {
870 struct ixgbe_adapter *adapter = hw->back;
871 struct pci_dev *pdev = adapter->pdev;
872 struct pci_dev *func0_pdev;
873
874 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
875 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
876 * It's not valid for function 0 to be disabled and function 1 is up,
877 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
878 * of those two root ports
879 */
880 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
881 if (func0_pdev) {
882 if (func0_pdev == pdev)
883 return true;
884 else
885 return false;
886 }
887 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
888 if (func0_pdev == pdev)
889 return true;
890
891 return false;
892 }
893
894 /**
895 * ixgbe_mii_bus_init - mii_bus structure setup
896 * @hw: pointer to hardware structure
897 *
898 * Returns 0 on success, negative on failure
899 *
900 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
901 **/
ixgbe_mii_bus_init(struct ixgbe_hw * hw)902 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
903 {
904 s32 (*write)(struct mii_bus *bus, int addr, int regnum, u16 val);
905 s32 (*read)(struct mii_bus *bus, int addr, int regnum);
906 struct ixgbe_adapter *adapter = hw->back;
907 struct pci_dev *pdev = adapter->pdev;
908 struct device *dev = &adapter->netdev->dev;
909 struct mii_bus *bus;
910
911 switch (hw->device_id) {
912 /* C3000 SoCs */
913 case IXGBE_DEV_ID_X550EM_A_KR:
914 case IXGBE_DEV_ID_X550EM_A_KR_L:
915 case IXGBE_DEV_ID_X550EM_A_SFP_N:
916 case IXGBE_DEV_ID_X550EM_A_SGMII:
917 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
918 case IXGBE_DEV_ID_X550EM_A_10G_T:
919 case IXGBE_DEV_ID_X550EM_A_SFP:
920 case IXGBE_DEV_ID_X550EM_A_1G_T:
921 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
922 if (!ixgbe_x550em_a_has_mii(hw))
923 return 0;
924 read = &ixgbe_x550em_a_mii_bus_read;
925 write = &ixgbe_x550em_a_mii_bus_write;
926 break;
927 default:
928 read = &ixgbe_mii_bus_read;
929 write = &ixgbe_mii_bus_write;
930 break;
931 }
932
933 bus = devm_mdiobus_alloc(dev);
934 if (!bus)
935 return -ENOMEM;
936
937 bus->read = read;
938 bus->write = write;
939
940 /* Use the position of the device in the PCI hierarchy as the id */
941 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
942 pci_name(pdev));
943
944 bus->name = "ixgbe-mdio";
945 bus->priv = adapter;
946 bus->parent = dev;
947 bus->phy_mask = GENMASK(31, 0);
948
949 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
950 * unfortunately that causes some clause 22 frames to be sent with
951 * clause 45 addressing. We don't want that.
952 */
953 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
954
955 adapter->mii_bus = bus;
956 return mdiobus_register(bus);
957 }
958
959 /**
960 * ixgbe_setup_phy_link_generic - Set and restart autoneg
961 * @hw: pointer to hardware structure
962 *
963 * Restart autonegotiation and PHY and waits for completion.
964 **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)965 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
966 {
967 s32 status = 0;
968 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
969 bool autoneg = false;
970 ixgbe_link_speed speed;
971
972 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
973
974 /* Set or unset auto-negotiation 10G advertisement */
975 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
976
977 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
978 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
979 (speed & IXGBE_LINK_SPEED_10GB_FULL))
980 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
981
982 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
983
984 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
985 MDIO_MMD_AN, &autoneg_reg);
986
987 if (hw->mac.type == ixgbe_mac_X550) {
988 /* Set or unset auto-negotiation 5G advertisement */
989 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
990 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
991 (speed & IXGBE_LINK_SPEED_5GB_FULL))
992 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
993
994 /* Set or unset auto-negotiation 2.5G advertisement */
995 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
996 if ((hw->phy.autoneg_advertised &
997 IXGBE_LINK_SPEED_2_5GB_FULL) &&
998 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
999 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1000 }
1001
1002 /* Set or unset auto-negotiation 1G advertisement */
1003 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1004 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1005 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1006 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1007
1008 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1009 MDIO_MMD_AN, autoneg_reg);
1010
1011 /* Set or unset auto-negotiation 100M advertisement */
1012 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1013
1014 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1015 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1016 (speed & IXGBE_LINK_SPEED_100_FULL))
1017 autoneg_reg |= ADVERTISE_100FULL;
1018
1019 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1020
1021 /* Blocked by MNG FW so don't reset PHY */
1022 if (ixgbe_check_reset_blocked(hw))
1023 return 0;
1024
1025 /* Restart PHY autonegotiation and wait for completion */
1026 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1027 MDIO_MMD_AN, &autoneg_reg);
1028
1029 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1030
1031 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1032 MDIO_MMD_AN, autoneg_reg);
1033
1034 return status;
1035 }
1036
1037 /**
1038 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1039 * @hw: pointer to hardware structure
1040 * @speed: new link speed
1041 * @autoneg_wait_to_complete: unused
1042 **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)1043 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1044 ixgbe_link_speed speed,
1045 bool autoneg_wait_to_complete)
1046 {
1047 /* Clear autoneg_advertised and set new values based on input link
1048 * speed.
1049 */
1050 hw->phy.autoneg_advertised = 0;
1051
1052 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1053 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1054
1055 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1056 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1057
1058 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1059 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1060
1061 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1062 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1063
1064 if (speed & IXGBE_LINK_SPEED_100_FULL)
1065 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1066
1067 if (speed & IXGBE_LINK_SPEED_10_FULL)
1068 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1069
1070 /* Setup link based on the new speed settings */
1071 if (hw->phy.ops.setup_link)
1072 hw->phy.ops.setup_link(hw);
1073
1074 return 0;
1075 }
1076
1077 /**
1078 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1079 * @hw: pointer to hardware structure
1080 *
1081 * Determines the supported link capabilities by reading the PHY auto
1082 * negotiation register.
1083 */
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)1084 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1085 {
1086 u16 speed_ability;
1087 s32 status;
1088
1089 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1090 &speed_ability);
1091 if (status)
1092 return status;
1093
1094 if (speed_ability & MDIO_SPEED_10G)
1095 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1096 if (speed_ability & MDIO_PMA_SPEED_1000)
1097 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1098 if (speed_ability & MDIO_PMA_SPEED_100)
1099 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1100
1101 switch (hw->mac.type) {
1102 case ixgbe_mac_X550:
1103 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1104 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1105 break;
1106 case ixgbe_mac_X550EM_x:
1107 case ixgbe_mac_x550em_a:
1108 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1109 break;
1110 default:
1111 break;
1112 }
1113
1114 return 0;
1115 }
1116
1117 /**
1118 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1119 * @hw: pointer to hardware structure
1120 * @speed: pointer to link speed
1121 * @autoneg: boolean auto-negotiation value
1122 */
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)1123 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1124 ixgbe_link_speed *speed,
1125 bool *autoneg)
1126 {
1127 s32 status = 0;
1128
1129 *autoneg = true;
1130 if (!hw->phy.speeds_supported)
1131 status = ixgbe_get_copper_speeds_supported(hw);
1132
1133 *speed = hw->phy.speeds_supported;
1134 return status;
1135 }
1136
1137 /**
1138 * ixgbe_check_phy_link_tnx - Determine link and speed status
1139 * @hw: pointer to hardware structure
1140 * @speed: link speed
1141 * @link_up: status of link
1142 *
1143 * Reads the VS1 register to determine if link is up and the current speed for
1144 * the PHY.
1145 **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)1146 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1147 bool *link_up)
1148 {
1149 s32 status;
1150 u32 time_out;
1151 u32 max_time_out = 10;
1152 u16 phy_link = 0;
1153 u16 phy_speed = 0;
1154 u16 phy_data = 0;
1155
1156 /* Initialize speed and link to default case */
1157 *link_up = false;
1158 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1159
1160 /*
1161 * Check current speed and link status of the PHY register.
1162 * This is a vendor specific register and may have to
1163 * be changed for other copper PHYs.
1164 */
1165 for (time_out = 0; time_out < max_time_out; time_out++) {
1166 udelay(10);
1167 status = hw->phy.ops.read_reg(hw,
1168 MDIO_STAT1,
1169 MDIO_MMD_VEND1,
1170 &phy_data);
1171 phy_link = phy_data &
1172 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1173 phy_speed = phy_data &
1174 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1175 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1176 *link_up = true;
1177 if (phy_speed ==
1178 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1179 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1180 break;
1181 }
1182 }
1183
1184 return status;
1185 }
1186
1187 /**
1188 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1189 * @hw: pointer to hardware structure
1190 *
1191 * Restart autonegotiation and PHY and waits for completion.
1192 * This function always returns success, this is nessary since
1193 * it is called via a function pointer that could call other
1194 * functions that could return an error.
1195 **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1196 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1197 {
1198 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1199 bool autoneg = false;
1200 ixgbe_link_speed speed;
1201
1202 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1203
1204 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1205 /* Set or unset auto-negotiation 10G advertisement */
1206 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1207 MDIO_MMD_AN,
1208 &autoneg_reg);
1209
1210 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1211 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1212 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1213
1214 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1215 MDIO_MMD_AN,
1216 autoneg_reg);
1217 }
1218
1219 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1220 /* Set or unset auto-negotiation 1G advertisement */
1221 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1222 MDIO_MMD_AN,
1223 &autoneg_reg);
1224
1225 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1226 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1227 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1228
1229 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1230 MDIO_MMD_AN,
1231 autoneg_reg);
1232 }
1233
1234 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1235 /* Set or unset auto-negotiation 100M advertisement */
1236 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1237 MDIO_MMD_AN,
1238 &autoneg_reg);
1239
1240 autoneg_reg &= ~(ADVERTISE_100FULL |
1241 ADVERTISE_100HALF);
1242 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1243 autoneg_reg |= ADVERTISE_100FULL;
1244
1245 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1246 MDIO_MMD_AN,
1247 autoneg_reg);
1248 }
1249
1250 /* Blocked by MNG FW so don't reset PHY */
1251 if (ixgbe_check_reset_blocked(hw))
1252 return 0;
1253
1254 /* Restart PHY autonegotiation and wait for completion */
1255 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1256 MDIO_MMD_AN, &autoneg_reg);
1257
1258 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1259
1260 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1261 MDIO_MMD_AN, autoneg_reg);
1262 return 0;
1263 }
1264
1265 /**
1266 * ixgbe_reset_phy_nl - Performs a PHY reset
1267 * @hw: pointer to hardware structure
1268 **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1269 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1270 {
1271 u16 phy_offset, control, eword, edata, block_crc;
1272 bool end_data = false;
1273 u16 list_offset, data_offset;
1274 u16 phy_data = 0;
1275 s32 ret_val;
1276 u32 i;
1277
1278 /* Blocked by MNG FW so bail */
1279 if (ixgbe_check_reset_blocked(hw))
1280 return 0;
1281
1282 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1283
1284 /* reset the PHY and poll for completion */
1285 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1286 (phy_data | MDIO_CTRL1_RESET));
1287
1288 for (i = 0; i < 100; i++) {
1289 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1290 &phy_data);
1291 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1292 break;
1293 usleep_range(10000, 20000);
1294 }
1295
1296 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1297 hw_dbg(hw, "PHY reset did not complete.\n");
1298 return IXGBE_ERR_PHY;
1299 }
1300
1301 /* Get init offsets */
1302 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1303 &data_offset);
1304 if (ret_val)
1305 return ret_val;
1306
1307 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1308 data_offset++;
1309 while (!end_data) {
1310 /*
1311 * Read control word from PHY init contents offset
1312 */
1313 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1314 if (ret_val)
1315 goto err_eeprom;
1316 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1317 IXGBE_CONTROL_SHIFT_NL;
1318 edata = eword & IXGBE_DATA_MASK_NL;
1319 switch (control) {
1320 case IXGBE_DELAY_NL:
1321 data_offset++;
1322 hw_dbg(hw, "DELAY: %d MS\n", edata);
1323 usleep_range(edata * 1000, edata * 2000);
1324 break;
1325 case IXGBE_DATA_NL:
1326 hw_dbg(hw, "DATA:\n");
1327 data_offset++;
1328 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1329 &phy_offset);
1330 if (ret_val)
1331 goto err_eeprom;
1332 for (i = 0; i < edata; i++) {
1333 ret_val = hw->eeprom.ops.read(hw, data_offset,
1334 &eword);
1335 if (ret_val)
1336 goto err_eeprom;
1337 hw->phy.ops.write_reg(hw, phy_offset,
1338 MDIO_MMD_PMAPMD, eword);
1339 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1340 phy_offset);
1341 data_offset++;
1342 phy_offset++;
1343 }
1344 break;
1345 case IXGBE_CONTROL_NL:
1346 data_offset++;
1347 hw_dbg(hw, "CONTROL:\n");
1348 if (edata == IXGBE_CONTROL_EOL_NL) {
1349 hw_dbg(hw, "EOL\n");
1350 end_data = true;
1351 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1352 hw_dbg(hw, "SOL\n");
1353 } else {
1354 hw_dbg(hw, "Bad control value\n");
1355 return IXGBE_ERR_PHY;
1356 }
1357 break;
1358 default:
1359 hw_dbg(hw, "Bad control type\n");
1360 return IXGBE_ERR_PHY;
1361 }
1362 }
1363
1364 return ret_val;
1365
1366 err_eeprom:
1367 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1368 return IXGBE_ERR_PHY;
1369 }
1370
1371 /**
1372 * ixgbe_identify_module_generic - Identifies module type
1373 * @hw: pointer to hardware structure
1374 *
1375 * Determines HW type and calls appropriate function.
1376 **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1377 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1378 {
1379 switch (hw->mac.ops.get_media_type(hw)) {
1380 case ixgbe_media_type_fiber:
1381 return ixgbe_identify_sfp_module_generic(hw);
1382 case ixgbe_media_type_fiber_qsfp:
1383 return ixgbe_identify_qsfp_module_generic(hw);
1384 default:
1385 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1386 return IXGBE_ERR_SFP_NOT_PRESENT;
1387 }
1388
1389 return IXGBE_ERR_SFP_NOT_PRESENT;
1390 }
1391
1392 /**
1393 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1394 * @hw: pointer to hardware structure
1395 *
1396 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1397 **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1398 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1399 {
1400 struct ixgbe_adapter *adapter = hw->back;
1401 s32 status;
1402 u32 vendor_oui = 0;
1403 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1404 u8 identifier = 0;
1405 u8 comp_codes_1g = 0;
1406 u8 comp_codes_10g = 0;
1407 u8 oui_bytes[3] = {0, 0, 0};
1408 u8 cable_tech = 0;
1409 u8 cable_spec = 0;
1410 u16 enforce_sfp = 0;
1411
1412 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1413 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1414 return IXGBE_ERR_SFP_NOT_PRESENT;
1415 }
1416
1417 /* LAN ID is needed for sfp_type determination */
1418 hw->mac.ops.set_lan_id(hw);
1419
1420 status = hw->phy.ops.read_i2c_eeprom(hw,
1421 IXGBE_SFF_IDENTIFIER,
1422 &identifier);
1423
1424 if (status)
1425 goto err_read_i2c_eeprom;
1426
1427 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1428 hw->phy.type = ixgbe_phy_sfp_unsupported;
1429 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1430 }
1431 status = hw->phy.ops.read_i2c_eeprom(hw,
1432 IXGBE_SFF_1GBE_COMP_CODES,
1433 &comp_codes_1g);
1434
1435 if (status)
1436 goto err_read_i2c_eeprom;
1437
1438 status = hw->phy.ops.read_i2c_eeprom(hw,
1439 IXGBE_SFF_10GBE_COMP_CODES,
1440 &comp_codes_10g);
1441
1442 if (status)
1443 goto err_read_i2c_eeprom;
1444 status = hw->phy.ops.read_i2c_eeprom(hw,
1445 IXGBE_SFF_CABLE_TECHNOLOGY,
1446 &cable_tech);
1447
1448 if (status)
1449 goto err_read_i2c_eeprom;
1450
1451 /* ID Module
1452 * =========
1453 * 0 SFP_DA_CU
1454 * 1 SFP_SR
1455 * 2 SFP_LR
1456 * 3 SFP_DA_CORE0 - 82599-specific
1457 * 4 SFP_DA_CORE1 - 82599-specific
1458 * 5 SFP_SR/LR_CORE0 - 82599-specific
1459 * 6 SFP_SR/LR_CORE1 - 82599-specific
1460 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1461 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1462 * 9 SFP_1g_cu_CORE0 - 82599-specific
1463 * 10 SFP_1g_cu_CORE1 - 82599-specific
1464 * 11 SFP_1g_sx_CORE0 - 82599-specific
1465 * 12 SFP_1g_sx_CORE1 - 82599-specific
1466 */
1467 if (hw->mac.type == ixgbe_mac_82598EB) {
1468 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1469 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1470 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1471 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1472 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1473 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1474 else
1475 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1476 } else {
1477 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1478 if (hw->bus.lan_id == 0)
1479 hw->phy.sfp_type =
1480 ixgbe_sfp_type_da_cu_core0;
1481 else
1482 hw->phy.sfp_type =
1483 ixgbe_sfp_type_da_cu_core1;
1484 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1485 hw->phy.ops.read_i2c_eeprom(
1486 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1487 &cable_spec);
1488 if (cable_spec &
1489 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1490 if (hw->bus.lan_id == 0)
1491 hw->phy.sfp_type =
1492 ixgbe_sfp_type_da_act_lmt_core0;
1493 else
1494 hw->phy.sfp_type =
1495 ixgbe_sfp_type_da_act_lmt_core1;
1496 } else {
1497 hw->phy.sfp_type =
1498 ixgbe_sfp_type_unknown;
1499 }
1500 } else if (comp_codes_10g &
1501 (IXGBE_SFF_10GBASESR_CAPABLE |
1502 IXGBE_SFF_10GBASELR_CAPABLE)) {
1503 if (hw->bus.lan_id == 0)
1504 hw->phy.sfp_type =
1505 ixgbe_sfp_type_srlr_core0;
1506 else
1507 hw->phy.sfp_type =
1508 ixgbe_sfp_type_srlr_core1;
1509 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1510 if (hw->bus.lan_id == 0)
1511 hw->phy.sfp_type =
1512 ixgbe_sfp_type_1g_cu_core0;
1513 else
1514 hw->phy.sfp_type =
1515 ixgbe_sfp_type_1g_cu_core1;
1516 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1517 if (hw->bus.lan_id == 0)
1518 hw->phy.sfp_type =
1519 ixgbe_sfp_type_1g_sx_core0;
1520 else
1521 hw->phy.sfp_type =
1522 ixgbe_sfp_type_1g_sx_core1;
1523 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1524 if (hw->bus.lan_id == 0)
1525 hw->phy.sfp_type =
1526 ixgbe_sfp_type_1g_lx_core0;
1527 else
1528 hw->phy.sfp_type =
1529 ixgbe_sfp_type_1g_lx_core1;
1530 } else {
1531 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1532 }
1533 }
1534
1535 if (hw->phy.sfp_type != stored_sfp_type)
1536 hw->phy.sfp_setup_needed = true;
1537
1538 /* Determine if the SFP+ PHY is dual speed or not. */
1539 hw->phy.multispeed_fiber = false;
1540 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1541 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1542 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1543 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1544 hw->phy.multispeed_fiber = true;
1545
1546 /* Determine PHY vendor */
1547 if (hw->phy.type != ixgbe_phy_nl) {
1548 hw->phy.id = identifier;
1549 status = hw->phy.ops.read_i2c_eeprom(hw,
1550 IXGBE_SFF_VENDOR_OUI_BYTE0,
1551 &oui_bytes[0]);
1552
1553 if (status != 0)
1554 goto err_read_i2c_eeprom;
1555
1556 status = hw->phy.ops.read_i2c_eeprom(hw,
1557 IXGBE_SFF_VENDOR_OUI_BYTE1,
1558 &oui_bytes[1]);
1559
1560 if (status != 0)
1561 goto err_read_i2c_eeprom;
1562
1563 status = hw->phy.ops.read_i2c_eeprom(hw,
1564 IXGBE_SFF_VENDOR_OUI_BYTE2,
1565 &oui_bytes[2]);
1566
1567 if (status != 0)
1568 goto err_read_i2c_eeprom;
1569
1570 vendor_oui =
1571 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1572 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1573 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1574
1575 switch (vendor_oui) {
1576 case IXGBE_SFF_VENDOR_OUI_TYCO:
1577 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1578 hw->phy.type =
1579 ixgbe_phy_sfp_passive_tyco;
1580 break;
1581 case IXGBE_SFF_VENDOR_OUI_FTL:
1582 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1583 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1584 else
1585 hw->phy.type = ixgbe_phy_sfp_ftl;
1586 break;
1587 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1588 hw->phy.type = ixgbe_phy_sfp_avago;
1589 break;
1590 case IXGBE_SFF_VENDOR_OUI_INTEL:
1591 hw->phy.type = ixgbe_phy_sfp_intel;
1592 break;
1593 default:
1594 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1595 hw->phy.type =
1596 ixgbe_phy_sfp_passive_unknown;
1597 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1598 hw->phy.type =
1599 ixgbe_phy_sfp_active_unknown;
1600 else
1601 hw->phy.type = ixgbe_phy_sfp_unknown;
1602 break;
1603 }
1604 }
1605
1606 /* Allow any DA cable vendor */
1607 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1608 IXGBE_SFF_DA_ACTIVE_CABLE))
1609 return 0;
1610
1611 /* Verify supported 1G SFP modules */
1612 if (comp_codes_10g == 0 &&
1613 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1614 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1615 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1616 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1617 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1618 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1619 hw->phy.type = ixgbe_phy_sfp_unsupported;
1620 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1621 }
1622
1623 /* Anything else 82598-based is supported */
1624 if (hw->mac.type == ixgbe_mac_82598EB)
1625 return 0;
1626
1627 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1628 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1629 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1630 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1631 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1632 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1633 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1634 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1635 /* Make sure we're a supported PHY type */
1636 if (hw->phy.type == ixgbe_phy_sfp_intel)
1637 return 0;
1638 if (hw->allow_unsupported_sfp) {
1639 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1640 return 0;
1641 }
1642 hw_dbg(hw, "SFP+ module not supported\n");
1643 hw->phy.type = ixgbe_phy_sfp_unsupported;
1644 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1645 }
1646 return 0;
1647
1648 err_read_i2c_eeprom:
1649 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1650 if (hw->phy.type != ixgbe_phy_nl) {
1651 hw->phy.id = 0;
1652 hw->phy.type = ixgbe_phy_unknown;
1653 }
1654 return IXGBE_ERR_SFP_NOT_PRESENT;
1655 }
1656
1657 /**
1658 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1659 * @hw: pointer to hardware structure
1660 *
1661 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1662 **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1663 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1664 {
1665 struct ixgbe_adapter *adapter = hw->back;
1666 s32 status;
1667 u32 vendor_oui = 0;
1668 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1669 u8 identifier = 0;
1670 u8 comp_codes_1g = 0;
1671 u8 comp_codes_10g = 0;
1672 u8 oui_bytes[3] = {0, 0, 0};
1673 u16 enforce_sfp = 0;
1674 u8 connector = 0;
1675 u8 cable_length = 0;
1676 u8 device_tech = 0;
1677 bool active_cable = false;
1678
1679 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1680 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1681 return IXGBE_ERR_SFP_NOT_PRESENT;
1682 }
1683
1684 /* LAN ID is needed for sfp_type determination */
1685 hw->mac.ops.set_lan_id(hw);
1686
1687 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1688 &identifier);
1689
1690 if (status != 0)
1691 goto err_read_i2c_eeprom;
1692
1693 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1694 hw->phy.type = ixgbe_phy_sfp_unsupported;
1695 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1696 }
1697
1698 hw->phy.id = identifier;
1699
1700 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1701 &comp_codes_10g);
1702
1703 if (status != 0)
1704 goto err_read_i2c_eeprom;
1705
1706 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1707 &comp_codes_1g);
1708
1709 if (status != 0)
1710 goto err_read_i2c_eeprom;
1711
1712 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1713 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1714 if (hw->bus.lan_id == 0)
1715 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1716 else
1717 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1718 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1719 IXGBE_SFF_10GBASELR_CAPABLE)) {
1720 if (hw->bus.lan_id == 0)
1721 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1722 else
1723 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1724 } else {
1725 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1726 active_cable = true;
1727
1728 if (!active_cable) {
1729 /* check for active DA cables that pre-date
1730 * SFF-8436 v3.6
1731 */
1732 hw->phy.ops.read_i2c_eeprom(hw,
1733 IXGBE_SFF_QSFP_CONNECTOR,
1734 &connector);
1735
1736 hw->phy.ops.read_i2c_eeprom(hw,
1737 IXGBE_SFF_QSFP_CABLE_LENGTH,
1738 &cable_length);
1739
1740 hw->phy.ops.read_i2c_eeprom(hw,
1741 IXGBE_SFF_QSFP_DEVICE_TECH,
1742 &device_tech);
1743
1744 if ((connector ==
1745 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1746 (cable_length > 0) &&
1747 ((device_tech >> 4) ==
1748 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1749 active_cable = true;
1750 }
1751
1752 if (active_cable) {
1753 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1754 if (hw->bus.lan_id == 0)
1755 hw->phy.sfp_type =
1756 ixgbe_sfp_type_da_act_lmt_core0;
1757 else
1758 hw->phy.sfp_type =
1759 ixgbe_sfp_type_da_act_lmt_core1;
1760 } else {
1761 /* unsupported module type */
1762 hw->phy.type = ixgbe_phy_sfp_unsupported;
1763 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1764 }
1765 }
1766
1767 if (hw->phy.sfp_type != stored_sfp_type)
1768 hw->phy.sfp_setup_needed = true;
1769
1770 /* Determine if the QSFP+ PHY is dual speed or not. */
1771 hw->phy.multispeed_fiber = false;
1772 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1773 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1774 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1775 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1776 hw->phy.multispeed_fiber = true;
1777
1778 /* Determine PHY vendor for optical modules */
1779 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1780 IXGBE_SFF_10GBASELR_CAPABLE)) {
1781 status = hw->phy.ops.read_i2c_eeprom(hw,
1782 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1783 &oui_bytes[0]);
1784
1785 if (status != 0)
1786 goto err_read_i2c_eeprom;
1787
1788 status = hw->phy.ops.read_i2c_eeprom(hw,
1789 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1790 &oui_bytes[1]);
1791
1792 if (status != 0)
1793 goto err_read_i2c_eeprom;
1794
1795 status = hw->phy.ops.read_i2c_eeprom(hw,
1796 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1797 &oui_bytes[2]);
1798
1799 if (status != 0)
1800 goto err_read_i2c_eeprom;
1801
1802 vendor_oui =
1803 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1804 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1805 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1806
1807 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1808 hw->phy.type = ixgbe_phy_qsfp_intel;
1809 else
1810 hw->phy.type = ixgbe_phy_qsfp_unknown;
1811
1812 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1813 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1814 /* Make sure we're a supported PHY type */
1815 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1816 return 0;
1817 if (hw->allow_unsupported_sfp) {
1818 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1819 return 0;
1820 }
1821 hw_dbg(hw, "QSFP module not supported\n");
1822 hw->phy.type = ixgbe_phy_sfp_unsupported;
1823 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1824 }
1825 return 0;
1826 }
1827 return 0;
1828
1829 err_read_i2c_eeprom:
1830 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1831 hw->phy.id = 0;
1832 hw->phy.type = ixgbe_phy_unknown;
1833
1834 return IXGBE_ERR_SFP_NOT_PRESENT;
1835 }
1836
1837 /**
1838 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1839 * @hw: pointer to hardware structure
1840 * @list_offset: offset to the SFP ID list
1841 * @data_offset: offset to the SFP data block
1842 *
1843 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1844 * so it returns the offsets to the phy init sequence block.
1845 **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1846 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1847 u16 *list_offset,
1848 u16 *data_offset)
1849 {
1850 u16 sfp_id;
1851 u16 sfp_type = hw->phy.sfp_type;
1852
1853 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1854 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1855
1856 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1857 return IXGBE_ERR_SFP_NOT_PRESENT;
1858
1859 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1860 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1861 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1862
1863 /*
1864 * Limiting active cables and 1G Phys must be initialized as
1865 * SR modules
1866 */
1867 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1868 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1869 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1870 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1871 sfp_type = ixgbe_sfp_type_srlr_core0;
1872 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1873 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1874 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1875 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1876 sfp_type = ixgbe_sfp_type_srlr_core1;
1877
1878 /* Read offset to PHY init contents */
1879 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1880 hw_err(hw, "eeprom read at %d failed\n",
1881 IXGBE_PHY_INIT_OFFSET_NL);
1882 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1883 }
1884
1885 if ((!*list_offset) || (*list_offset == 0xFFFF))
1886 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1887
1888 /* Shift offset to first ID word */
1889 (*list_offset)++;
1890
1891 /*
1892 * Find the matching SFP ID in the EEPROM
1893 * and program the init sequence
1894 */
1895 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1896 goto err_phy;
1897
1898 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1899 if (sfp_id == sfp_type) {
1900 (*list_offset)++;
1901 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1902 goto err_phy;
1903 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1904 hw_dbg(hw, "SFP+ module not supported\n");
1905 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1906 } else {
1907 break;
1908 }
1909 } else {
1910 (*list_offset) += 2;
1911 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1912 goto err_phy;
1913 }
1914 }
1915
1916 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1917 hw_dbg(hw, "No matching SFP+ module found\n");
1918 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1919 }
1920
1921 return 0;
1922
1923 err_phy:
1924 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1925 return IXGBE_ERR_PHY;
1926 }
1927
1928 /**
1929 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1930 * @hw: pointer to hardware structure
1931 * @byte_offset: EEPROM byte offset to read
1932 * @eeprom_data: value read
1933 *
1934 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1935 **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1936 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1937 u8 *eeprom_data)
1938 {
1939 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1940 IXGBE_I2C_EEPROM_DEV_ADDR,
1941 eeprom_data);
1942 }
1943
1944 /**
1945 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1946 * @hw: pointer to hardware structure
1947 * @byte_offset: byte offset at address 0xA2
1948 * @sff8472_data: value read
1949 *
1950 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1951 **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1952 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1953 u8 *sff8472_data)
1954 {
1955 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1956 IXGBE_I2C_EEPROM_DEV_ADDR2,
1957 sff8472_data);
1958 }
1959
1960 /**
1961 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1962 * @hw: pointer to hardware structure
1963 * @byte_offset: EEPROM byte offset to write
1964 * @eeprom_data: value to write
1965 *
1966 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1967 **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1968 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1969 u8 eeprom_data)
1970 {
1971 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1972 IXGBE_I2C_EEPROM_DEV_ADDR,
1973 eeprom_data);
1974 }
1975
1976 /**
1977 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1978 * @hw: pointer to hardware structure
1979 * @offset: eeprom offset to be read
1980 * @addr: I2C address to be read
1981 */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1982 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1983 {
1984 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1985 offset == IXGBE_SFF_IDENTIFIER &&
1986 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1987 return true;
1988 return false;
1989 }
1990
1991 /**
1992 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1993 * @hw: pointer to hardware structure
1994 * @byte_offset: byte offset to read
1995 * @dev_addr: device address
1996 * @data: value read
1997 * @lock: true if to take and release semaphore
1998 *
1999 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2000 * a specified device address.
2001 */
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)2002 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2003 u8 dev_addr, u8 *data, bool lock)
2004 {
2005 s32 status;
2006 u32 max_retry = 10;
2007 u32 retry = 0;
2008 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2009 bool nack = true;
2010
2011 if (hw->mac.type >= ixgbe_mac_X550)
2012 max_retry = 3;
2013 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2014 max_retry = IXGBE_SFP_DETECT_RETRIES;
2015
2016 *data = 0;
2017
2018 do {
2019 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2020 return IXGBE_ERR_SWFW_SYNC;
2021
2022 ixgbe_i2c_start(hw);
2023
2024 /* Device Address and write indication */
2025 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2026 if (status != 0)
2027 goto fail;
2028
2029 status = ixgbe_get_i2c_ack(hw);
2030 if (status != 0)
2031 goto fail;
2032
2033 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2034 if (status != 0)
2035 goto fail;
2036
2037 status = ixgbe_get_i2c_ack(hw);
2038 if (status != 0)
2039 goto fail;
2040
2041 ixgbe_i2c_start(hw);
2042
2043 /* Device Address and read indication */
2044 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2045 if (status != 0)
2046 goto fail;
2047
2048 status = ixgbe_get_i2c_ack(hw);
2049 if (status != 0)
2050 goto fail;
2051
2052 status = ixgbe_clock_in_i2c_byte(hw, data);
2053 if (status != 0)
2054 goto fail;
2055
2056 status = ixgbe_clock_out_i2c_bit(hw, nack);
2057 if (status != 0)
2058 goto fail;
2059
2060 ixgbe_i2c_stop(hw);
2061 if (lock)
2062 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2063 return 0;
2064
2065 fail:
2066 ixgbe_i2c_bus_clear(hw);
2067 if (lock) {
2068 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2069 msleep(100);
2070 }
2071 retry++;
2072 if (retry < max_retry)
2073 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2074 else
2075 hw_dbg(hw, "I2C byte read error.\n");
2076
2077 } while (retry < max_retry);
2078
2079 return status;
2080 }
2081
2082 /**
2083 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2084 * @hw: pointer to hardware structure
2085 * @byte_offset: byte offset to read
2086 * @dev_addr: device address
2087 * @data: value read
2088 *
2089 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2090 * a specified device address.
2091 */
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2092 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2093 u8 dev_addr, u8 *data)
2094 {
2095 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2096 data, true);
2097 }
2098
2099 /**
2100 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2101 * @hw: pointer to hardware structure
2102 * @byte_offset: byte offset to read
2103 * @dev_addr: device address
2104 * @data: value read
2105 *
2106 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2107 * a specified device address.
2108 */
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2109 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2110 u8 dev_addr, u8 *data)
2111 {
2112 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2113 data, false);
2114 }
2115
2116 /**
2117 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2118 * @hw: pointer to hardware structure
2119 * @byte_offset: byte offset to write
2120 * @dev_addr: device address
2121 * @data: value to write
2122 * @lock: true if to take and release semaphore
2123 *
2124 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2125 * a specified device address.
2126 */
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2127 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2128 u8 dev_addr, u8 data, bool lock)
2129 {
2130 s32 status;
2131 u32 max_retry = 1;
2132 u32 retry = 0;
2133 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2134
2135 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2136 return IXGBE_ERR_SWFW_SYNC;
2137
2138 do {
2139 ixgbe_i2c_start(hw);
2140
2141 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2142 if (status != 0)
2143 goto fail;
2144
2145 status = ixgbe_get_i2c_ack(hw);
2146 if (status != 0)
2147 goto fail;
2148
2149 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2150 if (status != 0)
2151 goto fail;
2152
2153 status = ixgbe_get_i2c_ack(hw);
2154 if (status != 0)
2155 goto fail;
2156
2157 status = ixgbe_clock_out_i2c_byte(hw, data);
2158 if (status != 0)
2159 goto fail;
2160
2161 status = ixgbe_get_i2c_ack(hw);
2162 if (status != 0)
2163 goto fail;
2164
2165 ixgbe_i2c_stop(hw);
2166 if (lock)
2167 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2168 return 0;
2169
2170 fail:
2171 ixgbe_i2c_bus_clear(hw);
2172 retry++;
2173 if (retry < max_retry)
2174 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2175 else
2176 hw_dbg(hw, "I2C byte write error.\n");
2177 } while (retry < max_retry);
2178
2179 if (lock)
2180 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2181
2182 return status;
2183 }
2184
2185 /**
2186 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2187 * @hw: pointer to hardware structure
2188 * @byte_offset: byte offset to write
2189 * @dev_addr: device address
2190 * @data: value to write
2191 *
2192 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2193 * a specified device address.
2194 */
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2195 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2196 u8 dev_addr, u8 data)
2197 {
2198 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2199 data, true);
2200 }
2201
2202 /**
2203 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2204 * @hw: pointer to hardware structure
2205 * @byte_offset: byte offset to write
2206 * @dev_addr: device address
2207 * @data: value to write
2208 *
2209 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2210 * a specified device address.
2211 */
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2212 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2213 u8 dev_addr, u8 data)
2214 {
2215 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2216 data, false);
2217 }
2218
2219 /**
2220 * ixgbe_i2c_start - Sets I2C start condition
2221 * @hw: pointer to hardware structure
2222 *
2223 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2224 * Set bit-bang mode on X550 hardware.
2225 **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2226 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2227 {
2228 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2229
2230 i2cctl |= IXGBE_I2C_BB_EN(hw);
2231
2232 /* Start condition must begin with data and clock high */
2233 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2234 ixgbe_raise_i2c_clk(hw, &i2cctl);
2235
2236 /* Setup time for start condition (4.7us) */
2237 udelay(IXGBE_I2C_T_SU_STA);
2238
2239 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2240
2241 /* Hold time for start condition (4us) */
2242 udelay(IXGBE_I2C_T_HD_STA);
2243
2244 ixgbe_lower_i2c_clk(hw, &i2cctl);
2245
2246 /* Minimum low period of clock is 4.7 us */
2247 udelay(IXGBE_I2C_T_LOW);
2248
2249 }
2250
2251 /**
2252 * ixgbe_i2c_stop - Sets I2C stop condition
2253 * @hw: pointer to hardware structure
2254 *
2255 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2256 * Disables bit-bang mode and negates data output enable on X550
2257 * hardware.
2258 **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2259 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2260 {
2261 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2262 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2263 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2264 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2265
2266 /* Stop condition must begin with data low and clock high */
2267 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2268 ixgbe_raise_i2c_clk(hw, &i2cctl);
2269
2270 /* Setup time for stop condition (4us) */
2271 udelay(IXGBE_I2C_T_SU_STO);
2272
2273 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2274
2275 /* bus free time between stop and start (4.7us)*/
2276 udelay(IXGBE_I2C_T_BUF);
2277
2278 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2279 i2cctl &= ~bb_en_bit;
2280 i2cctl |= data_oe_bit | clk_oe_bit;
2281 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2282 IXGBE_WRITE_FLUSH(hw);
2283 }
2284 }
2285
2286 /**
2287 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2288 * @hw: pointer to hardware structure
2289 * @data: data byte to clock in
2290 *
2291 * Clocks in one byte data via I2C data/clock
2292 **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2293 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2294 {
2295 s32 i;
2296 bool bit = false;
2297
2298 *data = 0;
2299 for (i = 7; i >= 0; i--) {
2300 ixgbe_clock_in_i2c_bit(hw, &bit);
2301 *data |= bit << i;
2302 }
2303
2304 return 0;
2305 }
2306
2307 /**
2308 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2309 * @hw: pointer to hardware structure
2310 * @data: data byte clocked out
2311 *
2312 * Clocks out one byte data via I2C data/clock
2313 **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2314 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2315 {
2316 s32 status;
2317 s32 i;
2318 u32 i2cctl;
2319 bool bit = false;
2320
2321 for (i = 7; i >= 0; i--) {
2322 bit = (data >> i) & 0x1;
2323 status = ixgbe_clock_out_i2c_bit(hw, bit);
2324
2325 if (status != 0)
2326 break;
2327 }
2328
2329 /* Release SDA line (set high) */
2330 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2331 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2332 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2333 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2334 IXGBE_WRITE_FLUSH(hw);
2335
2336 return status;
2337 }
2338
2339 /**
2340 * ixgbe_get_i2c_ack - Polls for I2C ACK
2341 * @hw: pointer to hardware structure
2342 *
2343 * Clocks in/out one bit via I2C data/clock
2344 **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2345 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2346 {
2347 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2348 s32 status = 0;
2349 u32 i = 0;
2350 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2351 u32 timeout = 10;
2352 bool ack = true;
2353
2354 if (data_oe_bit) {
2355 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2356 i2cctl |= data_oe_bit;
2357 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2358 IXGBE_WRITE_FLUSH(hw);
2359 }
2360 ixgbe_raise_i2c_clk(hw, &i2cctl);
2361
2362 /* Minimum high period of clock is 4us */
2363 udelay(IXGBE_I2C_T_HIGH);
2364
2365 /* Poll for ACK. Note that ACK in I2C spec is
2366 * transition from 1 to 0 */
2367 for (i = 0; i < timeout; i++) {
2368 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2369 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2370
2371 udelay(1);
2372 if (ack == 0)
2373 break;
2374 }
2375
2376 if (ack == 1) {
2377 hw_dbg(hw, "I2C ack was not received.\n");
2378 status = IXGBE_ERR_I2C;
2379 }
2380
2381 ixgbe_lower_i2c_clk(hw, &i2cctl);
2382
2383 /* Minimum low period of clock is 4.7 us */
2384 udelay(IXGBE_I2C_T_LOW);
2385
2386 return status;
2387 }
2388
2389 /**
2390 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2391 * @hw: pointer to hardware structure
2392 * @data: read data value
2393 *
2394 * Clocks in one bit via I2C data/clock
2395 **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2396 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2397 {
2398 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2399 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2400
2401 if (data_oe_bit) {
2402 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2403 i2cctl |= data_oe_bit;
2404 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2405 IXGBE_WRITE_FLUSH(hw);
2406 }
2407 ixgbe_raise_i2c_clk(hw, &i2cctl);
2408
2409 /* Minimum high period of clock is 4us */
2410 udelay(IXGBE_I2C_T_HIGH);
2411
2412 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2413 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2414
2415 ixgbe_lower_i2c_clk(hw, &i2cctl);
2416
2417 /* Minimum low period of clock is 4.7 us */
2418 udelay(IXGBE_I2C_T_LOW);
2419
2420 return 0;
2421 }
2422
2423 /**
2424 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2425 * @hw: pointer to hardware structure
2426 * @data: data value to write
2427 *
2428 * Clocks out one bit via I2C data/clock
2429 **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2430 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2431 {
2432 s32 status;
2433 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2434
2435 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2436 if (status == 0) {
2437 ixgbe_raise_i2c_clk(hw, &i2cctl);
2438
2439 /* Minimum high period of clock is 4us */
2440 udelay(IXGBE_I2C_T_HIGH);
2441
2442 ixgbe_lower_i2c_clk(hw, &i2cctl);
2443
2444 /* Minimum low period of clock is 4.7 us.
2445 * This also takes care of the data hold time.
2446 */
2447 udelay(IXGBE_I2C_T_LOW);
2448 } else {
2449 hw_dbg(hw, "I2C data was not set to %X\n", data);
2450 return IXGBE_ERR_I2C;
2451 }
2452
2453 return 0;
2454 }
2455 /**
2456 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2457 * @hw: pointer to hardware structure
2458 * @i2cctl: Current value of I2CCTL register
2459 *
2460 * Raises the I2C clock line '0'->'1'
2461 * Negates the I2C clock output enable on X550 hardware.
2462 **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2463 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2464 {
2465 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2466 u32 i = 0;
2467 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2468 u32 i2cctl_r = 0;
2469
2470 if (clk_oe_bit) {
2471 *i2cctl |= clk_oe_bit;
2472 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2473 }
2474
2475 for (i = 0; i < timeout; i++) {
2476 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2477 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2478 IXGBE_WRITE_FLUSH(hw);
2479 /* SCL rise time (1000ns) */
2480 udelay(IXGBE_I2C_T_RISE);
2481
2482 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2483 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2484 break;
2485 }
2486 }
2487
2488 /**
2489 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2490 * @hw: pointer to hardware structure
2491 * @i2cctl: Current value of I2CCTL register
2492 *
2493 * Lowers the I2C clock line '1'->'0'
2494 * Asserts the I2C clock output enable on X550 hardware.
2495 **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2496 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2497 {
2498
2499 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2500 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2501
2502 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2503 IXGBE_WRITE_FLUSH(hw);
2504
2505 /* SCL fall time (300ns) */
2506 udelay(IXGBE_I2C_T_FALL);
2507 }
2508
2509 /**
2510 * ixgbe_set_i2c_data - Sets the I2C data bit
2511 * @hw: pointer to hardware structure
2512 * @i2cctl: Current value of I2CCTL register
2513 * @data: I2C data value (0 or 1) to set
2514 *
2515 * Sets the I2C data bit
2516 * Asserts the I2C data output enable on X550 hardware.
2517 **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2518 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2519 {
2520 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2521
2522 if (data)
2523 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2524 else
2525 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2526 *i2cctl &= ~data_oe_bit;
2527
2528 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2529 IXGBE_WRITE_FLUSH(hw);
2530
2531 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2532 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2533
2534 if (!data) /* Can't verify data in this case */
2535 return 0;
2536 if (data_oe_bit) {
2537 *i2cctl |= data_oe_bit;
2538 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2539 IXGBE_WRITE_FLUSH(hw);
2540 }
2541
2542 /* Verify data was set correctly */
2543 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2544 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2545 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2546 return IXGBE_ERR_I2C;
2547 }
2548
2549 return 0;
2550 }
2551
2552 /**
2553 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2554 * @hw: pointer to hardware structure
2555 * @i2cctl: Current value of I2CCTL register
2556 *
2557 * Returns the I2C data bit value
2558 * Negates the I2C data output enable on X550 hardware.
2559 **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2560 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2561 {
2562 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2563
2564 if (data_oe_bit) {
2565 *i2cctl |= data_oe_bit;
2566 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2567 IXGBE_WRITE_FLUSH(hw);
2568 udelay(IXGBE_I2C_T_FALL);
2569 }
2570
2571 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2572 return true;
2573 return false;
2574 }
2575
2576 /**
2577 * ixgbe_i2c_bus_clear - Clears the I2C bus
2578 * @hw: pointer to hardware structure
2579 *
2580 * Clears the I2C bus by sending nine clock pulses.
2581 * Used when data line is stuck low.
2582 **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2583 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2584 {
2585 u32 i2cctl;
2586 u32 i;
2587
2588 ixgbe_i2c_start(hw);
2589 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2590
2591 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2592
2593 for (i = 0; i < 9; i++) {
2594 ixgbe_raise_i2c_clk(hw, &i2cctl);
2595
2596 /* Min high period of clock is 4us */
2597 udelay(IXGBE_I2C_T_HIGH);
2598
2599 ixgbe_lower_i2c_clk(hw, &i2cctl);
2600
2601 /* Min low period of clock is 4.7us*/
2602 udelay(IXGBE_I2C_T_LOW);
2603 }
2604
2605 ixgbe_i2c_start(hw);
2606
2607 /* Put the i2c bus back to default state */
2608 ixgbe_i2c_stop(hw);
2609 }
2610
2611 /**
2612 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2613 * @hw: pointer to hardware structure
2614 *
2615 * Checks if the LASI temp alarm status was triggered due to overtemp
2616 **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2617 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2618 {
2619 u16 phy_data = 0;
2620
2621 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2622 return 0;
2623
2624 /* Check that the LASI temp alarm status was triggered */
2625 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2626 MDIO_MMD_PMAPMD, &phy_data);
2627
2628 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2629 return 0;
2630
2631 return IXGBE_ERR_OVERTEMP;
2632 }
2633
2634 /** ixgbe_set_copper_phy_power - Control power for copper phy
2635 * @hw: pointer to hardware structure
2636 * @on: true for on, false for off
2637 **/
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2638 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2639 {
2640 u32 status;
2641 u16 reg;
2642
2643 /* Bail if we don't have copper phy */
2644 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2645 return 0;
2646
2647 if (!on && ixgbe_mng_present(hw))
2648 return 0;
2649
2650 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2651 if (status)
2652 return status;
2653
2654 if (on) {
2655 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2656 } else {
2657 if (ixgbe_check_reset_blocked(hw))
2658 return 0;
2659 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2660 }
2661
2662 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2663 return status;
2664 }
2665