1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2024 Intel Corporation. */
3
4 #include <linux/pci.h>
5 #include <linux/delay.h>
6 #include <linux/iopoll.h>
7 #include <linux/sched.h>
8
9 #include "ixgbe.h"
10 #include "ixgbe_phy.h"
11
12 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14 static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15 static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16 static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17 static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18 static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21 static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25 static int ixgbe_get_phy_id(struct ixgbe_hw *hw);
26 static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28 /**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)35 static int ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36 {
37 int status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43 }
44
45 /**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)52 static int ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53 {
54 int status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61 }
62
63 /**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)70 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71 {
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76 }
77
78 /**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)88 int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90 {
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return -EBUSY;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142 fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return -EIO;
154 }
155
156 /**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)166 int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168 {
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 3;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return -EBUSY;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207 fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return -EIO;
219 }
220
221 /**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)228 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229 {
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255 }
256
257 /**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)263 int ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264 {
265 u32 status = -EFAULT;
266 u32 phy_addr;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
280 hw->phy.nw_mng_if_sel);
281 if (ixgbe_probe_phy(hw, phy_addr))
282 return 0;
283 else
284 return -EFAULT;
285 }
286
287 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
288 if (ixgbe_probe_phy(hw, phy_addr)) {
289 status = 0;
290 break;
291 }
292 }
293
294 /* Certain media types do not have a phy so an address will not
295 * be found and the code will take this path. Caller has to
296 * decide if it is an error or not.
297 */
298 if (status)
299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
300
301 return status;
302 }
303
304 /**
305 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
306 * @hw: pointer to the hardware structure
307 *
308 * This function checks the MMNGC.MNG_VETO bit to see if there are
309 * any constraints on link from manageability. For MAC's that don't
310 * have this bit just return false since the link can not be blocked
311 * via this method.
312 **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)313 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
314 {
315 u32 mmngc;
316
317 /* If we don't have this bit, it can't be blocking */
318 if (hw->mac.type == ixgbe_mac_82598EB)
319 return false;
320
321 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
322 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
323 hw_dbg(hw, "MNG_VETO bit detected.\n");
324 return true;
325 }
326
327 return false;
328 }
329
330 /**
331 * ixgbe_get_phy_id - Get the phy type
332 * @hw: pointer to hardware structure
333 *
334 **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)335 static int ixgbe_get_phy_id(struct ixgbe_hw *hw)
336 {
337 u16 phy_id_high = 0;
338 u16 phy_id_low = 0;
339 int status;
340
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
342 &phy_id_high);
343
344 if (!status) {
345 hw->phy.id = (u32)(phy_id_high << 16);
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
347 &phy_id_low);
348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
350 }
351 return status;
352 }
353
354 /**
355 * ixgbe_get_phy_type_from_id - Get the phy type
356 * @phy_id: hardware phy id
357 *
358 **/
ixgbe_get_phy_type_from_id(u32 phy_id)359 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
360 {
361 enum ixgbe_phy_type phy_type;
362
363 switch (phy_id) {
364 case TN1010_PHY_ID:
365 phy_type = ixgbe_phy_tn;
366 break;
367 case X550_PHY_ID2:
368 case X550_PHY_ID3:
369 case X540_PHY_ID:
370 phy_type = ixgbe_phy_aq;
371 break;
372 case QT2022_PHY_ID:
373 phy_type = ixgbe_phy_qt;
374 break;
375 case ATH_PHY_ID:
376 phy_type = ixgbe_phy_nl;
377 break;
378 case X557_PHY_ID:
379 case X557_PHY_ID2:
380 phy_type = ixgbe_phy_x550em_ext_t;
381 break;
382 case BCM54616S_E_PHY_ID:
383 phy_type = ixgbe_phy_ext_1g_t;
384 break;
385 default:
386 phy_type = ixgbe_phy_unknown;
387 break;
388 }
389
390 return phy_type;
391 }
392
393 /**
394 * ixgbe_reset_phy_generic - Performs a PHY reset
395 * @hw: pointer to hardware structure
396 **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)397 int ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
398 {
399 u32 i;
400 u16 ctrl = 0;
401 int status = 0;
402
403 if (hw->phy.type == ixgbe_phy_unknown)
404 status = ixgbe_identify_phy_generic(hw);
405
406 if (status != 0 || hw->phy.type == ixgbe_phy_none)
407 return status;
408
409 /* Don't reset PHY if it's shut down due to overtemp. */
410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
411 return 0;
412
413 /* Blocked by MNG FW so bail */
414 if (ixgbe_check_reset_blocked(hw))
415 return 0;
416
417 /*
418 * Perform soft PHY reset to the PHY_XS.
419 * This will cause a soft reset to the PHY
420 */
421 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
422 MDIO_MMD_PHYXS,
423 MDIO_CTRL1_RESET);
424
425 /*
426 * Poll for reset bit to self-clear indicating reset is complete.
427 * Some PHYs could take up to 3 seconds to complete and need about
428 * 1.7 usec delay after the reset is complete.
429 */
430 for (i = 0; i < 30; i++) {
431 msleep(100);
432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
433 status = hw->phy.ops.read_reg(hw,
434 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
435 MDIO_MMD_PMAPMD, &ctrl);
436 if (status)
437 return status;
438
439 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
440 udelay(2);
441 break;
442 }
443 } else {
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
445 MDIO_MMD_PHYXS, &ctrl);
446 if (status)
447 return status;
448
449 if (!(ctrl & MDIO_CTRL1_RESET)) {
450 udelay(2);
451 break;
452 }
453 }
454 }
455
456 if (ctrl & MDIO_CTRL1_RESET) {
457 hw_dbg(hw, "PHY reset polling failed to complete.\n");
458 return -EIO;
459 }
460
461 return 0;
462 }
463
464 /**
465 * ixgbe_read_phy_reg_mdi - read PHY register
466 * @hw: pointer to hardware structure
467 * @reg_addr: 32 bit address of PHY register to read
468 * @device_type: 5 bit device type
469 * @phy_data: Pointer to read data from PHY register
470 *
471 * Reads a value from a specified PHY register without the SWFW lock
472 **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)473 int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
474 u16 *phy_data)
475 {
476 u32 i, data, command;
477
478 /* Setup and write the address cycle command */
479 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
480 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
482 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
483
484 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
485
486 /* Check every 10 usec to see if the address cycle completed.
487 * The MDI Command bit will clear when the operation is
488 * complete
489 */
490 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
491 udelay(10);
492
493 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
494 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
495 break;
496 }
497
498
499 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
500 hw_dbg(hw, "PHY address command did not complete.\n");
501 return -EIO;
502 }
503
504 /* Address cycle complete, setup and write the read
505 * command
506 */
507 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
508 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
510 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
511
512 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
513
514 /* Check every 10 usec to see if the address cycle
515 * completed. The MDI Command bit will clear when the
516 * operation is complete
517 */
518 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
519 udelay(10);
520
521 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
522 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
523 break;
524 }
525
526 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
527 hw_dbg(hw, "PHY read command didn't complete\n");
528 return -EIO;
529 }
530
531 /* Read operation is complete. Get the data
532 * from MSRWD
533 */
534 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
535 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
536 *phy_data = (u16)(data);
537
538 return 0;
539 }
540
541 /**
542 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
543 * using the SWFW lock - this function is needed in most cases
544 * @hw: pointer to hardware structure
545 * @reg_addr: 32 bit address of PHY register to read
546 * @device_type: 5 bit device type
547 * @phy_data: Pointer to read data from PHY register
548 **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)549 int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
550 u32 device_type, u16 *phy_data)
551 {
552 u32 gssr = hw->phy.phy_semaphore_mask;
553 int status;
554
555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
556 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
557 phy_data);
558 hw->mac.ops.release_swfw_sync(hw, gssr);
559 } else {
560 return -EBUSY;
561 }
562
563 return status;
564 }
565
566 /**
567 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
568 * without SWFW lock
569 * @hw: pointer to hardware structure
570 * @reg_addr: 32 bit PHY register to write
571 * @device_type: 5 bit device type
572 * @phy_data: Data to write to the PHY register
573 **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)574 int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
575 u16 phy_data)
576 {
577 u32 i, command;
578
579 /* Put the data in the MDI single read and write data register*/
580 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
581
582 /* Setup and write the address cycle command */
583 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
584 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
586 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
587
588 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
589
590 /*
591 * Check every 10 usec to see if the address cycle completed.
592 * The MDI Command bit will clear when the operation is
593 * complete
594 */
595 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
596 udelay(10);
597
598 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
599 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
600 break;
601 }
602
603 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
604 hw_dbg(hw, "PHY address cmd didn't complete\n");
605 return -EIO;
606 }
607
608 /*
609 * Address cycle complete, setup and write the write
610 * command
611 */
612 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
613 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
615 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
616
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618
619 /* Check every 10 usec to see if the address cycle
620 * completed. The MDI Command bit will clear when the
621 * operation is complete
622 */
623 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
624 udelay(10);
625
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
627 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
628 break;
629 }
630
631 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
632 hw_dbg(hw, "PHY write cmd didn't complete\n");
633 return -EIO;
634 }
635
636 return 0;
637 }
638
639 /**
640 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
641 * using SWFW lock- this function is needed in most cases
642 * @hw: pointer to hardware structure
643 * @reg_addr: 32 bit PHY register to write
644 * @device_type: 5 bit device type
645 * @phy_data: Data to write to the PHY register
646 **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)647 int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
648 u32 device_type, u16 phy_data)
649 {
650 u32 gssr = hw->phy.phy_semaphore_mask;
651 int status;
652
653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
654 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
655 phy_data);
656 hw->mac.ops.release_swfw_sync(hw, gssr);
657 } else {
658 return -EBUSY;
659 }
660
661 return status;
662 }
663
664 #define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
665
666 /**
667 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
668 * @hw: pointer to hardware structure
669 * @cmd: command register value to write
670 **/
ixgbe_msca_cmd(struct ixgbe_hw * hw,u32 cmd)671 static int ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
672 {
673 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
674
675 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
676 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
677 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
678 }
679
680 /**
681 * ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
682 * @hw: pointer to hardware structure
683 * @addr: address
684 * @regnum: register number
685 * @gssr: semaphore flags to acquire
686 **/
ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw * hw,int addr,int regnum,u32 gssr)687 static int ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr,
688 int regnum, u32 gssr)
689 {
690 u32 hwaddr, cmd;
691 int data;
692
693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
694 return -EBUSY;
695
696 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
697 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
698 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
699 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
700
701 data = ixgbe_msca_cmd(hw, cmd);
702 if (data < 0)
703 goto mii_bus_read_done;
704
705 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
706 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
707
708 mii_bus_read_done:
709 hw->mac.ops.release_swfw_sync(hw, gssr);
710 return data;
711 }
712
713 /**
714 * ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
715 * @hw: pointer to hardware structure
716 * @addr: address
717 * @devad: device address to read
718 * @regnum: register number
719 * @gssr: semaphore flags to acquire
720 **/
ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw * hw,int addr,int devad,int regnum,u32 gssr)721 static int ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr,
722 int devad, int regnum, u32 gssr)
723 {
724 u32 hwaddr, cmd;
725 int data;
726
727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
728 return -EBUSY;
729
730 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
731 hwaddr |= devad << 16 | regnum;
732 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
733
734 data = ixgbe_msca_cmd(hw, cmd);
735 if (data < 0)
736 goto mii_bus_read_done;
737
738 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
739 data = ixgbe_msca_cmd(hw, cmd);
740 if (data < 0)
741 goto mii_bus_read_done;
742
743 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
744 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
745
746 mii_bus_read_done:
747 hw->mac.ops.release_swfw_sync(hw, gssr);
748 return data;
749 }
750
751 /**
752 * ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
753 * @hw: pointer to hardware structure
754 * @addr: address
755 * @regnum: register number
756 * @val: value to write
757 * @gssr: semaphore flags to acquire
758 **/
ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw * hw,int addr,int regnum,u16 val,u32 gssr)759 static int ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr,
760 int regnum, u16 val, u32 gssr)
761 {
762 u32 hwaddr, cmd;
763 int err;
764
765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
766 return -EBUSY;
767
768 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
769
770 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
771 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
772 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
773 IXGBE_MSCA_MDI_COMMAND;
774
775 err = ixgbe_msca_cmd(hw, cmd);
776
777 hw->mac.ops.release_swfw_sync(hw, gssr);
778 return err;
779 }
780
781 /**
782 * ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
783 * @hw: pointer to hardware structure
784 * @addr: address
785 * @devad: device address to read
786 * @regnum: register number
787 * @val: value to write
788 * @gssr: semaphore flags to acquire
789 **/
ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw * hw,int addr,int devad,int regnum,u16 val,u32 gssr)790 static int ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr,
791 int devad, int regnum, u16 val,
792 u32 gssr)
793 {
794 u32 hwaddr, cmd;
795 int err;
796
797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
798 return -EBUSY;
799
800 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
801
802 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
803 hwaddr |= devad << 16 | regnum;
804 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
805
806 err = ixgbe_msca_cmd(hw, cmd);
807 if (err < 0)
808 goto mii_bus_write_done;
809
810 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
811 err = ixgbe_msca_cmd(hw, cmd);
812
813 mii_bus_write_done:
814 hw->mac.ops.release_swfw_sync(hw, gssr);
815 return err;
816 }
817
818 /**
819 * ixgbe_mii_bus_read_c22 - Read a clause 22 register
820 * @bus: pointer to mii_bus structure which points to our driver private
821 * @addr: address
822 * @regnum: register number
823 **/
ixgbe_mii_bus_read_c22(struct mii_bus * bus,int addr,int regnum)824 static int ixgbe_mii_bus_read_c22(struct mii_bus *bus, int addr, int regnum)
825 {
826 struct ixgbe_adapter *adapter = bus->priv;
827 struct ixgbe_hw *hw = &adapter->hw;
828 u32 gssr = hw->phy.phy_semaphore_mask;
829
830 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
831 }
832
833 /**
834 * ixgbe_mii_bus_read_c45 - Read a clause 45 register
835 * @bus: pointer to mii_bus structure which points to our driver private
836 * @devad: device address to read
837 * @addr: address
838 * @regnum: register number
839 **/
ixgbe_mii_bus_read_c45(struct mii_bus * bus,int devad,int addr,int regnum)840 static int ixgbe_mii_bus_read_c45(struct mii_bus *bus, int devad, int addr,
841 int regnum)
842 {
843 struct ixgbe_adapter *adapter = bus->priv;
844 struct ixgbe_hw *hw = &adapter->hw;
845 u32 gssr = hw->phy.phy_semaphore_mask;
846
847 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
848 }
849
850 /**
851 * ixgbe_mii_bus_write_c22 - Write a clause 22 register
852 * @bus: pointer to mii_bus structure which points to our driver private
853 * @addr: address
854 * @regnum: register number
855 * @val: value to write
856 **/
ixgbe_mii_bus_write_c22(struct mii_bus * bus,int addr,int regnum,u16 val)857 static int ixgbe_mii_bus_write_c22(struct mii_bus *bus, int addr, int regnum,
858 u16 val)
859 {
860 struct ixgbe_adapter *adapter = bus->priv;
861 struct ixgbe_hw *hw = &adapter->hw;
862 u32 gssr = hw->phy.phy_semaphore_mask;
863
864 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
865 }
866
867 /**
868 * ixgbe_mii_bus_write_c45 - Write a clause 45 register
869 * @bus: pointer to mii_bus structure which points to our driver private
870 * @addr: address
871 * @devad: device address to read
872 * @regnum: register number
873 * @val: value to write
874 **/
ixgbe_mii_bus_write_c45(struct mii_bus * bus,int addr,int devad,int regnum,u16 val)875 static int ixgbe_mii_bus_write_c45(struct mii_bus *bus, int addr, int devad,
876 int regnum, u16 val)
877 {
878 struct ixgbe_adapter *adapter = bus->priv;
879 struct ixgbe_hw *hw = &adapter->hw;
880 u32 gssr = hw->phy.phy_semaphore_mask;
881
882 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
883 gssr);
884 }
885
886 /**
887 * ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
888 * @bus: pointer to mii_bus structure which points to our driver private
889 * @addr: address
890 * @regnum: register number
891 **/
ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus * bus,int addr,int regnum)892 static int ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus *bus, int addr,
893 int regnum)
894 {
895 struct ixgbe_adapter *adapter = bus->priv;
896 struct ixgbe_hw *hw = &adapter->hw;
897 u32 gssr = hw->phy.phy_semaphore_mask;
898
899 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
900 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
901 }
902
903 /**
904 * ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
905 * @bus: pointer to mii_bus structure which points to our driver private
906 * @addr: address
907 * @devad: device address to read
908 * @regnum: register number
909 **/
ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus * bus,int addr,int devad,int regnum)910 static int ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus *bus, int addr,
911 int devad, int regnum)
912 {
913 struct ixgbe_adapter *adapter = bus->priv;
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 gssr = hw->phy.phy_semaphore_mask;
916
917 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
918 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
919 }
920
921 /**
922 * ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
923 * @bus: pointer to mii_bus structure which points to our driver private
924 * @addr: address
925 * @regnum: register number
926 * @val: value to write
927 **/
ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus * bus,int addr,int regnum,u16 val)928 static int ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus *bus, int addr,
929 int regnum, u16 val)
930 {
931 struct ixgbe_adapter *adapter = bus->priv;
932 struct ixgbe_hw *hw = &adapter->hw;
933 u32 gssr = hw->phy.phy_semaphore_mask;
934
935 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
936 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
937 }
938
939 /**
940 * ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
941 * @bus: pointer to mii_bus structure which points to our driver private
942 * @addr: address
943 * @devad: device address to read
944 * @regnum: register number
945 * @val: value to write
946 **/
ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus * bus,int addr,int devad,int regnum,u16 val)947 static int ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus *bus, int addr,
948 int devad, int regnum, u16 val)
949 {
950 struct ixgbe_adapter *adapter = bus->priv;
951 struct ixgbe_hw *hw = &adapter->hw;
952 u32 gssr = hw->phy.phy_semaphore_mask;
953
954 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
955 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
956 gssr);
957 }
958
959 /**
960 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
961 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
962 *
963 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
964 * on domain 0, bus 0, devfn = 'devfn'
965 **/
ixgbe_get_first_secondary_devfn(unsigned int devfn)966 static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
967 {
968 struct pci_dev *rp_pdev;
969 int bus;
970
971 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
972 if (rp_pdev && rp_pdev->subordinate) {
973 bus = rp_pdev->subordinate->number;
974 pci_dev_put(rp_pdev);
975 return pci_get_domain_bus_and_slot(0, bus, 0);
976 }
977
978 pci_dev_put(rp_pdev);
979 return NULL;
980 }
981
982 /**
983 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
984 * @hw: pointer to hardware structure
985 *
986 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
987 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
988 * but we only want to register one MDIO bus.
989 **/
ixgbe_x550em_a_has_mii(struct ixgbe_hw * hw)990 static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
991 {
992 struct ixgbe_adapter *adapter = hw->back;
993 struct pci_dev *pdev = adapter->pdev;
994 struct pci_dev *func0_pdev;
995 bool has_mii = false;
996
997 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
998 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
999 * It's not valid for function 0 to be disabled and function 1 is up,
1000 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
1001 * of those two root ports
1002 */
1003 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
1004 if (func0_pdev) {
1005 if (func0_pdev == pdev)
1006 has_mii = true;
1007 goto out;
1008 }
1009 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
1010 if (func0_pdev == pdev)
1011 has_mii = true;
1012
1013 out:
1014 pci_dev_put(func0_pdev);
1015 return has_mii;
1016 }
1017
1018 /**
1019 * ixgbe_mii_bus_init - mii_bus structure setup
1020 * @hw: pointer to hardware structure
1021 *
1022 * Returns 0 on success, negative on failure
1023 *
1024 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
1025 **/
ixgbe_mii_bus_init(struct ixgbe_hw * hw)1026 int ixgbe_mii_bus_init(struct ixgbe_hw *hw)
1027 {
1028 int (*write_c22)(struct mii_bus *bus, int addr, int regnum, u16 val);
1029 int (*read_c22)(struct mii_bus *bus, int addr, int regnum);
1030 int (*write_c45)(struct mii_bus *bus, int addr, int devad, int regnum,
1031 u16 val);
1032 int (*read_c45)(struct mii_bus *bus, int addr, int devad, int regnum);
1033 struct ixgbe_adapter *adapter = hw->back;
1034 struct pci_dev *pdev = adapter->pdev;
1035 struct device *dev = &adapter->netdev->dev;
1036 struct mii_bus *bus;
1037
1038 switch (hw->device_id) {
1039 /* C3000 SoCs */
1040 case IXGBE_DEV_ID_X550EM_A_KR:
1041 case IXGBE_DEV_ID_X550EM_A_KR_L:
1042 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1043 case IXGBE_DEV_ID_X550EM_A_SGMII:
1044 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1045 case IXGBE_DEV_ID_X550EM_A_10G_T:
1046 case IXGBE_DEV_ID_X550EM_A_SFP:
1047 case IXGBE_DEV_ID_X550EM_A_1G_T:
1048 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1049 if (!ixgbe_x550em_a_has_mii(hw))
1050 return 0;
1051 read_c22 = ixgbe_x550em_a_mii_bus_read_c22;
1052 write_c22 = ixgbe_x550em_a_mii_bus_write_c22;
1053 read_c45 = ixgbe_x550em_a_mii_bus_read_c45;
1054 write_c45 = ixgbe_x550em_a_mii_bus_write_c45;
1055 break;
1056 default:
1057 read_c22 = ixgbe_mii_bus_read_c22;
1058 write_c22 = ixgbe_mii_bus_write_c22;
1059 read_c45 = ixgbe_mii_bus_read_c45;
1060 write_c45 = ixgbe_mii_bus_write_c45;
1061 break;
1062 }
1063
1064 bus = devm_mdiobus_alloc(dev);
1065 if (!bus)
1066 return -ENOMEM;
1067
1068 bus->read = read_c22;
1069 bus->write = write_c22;
1070 bus->read_c45 = read_c45;
1071 bus->write_c45 = write_c45;
1072
1073 /* Use the position of the device in the PCI hierarchy as the id */
1074 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
1075 pci_name(pdev));
1076
1077 bus->name = "ixgbe-mdio";
1078 bus->priv = adapter;
1079 bus->parent = dev;
1080 bus->phy_mask = GENMASK(31, 0);
1081
1082 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
1083 * unfortunately that causes some clause 22 frames to be sent with
1084 * clause 45 addressing. We don't want that.
1085 */
1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1087
1088 adapter->mii_bus = bus;
1089 return mdiobus_register(bus);
1090 }
1091
1092 /**
1093 * ixgbe_setup_phy_link_generic - Set and restart autoneg
1094 * @hw: pointer to hardware structure
1095 *
1096 * Restart autonegotiation and PHY and waits for completion.
1097 **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)1098 int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
1099 {
1100 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1101 ixgbe_link_speed speed;
1102 bool autoneg = false;
1103 int status = 0;
1104
1105 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1106
1107 /* Set or unset auto-negotiation 10G advertisement */
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1109
1110 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1112 (speed & IXGBE_LINK_SPEED_10GB_FULL))
1113 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1114
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1116
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1118 MDIO_MMD_AN, &autoneg_reg);
1119
1120 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_e610) {
1121 /* Set or unset auto-negotiation 5G advertisement */
1122 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1124 (speed & IXGBE_LINK_SPEED_5GB_FULL))
1125 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1126
1127 /* Set or unset auto-negotiation 2.5G advertisement */
1128 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1129 if ((hw->phy.autoneg_advertised &
1130 IXGBE_LINK_SPEED_2_5GB_FULL) &&
1131 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1132 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1133 }
1134
1135 /* Set or unset auto-negotiation 1G advertisement */
1136 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1138 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1139 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1140
1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1142 MDIO_MMD_AN, autoneg_reg);
1143
1144 /* Set or unset auto-negotiation 100M advertisement */
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1146
1147 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1149 (speed & IXGBE_LINK_SPEED_100_FULL))
1150 autoneg_reg |= ADVERTISE_100FULL;
1151
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1153
1154 /* Blocked by MNG FW so don't reset PHY */
1155 if (ixgbe_check_reset_blocked(hw))
1156 return 0;
1157
1158 /* Restart PHY autonegotiation and wait for completion */
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1160 MDIO_MMD_AN, &autoneg_reg);
1161
1162 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1163
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1165 MDIO_MMD_AN, autoneg_reg);
1166
1167 return status;
1168 }
1169
1170 /**
1171 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1172 * @hw: pointer to hardware structure
1173 * @speed: new link speed
1174 * @autoneg_wait_to_complete: unused
1175 **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)1176 int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1177 ixgbe_link_speed speed,
1178 bool autoneg_wait_to_complete)
1179 {
1180 /* Clear autoneg_advertised and set new values based on input link
1181 * speed.
1182 */
1183 hw->phy.autoneg_advertised = 0;
1184
1185 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1187
1188 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1190
1191 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1193
1194 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1196
1197 if (speed & IXGBE_LINK_SPEED_100_FULL)
1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1199
1200 if (speed & IXGBE_LINK_SPEED_10_FULL)
1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1202
1203 /* Setup link based on the new speed settings */
1204 if (hw->phy.ops.setup_link)
1205 hw->phy.ops.setup_link(hw);
1206
1207 return 0;
1208 }
1209
1210 /**
1211 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1212 * @hw: pointer to hardware structure
1213 *
1214 * Determines the supported link capabilities by reading the PHY auto
1215 * negotiation register.
1216 */
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)1217 static int ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1218 {
1219 u16 speed_ability;
1220 int status;
1221
1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1223 &speed_ability);
1224 if (status)
1225 return status;
1226
1227 if (speed_ability & MDIO_SPEED_10G)
1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1229 if (speed_ability & MDIO_PMA_SPEED_1000)
1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1231 if (speed_ability & MDIO_PMA_SPEED_100)
1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1233
1234 switch (hw->mac.type) {
1235 case ixgbe_mac_X550:
1236 case ixgbe_mac_e610:
1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1238 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1239 break;
1240 case ixgbe_mac_X550EM_x:
1241 case ixgbe_mac_x550em_a:
1242 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1243 break;
1244 default:
1245 break;
1246 }
1247
1248 return 0;
1249 }
1250
1251 /**
1252 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1253 * @hw: pointer to hardware structure
1254 * @speed: pointer to link speed
1255 * @autoneg: boolean auto-negotiation value
1256 */
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)1257 int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1258 ixgbe_link_speed *speed,
1259 bool *autoneg)
1260 {
1261 int status = 0;
1262
1263 *autoneg = true;
1264 if (!hw->phy.speeds_supported)
1265 status = ixgbe_get_copper_speeds_supported(hw);
1266
1267 *speed = hw->phy.speeds_supported;
1268 return status;
1269 }
1270
1271 /**
1272 * ixgbe_check_phy_link_tnx - Determine link and speed status
1273 * @hw: pointer to hardware structure
1274 * @speed: link speed
1275 * @link_up: status of link
1276 *
1277 * Reads the VS1 register to determine if link is up and the current speed for
1278 * the PHY.
1279 **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)1280 int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1281 bool *link_up)
1282 {
1283 u32 max_time_out = 10;
1284 u16 phy_speed = 0;
1285 u16 phy_link = 0;
1286 u16 phy_data = 0;
1287 u32 time_out;
1288 int status;
1289
1290 /* Initialize speed and link to default case */
1291 *link_up = false;
1292 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1293
1294 /*
1295 * Check current speed and link status of the PHY register.
1296 * This is a vendor specific register and may have to
1297 * be changed for other copper PHYs.
1298 */
1299 for (time_out = 0; time_out < max_time_out; time_out++) {
1300 udelay(10);
1301 status = hw->phy.ops.read_reg(hw,
1302 MDIO_STAT1,
1303 MDIO_MMD_VEND1,
1304 &phy_data);
1305 phy_link = phy_data &
1306 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1307 phy_speed = phy_data &
1308 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1309 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1310 *link_up = true;
1311 if (phy_speed ==
1312 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1313 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1314 break;
1315 }
1316 }
1317
1318 return status;
1319 }
1320
1321 /**
1322 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1323 * @hw: pointer to hardware structure
1324 *
1325 * Restart autonegotiation and PHY and waits for completion.
1326 * This function always returns success, this is necessary since
1327 * it is called via a function pointer that could call other
1328 * functions that could return an error.
1329 **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1330 int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1331 {
1332 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1333 bool autoneg = false;
1334 ixgbe_link_speed speed;
1335
1336 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1337
1338 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1339 /* Set or unset auto-negotiation 10G advertisement */
1340 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1341 MDIO_MMD_AN,
1342 &autoneg_reg);
1343
1344 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1345 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1346 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1347
1348 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1349 MDIO_MMD_AN,
1350 autoneg_reg);
1351 }
1352
1353 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1354 /* Set or unset auto-negotiation 1G advertisement */
1355 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1356 MDIO_MMD_AN,
1357 &autoneg_reg);
1358
1359 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1360 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1361 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1362
1363 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1364 MDIO_MMD_AN,
1365 autoneg_reg);
1366 }
1367
1368 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1369 /* Set or unset auto-negotiation 100M advertisement */
1370 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1371 MDIO_MMD_AN,
1372 &autoneg_reg);
1373
1374 autoneg_reg &= ~(ADVERTISE_100FULL |
1375 ADVERTISE_100HALF);
1376 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1377 autoneg_reg |= ADVERTISE_100FULL;
1378
1379 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1380 MDIO_MMD_AN,
1381 autoneg_reg);
1382 }
1383
1384 /* Blocked by MNG FW so don't reset PHY */
1385 if (ixgbe_check_reset_blocked(hw))
1386 return 0;
1387
1388 /* Restart PHY autonegotiation and wait for completion */
1389 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1390 MDIO_MMD_AN, &autoneg_reg);
1391
1392 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1393
1394 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1395 MDIO_MMD_AN, autoneg_reg);
1396 return 0;
1397 }
1398
1399 /**
1400 * ixgbe_reset_phy_nl - Performs a PHY reset
1401 * @hw: pointer to hardware structure
1402 **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1403 int ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1404 {
1405 u16 phy_offset, control, eword, edata, block_crc;
1406 u16 list_offset, data_offset;
1407 bool end_data = false;
1408 u16 phy_data = 0;
1409 int ret_val;
1410 u32 i;
1411
1412 /* Blocked by MNG FW so bail */
1413 if (ixgbe_check_reset_blocked(hw))
1414 return 0;
1415
1416 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1417
1418 /* reset the PHY and poll for completion */
1419 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1420 (phy_data | MDIO_CTRL1_RESET));
1421
1422 for (i = 0; i < 100; i++) {
1423 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1424 &phy_data);
1425 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1426 break;
1427 usleep_range(10000, 20000);
1428 }
1429
1430 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1431 hw_dbg(hw, "PHY reset did not complete.\n");
1432 return -EIO;
1433 }
1434
1435 /* Get init offsets */
1436 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1437 &data_offset);
1438 if (ret_val)
1439 return ret_val;
1440
1441 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1442 data_offset++;
1443 while (!end_data) {
1444 /*
1445 * Read control word from PHY init contents offset
1446 */
1447 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1448 if (ret_val)
1449 goto err_eeprom;
1450 control = FIELD_GET(IXGBE_CONTROL_MASK_NL, eword);
1451 edata = eword & IXGBE_DATA_MASK_NL;
1452 switch (control) {
1453 case IXGBE_DELAY_NL:
1454 data_offset++;
1455 hw_dbg(hw, "DELAY: %d MS\n", edata);
1456 usleep_range(edata * 1000, edata * 2000);
1457 break;
1458 case IXGBE_DATA_NL:
1459 hw_dbg(hw, "DATA:\n");
1460 data_offset++;
1461 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1462 &phy_offset);
1463 if (ret_val)
1464 goto err_eeprom;
1465 for (i = 0; i < edata; i++) {
1466 ret_val = hw->eeprom.ops.read(hw, data_offset,
1467 &eword);
1468 if (ret_val)
1469 goto err_eeprom;
1470 hw->phy.ops.write_reg(hw, phy_offset,
1471 MDIO_MMD_PMAPMD, eword);
1472 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1473 phy_offset);
1474 data_offset++;
1475 phy_offset++;
1476 }
1477 break;
1478 case IXGBE_CONTROL_NL:
1479 data_offset++;
1480 hw_dbg(hw, "CONTROL:\n");
1481 if (edata == IXGBE_CONTROL_EOL_NL) {
1482 hw_dbg(hw, "EOL\n");
1483 end_data = true;
1484 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1485 hw_dbg(hw, "SOL\n");
1486 } else {
1487 hw_dbg(hw, "Bad control value\n");
1488 return -EIO;
1489 }
1490 break;
1491 default:
1492 hw_dbg(hw, "Bad control type\n");
1493 return -EIO;
1494 }
1495 }
1496
1497 return ret_val;
1498
1499 err_eeprom:
1500 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1501 return -EIO;
1502 }
1503
1504 /**
1505 * ixgbe_identify_module_generic - Identifies module type
1506 * @hw: pointer to hardware structure
1507 *
1508 * Determines HW type and calls appropriate function.
1509 **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1510 int ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1511 {
1512 switch (hw->mac.ops.get_media_type(hw)) {
1513 case ixgbe_media_type_fiber:
1514 return ixgbe_identify_sfp_module_generic(hw);
1515 case ixgbe_media_type_fiber_qsfp:
1516 return ixgbe_identify_qsfp_module_generic(hw);
1517 default:
1518 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1519 return -ENOENT;
1520 }
1521
1522 return -ENOENT;
1523 }
1524
1525 /**
1526 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1527 * @hw: pointer to hardware structure
1528 *
1529 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1530 **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1531 int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1532 {
1533 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1534 struct ixgbe_adapter *adapter = hw->back;
1535 u8 oui_bytes[3] = {0, 0, 0};
1536 u8 bitrate_nominal = 0;
1537 u8 sm_length_100m = 0;
1538 u8 comp_codes_10g = 0;
1539 u8 comp_codes_1g = 0;
1540 u8 sm_length_km = 0;
1541 u16 enforce_sfp = 0;
1542 u32 vendor_oui = 0;
1543 u8 identifier = 0;
1544 u8 cable_tech = 0;
1545 u8 cable_spec = 0;
1546 int status;
1547
1548 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1549 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1550 return -ENOENT;
1551 }
1552
1553 /* LAN ID is needed for sfp_type determination */
1554 hw->mac.ops.set_lan_id(hw);
1555
1556 status = hw->phy.ops.read_i2c_eeprom(hw,
1557 IXGBE_SFF_IDENTIFIER,
1558 &identifier);
1559
1560 if (status)
1561 goto err_read_i2c_eeprom;
1562
1563 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1564 hw->phy.type = ixgbe_phy_sfp_unsupported;
1565 return -EOPNOTSUPP;
1566 }
1567 status = hw->phy.ops.read_i2c_eeprom(hw,
1568 IXGBE_SFF_1GBE_COMP_CODES,
1569 &comp_codes_1g);
1570
1571 if (status)
1572 goto err_read_i2c_eeprom;
1573
1574 status = hw->phy.ops.read_i2c_eeprom(hw,
1575 IXGBE_SFF_10GBE_COMP_CODES,
1576 &comp_codes_10g);
1577
1578 if (status)
1579 goto err_read_i2c_eeprom;
1580 status = hw->phy.ops.read_i2c_eeprom(hw,
1581 IXGBE_SFF_CABLE_TECHNOLOGY,
1582 &cable_tech);
1583 if (status)
1584 goto err_read_i2c_eeprom;
1585
1586 status = hw->phy.ops.read_i2c_eeprom(hw,
1587 IXGBE_SFF_BITRATE_NOMINAL,
1588 &bitrate_nominal);
1589 if (status)
1590 goto err_read_i2c_eeprom;
1591
1592 /* ID Module
1593 * =========
1594 * 0 SFP_DA_CU
1595 * 1 SFP_SR
1596 * 2 SFP_LR
1597 * 3 SFP_DA_CORE0 - 82599-specific
1598 * 4 SFP_DA_CORE1 - 82599-specific
1599 * 5 SFP_SR/LR_CORE0 - 82599-specific
1600 * 6 SFP_SR/LR_CORE1 - 82599-specific
1601 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1602 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1603 * 9 SFP_1g_cu_CORE0 - 82599-specific
1604 * 10 SFP_1g_cu_CORE1 - 82599-specific
1605 * 11 SFP_1g_sx_CORE0 - 82599-specific
1606 * 12 SFP_1g_sx_CORE1 - 82599-specific
1607 */
1608 if (hw->mac.type == ixgbe_mac_82598EB) {
1609 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1610 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1611 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1612 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1613 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1614 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1615 else
1616 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1617 } else {
1618 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1619 if (hw->bus.lan_id == 0)
1620 hw->phy.sfp_type =
1621 ixgbe_sfp_type_da_cu_core0;
1622 else
1623 hw->phy.sfp_type =
1624 ixgbe_sfp_type_da_cu_core1;
1625 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1626 hw->phy.ops.read_i2c_eeprom(
1627 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1628 &cable_spec);
1629 if (cable_spec &
1630 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1631 if (hw->bus.lan_id == 0)
1632 hw->phy.sfp_type =
1633 ixgbe_sfp_type_da_act_lmt_core0;
1634 else
1635 hw->phy.sfp_type =
1636 ixgbe_sfp_type_da_act_lmt_core1;
1637 } else {
1638 hw->phy.sfp_type =
1639 ixgbe_sfp_type_unknown;
1640 }
1641 } else if (comp_codes_10g &
1642 (IXGBE_SFF_10GBASESR_CAPABLE |
1643 IXGBE_SFF_10GBASELR_CAPABLE)) {
1644 if (hw->bus.lan_id == 0)
1645 hw->phy.sfp_type =
1646 ixgbe_sfp_type_srlr_core0;
1647 else
1648 hw->phy.sfp_type =
1649 ixgbe_sfp_type_srlr_core1;
1650 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1651 if (hw->bus.lan_id == 0)
1652 hw->phy.sfp_type =
1653 ixgbe_sfp_type_1g_cu_core0;
1654 else
1655 hw->phy.sfp_type =
1656 ixgbe_sfp_type_1g_cu_core1;
1657 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1658 if (hw->bus.lan_id == 0)
1659 hw->phy.sfp_type =
1660 ixgbe_sfp_type_1g_sx_core0;
1661 else
1662 hw->phy.sfp_type =
1663 ixgbe_sfp_type_1g_sx_core1;
1664 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1665 if (hw->bus.lan_id == 0)
1666 hw->phy.sfp_type =
1667 ixgbe_sfp_type_1g_lx_core0;
1668 else
1669 hw->phy.sfp_type =
1670 ixgbe_sfp_type_1g_lx_core1;
1671 /* Support only Ethernet 1000BASE-BX10, checking the Bit Rate
1672 * Nominal Value as per SFF-8472 by convention 1.25 Gb/s should
1673 * be rounded up to 0Dh (13 in units of 100 MBd) for 1000BASE-BX
1674 */
1675 } else if ((comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) &&
1676 (bitrate_nominal == 0xD)) {
1677 if (hw->bus.lan_id == 0)
1678 hw->phy.sfp_type =
1679 ixgbe_sfp_type_1g_bx_core0;
1680 else
1681 hw->phy.sfp_type =
1682 ixgbe_sfp_type_1g_bx_core1;
1683 /* Support Ethernet 10G-BX, checking the Bit Rate
1684 * Nominal Value as per SFF-8472 to be 12.5 Gb/s (67h) and
1685 * Single Mode fibre with at least 1km link length
1686 */
1687 } else if ((!comp_codes_10g) && (bitrate_nominal == 0x67) &&
1688 (!(cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)) &&
1689 (!(cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE))) {
1690 status = hw->phy.ops.read_i2c_eeprom(hw,
1691 IXGBE_SFF_SM_LENGTH_KM,
1692 &sm_length_km);
1693 if (status != 0)
1694 goto err_read_i2c_eeprom;
1695 status = hw->phy.ops.read_i2c_eeprom(hw,
1696 IXGBE_SFF_SM_LENGTH_100M,
1697 &sm_length_100m);
1698 if (status != 0)
1699 goto err_read_i2c_eeprom;
1700 if (sm_length_km > 0 || sm_length_100m >= 10) {
1701 if (hw->bus.lan_id == 0)
1702 hw->phy.sfp_type =
1703 ixgbe_sfp_type_10g_bx_core0;
1704 else
1705 hw->phy.sfp_type =
1706 ixgbe_sfp_type_10g_bx_core1;
1707 } else {
1708 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1709 }
1710 } else {
1711 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1712 }
1713 }
1714
1715 if (hw->phy.sfp_type != stored_sfp_type)
1716 hw->phy.sfp_setup_needed = true;
1717
1718 /* Determine if the SFP+ PHY is dual speed or not. */
1719 hw->phy.multispeed_fiber = false;
1720 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1721 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1722 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1723 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1724 hw->phy.multispeed_fiber = true;
1725
1726 /* Determine PHY vendor */
1727 if (hw->phy.type != ixgbe_phy_nl) {
1728 hw->phy.id = identifier;
1729 status = hw->phy.ops.read_i2c_eeprom(hw,
1730 IXGBE_SFF_VENDOR_OUI_BYTE0,
1731 &oui_bytes[0]);
1732
1733 if (status != 0)
1734 goto err_read_i2c_eeprom;
1735
1736 status = hw->phy.ops.read_i2c_eeprom(hw,
1737 IXGBE_SFF_VENDOR_OUI_BYTE1,
1738 &oui_bytes[1]);
1739
1740 if (status != 0)
1741 goto err_read_i2c_eeprom;
1742
1743 status = hw->phy.ops.read_i2c_eeprom(hw,
1744 IXGBE_SFF_VENDOR_OUI_BYTE2,
1745 &oui_bytes[2]);
1746
1747 if (status != 0)
1748 goto err_read_i2c_eeprom;
1749
1750 vendor_oui =
1751 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1752 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1753 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1754
1755 switch (vendor_oui) {
1756 case IXGBE_SFF_VENDOR_OUI_TYCO:
1757 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1758 hw->phy.type =
1759 ixgbe_phy_sfp_passive_tyco;
1760 break;
1761 case IXGBE_SFF_VENDOR_OUI_FTL:
1762 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1763 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1764 else
1765 hw->phy.type = ixgbe_phy_sfp_ftl;
1766 break;
1767 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1768 hw->phy.type = ixgbe_phy_sfp_avago;
1769 break;
1770 case IXGBE_SFF_VENDOR_OUI_INTEL:
1771 hw->phy.type = ixgbe_phy_sfp_intel;
1772 break;
1773 default:
1774 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1775 hw->phy.type =
1776 ixgbe_phy_sfp_passive_unknown;
1777 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1778 hw->phy.type =
1779 ixgbe_phy_sfp_active_unknown;
1780 else
1781 hw->phy.type = ixgbe_phy_sfp_unknown;
1782 break;
1783 }
1784 }
1785
1786 /* Allow any DA cable vendor */
1787 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1788 IXGBE_SFF_DA_ACTIVE_CABLE))
1789 return 0;
1790
1791 /* Verify supported 1G SFP modules */
1792 if (comp_codes_10g == 0 &&
1793 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1794 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1795 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1796 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1797 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1798 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1799 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1800 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1 ||
1801 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core0 ||
1802 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core1)) {
1803 hw->phy.type = ixgbe_phy_sfp_unsupported;
1804 return -EOPNOTSUPP;
1805 }
1806
1807 /* Anything else 82598-based is supported */
1808 if (hw->mac.type == ixgbe_mac_82598EB)
1809 return 0;
1810
1811 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1812 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1813 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1814 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1815 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1816 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1817 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1818 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1819 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1820 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1 ||
1821 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core0 ||
1822 hw->phy.sfp_type == ixgbe_sfp_type_10g_bx_core1)) {
1823 /* Make sure we're a supported PHY type */
1824 if (hw->phy.type == ixgbe_phy_sfp_intel)
1825 return 0;
1826 if (hw->allow_unsupported_sfp) {
1827 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1828 return 0;
1829 }
1830 hw_dbg(hw, "SFP+ module not supported\n");
1831 hw->phy.type = ixgbe_phy_sfp_unsupported;
1832 return -EOPNOTSUPP;
1833 }
1834 return 0;
1835
1836 err_read_i2c_eeprom:
1837 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1838 if (hw->phy.type != ixgbe_phy_nl) {
1839 hw->phy.id = 0;
1840 hw->phy.type = ixgbe_phy_unknown;
1841 }
1842 return -ENOENT;
1843 }
1844
1845 /**
1846 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1847 * @hw: pointer to hardware structure
1848 *
1849 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1850 **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1851 static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1852 {
1853 struct ixgbe_adapter *adapter = hw->back;
1854 int status;
1855 u32 vendor_oui = 0;
1856 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1857 u8 identifier = 0;
1858 u8 comp_codes_1g = 0;
1859 u8 comp_codes_10g = 0;
1860 u8 oui_bytes[3] = {0, 0, 0};
1861 u16 enforce_sfp = 0;
1862 u8 connector = 0;
1863 u8 cable_length = 0;
1864 u8 device_tech = 0;
1865 bool active_cable = false;
1866
1867 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1868 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1869 return -ENOENT;
1870 }
1871
1872 /* LAN ID is needed for sfp_type determination */
1873 hw->mac.ops.set_lan_id(hw);
1874
1875 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1876 &identifier);
1877
1878 if (status != 0)
1879 goto err_read_i2c_eeprom;
1880
1881 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1882 hw->phy.type = ixgbe_phy_sfp_unsupported;
1883 return -EOPNOTSUPP;
1884 }
1885
1886 hw->phy.id = identifier;
1887
1888 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1889 &comp_codes_10g);
1890
1891 if (status != 0)
1892 goto err_read_i2c_eeprom;
1893
1894 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1895 &comp_codes_1g);
1896
1897 if (status != 0)
1898 goto err_read_i2c_eeprom;
1899
1900 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1901 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1902 if (hw->bus.lan_id == 0)
1903 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1904 else
1905 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1906 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1907 IXGBE_SFF_10GBASELR_CAPABLE)) {
1908 if (hw->bus.lan_id == 0)
1909 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1910 else
1911 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1912 } else {
1913 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1914 active_cable = true;
1915
1916 if (!active_cable) {
1917 /* check for active DA cables that pre-date
1918 * SFF-8436 v3.6
1919 */
1920 hw->phy.ops.read_i2c_eeprom(hw,
1921 IXGBE_SFF_QSFP_CONNECTOR,
1922 &connector);
1923
1924 hw->phy.ops.read_i2c_eeprom(hw,
1925 IXGBE_SFF_QSFP_CABLE_LENGTH,
1926 &cable_length);
1927
1928 hw->phy.ops.read_i2c_eeprom(hw,
1929 IXGBE_SFF_QSFP_DEVICE_TECH,
1930 &device_tech);
1931
1932 if ((connector ==
1933 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1934 (cable_length > 0) &&
1935 ((device_tech >> 4) ==
1936 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1937 active_cable = true;
1938 }
1939
1940 if (active_cable) {
1941 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1942 if (hw->bus.lan_id == 0)
1943 hw->phy.sfp_type =
1944 ixgbe_sfp_type_da_act_lmt_core0;
1945 else
1946 hw->phy.sfp_type =
1947 ixgbe_sfp_type_da_act_lmt_core1;
1948 } else {
1949 /* unsupported module type */
1950 hw->phy.type = ixgbe_phy_sfp_unsupported;
1951 return -EOPNOTSUPP;
1952 }
1953 }
1954
1955 if (hw->phy.sfp_type != stored_sfp_type)
1956 hw->phy.sfp_setup_needed = true;
1957
1958 /* Determine if the QSFP+ PHY is dual speed or not. */
1959 hw->phy.multispeed_fiber = false;
1960 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1961 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1962 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1963 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1964 hw->phy.multispeed_fiber = true;
1965
1966 /* Determine PHY vendor for optical modules */
1967 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1968 IXGBE_SFF_10GBASELR_CAPABLE)) {
1969 status = hw->phy.ops.read_i2c_eeprom(hw,
1970 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1971 &oui_bytes[0]);
1972
1973 if (status != 0)
1974 goto err_read_i2c_eeprom;
1975
1976 status = hw->phy.ops.read_i2c_eeprom(hw,
1977 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1978 &oui_bytes[1]);
1979
1980 if (status != 0)
1981 goto err_read_i2c_eeprom;
1982
1983 status = hw->phy.ops.read_i2c_eeprom(hw,
1984 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1985 &oui_bytes[2]);
1986
1987 if (status != 0)
1988 goto err_read_i2c_eeprom;
1989
1990 vendor_oui =
1991 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1992 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1993 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1994
1995 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1996 hw->phy.type = ixgbe_phy_qsfp_intel;
1997 else
1998 hw->phy.type = ixgbe_phy_qsfp_unknown;
1999
2000 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
2001 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
2002 /* Make sure we're a supported PHY type */
2003 if (hw->phy.type == ixgbe_phy_qsfp_intel)
2004 return 0;
2005 if (hw->allow_unsupported_sfp) {
2006 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
2007 return 0;
2008 }
2009 hw_dbg(hw, "QSFP module not supported\n");
2010 hw->phy.type = ixgbe_phy_sfp_unsupported;
2011 return -EOPNOTSUPP;
2012 }
2013 return 0;
2014 }
2015 return 0;
2016
2017 err_read_i2c_eeprom:
2018 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
2019 hw->phy.id = 0;
2020 hw->phy.type = ixgbe_phy_unknown;
2021
2022 return -ENOENT;
2023 }
2024
2025 /**
2026 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
2027 * @hw: pointer to hardware structure
2028 * @list_offset: offset to the SFP ID list
2029 * @data_offset: offset to the SFP data block
2030 *
2031 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
2032 * so it returns the offsets to the phy init sequence block.
2033 **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)2034 int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
2035 u16 *list_offset,
2036 u16 *data_offset)
2037 {
2038 u16 sfp_id;
2039 u16 sfp_type = hw->phy.sfp_type;
2040
2041 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
2042 return -EOPNOTSUPP;
2043
2044 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2045 return -ENOENT;
2046
2047 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
2048 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
2049 return -EOPNOTSUPP;
2050
2051 /*
2052 * Limiting active cables, 10G BX and 1G Phys must be initialized as
2053 * SR modules
2054 */
2055 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
2056 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2057 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
2058 sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2059 sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
2060 sfp_type == ixgbe_sfp_type_10g_bx_core0)
2061 sfp_type = ixgbe_sfp_type_srlr_core0;
2062 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
2063 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
2064 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
2065 sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2066 sfp_type == ixgbe_sfp_type_1g_bx_core1 ||
2067 sfp_type == ixgbe_sfp_type_10g_bx_core1)
2068 sfp_type = ixgbe_sfp_type_srlr_core1;
2069
2070 /* Read offset to PHY init contents */
2071 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2072 hw_err(hw, "eeprom read at %d failed\n",
2073 IXGBE_PHY_INIT_OFFSET_NL);
2074 return -EIO;
2075 }
2076
2077 if ((!*list_offset) || (*list_offset == 0xFFFF))
2078 return -EIO;
2079
2080 /* Shift offset to first ID word */
2081 (*list_offset)++;
2082
2083 /*
2084 * Find the matching SFP ID in the EEPROM
2085 * and program the init sequence
2086 */
2087 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2088 goto err_phy;
2089
2090 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
2091 if (sfp_id == sfp_type) {
2092 (*list_offset)++;
2093 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2094 goto err_phy;
2095 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
2096 hw_dbg(hw, "SFP+ module not supported\n");
2097 return -EOPNOTSUPP;
2098 } else {
2099 break;
2100 }
2101 } else {
2102 (*list_offset) += 2;
2103 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2104 goto err_phy;
2105 }
2106 }
2107
2108 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
2109 hw_dbg(hw, "No matching SFP+ module found\n");
2110 return -EOPNOTSUPP;
2111 }
2112
2113 return 0;
2114
2115 err_phy:
2116 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
2117 return -EIO;
2118 }
2119
2120 /**
2121 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2122 * @hw: pointer to hardware structure
2123 * @byte_offset: EEPROM byte offset to read
2124 * @eeprom_data: value read
2125 *
2126 * Performs byte read operation to SFP module's EEPROM over I2C interface.
2127 **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)2128 int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2129 u8 *eeprom_data)
2130 {
2131 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2132 IXGBE_I2C_EEPROM_DEV_ADDR,
2133 eeprom_data);
2134 }
2135
2136 /**
2137 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2138 * @hw: pointer to hardware structure
2139 * @byte_offset: byte offset at address 0xA2
2140 * @sff8472_data: value read
2141 *
2142 * Performs byte read operation to SFP module's SFF-8472 data over I2C
2143 **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)2144 int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2145 u8 *sff8472_data)
2146 {
2147 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2148 IXGBE_I2C_EEPROM_DEV_ADDR2,
2149 sff8472_data);
2150 }
2151
2152 /**
2153 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2154 * @hw: pointer to hardware structure
2155 * @byte_offset: EEPROM byte offset to write
2156 * @eeprom_data: value to write
2157 *
2158 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2159 **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)2160 int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2161 u8 eeprom_data)
2162 {
2163 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2164 IXGBE_I2C_EEPROM_DEV_ADDR,
2165 eeprom_data);
2166 }
2167
2168 /**
2169 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2170 * @hw: pointer to hardware structure
2171 * @offset: eeprom offset to be read
2172 * @addr: I2C address to be read
2173 */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)2174 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2175 {
2176 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2177 offset == IXGBE_SFF_IDENTIFIER &&
2178 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2179 return true;
2180 return false;
2181 }
2182
2183 /**
2184 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2185 * @hw: pointer to hardware structure
2186 * @byte_offset: byte offset to read
2187 * @dev_addr: device address
2188 * @data: value read
2189 * @lock: true if to take and release semaphore
2190 *
2191 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2192 * a specified device address.
2193 */
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)2194 static int ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2195 u8 dev_addr, u8 *data, bool lock)
2196 {
2197 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2198 u32 max_retry = 10;
2199 bool nack = true;
2200 u32 retry = 0;
2201 int status;
2202
2203 if (hw->mac.type >= ixgbe_mac_X550)
2204 max_retry = 3;
2205 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2206 max_retry = IXGBE_SFP_DETECT_RETRIES;
2207
2208 *data = 0;
2209
2210 do {
2211 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2212 return -EBUSY;
2213
2214 ixgbe_i2c_start(hw);
2215
2216 /* Device Address and write indication */
2217 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2218 if (status != 0)
2219 goto fail;
2220
2221 status = ixgbe_get_i2c_ack(hw);
2222 if (status != 0)
2223 goto fail;
2224
2225 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2226 if (status != 0)
2227 goto fail;
2228
2229 status = ixgbe_get_i2c_ack(hw);
2230 if (status != 0)
2231 goto fail;
2232
2233 ixgbe_i2c_start(hw);
2234
2235 /* Device Address and read indication */
2236 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2237 if (status != 0)
2238 goto fail;
2239
2240 status = ixgbe_get_i2c_ack(hw);
2241 if (status != 0)
2242 goto fail;
2243
2244 status = ixgbe_clock_in_i2c_byte(hw, data);
2245 if (status != 0)
2246 goto fail;
2247
2248 status = ixgbe_clock_out_i2c_bit(hw, nack);
2249 if (status != 0)
2250 goto fail;
2251
2252 ixgbe_i2c_stop(hw);
2253 if (lock)
2254 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2255 return 0;
2256
2257 fail:
2258 ixgbe_i2c_bus_clear(hw);
2259 if (lock) {
2260 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2261 msleep(100);
2262 }
2263 retry++;
2264 if (retry < max_retry)
2265 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2266 else
2267 hw_dbg(hw, "I2C byte read error.\n");
2268
2269 } while (retry < max_retry);
2270
2271 return status;
2272 }
2273
2274 /**
2275 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2276 * @hw: pointer to hardware structure
2277 * @byte_offset: byte offset to read
2278 * @dev_addr: device address
2279 * @data: value read
2280 *
2281 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2282 * a specified device address.
2283 */
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2284 int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2285 u8 dev_addr, u8 *data)
2286 {
2287 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2288 data, true);
2289 }
2290
2291 /**
2292 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2293 * @hw: pointer to hardware structure
2294 * @byte_offset: byte offset to read
2295 * @dev_addr: device address
2296 * @data: value read
2297 *
2298 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2299 * a specified device address.
2300 */
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2301 int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2302 u8 dev_addr, u8 *data)
2303 {
2304 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2305 data, false);
2306 }
2307
2308 /**
2309 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2310 * @hw: pointer to hardware structure
2311 * @byte_offset: byte offset to write
2312 * @dev_addr: device address
2313 * @data: value to write
2314 * @lock: true if to take and release semaphore
2315 *
2316 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2317 * a specified device address.
2318 */
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2319 static int ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2320 u8 dev_addr, u8 data, bool lock)
2321 {
2322 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2323 u32 max_retry = 3;
2324 u32 retry = 0;
2325 int status;
2326
2327 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2328 return -EBUSY;
2329
2330 do {
2331 ixgbe_i2c_start(hw);
2332
2333 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2334 if (status != 0)
2335 goto fail;
2336
2337 status = ixgbe_get_i2c_ack(hw);
2338 if (status != 0)
2339 goto fail;
2340
2341 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2342 if (status != 0)
2343 goto fail;
2344
2345 status = ixgbe_get_i2c_ack(hw);
2346 if (status != 0)
2347 goto fail;
2348
2349 status = ixgbe_clock_out_i2c_byte(hw, data);
2350 if (status != 0)
2351 goto fail;
2352
2353 status = ixgbe_get_i2c_ack(hw);
2354 if (status != 0)
2355 goto fail;
2356
2357 ixgbe_i2c_stop(hw);
2358 if (lock)
2359 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2360 return 0;
2361
2362 fail:
2363 ixgbe_i2c_bus_clear(hw);
2364 retry++;
2365 if (retry < max_retry)
2366 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2367 else
2368 hw_dbg(hw, "I2C byte write error.\n");
2369 } while (retry < max_retry);
2370
2371 if (lock)
2372 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2373
2374 return status;
2375 }
2376
2377 /**
2378 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2379 * @hw: pointer to hardware structure
2380 * @byte_offset: byte offset to write
2381 * @dev_addr: device address
2382 * @data: value to write
2383 *
2384 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2385 * a specified device address.
2386 */
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2387 int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2388 u8 dev_addr, u8 data)
2389 {
2390 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2391 data, true);
2392 }
2393
2394 /**
2395 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2396 * @hw: pointer to hardware structure
2397 * @byte_offset: byte offset to write
2398 * @dev_addr: device address
2399 * @data: value to write
2400 *
2401 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2402 * a specified device address.
2403 */
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2404 int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2405 u8 dev_addr, u8 data)
2406 {
2407 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2408 data, false);
2409 }
2410
2411 /**
2412 * ixgbe_i2c_start - Sets I2C start condition
2413 * @hw: pointer to hardware structure
2414 *
2415 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2416 * Set bit-bang mode on X550 hardware.
2417 **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2418 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2419 {
2420 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2421
2422 i2cctl |= IXGBE_I2C_BB_EN(hw);
2423
2424 /* Start condition must begin with data and clock high */
2425 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2426 ixgbe_raise_i2c_clk(hw, &i2cctl);
2427
2428 /* Setup time for start condition (4.7us) */
2429 udelay(IXGBE_I2C_T_SU_STA);
2430
2431 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2432
2433 /* Hold time for start condition (4us) */
2434 udelay(IXGBE_I2C_T_HD_STA);
2435
2436 ixgbe_lower_i2c_clk(hw, &i2cctl);
2437
2438 /* Minimum low period of clock is 4.7 us */
2439 udelay(IXGBE_I2C_T_LOW);
2440
2441 }
2442
2443 /**
2444 * ixgbe_i2c_stop - Sets I2C stop condition
2445 * @hw: pointer to hardware structure
2446 *
2447 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2448 * Disables bit-bang mode and negates data output enable on X550
2449 * hardware.
2450 **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2451 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2452 {
2453 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2454 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2455 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2456 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2457
2458 /* Stop condition must begin with data low and clock high */
2459 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2460 ixgbe_raise_i2c_clk(hw, &i2cctl);
2461
2462 /* Setup time for stop condition (4us) */
2463 udelay(IXGBE_I2C_T_SU_STO);
2464
2465 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2466
2467 /* bus free time between stop and start (4.7us)*/
2468 udelay(IXGBE_I2C_T_BUF);
2469
2470 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2471 i2cctl &= ~bb_en_bit;
2472 i2cctl |= data_oe_bit | clk_oe_bit;
2473 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2474 IXGBE_WRITE_FLUSH(hw);
2475 }
2476 }
2477
2478 /**
2479 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2480 * @hw: pointer to hardware structure
2481 * @data: data byte to clock in
2482 *
2483 * Clocks in one byte data via I2C data/clock
2484 **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2485 static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2486 {
2487 bool bit = false;
2488 int i;
2489
2490 *data = 0;
2491 for (i = 7; i >= 0; i--) {
2492 ixgbe_clock_in_i2c_bit(hw, &bit);
2493 *data |= bit << i;
2494 }
2495
2496 return 0;
2497 }
2498
2499 /**
2500 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2501 * @hw: pointer to hardware structure
2502 * @data: data byte clocked out
2503 *
2504 * Clocks out one byte data via I2C data/clock
2505 **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2506 static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2507 {
2508 bool bit = false;
2509 int status;
2510 u32 i2cctl;
2511 int i;
2512
2513 for (i = 7; i >= 0; i--) {
2514 bit = (data >> i) & 0x1;
2515 status = ixgbe_clock_out_i2c_bit(hw, bit);
2516
2517 if (status != 0)
2518 break;
2519 }
2520
2521 /* Release SDA line (set high) */
2522 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2523 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2524 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2525 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2526 IXGBE_WRITE_FLUSH(hw);
2527
2528 return status;
2529 }
2530
2531 /**
2532 * ixgbe_get_i2c_ack - Polls for I2C ACK
2533 * @hw: pointer to hardware structure
2534 *
2535 * Clocks in/out one bit via I2C data/clock
2536 **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2537 static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2538 {
2539 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2540 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2541 u32 timeout = 10;
2542 bool ack = true;
2543 int status = 0;
2544 u32 i = 0;
2545
2546 if (data_oe_bit) {
2547 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2548 i2cctl |= data_oe_bit;
2549 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2550 IXGBE_WRITE_FLUSH(hw);
2551 }
2552 ixgbe_raise_i2c_clk(hw, &i2cctl);
2553
2554 /* Minimum high period of clock is 4us */
2555 udelay(IXGBE_I2C_T_HIGH);
2556
2557 /* Poll for ACK. Note that ACK in I2C spec is
2558 * transition from 1 to 0 */
2559 for (i = 0; i < timeout; i++) {
2560 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2561 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2562
2563 udelay(1);
2564 if (ack == 0)
2565 break;
2566 }
2567
2568 if (ack == 1) {
2569 hw_dbg(hw, "I2C ack was not received.\n");
2570 status = -EIO;
2571 }
2572
2573 ixgbe_lower_i2c_clk(hw, &i2cctl);
2574
2575 /* Minimum low period of clock is 4.7 us */
2576 udelay(IXGBE_I2C_T_LOW);
2577
2578 return status;
2579 }
2580
2581 /**
2582 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2583 * @hw: pointer to hardware structure
2584 * @data: read data value
2585 *
2586 * Clocks in one bit via I2C data/clock
2587 **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2588 static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2589 {
2590 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2591 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2592
2593 if (data_oe_bit) {
2594 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2595 i2cctl |= data_oe_bit;
2596 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2597 IXGBE_WRITE_FLUSH(hw);
2598 }
2599 ixgbe_raise_i2c_clk(hw, &i2cctl);
2600
2601 /* Minimum high period of clock is 4us */
2602 udelay(IXGBE_I2C_T_HIGH);
2603
2604 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2605 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2606
2607 ixgbe_lower_i2c_clk(hw, &i2cctl);
2608
2609 /* Minimum low period of clock is 4.7 us */
2610 udelay(IXGBE_I2C_T_LOW);
2611
2612 return 0;
2613 }
2614
2615 /**
2616 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2617 * @hw: pointer to hardware structure
2618 * @data: data value to write
2619 *
2620 * Clocks out one bit via I2C data/clock
2621 **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2622 static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2623 {
2624 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2625 int status;
2626
2627 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2628 if (status == 0) {
2629 ixgbe_raise_i2c_clk(hw, &i2cctl);
2630
2631 /* Minimum high period of clock is 4us */
2632 udelay(IXGBE_I2C_T_HIGH);
2633
2634 ixgbe_lower_i2c_clk(hw, &i2cctl);
2635
2636 /* Minimum low period of clock is 4.7 us.
2637 * This also takes care of the data hold time.
2638 */
2639 udelay(IXGBE_I2C_T_LOW);
2640 } else {
2641 hw_dbg(hw, "I2C data was not set to %X\n", data);
2642 return -EIO;
2643 }
2644
2645 return 0;
2646 }
2647 /**
2648 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2649 * @hw: pointer to hardware structure
2650 * @i2cctl: Current value of I2CCTL register
2651 *
2652 * Raises the I2C clock line '0'->'1'
2653 * Negates the I2C clock output enable on X550 hardware.
2654 **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2655 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2656 {
2657 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2658 u32 i = 0;
2659 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2660 u32 i2cctl_r = 0;
2661
2662 if (clk_oe_bit) {
2663 *i2cctl |= clk_oe_bit;
2664 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2665 }
2666
2667 for (i = 0; i < timeout; i++) {
2668 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2669 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2670 IXGBE_WRITE_FLUSH(hw);
2671 /* SCL rise time (1000ns) */
2672 udelay(IXGBE_I2C_T_RISE);
2673
2674 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2675 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2676 break;
2677 }
2678 }
2679
2680 /**
2681 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2682 * @hw: pointer to hardware structure
2683 * @i2cctl: Current value of I2CCTL register
2684 *
2685 * Lowers the I2C clock line '1'->'0'
2686 * Asserts the I2C clock output enable on X550 hardware.
2687 **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2688 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2689 {
2690
2691 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2692 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2693
2694 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2695 IXGBE_WRITE_FLUSH(hw);
2696
2697 /* SCL fall time (300ns) */
2698 udelay(IXGBE_I2C_T_FALL);
2699 }
2700
2701 /**
2702 * ixgbe_set_i2c_data - Sets the I2C data bit
2703 * @hw: pointer to hardware structure
2704 * @i2cctl: Current value of I2CCTL register
2705 * @data: I2C data value (0 or 1) to set
2706 *
2707 * Sets the I2C data bit
2708 * Asserts the I2C data output enable on X550 hardware.
2709 **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2710 static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2711 {
2712 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2713
2714 if (data)
2715 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2716 else
2717 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2718 *i2cctl &= ~data_oe_bit;
2719
2720 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2721 IXGBE_WRITE_FLUSH(hw);
2722
2723 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2724 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2725
2726 if (!data) /* Can't verify data in this case */
2727 return 0;
2728 if (data_oe_bit) {
2729 *i2cctl |= data_oe_bit;
2730 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2731 IXGBE_WRITE_FLUSH(hw);
2732 }
2733
2734 /* Verify data was set correctly */
2735 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2736 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2737 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2738 return -EIO;
2739 }
2740
2741 return 0;
2742 }
2743
2744 /**
2745 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2746 * @hw: pointer to hardware structure
2747 * @i2cctl: Current value of I2CCTL register
2748 *
2749 * Returns the I2C data bit value
2750 * Negates the I2C data output enable on X550 hardware.
2751 **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2752 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2753 {
2754 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2755
2756 if (data_oe_bit) {
2757 *i2cctl |= data_oe_bit;
2758 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2759 IXGBE_WRITE_FLUSH(hw);
2760 udelay(IXGBE_I2C_T_FALL);
2761 }
2762
2763 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2764 return true;
2765 return false;
2766 }
2767
2768 /**
2769 * ixgbe_i2c_bus_clear - Clears the I2C bus
2770 * @hw: pointer to hardware structure
2771 *
2772 * Clears the I2C bus by sending nine clock pulses.
2773 * Used when data line is stuck low.
2774 **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2775 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2776 {
2777 u32 i2cctl;
2778 u32 i;
2779
2780 ixgbe_i2c_start(hw);
2781 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2782
2783 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2784
2785 for (i = 0; i < 9; i++) {
2786 ixgbe_raise_i2c_clk(hw, &i2cctl);
2787
2788 /* Min high period of clock is 4us */
2789 udelay(IXGBE_I2C_T_HIGH);
2790
2791 ixgbe_lower_i2c_clk(hw, &i2cctl);
2792
2793 /* Min low period of clock is 4.7us*/
2794 udelay(IXGBE_I2C_T_LOW);
2795 }
2796
2797 ixgbe_i2c_start(hw);
2798
2799 /* Put the i2c bus back to default state */
2800 ixgbe_i2c_stop(hw);
2801 }
2802
2803 /**
2804 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2805 * @hw: pointer to hardware structure
2806 *
2807 * Checks if the LASI temp alarm status was triggered due to overtemp
2808 *
2809 * Return true when an overtemp event detected, otherwise false.
2810 **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2811 bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2812 {
2813 u16 phy_data = 0;
2814 u32 status;
2815
2816 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2817 return false;
2818
2819 /* Check that the LASI temp alarm status was triggered */
2820 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2821 MDIO_MMD_PMAPMD, &phy_data);
2822 if (status)
2823 return false;
2824
2825 return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM);
2826 }
2827
2828 /** ixgbe_set_copper_phy_power - Control power for copper phy
2829 * @hw: pointer to hardware structure
2830 * @on: true for on, false for off
2831 **/
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2832 int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2833 {
2834 u32 status;
2835 u16 reg;
2836
2837 /* Bail if we don't have copper phy */
2838 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2839 return 0;
2840
2841 if (!on && ixgbe_mng_present(hw))
2842 return 0;
2843
2844 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2845 if (status)
2846 return status;
2847
2848 if (on) {
2849 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2850 } else {
2851 if (ixgbe_check_reset_blocked(hw))
2852 return 0;
2853 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2854 }
2855
2856 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2857 return status;
2858 }
2859