1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018-2025 Intel Corporation
4 */
5 #include <linux/dmi.h>
6 #include "iwl-trans.h"
7 #include "iwl-fh.h"
8 #include "iwl-context-info-gen3.h"
9 #include "internal.h"
10 #include "iwl-prph.h"
11
12 static const struct dmi_system_id dmi_force_scu_active_approved_list[] = {
13 { .ident = "DELL",
14 .matches = {
15 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
16 },
17 },
18 { .ident = "DELL",
19 .matches = {
20 DMI_MATCH(DMI_SYS_VENDOR, "Alienware"),
21 },
22 },
23 /* keep last */
24 {}
25 };
26
iwl_is_force_scu_active_approved(void)27 static bool iwl_is_force_scu_active_approved(void)
28 {
29 return !!dmi_check_system(dmi_force_scu_active_approved_list);
30 }
31
32 static void
iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans * trans,struct iwl_prph_scratch_hwm_cfg * dbg_cfg,u32 * control_flags)33 iwl_pcie_ctxt_info_dbg_enable(struct iwl_trans *trans,
34 struct iwl_prph_scratch_hwm_cfg *dbg_cfg,
35 u32 *control_flags)
36 {
37 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1;
38 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg;
39 u32 dbg_flags = 0;
40
41 if (!iwl_trans_dbg_ini_valid(trans)) {
42 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon;
43
44 iwl_pcie_alloc_fw_monitor(trans, 0);
45
46 if (fw_mon->size) {
47 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
48
49 IWL_DEBUG_FW(trans,
50 "WRT: Applying DRAM buffer destination\n");
51
52 dbg_cfg->hwm_base_addr = cpu_to_le64(fw_mon->physical);
53 dbg_cfg->hwm_size = cpu_to_le32(fw_mon->size);
54 }
55
56 goto out;
57 }
58
59 fw_mon_cfg = &trans->dbg.fw_mon_cfg[alloc_id];
60
61 switch (le32_to_cpu(fw_mon_cfg->buf_location)) {
62 case IWL_FW_INI_LOCATION_SRAM_PATH:
63 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_INTERNAL;
64 IWL_DEBUG_FW(trans,
65 "WRT: Applying SMEM buffer destination\n");
66 break;
67
68 case IWL_FW_INI_LOCATION_NPK_PATH:
69 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_TB22DTF;
70 IWL_DEBUG_FW(trans,
71 "WRT: Applying NPK buffer destination\n");
72 break;
73
74 case IWL_FW_INI_LOCATION_DRAM_PATH:
75 if (trans->dbg.fw_mon_ini[alloc_id].num_frags) {
76 struct iwl_dram_data *frag =
77 &trans->dbg.fw_mon_ini[alloc_id].frags[0];
78 dbg_flags |= IWL_PRPH_SCRATCH_EDBG_DEST_DRAM;
79 dbg_cfg->hwm_base_addr = cpu_to_le64(frag->physical);
80 dbg_cfg->hwm_size = cpu_to_le32(frag->size);
81 dbg_cfg->debug_token_config = cpu_to_le32(trans->dbg.ucode_preset);
82 IWL_DEBUG_FW(trans,
83 "WRT: Applying DRAM destination (debug_token_config=%u)\n",
84 dbg_cfg->debug_token_config);
85 IWL_DEBUG_FW(trans,
86 "WRT: Applying DRAM destination (alloc_id=%u, num_frags=%u)\n",
87 alloc_id,
88 trans->dbg.fw_mon_ini[alloc_id].num_frags);
89 }
90 break;
91 default:
92 IWL_DEBUG_FW(trans, "WRT: Invalid buffer destination (%d)\n",
93 le32_to_cpu(fw_mon_cfg->buf_location));
94 }
95 out:
96 if (dbg_flags)
97 *control_flags |= IWL_PRPH_SCRATCH_EARLY_DEBUG_EN | dbg_flags;
98 }
99
iwl_pcie_ctxt_info_gen3_init(struct iwl_trans * trans,const struct fw_img * fw)100 int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
101 const struct fw_img *fw)
102 {
103 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
104 struct iwl_context_info_gen3 *ctxt_info_gen3;
105 struct iwl_prph_scratch *prph_scratch;
106 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl;
107 struct iwl_prph_info *prph_info;
108 u32 control_flags = 0;
109 u32 control_flags_ext = 0;
110 int ret;
111 int cmdq_size = max_t(u32, IWL_CMD_QUEUE_SIZE,
112 trans->cfg->min_txq_size);
113
114 switch (trans_pcie->rx_buf_size) {
115 case IWL_AMSDU_DEF:
116 return -EINVAL;
117 case IWL_AMSDU_2K:
118 break;
119 case IWL_AMSDU_4K:
120 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
121 break;
122 case IWL_AMSDU_8K:
123 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
124 /* if firmware supports the ext size, tell it */
125 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_8K;
126 break;
127 case IWL_AMSDU_12K:
128 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_4K;
129 /* if firmware supports the ext size, tell it */
130 control_flags |= IWL_PRPH_SCRATCH_RB_SIZE_EXT_16K;
131 break;
132 }
133
134 if (trans->dsbr_urm_fw_dependent)
135 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_FW;
136
137 if (trans->dsbr_urm_permanent)
138 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_URM_PERM;
139
140 if (trans->ext_32khz_clock_valid)
141 control_flags_ext |= IWL_PRPH_SCRATCH_EXT_32KHZ_CLK_VALID;
142
143 /* Allocate prph scratch */
144 prph_scratch = dma_alloc_coherent(trans->dev, sizeof(*prph_scratch),
145 &trans_pcie->prph_scratch_dma_addr,
146 GFP_KERNEL);
147 if (!prph_scratch)
148 return -ENOMEM;
149
150 prph_sc_ctrl = &prph_scratch->ctrl_cfg;
151
152 prph_sc_ctrl->version.version = 0;
153 prph_sc_ctrl->version.mac_id =
154 cpu_to_le16((u16)trans->hw_rev);
155 prph_sc_ctrl->version.size = cpu_to_le16(sizeof(*prph_scratch) / 4);
156
157 control_flags |= IWL_PRPH_SCRATCH_MTR_MODE;
158 control_flags |= IWL_PRPH_MTR_FORMAT_256B & IWL_PRPH_SCRATCH_MTR_FORMAT;
159
160 if (trans->trans_cfg->imr_enabled)
161 control_flags |= IWL_PRPH_SCRATCH_IMR_DEBUG_EN;
162
163 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
164 iwl_is_force_scu_active_approved()) {
165 control_flags |= IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE;
166 IWL_DEBUG_FW(trans,
167 "Context Info: Set SCU_FORCE_ACTIVE (0x%x) in control_flags\n",
168 IWL_PRPH_SCRATCH_SCU_FORCE_ACTIVE);
169 }
170
171 /* initialize RX default queue */
172 prph_sc_ctrl->rbd_cfg.free_rbd_addr =
173 cpu_to_le64(trans_pcie->rxq->bd_dma);
174
175 iwl_pcie_ctxt_info_dbg_enable(trans, &prph_sc_ctrl->hwm_cfg,
176 &control_flags);
177 prph_sc_ctrl->control.control_flags = cpu_to_le32(control_flags);
178 prph_sc_ctrl->control.control_flags_ext = cpu_to_le32(control_flags_ext);
179
180 /* initialize the Step equalizer data */
181 prph_sc_ctrl->step_cfg.mbx_addr_0 = cpu_to_le32(trans->mbx_addr_0_step);
182 prph_sc_ctrl->step_cfg.mbx_addr_1 = cpu_to_le32(trans->mbx_addr_1_step);
183
184 /* allocate ucode sections in dram and set addresses */
185 ret = iwl_pcie_init_fw_sec(trans, fw, &prph_scratch->dram);
186 if (ret)
187 goto err_free_prph_scratch;
188
189
190 /* Allocate prph information
191 * currently we don't assign to the prph info anything, but it would get
192 * assigned later
193 *
194 * We also use the second half of this page to give the device some
195 * dummy TR/CR tail pointers - which shouldn't be necessary as we don't
196 * use this, but the hardware still reads/writes there and we can't let
197 * it go do that with a NULL pointer.
198 */
199 BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2);
200 prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE,
201 &trans_pcie->prph_info_dma_addr,
202 GFP_KERNEL);
203 if (!prph_info) {
204 ret = -ENOMEM;
205 goto err_free_prph_scratch;
206 }
207
208 /* Allocate context info */
209 ctxt_info_gen3 = dma_alloc_coherent(trans->dev,
210 sizeof(*ctxt_info_gen3),
211 &trans_pcie->ctxt_info_dma_addr,
212 GFP_KERNEL);
213 if (!ctxt_info_gen3) {
214 ret = -ENOMEM;
215 goto err_free_prph_info;
216 }
217
218 ctxt_info_gen3->prph_info_base_addr =
219 cpu_to_le64(trans_pcie->prph_info_dma_addr);
220 ctxt_info_gen3->prph_scratch_base_addr =
221 cpu_to_le64(trans_pcie->prph_scratch_dma_addr);
222 ctxt_info_gen3->prph_scratch_size =
223 cpu_to_le32(sizeof(*prph_scratch));
224 ctxt_info_gen3->cr_head_idx_arr_base_addr =
225 cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
226 ctxt_info_gen3->tr_tail_idx_arr_base_addr =
227 cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2);
228 ctxt_info_gen3->cr_tail_idx_arr_base_addr =
229 cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4);
230 ctxt_info_gen3->mtr_base_addr =
231 cpu_to_le64(trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]->dma_addr);
232 ctxt_info_gen3->mcr_base_addr =
233 cpu_to_le64(trans_pcie->rxq->used_bd_dma);
234 ctxt_info_gen3->mtr_size =
235 cpu_to_le16(TFD_QUEUE_CB_SIZE(cmdq_size));
236 ctxt_info_gen3->mcr_size =
237 cpu_to_le16(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds));
238
239 trans_pcie->ctxt_info_gen3 = ctxt_info_gen3;
240 trans_pcie->prph_info = prph_info;
241 trans_pcie->prph_scratch = prph_scratch;
242
243 /* Allocate IML */
244 trans_pcie->iml = dma_alloc_coherent(trans->dev, trans->iml_len,
245 &trans_pcie->iml_dma_addr,
246 GFP_KERNEL);
247 if (!trans_pcie->iml) {
248 ret = -ENOMEM;
249 goto err_free_ctxt_info;
250 }
251
252 memcpy(trans_pcie->iml, trans->iml, trans->iml_len);
253
254 iwl_enable_fw_load_int_ctx_info(trans);
255
256 /* kick FW self load */
257 iwl_write64(trans, CSR_CTXT_INFO_ADDR,
258 trans_pcie->ctxt_info_dma_addr);
259 iwl_write64(trans, CSR_IML_DATA_ADDR,
260 trans_pcie->iml_dma_addr);
261 iwl_write32(trans, CSR_IML_SIZE_ADDR, trans->iml_len);
262
263 iwl_set_bit(trans, CSR_CTXT_INFO_BOOT_CTRL,
264 CSR_AUTO_FUNC_BOOT_ENA);
265
266 return 0;
267
268 err_free_ctxt_info:
269 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
270 trans_pcie->ctxt_info_gen3,
271 trans_pcie->ctxt_info_dma_addr);
272 trans_pcie->ctxt_info_gen3 = NULL;
273 err_free_prph_info:
274 dma_free_coherent(trans->dev, PAGE_SIZE, prph_info,
275 trans_pcie->prph_info_dma_addr);
276
277 err_free_prph_scratch:
278 dma_free_coherent(trans->dev,
279 sizeof(*prph_scratch),
280 prph_scratch,
281 trans_pcie->prph_scratch_dma_addr);
282 return ret;
283
284 }
285
iwl_pcie_ctxt_info_gen3_free(struct iwl_trans * trans,bool alive)286 void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans, bool alive)
287 {
288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
289
290 if (trans_pcie->iml) {
291 dma_free_coherent(trans->dev, trans->iml_len, trans_pcie->iml,
292 trans_pcie->iml_dma_addr);
293 trans_pcie->iml_dma_addr = 0;
294 trans_pcie->iml = NULL;
295 }
296
297 iwl_pcie_ctxt_info_free_fw_img(trans);
298
299 if (alive)
300 return;
301
302 if (!trans_pcie->ctxt_info_gen3)
303 return;
304
305 /* ctxt_info_gen3 and prph_scratch are still needed for PNVM load */
306 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info_gen3),
307 trans_pcie->ctxt_info_gen3,
308 trans_pcie->ctxt_info_dma_addr);
309 trans_pcie->ctxt_info_dma_addr = 0;
310 trans_pcie->ctxt_info_gen3 = NULL;
311
312 dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_scratch),
313 trans_pcie->prph_scratch,
314 trans_pcie->prph_scratch_dma_addr);
315 trans_pcie->prph_scratch_dma_addr = 0;
316 trans_pcie->prph_scratch = NULL;
317
318 /* this is needed for the entire lifetime */
319 dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info,
320 trans_pcie->prph_info_dma_addr);
321 trans_pcie->prph_info_dma_addr = 0;
322 trans_pcie->prph_info = NULL;
323 }
324
iwl_pcie_load_payloads_continuously(struct iwl_trans * trans,const struct iwl_pnvm_image * pnvm_data,struct iwl_dram_data * dram)325 static int iwl_pcie_load_payloads_continuously(struct iwl_trans *trans,
326 const struct iwl_pnvm_image *pnvm_data,
327 struct iwl_dram_data *dram)
328 {
329 u32 len, len0, len1;
330
331 if (pnvm_data->n_chunks != UNFRAGMENTED_PNVM_PAYLOADS_NUMBER) {
332 IWL_DEBUG_FW(trans, "expected 2 payloads, got %d.\n",
333 pnvm_data->n_chunks);
334 return -EINVAL;
335 }
336
337 len0 = pnvm_data->chunks[0].len;
338 len1 = pnvm_data->chunks[1].len;
339 if (len1 > 0xFFFFFFFF - len0) {
340 IWL_DEBUG_FW(trans, "sizes of payloads overflow.\n");
341 return -EINVAL;
342 }
343 len = len0 + len1;
344
345 dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent(trans, len,
346 &dram->physical);
347 if (!dram->block) {
348 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n");
349 return -ENOMEM;
350 }
351
352 dram->size = len;
353 memcpy(dram->block, pnvm_data->chunks[0].data, len0);
354 memcpy((u8 *)dram->block + len0, pnvm_data->chunks[1].data, len1);
355
356 return 0;
357 }
358
iwl_pcie_load_payloads_segments(struct iwl_trans * trans,struct iwl_dram_regions * dram_regions,const struct iwl_pnvm_image * pnvm_data)359 static int iwl_pcie_load_payloads_segments
360 (struct iwl_trans *trans,
361 struct iwl_dram_regions *dram_regions,
362 const struct iwl_pnvm_image *pnvm_data)
363 {
364 struct iwl_dram_data *cur_payload_dram = &dram_regions->drams[0];
365 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
366 struct iwl_prph_scrath_mem_desc_addr_array *addresses;
367 const void *data;
368 u32 len;
369 int i;
370
371 /* allocate and init DRAM descriptors array */
372 len = sizeof(struct iwl_prph_scrath_mem_desc_addr_array);
373 desc_dram->block = iwl_pcie_ctxt_info_dma_alloc_coherent
374 (trans,
375 len,
376 &desc_dram->physical);
377 if (!desc_dram->block) {
378 IWL_DEBUG_FW(trans, "Failed to allocate PNVM DMA.\n");
379 return -ENOMEM;
380 }
381 desc_dram->size = len;
382 memset(desc_dram->block, 0, len);
383
384 /* allocate DRAM region for each payload */
385 dram_regions->n_regions = 0;
386 for (i = 0; i < pnvm_data->n_chunks; i++) {
387 len = pnvm_data->chunks[i].len;
388 data = pnvm_data->chunks[i].data;
389
390 if (iwl_pcie_ctxt_info_alloc_dma(trans,
391 data,
392 len,
393 cur_payload_dram)) {
394 iwl_trans_pcie_free_pnvm_dram_regions(dram_regions,
395 trans->dev);
396 return -ENOMEM;
397 }
398
399 dram_regions->n_regions++;
400 cur_payload_dram++;
401 }
402
403 /* fill desc with the DRAM payloads addresses */
404 addresses = desc_dram->block;
405 for (i = 0; i < pnvm_data->n_chunks; i++) {
406 addresses->mem_descs[i] =
407 cpu_to_le64(dram_regions->drams[i].physical);
408 }
409
410 return 0;
411
412 }
413
iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans * trans,const struct iwl_pnvm_image * pnvm_payloads,const struct iwl_ucode_capabilities * capa)414 int iwl_trans_pcie_ctx_info_gen3_load_pnvm(struct iwl_trans *trans,
415 const struct iwl_pnvm_image *pnvm_payloads,
416 const struct iwl_ucode_capabilities *capa)
417 {
418 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
419 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
420 &trans_pcie->prph_scratch->ctrl_cfg;
421 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data;
422 int ret = 0;
423
424 /* only allocate the DRAM if not allocated yet */
425 if (trans->pnvm_loaded)
426 return 0;
427
428 if (WARN_ON(prph_sc_ctrl->pnvm_cfg.pnvm_size))
429 return -EBUSY;
430
431 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
432 return 0;
433
434 if (!pnvm_payloads->n_chunks) {
435 IWL_DEBUG_FW(trans, "no payloads\n");
436 return -EINVAL;
437 }
438
439 /* save payloads in several DRAM sections */
440 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) {
441 ret = iwl_pcie_load_payloads_segments(trans,
442 dram_regions,
443 pnvm_payloads);
444 if (!ret)
445 trans->pnvm_loaded = true;
446 } else {
447 /* save only in one DRAM section */
448 ret = iwl_pcie_load_payloads_continuously
449 (trans,
450 pnvm_payloads,
451 &dram_regions->drams[0]);
452 if (!ret) {
453 dram_regions->n_regions = 1;
454 trans->pnvm_loaded = true;
455 }
456 }
457
458 return ret;
459 }
460
461 static inline size_t
iwl_dram_regions_size(const struct iwl_dram_regions * dram_regions)462 iwl_dram_regions_size(const struct iwl_dram_regions *dram_regions)
463 {
464 size_t total_size = 0;
465 int i;
466
467 for (i = 0; i < dram_regions->n_regions; i++)
468 total_size += dram_regions->drams[i].size;
469
470 return total_size;
471 }
472
iwl_pcie_set_pnvm_segments(struct iwl_trans * trans)473 static void iwl_pcie_set_pnvm_segments(struct iwl_trans *trans)
474 {
475 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
476 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
477 &trans_pcie->prph_scratch->ctrl_cfg;
478 struct iwl_dram_regions *dram_regions = &trans_pcie->pnvm_data;
479
480 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
481 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical);
482 prph_sc_ctrl->pnvm_cfg.pnvm_size =
483 cpu_to_le32(iwl_dram_regions_size(dram_regions));
484 }
485
iwl_pcie_set_continuous_pnvm(struct iwl_trans * trans)486 static void iwl_pcie_set_continuous_pnvm(struct iwl_trans *trans)
487 {
488 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
489 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
490 &trans_pcie->prph_scratch->ctrl_cfg;
491
492 prph_sc_ctrl->pnvm_cfg.pnvm_base_addr =
493 cpu_to_le64(trans_pcie->pnvm_data.drams[0].physical);
494 prph_sc_ctrl->pnvm_cfg.pnvm_size =
495 cpu_to_le32(trans_pcie->pnvm_data.drams[0].size);
496 }
497
iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans * trans,const struct iwl_ucode_capabilities * capa)498 void iwl_trans_pcie_ctx_info_gen3_set_pnvm(struct iwl_trans *trans,
499 const struct iwl_ucode_capabilities *capa)
500 {
501 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
502 return;
503
504 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG))
505 iwl_pcie_set_pnvm_segments(trans);
506 else
507 iwl_pcie_set_continuous_pnvm(trans);
508 }
509
iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans * trans,const struct iwl_pnvm_image * payloads,const struct iwl_ucode_capabilities * capa)510 int iwl_trans_pcie_ctx_info_gen3_load_reduce_power(struct iwl_trans *trans,
511 const struct iwl_pnvm_image *payloads,
512 const struct iwl_ucode_capabilities *capa)
513 {
514 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
515 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
516 &trans_pcie->prph_scratch->ctrl_cfg;
517 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data;
518 int ret = 0;
519
520 /* only allocate the DRAM if not allocated yet */
521 if (trans->reduce_power_loaded)
522 return 0;
523
524 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
525 return 0;
526
527 if (WARN_ON(prph_sc_ctrl->reduce_power_cfg.size))
528 return -EBUSY;
529
530 if (!payloads->n_chunks) {
531 IWL_DEBUG_FW(trans, "no payloads\n");
532 return -EINVAL;
533 }
534
535 /* save payloads in several DRAM sections */
536 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG)) {
537 ret = iwl_pcie_load_payloads_segments(trans,
538 dram_regions,
539 payloads);
540 if (!ret)
541 trans->reduce_power_loaded = true;
542 } else {
543 /* save only in one DRAM section */
544 ret = iwl_pcie_load_payloads_continuously
545 (trans,
546 payloads,
547 &dram_regions->drams[0]);
548 if (!ret) {
549 dram_regions->n_regions = 1;
550 trans->reduce_power_loaded = true;
551 }
552 }
553
554 return ret;
555 }
556
iwl_pcie_set_reduce_power_segments(struct iwl_trans * trans)557 static void iwl_pcie_set_reduce_power_segments(struct iwl_trans *trans)
558 {
559 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
560 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
561 &trans_pcie->prph_scratch->ctrl_cfg;
562 struct iwl_dram_regions *dram_regions = &trans_pcie->reduced_tables_data;
563
564 prph_sc_ctrl->reduce_power_cfg.base_addr =
565 cpu_to_le64(dram_regions->prph_scratch_mem_desc.physical);
566 prph_sc_ctrl->reduce_power_cfg.size =
567 cpu_to_le32(iwl_dram_regions_size(dram_regions));
568 }
569
iwl_pcie_set_continuous_reduce_power(struct iwl_trans * trans)570 static void iwl_pcie_set_continuous_reduce_power(struct iwl_trans *trans)
571 {
572 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
573 struct iwl_prph_scratch_ctrl_cfg *prph_sc_ctrl =
574 &trans_pcie->prph_scratch->ctrl_cfg;
575
576 prph_sc_ctrl->reduce_power_cfg.base_addr =
577 cpu_to_le64(trans_pcie->reduced_tables_data.drams[0].physical);
578 prph_sc_ctrl->reduce_power_cfg.size =
579 cpu_to_le32(trans_pcie->reduced_tables_data.drams[0].size);
580 }
581
582 void
iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans * trans,const struct iwl_ucode_capabilities * capa)583 iwl_trans_pcie_ctx_info_gen3_set_reduce_power(struct iwl_trans *trans,
584 const struct iwl_ucode_capabilities *capa)
585 {
586 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
587 return;
588
589 if (fw_has_capa(capa, IWL_UCODE_TLV_CAPA_FRAGMENTED_PNVM_IMG))
590 iwl_pcie_set_reduce_power_segments(trans);
591 else
592 iwl_pcie_set_continuous_reduce_power(trans);
593 }
594
595