1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Common Performance counter support functions for PowerISA v2.07 processors.
4 *
5 * Copyright 2009 Paul Mackerras, IBM Corporation.
6 * Copyright 2013 Michael Ellerman, IBM Corporation.
7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
8 */
9 #include "isa207-common.h"
10
11 PMU_FORMAT_ATTR(event, "config:0-49");
12 PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
13 PMU_FORMAT_ATTR(mark, "config:8");
14 PMU_FORMAT_ATTR(combine, "config:11");
15 PMU_FORMAT_ATTR(unit, "config:12-15");
16 PMU_FORMAT_ATTR(pmc, "config:16-19");
17 PMU_FORMAT_ATTR(cache_sel, "config:20-23");
18 PMU_FORMAT_ATTR(sample_mode, "config:24-28");
19 PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
20 PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
21 PMU_FORMAT_ATTR(thresh_start, "config:36-39");
22 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
23
24 static struct attribute *isa207_pmu_format_attr[] = {
25 &format_attr_event.attr,
26 &format_attr_pmcxsel.attr,
27 &format_attr_mark.attr,
28 &format_attr_combine.attr,
29 &format_attr_unit.attr,
30 &format_attr_pmc.attr,
31 &format_attr_cache_sel.attr,
32 &format_attr_sample_mode.attr,
33 &format_attr_thresh_sel.attr,
34 &format_attr_thresh_stop.attr,
35 &format_attr_thresh_start.attr,
36 &format_attr_thresh_cmp.attr,
37 NULL,
38 };
39
40 const struct attribute_group isa207_pmu_format_group = {
41 .name = "format",
42 .attrs = isa207_pmu_format_attr,
43 };
44
event_is_fab_match(u64 event)45 static inline bool event_is_fab_match(u64 event)
46 {
47 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */
48 event &= 0xff0fe;
49
50 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */
51 return (event == 0x30056 || event == 0x4f052);
52 }
53
is_event_valid(u64 event)54 static bool is_event_valid(u64 event)
55 {
56 u64 valid_mask = EVENT_VALID_MASK;
57
58 if (cpu_has_feature(CPU_FTR_ARCH_31))
59 valid_mask = p10_EVENT_VALID_MASK;
60 else if (cpu_has_feature(CPU_FTR_ARCH_300))
61 valid_mask = p9_EVENT_VALID_MASK;
62
63 return !(event & ~valid_mask);
64 }
65
is_event_marked(u64 event)66 static inline bool is_event_marked(u64 event)
67 {
68 if (event & EVENT_IS_MARKED)
69 return true;
70
71 return false;
72 }
73
sdar_mod_val(u64 event)74 static unsigned long sdar_mod_val(u64 event)
75 {
76 if (cpu_has_feature(CPU_FTR_ARCH_31))
77 return p10_SDAR_MODE(event);
78
79 return p9_SDAR_MODE(event);
80 }
81
mmcra_sdar_mode(u64 event,unsigned long * mmcra)82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra)
83 {
84 /*
85 * MMCRA[SDAR_MODE] specifies how the SDAR should be updated in
86 * continuous sampling mode.
87 *
88 * Incase of Power8:
89 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continuous sampling
90 * mode and will be un-changed when setting MMCRA[63] (Marked events).
91 *
92 * Incase of Power9/power10:
93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'),
94 * or if group already have any marked events.
95 * For rest
96 * MMCRA[SDAR_MODE] will be set from event code.
97 * If sdar_mode from event is zero, default to 0b01. Hardware
98 * requires that we set a non-zero value.
99 */
100 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE))
102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES;
103 else if (sdar_mod_val(event))
104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT;
105 else
106 *mmcra |= MMCRA_SDAR_MODE_DCACHE;
107 } else
108 *mmcra |= MMCRA_SDAR_MODE_TLB;
109 }
110
p10_thresh_cmp_val(u64 value)111 static int p10_thresh_cmp_val(u64 value)
112 {
113 int exp = 0;
114 u64 result = value;
115
116 if (!value)
117 return value;
118
119 /*
120 * Incase of P10, thresh_cmp value is not part of raw event code
121 * and provided via attr.config1 parameter. To program threshold in MMCRA,
122 * take a 18 bit number N and shift right 2 places and increment
123 * the exponent E by 1 until the upper 10 bits of N are zero.
124 * Write E to the threshold exponent and write the lower 8 bits of N
125 * to the threshold mantissa.
126 * The max threshold that can be written is 261120.
127 */
128 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
129 if (value > 261120)
130 value = 261120;
131 while ((64 - __builtin_clzl(value)) > 8) {
132 exp++;
133 value >>= 2;
134 }
135
136 /*
137 * Note that it is invalid to write a mantissa with the
138 * upper 2 bits of mantissa being zero, unless the
139 * exponent is also zero.
140 */
141 if (!(value & 0xC0) && exp)
142 result = -1;
143 else
144 result = (exp << 8) | value;
145 }
146 return result;
147 }
148
thresh_cmp_val(u64 value)149 static u64 thresh_cmp_val(u64 value)
150 {
151 if (cpu_has_feature(CPU_FTR_ARCH_31))
152 value = p10_thresh_cmp_val(value);
153
154 /*
155 * Since location of threshold compare bits in MMCRA
156 * is different for p8, using different shift value.
157 */
158 if (cpu_has_feature(CPU_FTR_ARCH_300))
159 return value << p9_MMCRA_THR_CMP_SHIFT;
160 else
161 return value << MMCRA_THR_CMP_SHIFT;
162 }
163
combine_from_event(u64 event)164 static unsigned long combine_from_event(u64 event)
165 {
166 if (cpu_has_feature(CPU_FTR_ARCH_300))
167 return p9_EVENT_COMBINE(event);
168
169 return EVENT_COMBINE(event);
170 }
171
combine_shift(unsigned long pmc)172 static unsigned long combine_shift(unsigned long pmc)
173 {
174 if (cpu_has_feature(CPU_FTR_ARCH_300))
175 return p9_MMCR1_COMBINE_SHIFT(pmc);
176
177 return MMCR1_COMBINE_SHIFT(pmc);
178 }
179
event_is_threshold(u64 event)180 static inline bool event_is_threshold(u64 event)
181 {
182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
183 }
184
is_thresh_cmp_valid(u64 event)185 static bool is_thresh_cmp_valid(u64 event)
186 {
187 unsigned int cmp, exp;
188
189 if (cpu_has_feature(CPU_FTR_ARCH_31))
190 return p10_thresh_cmp_val(event) >= 0;
191
192 /*
193 * Check the mantissa upper two bits are not zero, unless the
194 * exponent is also zero. See the THRESH_CMP_MANTISSA doc.
195 */
196
197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK;
198 exp = cmp >> 7;
199
200 if (exp && (cmp & 0x60) == 0)
201 return false;
202
203 return true;
204 }
205
dc_ic_rld_quad_l1_sel(u64 event)206 static unsigned int dc_ic_rld_quad_l1_sel(u64 event)
207 {
208 unsigned int cache;
209
210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK;
211 return cache;
212 }
213
isa207_find_source(u64 idx,u32 sub_idx)214 static inline u64 isa207_find_source(u64 idx, u32 sub_idx)
215 {
216 u64 ret = PERF_MEM_NA;
217
218 switch(idx) {
219 case 0:
220 /* Nothing to do */
221 break;
222 case 1:
223 ret = PH(LVL, L1) | LEVEL(L1) | P(SNOOP, HIT);
224 break;
225 case 2:
226 ret = PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
227 break;
228 case 3:
229 ret = PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
230 break;
231 case 4:
232 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
233 ret = P(SNOOP, HIT);
234
235 if (sub_idx == 1)
236 ret |= PH(LVL, LOC_RAM) | LEVEL(RAM);
237 else if (sub_idx == 2 || sub_idx == 3)
238 ret |= P(LVL, HIT) | LEVEL(PMEM);
239 else if (sub_idx == 4)
240 ret |= PH(LVL, REM_RAM1) | REM | LEVEL(RAM) | P(HOPS, 2);
241 else if (sub_idx == 5 || sub_idx == 7)
242 ret |= P(LVL, HIT) | LEVEL(PMEM) | REM;
243 else if (sub_idx == 6)
244 ret |= PH(LVL, REM_RAM2) | REM | LEVEL(RAM) | P(HOPS, 3);
245 } else {
246 if (sub_idx <= 1)
247 ret = PH(LVL, LOC_RAM);
248 else if (sub_idx > 1 && sub_idx <= 2)
249 ret = PH(LVL, REM_RAM1);
250 else
251 ret = PH(LVL, REM_RAM2);
252 ret |= P(SNOOP, HIT);
253 }
254 break;
255 case 5:
256 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
257 ret = REM | P(HOPS, 0);
258
259 if (sub_idx == 0 || sub_idx == 4)
260 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT);
261 else if (sub_idx == 1 || sub_idx == 5)
262 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM);
263 else if (sub_idx == 2 || sub_idx == 6)
264 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
265 else if (sub_idx == 3 || sub_idx == 7)
266 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
267 } else {
268 if (sub_idx == 0)
269 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0);
270 else if (sub_idx == 1)
271 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0);
272 else if (sub_idx == 2 || sub_idx == 4)
273 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0);
274 else if (sub_idx == 3 || sub_idx == 5)
275 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0);
276 }
277 break;
278 case 6:
279 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
280 if (sub_idx == 0)
281 ret = PH(LVL, REM_CCE1) | LEVEL(ANY_CACHE) | REM |
282 P(SNOOP, HIT) | P(HOPS, 2);
283 else if (sub_idx == 1)
284 ret = PH(LVL, REM_CCE1) | LEVEL(ANY_CACHE) | REM |
285 P(SNOOP, HITM) | P(HOPS, 2);
286 else if (sub_idx == 2)
287 ret = PH(LVL, REM_CCE2) | LEVEL(ANY_CACHE) | REM |
288 P(SNOOP, HIT) | P(HOPS, 3);
289 else if (sub_idx == 3)
290 ret = PH(LVL, REM_CCE2) | LEVEL(ANY_CACHE) | REM |
291 P(SNOOP, HITM) | P(HOPS, 3);
292 } else {
293 ret = PH(LVL, REM_CCE2);
294 if (sub_idx == 0 || sub_idx == 2)
295 ret |= P(SNOOP, HIT);
296 else if (sub_idx == 1 || sub_idx == 3)
297 ret |= P(SNOOP, HITM);
298 }
299 break;
300 case 7:
301 ret = PM(LVL, L1);
302 break;
303 }
304
305 return ret;
306 }
307
isa207_get_mem_data_src(union perf_mem_data_src * dsrc,u32 flags,struct pt_regs * regs)308 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
309 struct pt_regs *regs)
310 {
311 u64 idx;
312 u32 sub_idx;
313 u64 sier;
314 u64 val;
315
316 /* Skip if no SIER support */
317 if (!(flags & PPMU_HAS_SIER)) {
318 dsrc->val = 0;
319 return;
320 }
321
322 /*
323 * Use regs-dar for SPRN_SIER which is saved
324 * during perf_read_regs at the beginning
325 * of the PMU interrupt handler to avoid multiple
326 * reads of SPRN_SIER
327 */
328 sier = regs->dar;
329 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
330 if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31))) {
331 dsrc->val = 0;
332 return;
333 }
334
335 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT;
336 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT;
337
338 dsrc->val = isa207_find_source(idx, sub_idx);
339 if (val == 7) {
340 u64 mmcra;
341 u32 op_type;
342
343 /*
344 * Type 0b111 denotes either larx or stcx instruction. Use the
345 * MMCRA sampling bits [57:59] along with the type value
346 * to determine the exact instruction type. If the sampling
347 * criteria is neither load or store, set the type as default
348 * to NA.
349 *
350 * Use regs->dsisr for MMCRA which is saved during perf_read_regs
351 * at the beginning of the PMU interrupt handler to avoid
352 * multiple reads of SPRN_MMCRA
353 */
354 mmcra = regs->dsisr;
355
356 op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK;
357 switch (op_type) {
358 case 5:
359 dsrc->val |= P(OP, LOAD);
360 break;
361 case 7:
362 dsrc->val |= P(OP, STORE);
363 break;
364 default:
365 dsrc->val |= P(OP, NA);
366 break;
367 }
368 } else {
369 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);
370 }
371 }
372
isa207_get_mem_weight(u64 * weight,u64 type)373 void isa207_get_mem_weight(u64 *weight, u64 type)
374 {
375 union perf_sample_weight *weight_fields;
376 u64 weight_lat;
377 u64 mmcra = mfspr(SPRN_MMCRA);
378 u64 exp = MMCRA_THR_CTR_EXP(mmcra);
379 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra);
380 u64 sier = mfspr(SPRN_SIER);
381 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT;
382
383 if (cpu_has_feature(CPU_FTR_ARCH_31))
384 mantissa = P10_MMCRA_THR_CTR_MANT(mmcra);
385
386 if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31)))
387 weight_lat = 0;
388 else
389 weight_lat = mantissa << (2 * exp);
390
391 /*
392 * Use 64 bit weight field (full) if sample type is
393 * WEIGHT.
394 *
395 * if sample type is WEIGHT_STRUCT:
396 * - store memory latency in the lower 32 bits.
397 * - For ISA v3.1, use remaining two 16 bit fields of
398 * perf_sample_weight to store cycle counter values
399 * from sier2.
400 */
401 weight_fields = (union perf_sample_weight *)weight;
402 if (type & PERF_SAMPLE_WEIGHT)
403 weight_fields->full = weight_lat;
404 else {
405 weight_fields->var1_dw = (u32)weight_lat;
406 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
407 weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2));
408 weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2));
409 }
410 }
411 }
412
isa207_get_constraint(u64 event,unsigned long * maskp,unsigned long * valp,u64 event_config1)413 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1)
414 {
415 unsigned int unit, pmc, cache, ebb;
416 unsigned long mask, value;
417
418 mask = value = 0;
419
420 if (!is_event_valid(event))
421 return -1;
422
423 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
424 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
425 if (cpu_has_feature(CPU_FTR_ARCH_31))
426 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
427 p10_EVENT_CACHE_SEL_MASK;
428 else
429 cache = (event >> EVENT_CACHE_SEL_SHIFT) &
430 EVENT_CACHE_SEL_MASK;
431 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK;
432
433 if (pmc) {
434 u64 base_event;
435
436 if (pmc > 6)
437 return -1;
438
439 /* Ignore Linux defined bits when checking event below */
440 base_event = event & ~EVENT_LINUX_MASK;
441
442 if (pmc >= 5 && base_event != 0x500fa &&
443 base_event != 0x600f4)
444 return -1;
445
446 mask |= CNST_PMC_MASK(pmc);
447 value |= CNST_PMC_VAL(pmc);
448
449 /*
450 * PMC5 and PMC6 are used to count cycles and instructions and
451 * they do not support most of the constraint bits. Add a check
452 * to exclude PMC5/6 from most of the constraints except for
453 * EBB/BHRB.
454 */
455 if (pmc >= 5)
456 goto ebb_bhrb;
457 }
458
459 if (pmc <= 4) {
460 /*
461 * Add to number of counters in use. Note this includes events with
462 * a PMC of 0 - they still need a PMC, it's just assigned later.
463 * Don't count events on PMC 5 & 6, there is only one valid event
464 * on each of those counters, and they are handled above.
465 */
466 mask |= CNST_NC_MASK;
467 value |= CNST_NC_VAL;
468 }
469
470 if (unit >= 6 && unit <= 9) {
471 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
472 if (unit == 6) {
473 mask |= CNST_L2L3_GROUP_MASK;
474 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT);
475 }
476 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
477 mask |= CNST_CACHE_GROUP_MASK;
478 value |= CNST_CACHE_GROUP_VAL(event & 0xff);
479
480 mask |= CNST_CACHE_PMC4_MASK;
481 if (pmc == 4)
482 value |= CNST_CACHE_PMC4_VAL;
483 } else if (cache & 0x7) {
484 /*
485 * L2/L3 events contain a cache selector field, which is
486 * supposed to be programmed into MMCRC. However MMCRC is only
487 * HV writable, and there is no API for guest kernels to modify
488 * it. The solution is for the hypervisor to initialise the
489 * field to zeroes, and for us to only ever allow events that
490 * have a cache selector of zero. The bank selector (bit 3) is
491 * irrelevant, as long as the rest of the value is 0.
492 */
493 return -1;
494 }
495
496 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) {
497 mask |= CNST_L1_QUAL_MASK;
498 value |= CNST_L1_QUAL_VAL(cache);
499 }
500
501 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
502 mask |= CNST_RADIX_SCOPE_GROUP_MASK;
503 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT);
504 }
505
506 if (is_event_marked(event)) {
507 mask |= CNST_SAMPLE_MASK;
508 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT);
509 }
510
511 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
512 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) {
513 mask |= CNST_THRESH_CTL_SEL_MASK;
514 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT);
515 mask |= p10_CNST_THRESH_CMP_MASK;
516 value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1));
517 } else if (event_is_threshold(event))
518 return -1;
519 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
520 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) {
521 mask |= CNST_THRESH_MASK;
522 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
523 } else if (event_is_threshold(event))
524 return -1;
525 } else {
526 /*
527 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
528 * the threshold control bits are used for the match value.
529 */
530 if (event_is_fab_match(event)) {
531 mask |= CNST_FAB_MATCH_MASK;
532 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT);
533 } else {
534 if (!is_thresh_cmp_valid(event))
535 return -1;
536
537 mask |= CNST_THRESH_MASK;
538 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
539 }
540 }
541
542 ebb_bhrb:
543 if (!pmc && ebb)
544 /* EBB events must specify the PMC */
545 return -1;
546
547 if (event & EVENT_WANTS_BHRB) {
548 if (!ebb)
549 /* Only EBB events can request BHRB */
550 return -1;
551
552 mask |= CNST_IFM_MASK;
553 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT);
554 }
555
556 /*
557 * All events must agree on EBB, either all request it or none.
558 * EBB events are pinned & exclusive, so this should never actually
559 * hit, but we leave it as a fallback in case.
560 */
561 mask |= CNST_EBB_MASK;
562 value |= CNST_EBB_VAL(ebb);
563
564 *maskp = mask;
565 *valp = value;
566
567 return 0;
568 }
569
isa207_compute_mmcr(u64 event[],int n_ev,unsigned int hwc[],struct mmcr_regs * mmcr,struct perf_event * pevents[],u32 flags)570 int isa207_compute_mmcr(u64 event[], int n_ev,
571 unsigned int hwc[], struct mmcr_regs *mmcr,
572 struct perf_event *pevents[], u32 flags)
573 {
574 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val;
575 unsigned long mmcr3;
576 unsigned int pmc, pmc_inuse;
577 int i;
578
579 pmc_inuse = 0;
580
581 /* First pass to count resource use */
582 for (i = 0; i < n_ev; ++i) {
583 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
584 if (pmc)
585 pmc_inuse |= 1 << pmc;
586 }
587
588 mmcra = mmcr1 = mmcr2 = mmcr3 = 0;
589
590 /*
591 * Disable bhrb unless explicitly requested
592 * by setting MMCRA (BHRBRD) bit.
593 */
594 if (cpu_has_feature(CPU_FTR_ARCH_31))
595 mmcra |= MMCRA_BHRB_DISABLE;
596
597 /* Second pass: assign PMCs, set all MMCR1 fields */
598 for (i = 0; i < n_ev; ++i) {
599 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK;
600 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK;
601 combine = combine_from_event(event[i]);
602 psel = event[i] & EVENT_PSEL_MASK;
603
604 if (!pmc) {
605 for (pmc = 1; pmc <= 4; ++pmc) {
606 if (!(pmc_inuse & (1 << pmc)))
607 break;
608 }
609
610 pmc_inuse |= 1 << pmc;
611 }
612
613 if (pmc <= 4) {
614 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc);
615 mmcr1 |= combine << combine_shift(pmc);
616 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc);
617 }
618
619 /* In continuous sampling mode, update SDAR on TLB miss */
620 mmcra_sdar_mode(event[i], &mmcra);
621
622 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
623 cache = dc_ic_rld_quad_l1_sel(event[i]);
624 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
625 } else {
626 if (event[i] & EVENT_IS_L1) {
627 cache = dc_ic_rld_quad_l1_sel(event[i]);
628 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT;
629 }
630 }
631
632 /* Set RADIX_SCOPE_QUAL bit */
633 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
634 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) &
635 p10_EVENT_RADIX_SCOPE_QUAL_MASK;
636 mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT;
637 }
638
639 if (is_event_marked(event[i])) {
640 mmcra |= MMCRA_SAMPLE_ENABLE;
641
642 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
643 if (val) {
644 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT;
645 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT;
646 }
647 }
648
649 /*
650 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC,
651 * the threshold bits are used for the match value.
652 */
653 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) {
654 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) &
655 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT;
656 } else {
657 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
658 mmcra |= val << MMCRA_THR_CTL_SHIFT;
659 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK;
660 mmcra |= val << MMCRA_THR_SEL_SHIFT;
661 if (!cpu_has_feature(CPU_FTR_ARCH_31)) {
662 val = (event[i] >> EVENT_THR_CMP_SHIFT) &
663 EVENT_THR_CMP_MASK;
664 mmcra |= thresh_cmp_val(val);
665 } else if (flags & PPMU_HAS_ATTR_CONFIG1) {
666 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &
667 p10_EVENT_THR_CMP_MASK;
668 mmcra |= thresh_cmp_val(val);
669 }
670 }
671
672 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) {
673 val = (event[i] >> p10_L2L3_EVENT_SHIFT) &
674 p10_EVENT_L2L3_SEL_MASK;
675 mmcr2 |= val << p10_L2L3_SEL_SHIFT;
676 }
677
678 if (event[i] & EVENT_WANTS_BHRB) {
679 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK;
680 mmcra |= val << MMCRA_IFM_SHIFT;
681 }
682
683 /* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */
684 if (cpu_has_feature(CPU_FTR_ARCH_31) &&
685 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB)))
686 mmcra &= ~MMCRA_BHRB_DISABLE;
687
688 if (pevents[i]->attr.exclude_user)
689 mmcr2 |= MMCR2_FCP(pmc);
690
691 if (pevents[i]->attr.exclude_hv)
692 mmcr2 |= MMCR2_FCH(pmc);
693
694 if (pevents[i]->attr.exclude_kernel) {
695 if (cpu_has_feature(CPU_FTR_HVMODE))
696 mmcr2 |= MMCR2_FCH(pmc);
697 else
698 mmcr2 |= MMCR2_FCS(pmc);
699 }
700
701 if (pevents[i]->attr.exclude_idle)
702 mmcr2 |= MMCR2_FCWAIT(pmc);
703
704 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
705 if (pmc <= 4) {
706 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) &
707 p10_EVENT_MMCR3_MASK;
708 mmcr3 |= val << MMCR3_SHIFT(pmc);
709 }
710 }
711
712 hwc[i] = pmc - 1;
713 }
714
715 /* Return MMCRx values */
716 mmcr->mmcr0 = 0;
717
718 /* pmc_inuse is 1-based */
719 if (pmc_inuse & 2)
720 mmcr->mmcr0 = MMCR0_PMC1CE;
721
722 if (pmc_inuse & 0x7c)
723 mmcr->mmcr0 |= MMCR0_PMCjCE;
724
725 /* If we're not using PMC 5 or 6, freeze them */
726 if (!(pmc_inuse & 0x60))
727 mmcr->mmcr0 |= MMCR0_FC56;
728
729 /*
730 * Set mmcr0 (PMCCEXT) for p10 which
731 * will restrict access to group B registers
732 * when MMCR0 PMCC=0b00.
733 */
734 if (cpu_has_feature(CPU_FTR_ARCH_31))
735 mmcr->mmcr0 |= MMCR0_PMCCEXT;
736
737 mmcr->mmcr1 = mmcr1;
738 mmcr->mmcra = mmcra;
739 mmcr->mmcr2 = mmcr2;
740 mmcr->mmcr3 = mmcr3;
741
742 return 0;
743 }
744
isa207_disable_pmc(unsigned int pmc,struct mmcr_regs * mmcr)745 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
746 {
747 if (pmc <= 3)
748 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));
749 }
750
find_alternative(u64 event,const unsigned int ev_alt[][MAX_ALT],int size)751 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size)
752 {
753 int i, j;
754
755 for (i = 0; i < size; ++i) {
756 if (event < ev_alt[i][0])
757 break;
758
759 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j)
760 if (event == ev_alt[i][j])
761 return i;
762 }
763
764 return -1;
765 }
766
isa207_get_alternatives(u64 event,u64 alt[],int size,unsigned int flags,const unsigned int ev_alt[][MAX_ALT])767 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
768 const unsigned int ev_alt[][MAX_ALT])
769 {
770 int i, j, num_alt = 0;
771 u64 alt_event;
772
773 alt[num_alt++] = event;
774 i = find_alternative(event, ev_alt, size);
775 if (i >= 0) {
776 /* Filter out the original event, it's already in alt[0] */
777 for (j = 0; j < MAX_ALT; ++j) {
778 alt_event = ev_alt[i][j];
779 if (alt_event && alt_event != event)
780 alt[num_alt++] = alt_event;
781 }
782 }
783
784 if (flags & PPMU_ONLY_COUNT_RUN) {
785 /*
786 * We're only counting in RUN state, so PM_CYC is equivalent to
787 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL.
788 */
789 j = num_alt;
790 for (i = 0; i < num_alt; ++i) {
791 switch (alt[i]) {
792 case 0x1e: /* PMC_CYC */
793 alt[j++] = 0x600f4; /* PM_RUN_CYC */
794 break;
795 case 0x600f4:
796 alt[j++] = 0x1e;
797 break;
798 case 0x2: /* PM_INST_CMPL */
799 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
800 break;
801 case 0x500fa:
802 alt[j++] = 0x2;
803 break;
804 }
805 }
806 num_alt = j;
807 }
808
809 return num_alt;
810 }
811
isa3XX_check_attr_config(struct perf_event * ev)812 int isa3XX_check_attr_config(struct perf_event *ev)
813 {
814 u64 val, sample_mode;
815 u64 event = ev->attr.config;
816
817 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
818 sample_mode = val & 0x3;
819
820 /*
821 * MMCRA[61:62] is Random Sampling Mode (SM).
822 * value of 0b11 is reserved.
823 */
824 if (sample_mode == 0x3)
825 return -EINVAL;
826
827 /*
828 * Check for all reserved value
829 * Source: Performance Monitoring Unit User Guide
830 */
831 switch (val) {
832 case 0x5:
833 case 0x9:
834 case 0xD:
835 case 0x19:
836 case 0x1D:
837 case 0x1A:
838 case 0x1E:
839 return -EINVAL;
840 }
841
842 /*
843 * MMCRA[48:51]/[52:55]) Threshold Start/Stop
844 * Events Selection.
845 * 0b11110000/0b00001111 is reserved.
846 */
847 val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK;
848 if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF))
849 return -EINVAL;
850
851 return 0;
852 }
853