1 /*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18
19 #define PA_BASE 0
20 #define PB_BASE 32
21 #define PC_BASE 64
22 #define PD_BASE 96
23 #define PE_BASE 128
24 #define PF_BASE 160
25 #define PG_BASE 192
26 #define PH_BASE 224
27 #define PI_BASE 256
28 #define PJ_BASE 288
29 #define PK_BASE 320
30 #define PL_BASE 352
31 #define PM_BASE 384
32 #define PN_BASE 416
33
34 /* maximum number of banks per controller (PA -> PK) */
35 #define SUNXI_PINCTRL_MAX_BANKS 11
36
37 #define SUNXI_PINCTRL_PIN(bank, pin) \
38 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
39
40 #define SUNXI_PIN_NAME_MAX_LEN 5
41
42 #define BANK_MEM_SIZE 0x24
43 #define MUX_REGS_OFFSET 0x0
44 #define MUX_FIELD_WIDTH 4
45 #define DATA_REGS_OFFSET 0x10
46 #define DATA_FIELD_WIDTH 1
47 #define DLEVEL_REGS_OFFSET 0x14
48 #define DLEVEL_FIELD_WIDTH 2
49 #define PULL_REGS_OFFSET 0x1c
50 #define PULL_FIELD_WIDTH 2
51
52 #define D1_BANK_MEM_SIZE 0x30
53 #define D1_DLEVEL_FIELD_WIDTH 4
54 #define D1_PULL_REGS_OFFSET 0x24
55
56 #define PINS_PER_BANK 32
57
58 #define IRQ_PER_BANK 32
59
60 #define IRQ_CFG_REG 0x200
61 #define IRQ_CFG_IRQ_PER_REG 8
62 #define IRQ_CFG_IRQ_BITS 4
63 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
64 #define IRQ_CTRL_REG 0x210
65 #define IRQ_CTRL_IRQ_PER_REG 32
66 #define IRQ_CTRL_IRQ_BITS 1
67 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
68 #define IRQ_STATUS_REG 0x214
69 #define IRQ_STATUS_IRQ_PER_REG 32
70 #define IRQ_STATUS_IRQ_BITS 1
71 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
72
73 #define IRQ_DEBOUNCE_REG 0x218
74
75 #define IRQ_MEM_SIZE 0x20
76
77 #define IRQ_EDGE_RISING 0x00
78 #define IRQ_EDGE_FALLING 0x01
79 #define IRQ_LEVEL_HIGH 0x02
80 #define IRQ_LEVEL_LOW 0x03
81 #define IRQ_EDGE_BOTH 0x04
82
83 #define GRP_CFG_REG 0x300
84
85 #define IO_BIAS_MASK GENMASK(3, 0)
86
87 #define SUN4I_FUNC_INPUT 0
88 #define SUN4I_FUNC_IRQ 6
89
90 #define SUNXI_PINCTRL_VARIANT_MASK GENMASK(7, 0)
91 #define SUNXI_PINCTRL_NEW_REG_LAYOUT BIT(8)
92 #define SUNXI_PINCTRL_PORTF_SWITCH BIT(9)
93 #define SUNXI_PINCTRL_ELEVEN_BANKS BIT(10)
94
95 #define PIO_POW_MOD_SEL_REG 0x340
96 #define PIO_11B_POW_MOD_SEL_REG 0x380
97 #define PIO_POW_MOD_CTL_OFS 0x004
98
99 #define PIO_BANK_K_OFFSET 0x500
100
101 enum sunxi_desc_bias_voltage {
102 BIAS_VOLTAGE_NONE,
103 /*
104 * Bias voltage configuration is done through
105 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
106 */
107 BIAS_VOLTAGE_GRP_CONFIG,
108 /*
109 * Bias voltage is set through PIO_POW_MOD_SEL_REG
110 * register, as seen on H6 SoC, for example.
111 */
112 BIAS_VOLTAGE_PIO_POW_MODE_SEL,
113 /*
114 * Bias voltage is set through PIO_POW_MOD_SEL_REG
115 * and PIO_POW_MOD_CTL_REG register, as seen on
116 * A100 and D1 SoC, for example.
117 */
118 BIAS_VOLTAGE_PIO_POW_MODE_CTL,
119 };
120
121 struct sunxi_desc_function {
122 unsigned long variant;
123 const char *name;
124 u8 muxval;
125 u8 irqbank;
126 u8 irqnum;
127 };
128
129 struct sunxi_desc_pin {
130 struct pinctrl_pin_desc pin;
131 unsigned long variant;
132 struct sunxi_desc_function *functions;
133 };
134
135 struct sunxi_pinctrl_desc {
136 const struct sunxi_desc_pin *pins;
137 int npins;
138 unsigned pin_base;
139 unsigned irq_banks;
140 const unsigned int *irq_bank_map;
141 bool irq_read_needs_mux;
142 bool disable_strict_mode;
143 enum sunxi_desc_bias_voltage io_bias_cfg_variant;
144 };
145
146 struct sunxi_pinctrl_function {
147 const char *name;
148 const char **groups;
149 unsigned ngroups;
150 };
151
152 struct sunxi_pinctrl_group {
153 const char *name;
154 unsigned pin;
155 };
156
157 struct sunxi_pinctrl_regulator {
158 struct regulator *regulator;
159 refcount_t refcount;
160 };
161
162 struct sunxi_pinctrl {
163 void __iomem *membase;
164 struct gpio_chip *chip;
165 const struct sunxi_pinctrl_desc *desc;
166 struct device *dev;
167 struct sunxi_pinctrl_regulator regulators[11];
168 struct irq_domain *domain;
169 struct sunxi_pinctrl_function *functions;
170 unsigned nfunctions;
171 struct sunxi_pinctrl_group *groups;
172 unsigned ngroups;
173 int *irq;
174 unsigned *irq_array;
175 raw_spinlock_t lock;
176 struct pinctrl_dev *pctl_dev;
177 unsigned long variant;
178 u32 bank_mem_size;
179 u32 pull_regs_offset;
180 u32 dlevel_field_width;
181 u32 pow_mod_sel_offset;
182 };
183
184 #define SUNXI_PIN(_pin, ...) \
185 { \
186 .pin = _pin, \
187 .functions = (struct sunxi_desc_function[]){ \
188 __VA_ARGS__, { } }, \
189 }
190
191 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
192 { \
193 .pin = _pin, \
194 .variant = _variant, \
195 .functions = (struct sunxi_desc_function[]){ \
196 __VA_ARGS__, { } }, \
197 }
198
199 #define SUNXI_FUNCTION(_val, _name) \
200 { \
201 .name = _name, \
202 .muxval = _val, \
203 }
204
205 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
206 { \
207 .name = _name, \
208 .muxval = _val, \
209 .variant = _variant, \
210 }
211
212 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
213 { \
214 .name = "irq", \
215 .muxval = _val, \
216 .irqnum = _irq, \
217 }
218
219 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
220 { \
221 .name = "irq", \
222 .muxval = _val, \
223 .irqbank = _bank, \
224 .irqnum = _irq, \
225 }
226
sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc * desc,u8 bank)227 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
228 {
229 if (!desc->irq_bank_map)
230 return bank;
231 else
232 return desc->irq_bank_map[bank];
233 }
234
sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)235 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
236 u16 irq)
237 {
238 u8 bank = irq / IRQ_PER_BANK;
239 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
240
241 return IRQ_CFG_REG +
242 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
243 }
244
sunxi_irq_cfg_offset(u16 irq)245 static inline u32 sunxi_irq_cfg_offset(u16 irq)
246 {
247 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
248 return irq_num * IRQ_CFG_IRQ_BITS;
249 }
250
sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)251 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
252 {
253 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
254 }
255
sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)256 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
257 u16 irq)
258 {
259 u8 bank = irq / IRQ_PER_BANK;
260
261 return sunxi_irq_ctrl_reg_from_bank(desc, bank);
262 }
263
sunxi_irq_ctrl_offset(u16 irq)264 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
265 {
266 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
267 return irq_num * IRQ_CTRL_IRQ_BITS;
268 }
269
sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)270 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
271 {
272 return IRQ_DEBOUNCE_REG +
273 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
274 }
275
sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)276 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
277 {
278 return IRQ_STATUS_REG +
279 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
280 }
281
sunxi_irq_status_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)282 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
283 u16 irq)
284 {
285 u8 bank = irq / IRQ_PER_BANK;
286
287 return sunxi_irq_status_reg_from_bank(desc, bank);
288 }
289
sunxi_irq_status_offset(u16 irq)290 static inline u32 sunxi_irq_status_offset(u16 irq)
291 {
292 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
293 return irq_num * IRQ_STATUS_IRQ_BITS;
294 }
295
sunxi_grp_config_reg(u16 pin)296 static inline u32 sunxi_grp_config_reg(u16 pin)
297 {
298 u8 bank = pin / PINS_PER_BANK;
299
300 return GRP_CFG_REG + bank * 0x4;
301 }
302
303 int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
304 const struct sunxi_pinctrl_desc *desc,
305 unsigned long flags);
306
307 #define sunxi_pinctrl_init(_dev, _desc) \
308 sunxi_pinctrl_init_with_flags(_dev, _desc, 0)
309
310 int sunxi_pinctrl_dt_table_init(struct platform_device *pdev,
311 const u8 *pins_per_bank,
312 const u8 *irq_bank_muxes,
313 struct sunxi_pinctrl_desc *desc,
314 unsigned long flags);
315
316 #endif /* __PINCTRL_SUNXI_H */
317