1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _LINUX_IRQ_H 3 #define _LINUX_IRQ_H 4 5 /* 6 * Please do not include this file in generic code. There is currently 7 * no requirement for any architecture to implement anything held 8 * within this file. 9 * 10 * Thanks. --rmk 11 */ 12 13 #include <linux/cache.h> 14 #include <linux/spinlock.h> 15 #include <linux/cpumask.h> 16 #include <linux/irqhandler.h> 17 #include <linux/irqreturn.h> 18 #include <linux/irqnr.h> 19 #include <linux/topology.h> 20 #include <linux/io.h> 21 #include <linux/slab.h> 22 23 #include <asm/irq.h> 24 #include <asm/ptrace.h> 25 #include <asm/irq_regs.h> 26 27 struct seq_file; 28 struct module; 29 struct msi_msg; 30 struct irq_affinity_desc; 31 enum irqchip_irq_state; 32 33 /* 34 * IRQ line status. 35 * 36 * Bits 0-7 are the same as the IRQF_* bits in linux/interrupt.h 37 * 38 * Note that the first 6 definitions are shadowed by C preprocessor definitions 39 * in include/dt-bindings/interrupt-controller/irq.h. This is not an issue, as 40 * the actual values must be the same, due to being part of the stable DT ABI. 41 * 42 * IRQ_TYPE_NONE - default, unspecified type 43 * IRQ_TYPE_EDGE_RISING - rising edge triggered 44 * IRQ_TYPE_EDGE_FALLING - falling edge triggered 45 * IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered 46 * IRQ_TYPE_LEVEL_HIGH - high level triggered 47 * IRQ_TYPE_LEVEL_LOW - low level triggered 48 * IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits 49 * IRQ_TYPE_SENSE_MASK - Mask for all the above bits 50 * IRQ_TYPE_DEFAULT - For use by some PICs to ask irq_set_type 51 * to setup the HW to a sane default (used 52 * by irqdomain map() callbacks to synchronize 53 * the HW state and SW flags for a newly 54 * allocated descriptor). 55 * 56 * IRQ_TYPE_PROBE - Special flag for probing in progress 57 * 58 * Bits which can be modified via irq_set/clear/modify_status_flags() 59 * IRQ_LEVEL - Interrupt is level type. Will be also 60 * updated in the code when the above trigger 61 * bits are modified via irq_set_irq_type() 62 * IRQ_PER_CPU - Mark an interrupt PER_CPU. Will protect 63 * it from affinity setting 64 * IRQ_NOPROBE - Interrupt cannot be probed by autoprobing 65 * IRQ_NOREQUEST - Interrupt cannot be requested via 66 * request_irq() 67 * IRQ_NOTHREAD - Interrupt cannot be threaded 68 * IRQ_NOAUTOEN - Interrupt is not automatically enabled in 69 * request/setup_irq() 70 * IRQ_NO_BALANCING - Interrupt cannot be balanced (affinity set) 71 * IRQ_NESTED_THREAD - Interrupt nests into another thread 72 * IRQ_PER_CPU_DEVID - Dev_id is a per-cpu variable 73 * IRQ_IS_POLLED - Always polled by another interrupt. Exclude 74 * it from the spurious interrupt detection 75 * mechanism and from core side polling. 76 * IRQ_DISABLE_UNLAZY - Disable lazy irq disable 77 * IRQ_HIDDEN - Don't show up in /proc/interrupts 78 * IRQ_NO_DEBUG - Exclude from note_interrupt() debugging 79 */ 80 enum { 81 IRQ_TYPE_NONE = 0x00000000, 82 IRQ_TYPE_EDGE_RISING = 0x00000001, 83 IRQ_TYPE_EDGE_FALLING = 0x00000002, 84 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING), 85 IRQ_TYPE_LEVEL_HIGH = 0x00000004, 86 IRQ_TYPE_LEVEL_LOW = 0x00000008, 87 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH), 88 IRQ_TYPE_SENSE_MASK = 0x0000000f, 89 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK, 90 91 IRQ_TYPE_PROBE = 0x00000010, 92 93 IRQ_LEVEL = (1 << 8), 94 IRQ_PER_CPU = (1 << 9), 95 IRQ_NOPROBE = (1 << 10), 96 IRQ_NOREQUEST = (1 << 11), 97 IRQ_NOAUTOEN = (1 << 12), 98 IRQ_NO_BALANCING = (1 << 13), 99 IRQ_NESTED_THREAD = (1 << 15), 100 IRQ_NOTHREAD = (1 << 16), 101 IRQ_PER_CPU_DEVID = (1 << 17), 102 IRQ_IS_POLLED = (1 << 18), 103 IRQ_DISABLE_UNLAZY = (1 << 19), 104 IRQ_HIDDEN = (1 << 20), 105 IRQ_NO_DEBUG = (1 << 21), 106 }; 107 108 #define IRQF_MODIFY_MASK \ 109 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \ 110 IRQ_NOAUTOEN | IRQ_LEVEL | IRQ_NO_BALANCING | \ 111 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \ 112 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY | IRQ_HIDDEN) 113 114 #define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING) 115 116 /* 117 * Return value for chip->irq_set_affinity() 118 * 119 * IRQ_SET_MASK_OK - OK, core updates irq_common_data.affinity 120 * IRQ_SET_MASK_NOCOPY - OK, chip did update irq_common_data.affinity 121 * IRQ_SET_MASK_OK_DONE - Same as IRQ_SET_MASK_OK for core. Special code to 122 * support stacked irqchips, which indicates skipping 123 * all descendant irqchips. 124 */ 125 enum { 126 IRQ_SET_MASK_OK = 0, 127 IRQ_SET_MASK_OK_NOCOPY, 128 IRQ_SET_MASK_OK_DONE, 129 }; 130 131 struct msi_desc; 132 struct irq_domain; 133 134 /** 135 * struct irq_common_data - per irq data shared by all irqchips 136 * @state_use_accessors: status information for irq chip functions. 137 * Use accessor functions to deal with it 138 * @node: node index useful for balancing 139 * @handler_data: per-IRQ data for the irq_chip methods 140 * @affinity: IRQ affinity on SMP. If this is an IPI 141 * related irq, then this is the mask of the 142 * CPUs to which an IPI can be sent. 143 * @effective_affinity: The effective IRQ affinity on SMP as some irq 144 * chips do not allow multi CPU destinations. 145 * A subset of @affinity. 146 * @msi_desc: MSI descriptor 147 * @ipi_offset: Offset of first IPI target cpu in @affinity. Optional. 148 */ 149 struct irq_common_data { 150 unsigned int __private state_use_accessors; 151 #ifdef CONFIG_NUMA 152 unsigned int node; 153 #endif 154 void *handler_data; 155 struct msi_desc *msi_desc; 156 #ifdef CONFIG_SMP 157 cpumask_var_t affinity; 158 #endif 159 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 160 cpumask_var_t effective_affinity; 161 #endif 162 #ifdef CONFIG_GENERIC_IRQ_IPI 163 unsigned int ipi_offset; 164 #endif 165 }; 166 167 /** 168 * struct irq_data - per irq chip data passed down to chip functions 169 * @mask: precomputed bitmask for accessing the chip registers 170 * @irq: interrupt number 171 * @hwirq: hardware interrupt number, local to the interrupt domain 172 * @common: point to data shared by all irqchips 173 * @chip: low level interrupt hardware access 174 * @domain: Interrupt translation domain; responsible for mapping 175 * between hwirq number and linux irq number. 176 * @parent_data: pointer to parent struct irq_data to support hierarchy 177 * irq_domain 178 * @chip_data: platform-specific per-chip private data for the chip 179 * methods, to allow shared chip implementations 180 */ 181 struct irq_data { 182 u32 mask; 183 unsigned int irq; 184 irq_hw_number_t hwirq; 185 struct irq_common_data *common; 186 struct irq_chip *chip; 187 struct irq_domain *domain; 188 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 189 struct irq_data *parent_data; 190 #endif 191 void *chip_data; 192 }; 193 194 /* 195 * Bit masks for irq_common_data.state_use_accessors 196 * 197 * IRQD_TRIGGER_MASK - Mask for the trigger type bits 198 * IRQD_SETAFFINITY_PENDING - Affinity setting is pending 199 * IRQD_ACTIVATED - Interrupt has already been activated 200 * IRQD_NO_BALANCING - Balancing disabled for this IRQ 201 * IRQD_PER_CPU - Interrupt is per cpu 202 * IRQD_AFFINITY_SET - Interrupt affinity was set 203 * IRQD_LEVEL - Interrupt is level triggered 204 * IRQD_WAKEUP_STATE - Interrupt is configured for wakeup 205 * from suspend 206 * IRQD_IRQ_DISABLED - Disabled state of the interrupt 207 * IRQD_IRQ_MASKED - Masked state of the interrupt 208 * IRQD_IRQ_INPROGRESS - In progress state of the interrupt 209 * IRQD_WAKEUP_ARMED - Wakeup mode armed 210 * IRQD_FORWARDED_TO_VCPU - The interrupt is forwarded to a VCPU 211 * IRQD_AFFINITY_MANAGED - Affinity is auto-managed by the kernel 212 * IRQD_IRQ_STARTED - Startup state of the interrupt 213 * IRQD_MANAGED_SHUTDOWN - Interrupt was shutdown due to empty affinity 214 * mask. Applies only to affinity managed irqs. 215 * IRQD_SINGLE_TARGET - IRQ allows only a single affinity target 216 * IRQD_DEFAULT_TRIGGER_SET - Expected trigger already been set 217 * IRQD_CAN_RESERVE - Can use reservation mode 218 * IRQD_HANDLE_ENFORCE_IRQCTX - Enforce that handle_irq_*() is only invoked 219 * from actual interrupt context. 220 * IRQD_AFFINITY_ON_ACTIVATE - Affinity is set on activation. Don't call 221 * irq_chip::irq_set_affinity() when deactivated. 222 * IRQD_IRQ_ENABLED_ON_SUSPEND - Interrupt is enabled on suspend by irq pm if 223 * irqchip have flag IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND set. 224 * IRQD_RESEND_WHEN_IN_PROGRESS - Interrupt may fire when already in progress in which 225 * case it must be resent at the next available opportunity. 226 */ 227 enum { 228 IRQD_TRIGGER_MASK = 0xf, 229 IRQD_SETAFFINITY_PENDING = BIT(8), 230 IRQD_ACTIVATED = BIT(9), 231 IRQD_NO_BALANCING = BIT(10), 232 IRQD_PER_CPU = BIT(11), 233 IRQD_AFFINITY_SET = BIT(12), 234 IRQD_LEVEL = BIT(13), 235 IRQD_WAKEUP_STATE = BIT(14), 236 IRQD_IRQ_DISABLED = BIT(16), 237 IRQD_IRQ_MASKED = BIT(17), 238 IRQD_IRQ_INPROGRESS = BIT(18), 239 IRQD_WAKEUP_ARMED = BIT(19), 240 IRQD_FORWARDED_TO_VCPU = BIT(20), 241 IRQD_AFFINITY_MANAGED = BIT(21), 242 IRQD_IRQ_STARTED = BIT(22), 243 IRQD_MANAGED_SHUTDOWN = BIT(23), 244 IRQD_SINGLE_TARGET = BIT(24), 245 IRQD_DEFAULT_TRIGGER_SET = BIT(25), 246 IRQD_CAN_RESERVE = BIT(26), 247 IRQD_HANDLE_ENFORCE_IRQCTX = BIT(27), 248 IRQD_AFFINITY_ON_ACTIVATE = BIT(28), 249 IRQD_IRQ_ENABLED_ON_SUSPEND = BIT(29), 250 IRQD_RESEND_WHEN_IN_PROGRESS = BIT(30), 251 }; 252 253 #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors) 254 255 static inline bool irqd_is_setaffinity_pending(struct irq_data *d) 256 { 257 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING; 258 } 259 260 static inline bool irqd_is_per_cpu(struct irq_data *d) 261 { 262 return __irqd_to_state(d) & IRQD_PER_CPU; 263 } 264 265 static inline bool irqd_can_balance(struct irq_data *d) 266 { 267 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING)); 268 } 269 270 static inline bool irqd_affinity_was_set(struct irq_data *d) 271 { 272 return __irqd_to_state(d) & IRQD_AFFINITY_SET; 273 } 274 275 static inline void irqd_mark_affinity_was_set(struct irq_data *d) 276 { 277 __irqd_to_state(d) |= IRQD_AFFINITY_SET; 278 } 279 280 static inline bool irqd_trigger_type_was_set(struct irq_data *d) 281 { 282 return __irqd_to_state(d) & IRQD_DEFAULT_TRIGGER_SET; 283 } 284 285 static inline u32 irqd_get_trigger_type(struct irq_data *d) 286 { 287 return __irqd_to_state(d) & IRQD_TRIGGER_MASK; 288 } 289 290 /* 291 * Must only be called inside irq_chip.irq_set_type() functions or 292 * from the DT/ACPI setup code. 293 */ 294 static inline void irqd_set_trigger_type(struct irq_data *d, u32 type) 295 { 296 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK; 297 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK; 298 __irqd_to_state(d) |= IRQD_DEFAULT_TRIGGER_SET; 299 } 300 301 static inline bool irqd_is_level_type(struct irq_data *d) 302 { 303 return __irqd_to_state(d) & IRQD_LEVEL; 304 } 305 306 /* 307 * Must only be called of irqchip.irq_set_affinity() or low level 308 * hierarchy domain allocation functions. 309 */ 310 static inline void irqd_set_single_target(struct irq_data *d) 311 { 312 __irqd_to_state(d) |= IRQD_SINGLE_TARGET; 313 } 314 315 static inline bool irqd_is_single_target(struct irq_data *d) 316 { 317 return __irqd_to_state(d) & IRQD_SINGLE_TARGET; 318 } 319 320 static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) 321 { 322 __irqd_to_state(d) |= IRQD_HANDLE_ENFORCE_IRQCTX; 323 } 324 325 static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) 326 { 327 return __irqd_to_state(d) & IRQD_HANDLE_ENFORCE_IRQCTX; 328 } 329 330 static inline bool irqd_is_enabled_on_suspend(struct irq_data *d) 331 { 332 return __irqd_to_state(d) & IRQD_IRQ_ENABLED_ON_SUSPEND; 333 } 334 335 static inline bool irqd_is_wakeup_set(struct irq_data *d) 336 { 337 return __irqd_to_state(d) & IRQD_WAKEUP_STATE; 338 } 339 340 static inline bool irqd_irq_disabled(struct irq_data *d) 341 { 342 return __irqd_to_state(d) & IRQD_IRQ_DISABLED; 343 } 344 345 static inline bool irqd_irq_masked(struct irq_data *d) 346 { 347 return __irqd_to_state(d) & IRQD_IRQ_MASKED; 348 } 349 350 static inline bool irqd_irq_inprogress(struct irq_data *d) 351 { 352 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS; 353 } 354 355 static inline bool irqd_is_wakeup_armed(struct irq_data *d) 356 { 357 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED; 358 } 359 360 static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d) 361 { 362 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU; 363 } 364 365 static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d) 366 { 367 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU; 368 } 369 370 static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d) 371 { 372 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU; 373 } 374 375 static inline bool irqd_affinity_is_managed(struct irq_data *d) 376 { 377 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED; 378 } 379 380 static inline bool irqd_is_activated(struct irq_data *d) 381 { 382 return __irqd_to_state(d) & IRQD_ACTIVATED; 383 } 384 385 static inline void irqd_set_activated(struct irq_data *d) 386 { 387 __irqd_to_state(d) |= IRQD_ACTIVATED; 388 } 389 390 static inline void irqd_clr_activated(struct irq_data *d) 391 { 392 __irqd_to_state(d) &= ~IRQD_ACTIVATED; 393 } 394 395 static inline bool irqd_is_started(struct irq_data *d) 396 { 397 return __irqd_to_state(d) & IRQD_IRQ_STARTED; 398 } 399 400 static inline bool irqd_is_managed_and_shutdown(struct irq_data *d) 401 { 402 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN; 403 } 404 405 static inline void irqd_set_can_reserve(struct irq_data *d) 406 { 407 __irqd_to_state(d) |= IRQD_CAN_RESERVE; 408 } 409 410 static inline void irqd_clr_can_reserve(struct irq_data *d) 411 { 412 __irqd_to_state(d) &= ~IRQD_CAN_RESERVE; 413 } 414 415 static inline bool irqd_can_reserve(struct irq_data *d) 416 { 417 return __irqd_to_state(d) & IRQD_CAN_RESERVE; 418 } 419 420 static inline void irqd_set_affinity_on_activate(struct irq_data *d) 421 { 422 __irqd_to_state(d) |= IRQD_AFFINITY_ON_ACTIVATE; 423 } 424 425 static inline bool irqd_affinity_on_activate(struct irq_data *d) 426 { 427 return __irqd_to_state(d) & IRQD_AFFINITY_ON_ACTIVATE; 428 } 429 430 static inline void irqd_set_resend_when_in_progress(struct irq_data *d) 431 { 432 __irqd_to_state(d) |= IRQD_RESEND_WHEN_IN_PROGRESS; 433 } 434 435 static inline bool irqd_needs_resend_when_in_progress(struct irq_data *d) 436 { 437 return __irqd_to_state(d) & IRQD_RESEND_WHEN_IN_PROGRESS; 438 } 439 440 #undef __irqd_to_state 441 442 static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d) 443 { 444 return d->hwirq; 445 } 446 447 /** 448 * struct irq_chip - hardware interrupt chip descriptor 449 * 450 * @name: name for /proc/interrupts 451 * @irq_startup: start up the interrupt (defaults to ->enable if NULL) 452 * @irq_shutdown: shut down the interrupt (defaults to ->disable if NULL) 453 * @irq_enable: enable the interrupt (defaults to chip->unmask if NULL) 454 * @irq_disable: disable the interrupt 455 * @irq_ack: start of a new interrupt 456 * @irq_mask: mask an interrupt source 457 * @irq_mask_ack: ack and mask an interrupt source 458 * @irq_unmask: unmask an interrupt source 459 * @irq_eoi: end of interrupt 460 * @irq_set_affinity: Set the CPU affinity on SMP machines. If the force 461 * argument is true, it tells the driver to 462 * unconditionally apply the affinity setting. Sanity 463 * checks against the supplied affinity mask are not 464 * required. This is used for CPU hotplug where the 465 * target CPU is not yet set in the cpu_online_mask. 466 * @irq_pre_redirect: Optional function to be invoked before redirecting 467 * an interrupt via irq_work. Called only on CONFIG_SMP. 468 * @irq_retrigger: resend an IRQ to the CPU 469 * @irq_set_type: set the flow type (IRQ_TYPE_LEVEL/etc.) of an IRQ 470 * @irq_set_wake: enable/disable power-management wake-on of an IRQ 471 * @irq_bus_lock: function to lock access to slow bus (i2c) chips 472 * @irq_bus_sync_unlock:function to sync and unlock slow bus (i2c) chips 473 * @irq_cpu_online: configure an interrupt source for a secondary CPU 474 * @irq_cpu_offline: un-configure an interrupt source for a secondary CPU 475 * @irq_suspend: function called from core code on suspend once per 476 * chip, when one or more interrupts are installed 477 * @irq_resume: function called from core code on resume once per chip, 478 * when one ore more interrupts are installed 479 * @irq_pm_shutdown: function called from core code on shutdown once per chip 480 * @irq_calc_mask: Optional function to set irq_data.mask for special cases 481 * @irq_print_chip: optional to print special chip info in show_interrupts 482 * @irq_request_resources: optional to request resources before calling 483 * any other callback related to this irq 484 * @irq_release_resources: optional to release resources acquired with 485 * irq_request_resources 486 * @irq_compose_msi_msg: optional to compose message content for MSI 487 * @irq_write_msi_msg: optional to write message content for MSI 488 * @irq_get_irqchip_state: return the internal state of an interrupt 489 * @irq_set_irqchip_state: set the internal state of a interrupt 490 * @irq_set_vcpu_affinity: optional to target a vCPU in a virtual machine 491 * @ipi_send_single: send a single IPI to destination cpus 492 * @ipi_send_mask: send an IPI to destination cpus in cpumask 493 * @irq_nmi_setup: function called from core code before enabling an NMI 494 * @irq_nmi_teardown: function called from core code after disabling an NMI 495 * @irq_force_complete_move: optional function to force complete pending irq move 496 * @flags: chip specific flags 497 */ 498 struct irq_chip { 499 const char *name; 500 unsigned int (*irq_startup)(struct irq_data *data); 501 void (*irq_shutdown)(struct irq_data *data); 502 void (*irq_enable)(struct irq_data *data); 503 void (*irq_disable)(struct irq_data *data); 504 505 void (*irq_ack)(struct irq_data *data); 506 void (*irq_mask)(struct irq_data *data); 507 void (*irq_mask_ack)(struct irq_data *data); 508 void (*irq_unmask)(struct irq_data *data); 509 void (*irq_eoi)(struct irq_data *data); 510 511 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force); 512 void (*irq_pre_redirect)(struct irq_data *data); 513 int (*irq_retrigger)(struct irq_data *data); 514 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type); 515 int (*irq_set_wake)(struct irq_data *data, unsigned int on); 516 517 void (*irq_bus_lock)(struct irq_data *data); 518 void (*irq_bus_sync_unlock)(struct irq_data *data); 519 520 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE 521 void (*irq_cpu_online)(struct irq_data *data); 522 void (*irq_cpu_offline)(struct irq_data *data); 523 #endif 524 void (*irq_suspend)(struct irq_data *data); 525 void (*irq_resume)(struct irq_data *data); 526 void (*irq_pm_shutdown)(struct irq_data *data); 527 528 void (*irq_calc_mask)(struct irq_data *data); 529 530 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p); 531 int (*irq_request_resources)(struct irq_data *data); 532 void (*irq_release_resources)(struct irq_data *data); 533 534 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg); 535 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg); 536 537 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state); 538 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state); 539 540 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info); 541 542 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu); 543 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest); 544 545 int (*irq_nmi_setup)(struct irq_data *data); 546 void (*irq_nmi_teardown)(struct irq_data *data); 547 548 void (*irq_force_complete_move)(struct irq_data *data); 549 550 unsigned long flags; 551 }; 552 553 /* 554 * irq_chip specific flags 555 * 556 * IRQCHIP_SET_TYPE_MASKED: Mask before calling chip.irq_set_type() 557 * IRQCHIP_EOI_IF_HANDLED: Only issue irq_eoi() when irq was handled 558 * IRQCHIP_MASK_ON_SUSPEND: Mask non wake irqs in the suspend path 559 * IRQCHIP_ONOFFLINE_ENABLED: Only call irq_on/off_line callbacks 560 * when irq enabled 561 * IRQCHIP_SKIP_SET_WAKE: Skip chip.irq_set_wake(), for this irq chip 562 * IRQCHIP_ONESHOT_SAFE: One shot does not require mask/unmask 563 * IRQCHIP_EOI_THREADED: Chip requires eoi() on unmask in threaded mode 564 * IRQCHIP_SUPPORTS_LEVEL_MSI: Chip can provide two doorbells for Level MSIs 565 * IRQCHIP_SUPPORTS_NMI: Chip can deliver NMIs, only for root irqchips 566 * IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND: Invokes __enable_irq()/__disable_irq() for wake irqs 567 * in the suspend path if they are in disabled state 568 * IRQCHIP_AFFINITY_PRE_STARTUP: Default affinity update before startup 569 * IRQCHIP_IMMUTABLE: Don't ever change anything in this chip 570 * IRQCHIP_MOVE_DEFERRED: Move the interrupt in actual interrupt context 571 */ 572 enum { 573 IRQCHIP_SET_TYPE_MASKED = (1 << 0), 574 IRQCHIP_EOI_IF_HANDLED = (1 << 1), 575 IRQCHIP_MASK_ON_SUSPEND = (1 << 2), 576 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3), 577 IRQCHIP_SKIP_SET_WAKE = (1 << 4), 578 IRQCHIP_ONESHOT_SAFE = (1 << 5), 579 IRQCHIP_EOI_THREADED = (1 << 6), 580 IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7), 581 IRQCHIP_SUPPORTS_NMI = (1 << 8), 582 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND = (1 << 9), 583 IRQCHIP_AFFINITY_PRE_STARTUP = (1 << 10), 584 IRQCHIP_IMMUTABLE = (1 << 11), 585 IRQCHIP_MOVE_DEFERRED = (1 << 12), 586 }; 587 588 #include <linux/irqdesc.h> 589 590 /* 591 * Pick up the arch-dependent methods: 592 */ 593 #include <asm/hw_irq.h> 594 595 #ifndef NR_IRQS_LEGACY 596 # define NR_IRQS_LEGACY 0 597 #endif 598 599 #ifndef ARCH_IRQ_INIT_FLAGS 600 # define ARCH_IRQ_INIT_FLAGS 0 601 #endif 602 603 #define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS 604 605 #ifdef CONFIG_DEPRECATED_IRQ_CPU_ONOFFLINE 606 extern void irq_cpu_online(void); 607 extern void irq_cpu_offline(void); 608 #endif 609 extern int irq_set_affinity_locked(struct irq_data *data, 610 const struct cpumask *cpumask, bool force); 611 extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info); 612 613 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION) 614 extern void irq_migrate_all_off_this_cpu(void); 615 extern int irq_affinity_online_cpu(unsigned int cpu); 616 #else 617 # define irq_affinity_online_cpu NULL 618 #endif 619 620 #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ) 621 bool irq_can_move_in_process_context(struct irq_data *data); 622 void __irq_move_irq(struct irq_data *data); 623 static inline void irq_move_irq(struct irq_data *data) 624 { 625 if (unlikely(irqd_is_setaffinity_pending(data))) 626 __irq_move_irq(data); 627 } 628 void irq_move_masked_irq(struct irq_data *data); 629 #else 630 static inline bool irq_can_move_in_process_context(struct irq_data *data) { return true; } 631 static inline void irq_move_irq(struct irq_data *data) { } 632 static inline void irq_move_masked_irq(struct irq_data *data) { } 633 #endif 634 635 extern int no_irq_affinity; 636 637 #ifdef CONFIG_HARDIRQS_SW_RESEND 638 int irq_set_parent(int irq, int parent_irq); 639 #else 640 static inline int irq_set_parent(int irq, int parent_irq) 641 { 642 return 0; 643 } 644 #endif 645 646 /* 647 * Built-in IRQ handlers for various IRQ types, 648 * callable via desc->handle_irq() 649 */ 650 extern void handle_level_irq(struct irq_desc *desc); 651 extern void handle_fasteoi_irq(struct irq_desc *desc); 652 extern void handle_edge_irq(struct irq_desc *desc); 653 extern void handle_edge_eoi_irq(struct irq_desc *desc); 654 extern void handle_simple_irq(struct irq_desc *desc); 655 extern void handle_untracked_irq(struct irq_desc *desc); 656 extern void handle_percpu_irq(struct irq_desc *desc); 657 extern void handle_percpu_devid_irq(struct irq_desc *desc); 658 extern void handle_bad_irq(struct irq_desc *desc); 659 extern void handle_nested_irq(unsigned int irq); 660 661 extern void handle_fasteoi_nmi(struct irq_desc *desc); 662 663 extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg); 664 extern int irq_chip_pm_get(struct irq_data *data); 665 extern void irq_chip_pm_put(struct irq_data *data); 666 #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY 667 extern void handle_fasteoi_ack_irq(struct irq_desc *desc); 668 extern void handle_fasteoi_mask_irq(struct irq_desc *desc); 669 extern int irq_chip_set_parent_state(struct irq_data *data, 670 enum irqchip_irq_state which, 671 bool val); 672 extern int irq_chip_get_parent_state(struct irq_data *data, 673 enum irqchip_irq_state which, 674 bool *state); 675 extern void irq_chip_shutdown_parent(struct irq_data *data); 676 extern unsigned int irq_chip_startup_parent(struct irq_data *data); 677 extern void irq_chip_enable_parent(struct irq_data *data); 678 extern void irq_chip_disable_parent(struct irq_data *data); 679 extern void irq_chip_ack_parent(struct irq_data *data); 680 extern int irq_chip_retrigger_hierarchy(struct irq_data *data); 681 extern void irq_chip_mask_parent(struct irq_data *data); 682 extern void irq_chip_mask_ack_parent(struct irq_data *data); 683 extern void irq_chip_unmask_parent(struct irq_data *data); 684 extern void irq_chip_eoi_parent(struct irq_data *data); 685 extern int irq_chip_set_affinity_parent(struct irq_data *data, 686 const struct cpumask *dest, 687 bool force); 688 extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on); 689 extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, 690 void *vcpu_info); 691 extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type); 692 extern int irq_chip_request_resources_parent(struct irq_data *data); 693 extern void irq_chip_release_resources_parent(struct irq_data *data); 694 #ifdef CONFIG_SMP 695 void irq_chip_pre_redirect_parent(struct irq_data *data); 696 #endif 697 #endif 698 699 #ifdef CONFIG_SMP 700 int irq_chip_redirect_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force); 701 #endif 702 703 /* Disable or mask interrupts during a kernel kexec */ 704 extern void machine_kexec_mask_interrupts(void); 705 706 /* Handling of unhandled and spurious interrupts: */ 707 extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret); 708 709 710 /* Enable/disable irq debugging output: */ 711 extern int noirqdebug_setup(char *str); 712 713 /* Checks whether the interrupt can be requested by request_irq(): */ 714 extern bool can_request_irq(unsigned int irq, unsigned long irqflags); 715 716 /* Dummy irq-chip implementations: */ 717 extern struct irq_chip no_irq_chip; 718 extern struct irq_chip dummy_irq_chip; 719 720 extern void 721 irq_set_chip_and_handler_name(unsigned int irq, const struct irq_chip *chip, 722 irq_flow_handler_t handle, const char *name); 723 724 static inline void irq_set_chip_and_handler(unsigned int irq, 725 const struct irq_chip *chip, 726 irq_flow_handler_t handle) 727 { 728 irq_set_chip_and_handler_name(irq, chip, handle, NULL); 729 } 730 731 extern int irq_set_percpu_devid(unsigned int irq); 732 733 extern void 734 __irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, 735 const char *name); 736 737 static inline void 738 irq_set_handler(unsigned int irq, irq_flow_handler_t handle) 739 { 740 __irq_set_handler(irq, handle, 0, NULL); 741 } 742 743 /* 744 * Set a highlevel chained flow handler for a given IRQ. 745 * (a chained handler is automatically enabled and set to 746 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 747 */ 748 static inline void 749 irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle) 750 { 751 __irq_set_handler(irq, handle, 1, NULL); 752 } 753 754 /* 755 * Set a highlevel chained flow handler and its data for a given IRQ. 756 * (a chained handler is automatically enabled and set to 757 * IRQ_NOREQUEST, IRQ_NOPROBE, and IRQ_NOTHREAD) 758 */ 759 void 760 irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle, 761 void *data); 762 763 void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set); 764 765 static inline void irq_set_status_flags(unsigned int irq, unsigned long set) 766 { 767 irq_modify_status(irq, 0, set); 768 } 769 770 static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr) 771 { 772 irq_modify_status(irq, clr, 0); 773 } 774 775 static inline void irq_set_noprobe(unsigned int irq) 776 { 777 irq_modify_status(irq, 0, IRQ_NOPROBE); 778 } 779 780 static inline void irq_set_probe(unsigned int irq) 781 { 782 irq_modify_status(irq, IRQ_NOPROBE, 0); 783 } 784 785 static inline void irq_set_nothread(unsigned int irq) 786 { 787 irq_modify_status(irq, 0, IRQ_NOTHREAD); 788 } 789 790 static inline void irq_set_thread(unsigned int irq) 791 { 792 irq_modify_status(irq, IRQ_NOTHREAD, 0); 793 } 794 795 static inline void irq_set_nested_thread(unsigned int irq, bool nest) 796 { 797 if (nest) 798 irq_set_status_flags(irq, IRQ_NESTED_THREAD); 799 else 800 irq_clear_status_flags(irq, IRQ_NESTED_THREAD); 801 } 802 803 static inline void irq_set_percpu_devid_flags(unsigned int irq) 804 { 805 irq_set_status_flags(irq, 806 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD | 807 IRQ_NOPROBE | IRQ_PER_CPU_DEVID); 808 } 809 810 /* Set/get chip/data for an IRQ: */ 811 extern int irq_set_chip(unsigned int irq, const struct irq_chip *chip); 812 extern int irq_set_handler_data(unsigned int irq, void *data); 813 extern int irq_set_chip_data(unsigned int irq, void *data); 814 extern int irq_set_irq_type(unsigned int irq, unsigned int type); 815 extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry); 816 extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset, 817 struct msi_desc *entry); 818 extern struct irq_data *irq_get_irq_data(unsigned int irq); 819 820 static inline struct irq_chip *irq_get_chip(unsigned int irq) 821 { 822 struct irq_data *d = irq_get_irq_data(irq); 823 return d ? d->chip : NULL; 824 } 825 826 static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d) 827 { 828 return d->chip; 829 } 830 831 static inline void *irq_get_chip_data(unsigned int irq) 832 { 833 struct irq_data *d = irq_get_irq_data(irq); 834 return d ? d->chip_data : NULL; 835 } 836 837 static inline void *irq_data_get_irq_chip_data(struct irq_data *d) 838 { 839 return d->chip_data; 840 } 841 842 static inline void *irq_get_handler_data(unsigned int irq) 843 { 844 struct irq_data *d = irq_get_irq_data(irq); 845 return d ? d->common->handler_data : NULL; 846 } 847 848 static inline void *irq_data_get_irq_handler_data(struct irq_data *d) 849 { 850 return d->common->handler_data; 851 } 852 853 static inline struct msi_desc *irq_get_msi_desc(unsigned int irq) 854 { 855 struct irq_data *d = irq_get_irq_data(irq); 856 return d ? d->common->msi_desc : NULL; 857 } 858 859 static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d) 860 { 861 return d->common->msi_desc; 862 } 863 864 static inline u32 irq_get_trigger_type(unsigned int irq) 865 { 866 struct irq_data *d = irq_get_irq_data(irq); 867 return d ? irqd_get_trigger_type(d) : 0; 868 } 869 870 static inline int irq_common_data_get_node(struct irq_common_data *d) 871 { 872 #ifdef CONFIG_NUMA 873 return d->node; 874 #else 875 return 0; 876 #endif 877 } 878 879 static inline int irq_data_get_node(struct irq_data *d) 880 { 881 return irq_common_data_get_node(d->common); 882 } 883 884 static inline 885 const struct cpumask *irq_data_get_affinity_mask(struct irq_data *d) 886 { 887 #ifdef CONFIG_SMP 888 return d->common->affinity; 889 #else 890 return cpumask_of(0); 891 #endif 892 } 893 894 static inline void irq_data_update_affinity(struct irq_data *d, 895 const struct cpumask *m) 896 { 897 #ifdef CONFIG_SMP 898 cpumask_copy(d->common->affinity, m); 899 #endif 900 } 901 902 static inline const struct cpumask *irq_get_affinity_mask(int irq) 903 { 904 struct irq_data *d = irq_get_irq_data(irq); 905 906 return d ? irq_data_get_affinity_mask(d) : NULL; 907 } 908 909 #ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK 910 static inline 911 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 912 { 913 return d->common->effective_affinity; 914 } 915 static inline void irq_data_update_effective_affinity(struct irq_data *d, 916 const struct cpumask *m) 917 { 918 cpumask_copy(d->common->effective_affinity, m); 919 } 920 #else 921 static inline void irq_data_update_effective_affinity(struct irq_data *d, 922 const struct cpumask *m) 923 { 924 } 925 static inline 926 const struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d) 927 { 928 return irq_data_get_affinity_mask(d); 929 } 930 #endif 931 932 static inline 933 const struct cpumask *irq_get_effective_affinity_mask(unsigned int irq) 934 { 935 struct irq_data *d = irq_get_irq_data(irq); 936 937 return d ? irq_data_get_effective_affinity_mask(d) : NULL; 938 } 939 940 unsigned int arch_dynirq_lower_bound(unsigned int from); 941 942 int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, 943 struct module *owner, 944 const struct irq_affinity_desc *affinity); 945 946 int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from, 947 unsigned int cnt, int node, struct module *owner, 948 const struct irq_affinity_desc *affinity); 949 950 /* use macros to avoid needing export.h for THIS_MODULE */ 951 #define irq_alloc_descs(irq, from, cnt, node) \ 952 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL) 953 954 #define irq_alloc_desc(node) \ 955 irq_alloc_descs(-1, 1, 1, node) 956 957 #define irq_alloc_desc_at(at, node) \ 958 irq_alloc_descs(at, at, 1, node) 959 960 #define irq_alloc_desc_from(from, node) \ 961 irq_alloc_descs(-1, from, 1, node) 962 963 #define irq_alloc_descs_from(from, cnt, node) \ 964 irq_alloc_descs(-1, from, cnt, node) 965 966 #define devm_irq_alloc_descs(dev, irq, from, cnt, node) \ 967 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL) 968 969 #define devm_irq_alloc_desc(dev, node) \ 970 devm_irq_alloc_descs(dev, -1, 1, 1, node) 971 972 #define devm_irq_alloc_desc_at(dev, at, node) \ 973 devm_irq_alloc_descs(dev, at, at, 1, node) 974 975 #define devm_irq_alloc_desc_from(dev, from, node) \ 976 devm_irq_alloc_descs(dev, -1, from, 1, node) 977 978 #define devm_irq_alloc_descs_from(dev, from, cnt, node) \ 979 devm_irq_alloc_descs(dev, -1, from, cnt, node) 980 981 void irq_free_descs(unsigned int irq, unsigned int cnt); 982 static inline void irq_free_desc(unsigned int irq) 983 { 984 irq_free_descs(irq, 1); 985 } 986 987 /** 988 * struct irq_chip_regs - register offsets for struct irq_gci 989 * @enable: Enable register offset to reg_base 990 * @disable: Disable register offset to reg_base 991 * @mask: Mask register offset to reg_base 992 * @ack: Ack register offset to reg_base 993 * @eoi: Eoi register offset to reg_base 994 * @type: Type configuration register offset to reg_base 995 */ 996 struct irq_chip_regs { 997 unsigned long enable; 998 unsigned long disable; 999 unsigned long mask; 1000 unsigned long ack; 1001 unsigned long eoi; 1002 unsigned long type; 1003 }; 1004 1005 /** 1006 * struct irq_chip_type - Generic interrupt chip instance for a flow type 1007 * @chip: The real interrupt chip which provides the callbacks 1008 * @regs: Register offsets for this chip 1009 * @handler: Flow handler associated with this chip 1010 * @type: Chip can handle these flow types 1011 * @mask_cache_priv: Cached mask register private to the chip type 1012 * @mask_cache: Pointer to cached mask register 1013 * 1014 * A irq_generic_chip can have several instances of irq_chip_type when 1015 * it requires different functions and register offsets for different 1016 * flow types. 1017 */ 1018 struct irq_chip_type { 1019 struct irq_chip chip; 1020 struct irq_chip_regs regs; 1021 irq_flow_handler_t handler; 1022 u32 type; 1023 u32 mask_cache_priv; 1024 u32 *mask_cache; 1025 }; 1026 1027 /** 1028 * struct irq_chip_generic - Generic irq chip data structure 1029 * @lock: Lock to protect register and cache data access 1030 * @reg_base: Register base address (virtual) 1031 * @reg_readl: Alternate I/O accessor (defaults to readl if NULL) 1032 * @reg_writel: Alternate I/O accessor (defaults to writel if NULL) 1033 * @suspend: Function called from core code on suspend once per 1034 * chip; can be useful instead of irq_chip::suspend to 1035 * handle chip details even when no interrupts are in use 1036 * @resume: Function called from core code on resume once per chip; 1037 * can be useful instead of irq_chip::suspend to handle 1038 * chip details even when no interrupts are in use 1039 * @irq_base: Interrupt base nr for this chip 1040 * @irq_cnt: Number of interrupts handled by this chip 1041 * @mask_cache: Cached mask register shared between all chip types 1042 * @wake_enabled: Interrupt can wakeup from suspend 1043 * @wake_active: Interrupt is marked as an wakeup from suspend source 1044 * @num_ct: Number of available irq_chip_type instances (usually 1) 1045 * @private: Private data for non generic chip callbacks 1046 * @installed: bitfield to denote installed interrupts 1047 * @unused: bitfield to denote unused interrupts 1048 * @domain: irq domain pointer 1049 * @list: List head for keeping track of instances 1050 * @chip_types: Array of interrupt irq_chip_types 1051 * 1052 * Note, that irq_chip_generic can have multiple irq_chip_type 1053 * implementations which can be associated to a particular irq line of 1054 * an irq_chip_generic instance. That allows to share and protect 1055 * state in an irq_chip_generic instance when we need to implement 1056 * different flow mechanisms (level/edge) for it. 1057 */ 1058 struct irq_chip_generic { 1059 raw_spinlock_t lock; 1060 void __iomem *reg_base; 1061 u32 (*reg_readl)(void __iomem *addr); 1062 void (*reg_writel)(u32 val, void __iomem *addr); 1063 void (*suspend)(struct irq_chip_generic *gc); 1064 void (*resume)(struct irq_chip_generic *gc); 1065 unsigned int irq_base; 1066 unsigned int irq_cnt; 1067 u32 mask_cache; 1068 u32 wake_enabled; 1069 u32 wake_active; 1070 unsigned int num_ct; 1071 void *private; 1072 unsigned long installed; 1073 unsigned long unused; 1074 struct irq_domain *domain; 1075 struct list_head list; 1076 struct irq_chip_type chip_types[]; 1077 }; 1078 1079 /** 1080 * enum irq_gc_flags - Initialization flags for generic irq chips 1081 * @IRQ_GC_INIT_MASK_CACHE: Initialize the mask_cache by reading mask reg 1082 * @IRQ_GC_INIT_NESTED_LOCK: Set the lock class of the irqs to nested for 1083 * irq chips which need to call irq_set_wake() on 1084 * the parent irq. Usually GPIO implementations 1085 * @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private 1086 * @IRQ_GC_NO_MASK: Do not calculate irq_data->mask 1087 * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE) 1088 */ 1089 enum irq_gc_flags { 1090 IRQ_GC_INIT_MASK_CACHE = 1 << 0, 1091 IRQ_GC_INIT_NESTED_LOCK = 1 << 1, 1092 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2, 1093 IRQ_GC_NO_MASK = 1 << 3, 1094 IRQ_GC_BE_IO = 1 << 4, 1095 }; 1096 1097 /* 1098 * struct irq_domain_chip_generic - Generic irq chip data structure for irq domains 1099 * @irqs_per_chip: Number of interrupts per chip 1100 * @num_chips: Number of chips 1101 * @irq_flags_to_set: IRQ* flags to set on irq setup 1102 * @irq_flags_to_clear: IRQ* flags to clear on irq setup 1103 * @gc_flags: Generic chip specific setup flags 1104 * @exit: Function called on each chip when they are destroyed. 1105 * @gc: Array of pointers to generic interrupt chips 1106 */ 1107 struct irq_domain_chip_generic { 1108 unsigned int irqs_per_chip; 1109 unsigned int num_chips; 1110 unsigned int irq_flags_to_clear; 1111 unsigned int irq_flags_to_set; 1112 enum irq_gc_flags gc_flags; 1113 void (*exit)(struct irq_chip_generic *gc); 1114 struct irq_chip_generic *gc[]; 1115 }; 1116 1117 /** 1118 * struct irq_domain_chip_generic_info - Generic chip information structure 1119 * @name: Name of the generic interrupt chip 1120 * @handler: Interrupt handler used by the generic interrupt chip 1121 * @irqs_per_chip: Number of interrupts each chip handles (max 32) 1122 * @num_ct: Number of irq_chip_type instances associated with each 1123 * chip 1124 * @irq_flags_to_clear: IRQ_* bits to clear in the mapping function 1125 * @irq_flags_to_set: IRQ_* bits to set in the mapping function 1126 * @gc_flags: Generic chip specific setup flags 1127 * @init: Function called on each chip when they are created. 1128 * Allow to do some additional chip initialisation. 1129 * @exit: Function called on each chip when they are destroyed. 1130 * Allow to do some chip cleanup operation. 1131 */ 1132 struct irq_domain_chip_generic_info { 1133 const char *name; 1134 irq_flow_handler_t handler; 1135 unsigned int irqs_per_chip; 1136 unsigned int num_ct; 1137 unsigned int irq_flags_to_clear; 1138 unsigned int irq_flags_to_set; 1139 enum irq_gc_flags gc_flags; 1140 int (*init)(struct irq_chip_generic *gc); 1141 void (*exit)(struct irq_chip_generic *gc); 1142 }; 1143 1144 /* Generic chip callback functions */ 1145 void irq_gc_noop(struct irq_data *d); 1146 void irq_gc_mask_disable_reg(struct irq_data *d); 1147 void irq_gc_mask_set_bit(struct irq_data *d); 1148 void irq_gc_mask_clr_bit(struct irq_data *d); 1149 void irq_gc_unmask_enable_reg(struct irq_data *d); 1150 void irq_gc_ack_set_bit(struct irq_data *d); 1151 void irq_gc_ack_clr_bit(struct irq_data *d); 1152 void irq_gc_mask_disable_and_ack_set(struct irq_data *d); 1153 void irq_gc_eoi(struct irq_data *d); 1154 int irq_gc_set_wake(struct irq_data *d, unsigned int on); 1155 1156 /* Setup functions for irq_chip_generic */ 1157 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, 1158 irq_hw_number_t hw_irq); 1159 void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq); 1160 struct irq_chip_generic * 1161 irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base, 1162 void __iomem *reg_base, irq_flow_handler_t handler); 1163 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, 1164 enum irq_gc_flags flags, unsigned int clr, 1165 unsigned int set); 1166 int irq_setup_alt_chip(struct irq_data *d, unsigned int type); 1167 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, 1168 unsigned int clr, unsigned int set); 1169 1170 struct irq_chip_generic * 1171 devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct, 1172 unsigned int irq_base, void __iomem *reg_base, 1173 irq_flow_handler_t handler); 1174 int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc, 1175 u32 msk, enum irq_gc_flags flags, 1176 unsigned int clr, unsigned int set); 1177 1178 struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq); 1179 1180 #ifdef CONFIG_GENERIC_IRQ_CHIP 1181 int irq_domain_alloc_generic_chips(struct irq_domain *d, 1182 const struct irq_domain_chip_generic_info *info); 1183 void irq_domain_remove_generic_chips(struct irq_domain *d); 1184 #else 1185 static inline int 1186 irq_domain_alloc_generic_chips(struct irq_domain *d, 1187 const struct irq_domain_chip_generic_info *info) 1188 { 1189 return -EINVAL; 1190 } 1191 static inline void irq_domain_remove_generic_chips(struct irq_domain *d) { } 1192 #endif /* CONFIG_GENERIC_IRQ_CHIP */ 1193 1194 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, 1195 int num_ct, const char *name, 1196 irq_flow_handler_t handler, 1197 unsigned int clr, unsigned int set, 1198 enum irq_gc_flags flags); 1199 1200 #define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \ 1201 handler, clr, set, flags) \ 1202 ({ \ 1203 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \ 1204 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\ 1205 handler, clr, set, flags); \ 1206 }) 1207 1208 static inline void irq_free_generic_chip(struct irq_chip_generic *gc) 1209 { 1210 kfree(gc); 1211 } 1212 1213 static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc, 1214 u32 msk, unsigned int clr, 1215 unsigned int set) 1216 { 1217 irq_remove_generic_chip(gc, msk, clr, set); 1218 irq_free_generic_chip(gc); 1219 } 1220 1221 static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d) 1222 { 1223 return container_of(d->chip, struct irq_chip_type, chip); 1224 } 1225 1226 #define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX) 1227 1228 static inline void irq_reg_writel(struct irq_chip_generic *gc, 1229 u32 val, int reg_offset) 1230 { 1231 if (gc->reg_writel) 1232 gc->reg_writel(val, gc->reg_base + reg_offset); 1233 else 1234 writel(val, gc->reg_base + reg_offset); 1235 } 1236 1237 static inline u32 irq_reg_readl(struct irq_chip_generic *gc, 1238 int reg_offset) 1239 { 1240 if (gc->reg_readl) 1241 return gc->reg_readl(gc->reg_base + reg_offset); 1242 else 1243 return readl(gc->reg_base + reg_offset); 1244 } 1245 1246 struct irq_matrix; 1247 struct irq_matrix *irq_alloc_matrix(unsigned int matrix_bits, 1248 unsigned int alloc_start, 1249 unsigned int alloc_end); 1250 void irq_matrix_online(struct irq_matrix *m); 1251 void irq_matrix_offline(struct irq_matrix *m); 1252 void irq_matrix_assign_system(struct irq_matrix *m, unsigned int bit, bool replace); 1253 int irq_matrix_reserve_managed(struct irq_matrix *m, const struct cpumask *msk); 1254 void irq_matrix_remove_managed(struct irq_matrix *m, const struct cpumask *msk); 1255 int irq_matrix_alloc_managed(struct irq_matrix *m, const struct cpumask *msk, 1256 unsigned int *mapped_cpu); 1257 void irq_matrix_reserve(struct irq_matrix *m); 1258 void irq_matrix_remove_reserved(struct irq_matrix *m); 1259 int irq_matrix_alloc(struct irq_matrix *m, const struct cpumask *msk, 1260 bool reserved, unsigned int *mapped_cpu); 1261 void irq_matrix_free(struct irq_matrix *m, unsigned int cpu, 1262 unsigned int bit, bool managed); 1263 void irq_matrix_assign(struct irq_matrix *m, unsigned int bit); 1264 unsigned int irq_matrix_available(struct irq_matrix *m, bool cpudown); 1265 unsigned int irq_matrix_allocated(struct irq_matrix *m); 1266 unsigned int irq_matrix_reserved(struct irq_matrix *m); 1267 void irq_matrix_debug_show(struct seq_file *sf, struct irq_matrix *m, int ind); 1268 1269 /* Contrary to Linux irqs, for hardware irqs the irq number 0 is valid */ 1270 #define INVALID_HWIRQ (~0UL) 1271 irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu); 1272 int __ipi_send_single(struct irq_desc *desc, unsigned int cpu); 1273 int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest); 1274 int ipi_send_single(unsigned int virq, unsigned int cpu); 1275 int ipi_send_mask(unsigned int virq, const struct cpumask *dest); 1276 1277 void ipi_mux_process(void); 1278 int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu)); 1279 1280 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER 1281 /* 1282 * Registers a generic IRQ handling function as the top-level IRQ handler in 1283 * the system, which is generally the first C code called from an assembly 1284 * architecture-specific interrupt handler. 1285 * 1286 * Returns 0 on success, or -EBUSY if an IRQ handler has already been 1287 * registered. 1288 */ 1289 int __init set_handle_irq(void (*handle_irq)(struct pt_regs *)); 1290 1291 /* 1292 * Allows interrupt handlers to find the irqchip that's been registered as the 1293 * top-level IRQ handler. 1294 */ 1295 extern void (*handle_arch_irq)(struct pt_regs *) __ro_after_init; 1296 asmlinkage void generic_handle_arch_irq(struct pt_regs *regs); 1297 #else 1298 #ifndef set_handle_irq 1299 #define set_handle_irq(handle_irq) \ 1300 do { \ 1301 (void)handle_irq; \ 1302 WARN_ON(1); \ 1303 } while (0) 1304 #endif 1305 #endif 1306 1307 #endif /* _LINUX_IRQ_H */ 1308