1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
4
5 #include <asm/processor-flags.h>
6
7 /* Forward declaration, a strange C thing */
8 struct task_struct;
9 struct mm_struct;
10 struct io_bitmap;
11 struct vm86;
12
13 #include <asm/math_emu.h>
14 #include <asm/segment.h>
15 #include <asm/types.h>
16 #include <uapi/asm/sigcontext.h>
17 #include <asm/current.h>
18 #include <asm/cpufeatures.h>
19 #include <asm/cpuid/api.h>
20 #include <asm/page.h>
21 #include <asm/pgtable_types.h>
22 #include <asm/percpu.h>
23 #include <asm/desc_defs.h>
24 #include <asm/nops.h>
25 #include <asm/special_insns.h>
26 #include <asm/fpu/types.h>
27 #include <asm/unwind_hints.h>
28 #include <asm/vmxfeatures.h>
29 #include <asm/vdso/processor.h>
30 #include <asm/shstk.h>
31
32 #include <linux/personality.h>
33 #include <linux/cache.h>
34 #include <linux/threads.h>
35 #include <linux/math64.h>
36 #include <linux/err.h>
37 #include <linux/irqflags.h>
38 #include <linux/mem_encrypt.h>
39
40 /*
41 * We handle most unaligned accesses in hardware. On the other hand
42 * unaligned DMA can be quite expensive on some Nehalem processors.
43 *
44 * Based on this we disable the IP header alignment in network drivers.
45 */
46 #define NET_IP_ALIGN 0
47
48 #define HBP_NUM 4
49
50 /*
51 * These alignment constraints are for performance in the vSMP case,
52 * but in the task_struct case we must also meet hardware imposed
53 * alignment requirements of the FPU state:
54 */
55 #ifdef CONFIG_X86_VSMP
56 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
57 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
58 #else
59 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
60 # define ARCH_MIN_MMSTRUCT_ALIGN 0
61 #endif
62
63 extern u16 __read_mostly tlb_lli_4k;
64 extern u16 __read_mostly tlb_lli_2m;
65 extern u16 __read_mostly tlb_lli_4m;
66 extern u16 __read_mostly tlb_lld_4k;
67 extern u16 __read_mostly tlb_lld_2m;
68 extern u16 __read_mostly tlb_lld_4m;
69 extern u16 __read_mostly tlb_lld_1g;
70
71 /*
72 * CPU type and hardware bug flags. Kept separately for each CPU.
73 */
74
75 struct cpuinfo_topology {
76 // Real APIC ID read from the local APIC
77 u32 apicid;
78 // The initial APIC ID provided by CPUID
79 u32 initial_apicid;
80
81 // Physical package ID
82 u32 pkg_id;
83
84 // Physical die ID on AMD, Relative on Intel
85 u32 die_id;
86
87 // Compute unit ID - AMD specific
88 u32 cu_id;
89
90 // Core ID relative to the package
91 u32 core_id;
92
93 // Logical ID mappings
94 u32 logical_pkg_id;
95 u32 logical_die_id;
96 u32 logical_core_id;
97
98 // AMD Node ID and Nodes per Package info
99 u32 amd_node_id;
100
101 // Cache level topology IDs
102 u32 llc_id;
103 u32 l2c_id;
104
105 // Hardware defined CPU-type
106 union {
107 u32 cpu_type;
108 struct {
109 // CPUID.1A.EAX[23-0]
110 u32 intel_native_model_id :24;
111 // CPUID.1A.EAX[31-24]
112 u32 intel_type :8;
113 };
114 struct {
115 // CPUID 0x80000026.EBX
116 u32 amd_num_processors :16,
117 amd_power_eff_ranking :8,
118 amd_native_model_id :4,
119 amd_type :4;
120 };
121 };
122 };
123
124 struct cpuinfo_x86 {
125 union {
126 /*
127 * The particular ordering (low-to-high) of (vendor,
128 * family, model) is done in case range of models, like
129 * it is usually done on AMD, need to be compared.
130 */
131 struct {
132 __u8 x86_model;
133 /* CPU family */
134 __u8 x86;
135 /* CPU vendor */
136 __u8 x86_vendor;
137 __u8 x86_reserved;
138 };
139 /* combined vendor, family, model */
140 __u32 x86_vfm;
141 };
142 __u8 x86_stepping;
143 union {
144 // MSR_IA32_PLATFORM_ID[52-50]
145 __u8 intel_platform_id;
146 __u8 amd_unused;
147 };
148 #ifdef CONFIG_X86_64
149 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
150 int x86_tlbsize;
151 #endif
152 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
153 __u32 vmx_capability[NVMXINTS];
154 #endif
155 __u8 x86_virt_bits;
156 __u8 x86_phys_bits;
157 /* Max extended CPUID function supported: */
158 __u32 extended_cpuid_level;
159 /* Maximum supported CPUID level, -1=no CPUID: */
160 int cpuid_level;
161 /*
162 * Align to size of unsigned long because the x86_capability array
163 * is passed to bitops which require the alignment. Use unnamed
164 * union to enforce the array is aligned to size of unsigned long.
165 */
166 union {
167 __u32 x86_capability[NCAPINTS + NBUGINTS];
168 unsigned long x86_capability_alignment;
169 };
170 char x86_vendor_id[16];
171 char x86_model_id[64];
172 struct cpuinfo_topology topo;
173 /* in KB - valid for CPUS which support this call: */
174 unsigned int x86_cache_size;
175 int x86_cache_alignment; /* In bytes */
176 /* Cache QoS architectural values, valid only on the BSP: */
177 int x86_cache_max_rmid; /* max index */
178 int x86_cache_occ_scale; /* scale to bytes */
179 int x86_cache_mbm_width_offset;
180 int x86_power;
181 unsigned long loops_per_jiffy;
182 /* protected processor identification number */
183 u64 ppin;
184 u16 x86_clflush_size;
185 /* number of cores as seen by the OS: */
186 u16 booted_cores;
187 /* Index into per_cpu list: */
188 u16 cpu_index;
189 /* Is SMT active on this core? */
190 bool smt_active;
191 u32 microcode;
192 /* Address space bits used by the cache internally */
193 u8 x86_cache_bits;
194 unsigned initialized : 1;
195 } __randomize_layout;
196
197 #define X86_VENDOR_INTEL 0
198 #define X86_VENDOR_CYRIX 1
199 #define X86_VENDOR_AMD 2
200 #define X86_VENDOR_UMC 3
201 #define X86_VENDOR_CENTAUR 5
202 #define X86_VENDOR_TRANSMETA 7
203 #define X86_VENDOR_NSC 8
204 #define X86_VENDOR_HYGON 9
205 #define X86_VENDOR_ZHAOXIN 10
206 #define X86_VENDOR_VORTEX 11
207 #define X86_VENDOR_NUM 12
208
209 #define X86_VENDOR_UNKNOWN 0xff
210
211 /*
212 * capabilities of CPUs
213 */
214 extern struct cpuinfo_x86 boot_cpu_data;
215 extern struct cpuinfo_x86 new_cpu_data;
216
217 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
218 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
219
220 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
221 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
222
223 extern const struct seq_operations cpuinfo_op;
224
225 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
226
227 extern void cpu_detect(struct cpuinfo_x86 *c);
228
l1tf_pfn_limit(void)229 static inline unsigned long long l1tf_pfn_limit(void)
230 {
231 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
232 }
233
234 void init_cpu_devs(void);
235 void get_cpu_vendor(struct cpuinfo_x86 *c);
236 extern void early_cpu_init(void);
237 extern void identify_secondary_cpu(unsigned int cpu);
238 extern void print_cpu_info(struct cpuinfo_x86 *);
239 void print_cpu_msr(struct cpuinfo_x86 *);
240
241 /*
242 * Friendlier CR3 helpers.
243 */
read_cr3_pa(void)244 static inline unsigned long read_cr3_pa(void)
245 {
246 return __read_cr3() & CR3_ADDR_MASK;
247 }
248
native_read_cr3_pa(void)249 static inline unsigned long native_read_cr3_pa(void)
250 {
251 return __native_read_cr3() & CR3_ADDR_MASK;
252 }
253
load_cr3(pgd_t * pgdir)254 static inline void load_cr3(pgd_t *pgdir)
255 {
256 write_cr3(__sme_pa(pgdir));
257 }
258
259 /*
260 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
261 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
262 * unrelated to the task-switch mechanism:
263 */
264 #ifdef CONFIG_X86_32
265 /* This is the TSS defined by the hardware. */
266 struct x86_hw_tss {
267 unsigned short back_link, __blh;
268 unsigned long sp0;
269 unsigned short ss0, __ss0h;
270 unsigned long sp1;
271
272 /*
273 * We don't use ring 1, so ss1 is a convenient scratch space in
274 * the same cacheline as sp0. We use ss1 to cache the value in
275 * MSR_IA32_SYSENTER_CS. When we context switch
276 * MSR_IA32_SYSENTER_CS, we first check if the new value being
277 * written matches ss1, and, if it's not, then we wrmsr the new
278 * value and update ss1.
279 *
280 * The only reason we context switch MSR_IA32_SYSENTER_CS is
281 * that we set it to zero in vm86 tasks to avoid corrupting the
282 * stack if we were to go through the sysenter path from vm86
283 * mode.
284 */
285 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
286
287 unsigned short __ss1h;
288 unsigned long sp2;
289 unsigned short ss2, __ss2h;
290 unsigned long __cr3;
291 unsigned long ip;
292 unsigned long flags;
293 unsigned long ax;
294 unsigned long cx;
295 unsigned long dx;
296 unsigned long bx;
297 unsigned long sp;
298 unsigned long bp;
299 unsigned long si;
300 unsigned long di;
301 unsigned short es, __esh;
302 unsigned short cs, __csh;
303 unsigned short ss, __ssh;
304 unsigned short ds, __dsh;
305 unsigned short fs, __fsh;
306 unsigned short gs, __gsh;
307 unsigned short ldt, __ldth;
308 unsigned short trace;
309 unsigned short io_bitmap_base;
310
311 } __attribute__((packed));
312 #else
313 struct x86_hw_tss {
314 u32 reserved1;
315 u64 sp0;
316 u64 sp1;
317
318 /*
319 * Since Linux does not use ring 2, the 'sp2' slot is unused by
320 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
321 * the user RSP value.
322 */
323 u64 sp2;
324
325 u64 reserved2;
326 u64 ist[7];
327 u32 reserved3;
328 u32 reserved4;
329 u16 reserved5;
330 u16 io_bitmap_base;
331
332 } __attribute__((packed));
333 #endif
334
335 /*
336 * IO-bitmap sizes:
337 */
338 #define IO_BITMAP_BITS 65536
339 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE)
340 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long))
341
342 #define IO_BITMAP_OFFSET_VALID_MAP \
343 (offsetof(struct tss_struct, io_bitmap.bitmap) - \
344 offsetof(struct tss_struct, x86_tss))
345
346 #define IO_BITMAP_OFFSET_VALID_ALL \
347 (offsetof(struct tss_struct, io_bitmap.mapall) - \
348 offsetof(struct tss_struct, x86_tss))
349
350 #ifdef CONFIG_X86_IOPL_IOPERM
351 /*
352 * sizeof(unsigned long) coming from an extra "long" at the end of the
353 * iobitmap. The limit is inclusive, i.e. the last valid byte.
354 */
355 # define __KERNEL_TSS_LIMIT \
356 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
357 sizeof(unsigned long) - 1)
358 #else
359 # define __KERNEL_TSS_LIMIT \
360 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
361 #endif
362
363 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
364 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1)
365
366 struct entry_stack {
367 char stack[PAGE_SIZE];
368 };
369
370 struct entry_stack_page {
371 struct entry_stack stack;
372 } __aligned(PAGE_SIZE);
373
374 /*
375 * All IO bitmap related data stored in the TSS:
376 */
377 struct x86_io_bitmap {
378 /* The sequence number of the last active bitmap. */
379 u64 prev_sequence;
380
381 /*
382 * Store the dirty size of the last io bitmap offender. The next
383 * one will have to do the cleanup as the switch out to a non io
384 * bitmap user will just set x86_tss.io_bitmap_base to a value
385 * outside of the TSS limit. So for sane tasks there is no need to
386 * actually touch the io_bitmap at all.
387 */
388 unsigned int prev_max;
389
390 /*
391 * The extra 1 is there because the CPU will access an
392 * additional byte beyond the end of the IO permission
393 * bitmap. The extra byte must be all 1 bits, and must
394 * be within the limit.
395 */
396 unsigned long bitmap[IO_BITMAP_LONGS + 1];
397
398 /*
399 * Special I/O bitmap to emulate IOPL(3). All bytes zero,
400 * except the additional byte at the end.
401 */
402 unsigned long mapall[IO_BITMAP_LONGS + 1];
403 };
404
405 struct tss_struct {
406 /*
407 * The fixed hardware portion. This must not cross a page boundary
408 * at risk of violating the SDM's advice and potentially triggering
409 * errata.
410 */
411 struct x86_hw_tss x86_tss;
412
413 struct x86_io_bitmap io_bitmap;
414 } __aligned(PAGE_SIZE);
415
416 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
417
418 /* Per CPU interrupt stacks */
419 struct irq_stack {
420 char stack[IRQ_STACK_SIZE];
421 } __aligned(IRQ_STACK_SIZE);
422
423 DECLARE_PER_CPU_CACHE_HOT(struct irq_stack *, hardirq_stack_ptr);
424 #ifdef CONFIG_X86_64
425 DECLARE_PER_CPU_CACHE_HOT(bool, hardirq_stack_inuse);
426 #else
427 DECLARE_PER_CPU_CACHE_HOT(struct irq_stack *, softirq_stack_ptr);
428 #endif
429
430 DECLARE_PER_CPU_CACHE_HOT(unsigned long, cpu_current_top_of_stack);
431 /* const-qualified alias provided by the linker. */
432 DECLARE_PER_CPU_CACHE_HOT(const unsigned long __percpu_seg_override,
433 const_cpu_current_top_of_stack);
434
435 #ifdef CONFIG_X86_64
cpu_kernelmode_gs_base(int cpu)436 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
437 {
438 #ifdef CONFIG_SMP
439 return per_cpu_offset(cpu);
440 #else
441 return 0;
442 #endif
443 }
444
445 extern asmlinkage void entry_SYSCALL32_ignore(void);
446
447 /* Save actual FS/GS selectors and bases to current->thread */
448 void current_save_fsgs(void);
449 #endif /* X86_64 */
450
451 struct perf_event;
452
453 struct thread_struct {
454 /* Cached TLS descriptors: */
455 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
456 #ifdef CONFIG_X86_32
457 unsigned long sp0;
458 #endif
459 unsigned long sp;
460 #ifdef CONFIG_X86_32
461 unsigned long sysenter_cs;
462 #else
463 unsigned short es;
464 unsigned short ds;
465 unsigned short fsindex;
466 unsigned short gsindex;
467 #endif
468
469 #ifdef CONFIG_X86_64
470 unsigned long fsbase;
471 unsigned long gsbase;
472 #else
473 /*
474 * XXX: this could presumably be unsigned short. Alternatively,
475 * 32-bit kernels could be taught to use fsindex instead.
476 */
477 unsigned long fs;
478 unsigned long gs;
479 #endif
480
481 /* Save middle states of ptrace breakpoints */
482 struct perf_event *ptrace_bps[HBP_NUM];
483 /* Debug status used for traps, single steps, etc... */
484 unsigned long virtual_dr6;
485 /* Keep track of the exact dr7 value set by the user */
486 unsigned long ptrace_dr7;
487 /* Fault info: */
488 unsigned long cr2;
489 unsigned long trap_nr;
490 unsigned long error_code;
491 #ifdef CONFIG_VM86
492 /* Virtual 86 mode info */
493 struct vm86 *vm86;
494 #endif
495 /* IO permissions: */
496 struct io_bitmap *io_bitmap;
497
498 /*
499 * IOPL. Privilege level dependent I/O permission which is
500 * emulated via the I/O bitmap to prevent user space from disabling
501 * interrupts.
502 */
503 unsigned long iopl_emul;
504
505 unsigned int iopl_warn:1;
506
507 /*
508 * Protection Keys Register for Userspace. Loaded immediately on
509 * context switch. Store it in thread_struct to avoid a lookup in
510 * the tasks's FPU xstate buffer. This value is only valid when a
511 * task is scheduled out. For 'current' the authoritative source of
512 * PKRU is the hardware itself.
513 */
514 u32 pkru;
515
516 #ifdef CONFIG_X86_USER_SHADOW_STACK
517 unsigned long features;
518 unsigned long features_locked;
519
520 struct thread_shstk shstk;
521 #endif
522 };
523
524 #ifdef CONFIG_X86_DEBUG_FPU
525 extern struct fpu *x86_task_fpu(struct task_struct *task);
526 #else
527 # define x86_task_fpu(task) ((struct fpu *)((void *)(task) + sizeof(*(task))))
528 #endif
529
530 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);
531
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)532 static inline void arch_thread_struct_whitelist(unsigned long *offset,
533 unsigned long *size)
534 {
535 fpu_thread_struct_whitelist(offset, size);
536 }
537
538 static inline void
native_load_sp0(unsigned long sp0)539 native_load_sp0(unsigned long sp0)
540 {
541 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
542 }
543
native_swapgs(void)544 static __always_inline void native_swapgs(void)
545 {
546 #ifdef CONFIG_X86_64
547 asm volatile("swapgs" ::: "memory");
548 #endif
549 }
550
current_top_of_stack(void)551 static __always_inline unsigned long current_top_of_stack(void)
552 {
553 /*
554 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
555 * and around vm86 mode and sp0 on x86_64 is special because of the
556 * entry trampoline.
557 */
558 if (IS_ENABLED(CONFIG_USE_X86_SEG_SUPPORT))
559 return this_cpu_read_const(const_cpu_current_top_of_stack);
560
561 return this_cpu_read_stable(cpu_current_top_of_stack);
562 }
563
on_thread_stack(void)564 static __always_inline bool on_thread_stack(void)
565 {
566 return (unsigned long)(current_top_of_stack() -
567 current_stack_pointer) < THREAD_SIZE;
568 }
569
570 #ifdef CONFIG_PARAVIRT_XXL
571 #include <asm/paravirt.h>
572 #else
573
load_sp0(unsigned long sp0)574 static inline void load_sp0(unsigned long sp0)
575 {
576 native_load_sp0(sp0);
577 }
578
579 #endif /* CONFIG_PARAVIRT_XXL */
580
581 unsigned long __get_wchan(struct task_struct *p);
582
583 extern void select_idle_routine(void);
584 extern void amd_e400_c1e_apic_setup(void);
585
586 extern unsigned long boot_option_idle_override;
587
588 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
589 IDLE_POLL};
590
591 extern void enable_sep_cpu(void);
592
593
594 /* Defined in head.S */
595 extern struct desc_ptr early_gdt_descr;
596
597 extern void switch_gdt_and_percpu_base(int);
598 extern void load_direct_gdt(int);
599 extern void load_fixmap_gdt(int);
600 extern void cpu_init(void);
601 extern void cpu_init_exception_handling(bool boot_cpu);
602 extern void cpu_init_replace_early_idt(void);
603 extern void cr4_init(void);
604
605 extern void set_task_blockstep(struct task_struct *task, bool on);
606
607 /* Boot loader type from the setup header: */
608 extern int bootloader_type;
609 extern int bootloader_version;
610
611 extern char ignore_fpu_irq;
612
613 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
614 #define ARCH_HAS_PREFETCHW
615
616 #ifdef CONFIG_X86_32
617 # define BASE_PREFETCH ""
618 # define ARCH_HAS_PREFETCH
619 #else
620 # define BASE_PREFETCH "prefetcht0 %1"
621 #endif
622
623 /*
624 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
625 *
626 * It's not worth to care about 3dnow prefetches for the K6
627 * because they are microcoded there and very slow.
628 */
prefetch(const void * x)629 static inline void prefetch(const void *x)
630 {
631 alternative_input(BASE_PREFETCH, "prefetchnta %1",
632 X86_FEATURE_XMM,
633 "m" (*(const char *)x));
634 }
635
636 /*
637 * 3dnow prefetch to get an exclusive cache line.
638 * Useful for spinlocks to avoid one state transition in the
639 * cache coherency protocol:
640 */
prefetchw(const void * x)641 static __always_inline void prefetchw(const void *x)
642 {
643 alternative_input(BASE_PREFETCH, "prefetchw %1",
644 X86_FEATURE_3DNOWPREFETCH,
645 "m" (*(const char *)x));
646 }
647
648 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
649 TOP_OF_KERNEL_STACK_PADDING)
650
651 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
652
653 #define task_pt_regs(task) \
654 ({ \
655 unsigned long __ptr = (unsigned long)task_stack_page(task); \
656 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
657 ((struct pt_regs *)__ptr) - 1; \
658 })
659
660 #ifdef CONFIG_X86_32
661 #define INIT_THREAD { \
662 .sp0 = TOP_OF_INIT_STACK, \
663 .sysenter_cs = __KERNEL_CS, \
664 }
665
666 #else
667 extern unsigned long __top_init_kernel_stack[];
668
669 #define INIT_THREAD { \
670 .sp = (unsigned long)&__top_init_kernel_stack, \
671 }
672
673 #endif /* CONFIG_X86_64 */
674
675 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
676 unsigned long new_sp);
677
678 /*
679 * This decides where the kernel will search for a free chunk of vm
680 * space during mmap's.
681 */
682 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
683 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
684
685 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
686 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
687
688 /* Get/set a process' ability to use the timestamp counter instruction */
689 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
690 #define SET_TSC_CTL(val) set_tsc_mode((val))
691
692 extern int get_tsc_mode(unsigned long adr);
693 extern int set_tsc_mode(unsigned int val);
694
695 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
696
per_cpu_llc_id(unsigned int cpu)697 static inline u32 per_cpu_llc_id(unsigned int cpu)
698 {
699 return per_cpu(cpu_info.topo.llc_id, cpu);
700 }
701
per_cpu_l2c_id(unsigned int cpu)702 static inline u32 per_cpu_l2c_id(unsigned int cpu)
703 {
704 return per_cpu(cpu_info.topo.l2c_id, cpu);
705 }
706
707 #ifdef CONFIG_CPU_SUP_AMD
708 /*
709 * Issue a DIV 0/1 insn to clear any division data from previous DIV
710 * operations.
711 */
amd_clear_divider(void)712 static __always_inline void amd_clear_divider(void)
713 {
714 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0)
715 :: "a" (0), "d" (0), "r" (1));
716 }
717
718 extern void amd_check_microcode(void);
719 #else
amd_clear_divider(void)720 static inline void amd_clear_divider(void) { }
amd_check_microcode(void)721 static inline void amd_check_microcode(void) { }
722 #endif
723
724 extern unsigned long arch_align_stack(unsigned long sp);
725 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
726 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
727
728 void default_idle(void);
729 #ifdef CONFIG_XEN
730 bool xen_set_default_idle(void);
731 #else
732 #define xen_set_default_idle 0
733 #endif
734
735 void __noreturn stop_this_cpu(void *dummy);
736 void microcode_check(struct cpuinfo_x86 *prev_info);
737 void store_cpu_caps(struct cpuinfo_x86 *info);
738
739 DECLARE_PER_CPU(bool, cache_state_incoherent);
740
741 enum l1tf_mitigations {
742 L1TF_MITIGATION_OFF,
743 L1TF_MITIGATION_AUTO,
744 L1TF_MITIGATION_FLUSH_NOWARN,
745 L1TF_MITIGATION_FLUSH,
746 L1TF_MITIGATION_FLUSH_NOSMT,
747 L1TF_MITIGATION_FULL,
748 L1TF_MITIGATION_FULL_FORCE
749 };
750
751 extern enum l1tf_mitigations l1tf_mitigation;
752
753 enum mds_mitigations {
754 MDS_MITIGATION_OFF,
755 MDS_MITIGATION_AUTO,
756 MDS_MITIGATION_FULL,
757 MDS_MITIGATION_VMWERV,
758 };
759
760 extern bool gds_ucode_mitigated(void);
761
762 /*
763 * Make previous memory operations globally visible before
764 * a WRMSR.
765 *
766 * MFENCE makes writes visible, but only affects load/store
767 * instructions. WRMSR is unfortunately not a load/store
768 * instruction and is unaffected by MFENCE. The LFENCE ensures
769 * that the WRMSR is not reordered.
770 *
771 * Most WRMSRs are full serializing instructions themselves and
772 * do not require this barrier. This is only required for the
773 * IA32_TSC_DEADLINE and X2APIC MSRs.
774 */
weak_wrmsr_fence(void)775 static inline void weak_wrmsr_fence(void)
776 {
777 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE));
778 }
779
780 #endif /* _ASM_X86_PROCESSOR_H */
781