1 #ifndef X86_SVM_H
2 #define X86_SVM_H
3
4 #include "libcflat.h"
5
6 enum {
7 INTERCEPT_INTR,
8 INTERCEPT_NMI,
9 INTERCEPT_SMI,
10 INTERCEPT_INIT,
11 INTERCEPT_VINTR,
12 INTERCEPT_SELECTIVE_CR0,
13 INTERCEPT_STORE_IDTR,
14 INTERCEPT_STORE_GDTR,
15 INTERCEPT_STORE_LDTR,
16 INTERCEPT_STORE_TR,
17 INTERCEPT_LOAD_IDTR,
18 INTERCEPT_LOAD_GDTR,
19 INTERCEPT_LOAD_LDTR,
20 INTERCEPT_LOAD_TR,
21 INTERCEPT_RDTSC,
22 INTERCEPT_RDPMC,
23 INTERCEPT_PUSHF,
24 INTERCEPT_POPF,
25 INTERCEPT_CPUID,
26 INTERCEPT_RSM,
27 INTERCEPT_IRET,
28 INTERCEPT_INTn,
29 INTERCEPT_INVD,
30 INTERCEPT_PAUSE,
31 INTERCEPT_HLT,
32 INTERCEPT_INVLPG,
33 INTERCEPT_INVLPGA,
34 INTERCEPT_IOIO_PROT,
35 INTERCEPT_MSR_PROT,
36 INTERCEPT_TASK_SWITCH,
37 INTERCEPT_FERR_FREEZE,
38 INTERCEPT_SHUTDOWN,
39 INTERCEPT_VMRUN,
40 INTERCEPT_VMMCALL,
41 INTERCEPT_VMLOAD,
42 INTERCEPT_VMSAVE,
43 INTERCEPT_STGI,
44 INTERCEPT_CLGI,
45 INTERCEPT_SKINIT,
46 INTERCEPT_RDTSCP,
47 INTERCEPT_ICEBP,
48 INTERCEPT_WBINVD,
49 INTERCEPT_MONITOR,
50 INTERCEPT_MWAIT,
51 INTERCEPT_MWAIT_COND,
52 };
53
54 enum {
55 VMCB_CLEAN_INTERCEPTS = 1, /* Intercept vectors, TSC offset, pause filter count */
56 VMCB_CLEAN_PERM_MAP = 2, /* IOPM Base and MSRPM Base */
57 VMCB_CLEAN_ASID = 4, /* ASID */
58 VMCB_CLEAN_INTR = 8, /* int_ctl, int_vector */
59 VMCB_CLEAN_NPT = 16, /* npt_en, nCR3, gPAT */
60 VMCB_CLEAN_CR = 32, /* CR0, CR3, CR4, EFER */
61 VMCB_CLEAN_DR = 64, /* DR6, DR7 */
62 VMCB_CLEAN_DT = 128, /* GDT, IDT */
63 VMCB_CLEAN_SEG = 256, /* CS, DS, SS, ES, CPL */
64 VMCB_CLEAN_CR2 = 512, /* CR2 only */
65 VMCB_CLEAN_LBR = 1024, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
66 VMCB_CLEAN_AVIC = 2048, /* APIC_BAR, APIC_BACKING_PAGE,
67 PHYSICAL_TABLE pointer, LOGICAL_TABLE pointer */
68 VMCB_CLEAN_ALL = 4095,
69 };
70
71 struct __attribute__ ((__packed__)) vmcb_control_area {
72 u16 intercept_cr_read;
73 u16 intercept_cr_write;
74 u16 intercept_dr_read;
75 u16 intercept_dr_write;
76 u32 intercept_exceptions;
77 u64 intercept;
78 u8 reserved_1[40];
79 u16 pause_filter_thresh;
80 u16 pause_filter_count;
81 u64 iopm_base_pa;
82 u64 msrpm_base_pa;
83 u64 tsc_offset;
84 u32 asid;
85 u8 tlb_ctl;
86 u8 reserved_2[3];
87 u32 int_ctl;
88 u32 int_vector;
89 u32 int_state;
90 u8 reserved_3[4];
91 u32 exit_code;
92 u32 exit_code_hi;
93 u64 exit_info_1;
94 u64 exit_info_2;
95 u32 exit_int_info;
96 u32 exit_int_info_err;
97 u64 nested_ctl;
98 u8 reserved_4[16];
99 u32 event_inj;
100 u32 event_inj_err;
101 u64 nested_cr3;
102 u64 virt_ext;
103 u32 clean;
104 u32 reserved_5;
105 u64 next_rip;
106 u8 insn_len;
107 u8 insn_bytes[15];
108 u8 reserved_6[800];
109 };
110
111 #define TLB_CONTROL_DO_NOTHING 0
112 #define TLB_CONTROL_FLUSH_ALL_ASID 1
113
114 #define V_TPR_MASK 0x0f
115
116 #define V_IRQ_SHIFT 8
117 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
118
119 #define V_GIF_ENABLED_SHIFT 25
120 #define V_GIF_ENABLED_MASK (1 << V_GIF_ENABLED_SHIFT)
121
122 #define V_GIF_SHIFT 9
123 #define V_GIF_MASK (1 << V_GIF_SHIFT)
124
125 #define V_INTR_PRIO_SHIFT 16
126 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
127
128 #define V_IGN_TPR_SHIFT 20
129 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
130
131 #define V_INTR_MASKING_SHIFT 24
132 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
133
134 #define V_NMI_PENDING_SHIFT 11
135 #define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
136 #define V_NMI_BLOCKING_SHIFT 12
137 #define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
138 #define V_NMI_ENABLE_SHIFT 26
139 #define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
140
141 #define SVM_INTERRUPT_SHADOW_MASK 1
142
143 #define SVM_IOIO_STR_SHIFT 2
144 #define SVM_IOIO_REP_SHIFT 3
145 #define SVM_IOIO_SIZE_SHIFT 4
146 #define SVM_IOIO_ASIZE_SHIFT 7
147
148 #define SVM_IOIO_TYPE_MASK 1
149 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
150 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
151 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
152 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
153
154 #define SVM_VM_CR_VALID_MASK 0x001fULL
155 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
156 #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
157
158 #define TSC_RATIO_DEFAULT 0x0100000000ULL
159
160 struct __attribute__ ((__packed__)) vmcb_seg {
161 u16 selector;
162 u16 attrib;
163 u32 limit;
164 u64 base;
165 };
166
167 struct __attribute__ ((__packed__)) vmcb_save_area {
168 struct vmcb_seg es;
169 struct vmcb_seg cs;
170 struct vmcb_seg ss;
171 struct vmcb_seg ds;
172 struct vmcb_seg fs;
173 struct vmcb_seg gs;
174 struct vmcb_seg gdtr;
175 struct vmcb_seg ldtr;
176 struct vmcb_seg idtr;
177 struct vmcb_seg tr;
178 u8 reserved_1[43];
179 u8 cpl;
180 u8 reserved_2[4];
181 u64 efer;
182 u8 reserved_3[112];
183 u64 cr4;
184 u64 cr3;
185 u64 cr0;
186 u64 dr7;
187 u64 dr6;
188 u64 rflags;
189 u64 rip;
190 u8 reserved_4[88];
191 u64 rsp;
192 u8 reserved_5[24];
193 u64 rax;
194 u64 star;
195 u64 lstar;
196 u64 cstar;
197 u64 sfmask;
198 u64 kernel_gs_base;
199 u64 sysenter_cs;
200 u64 sysenter_esp;
201 u64 sysenter_eip;
202 u64 cr2;
203 u8 reserved_6[32];
204 u64 g_pat;
205 u64 dbgctl;
206 u64 br_from;
207 u64 br_to;
208 u64 last_excp_from;
209 u64 last_excp_to;
210 };
211
212 struct __attribute__ ((__packed__)) vmcb {
213 struct vmcb_control_area control;
214 struct vmcb_save_area save;
215 };
216
217 #define SVM_CPUID_FEATURE_SHIFT 2
218 #define SVM_CPUID_FUNC 0x8000000a
219
220 #define SVM_VM_CR_SVM_DISABLE 4
221
222 #define SVM_SELECTOR_S_SHIFT 4
223 #define SVM_SELECTOR_DPL_SHIFT 5
224 #define SVM_SELECTOR_P_SHIFT 7
225 #define SVM_SELECTOR_AVL_SHIFT 8
226 #define SVM_SELECTOR_L_SHIFT 9
227 #define SVM_SELECTOR_DB_SHIFT 10
228 #define SVM_SELECTOR_G_SHIFT 11
229
230 #define SVM_SELECTOR_TYPE_MASK (0xf)
231 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
232 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
233 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
234 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
235 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
236 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
237 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
238
239 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
240 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
241 #define SVM_SELECTOR_CODE_MASK (1 << 3)
242
243 #define INTERCEPT_CR0_MASK 1
244 #define INTERCEPT_CR3_MASK (1 << 3)
245 #define INTERCEPT_CR4_MASK (1 << 4)
246 #define INTERCEPT_CR8_MASK (1 << 8)
247
248 #define INTERCEPT_DR0_MASK 1
249 #define INTERCEPT_DR1_MASK (1 << 1)
250 #define INTERCEPT_DR2_MASK (1 << 2)
251 #define INTERCEPT_DR3_MASK (1 << 3)
252 #define INTERCEPT_DR4_MASK (1 << 4)
253 #define INTERCEPT_DR5_MASK (1 << 5)
254 #define INTERCEPT_DR6_MASK (1 << 6)
255 #define INTERCEPT_DR7_MASK (1 << 7)
256
257 #define SVM_EVTINJ_VEC_MASK 0xff
258
259 #define SVM_EVTINJ_TYPE_SHIFT 8
260 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
261
262 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
263 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
264 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
265 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
266
267 #define SVM_EVTINJ_VALID (1 << 31)
268 #define SVM_EVTINJ_VALID_ERR (1 << 11)
269
270 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
271 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
272
273 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
274 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
275 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
276 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
277
278 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
279 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
280
281 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
282 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
283 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
284
285 #define SVM_EXIT_READ_CR0 0x000
286 #define SVM_EXIT_READ_CR3 0x003
287 #define SVM_EXIT_READ_CR4 0x004
288 #define SVM_EXIT_READ_CR8 0x008
289 #define SVM_EXIT_WRITE_CR0 0x010
290 #define SVM_EXIT_WRITE_CR3 0x013
291 #define SVM_EXIT_WRITE_CR4 0x014
292 #define SVM_EXIT_WRITE_CR8 0x018
293 #define SVM_EXIT_READ_DR0 0x020
294 #define SVM_EXIT_READ_DR1 0x021
295 #define SVM_EXIT_READ_DR2 0x022
296 #define SVM_EXIT_READ_DR3 0x023
297 #define SVM_EXIT_READ_DR4 0x024
298 #define SVM_EXIT_READ_DR5 0x025
299 #define SVM_EXIT_READ_DR6 0x026
300 #define SVM_EXIT_READ_DR7 0x027
301 #define SVM_EXIT_WRITE_DR0 0x030
302 #define SVM_EXIT_WRITE_DR1 0x031
303 #define SVM_EXIT_WRITE_DR2 0x032
304 #define SVM_EXIT_WRITE_DR3 0x033
305 #define SVM_EXIT_WRITE_DR4 0x034
306 #define SVM_EXIT_WRITE_DR5 0x035
307 #define SVM_EXIT_WRITE_DR6 0x036
308 #define SVM_EXIT_WRITE_DR7 0x037
309 #define SVM_EXIT_EXCP_BASE 0x040
310 #define SVM_EXIT_INTR 0x060
311 #define SVM_EXIT_NMI 0x061
312 #define SVM_EXIT_SMI 0x062
313 #define SVM_EXIT_INIT 0x063
314 #define SVM_EXIT_VINTR 0x064
315 #define SVM_EXIT_CR0_SEL_WRITE 0x065
316 #define SVM_EXIT_IDTR_READ 0x066
317 #define SVM_EXIT_GDTR_READ 0x067
318 #define SVM_EXIT_LDTR_READ 0x068
319 #define SVM_EXIT_TR_READ 0x069
320 #define SVM_EXIT_IDTR_WRITE 0x06a
321 #define SVM_EXIT_GDTR_WRITE 0x06b
322 #define SVM_EXIT_LDTR_WRITE 0x06c
323 #define SVM_EXIT_TR_WRITE 0x06d
324 #define SVM_EXIT_RDTSC 0x06e
325 #define SVM_EXIT_RDPMC 0x06f
326 #define SVM_EXIT_PUSHF 0x070
327 #define SVM_EXIT_POPF 0x071
328 #define SVM_EXIT_CPUID 0x072
329 #define SVM_EXIT_RSM 0x073
330 #define SVM_EXIT_IRET 0x074
331 #define SVM_EXIT_SWINT 0x075
332 #define SVM_EXIT_INVD 0x076
333 #define SVM_EXIT_PAUSE 0x077
334 #define SVM_EXIT_HLT 0x078
335 #define SVM_EXIT_INVLPG 0x079
336 #define SVM_EXIT_INVLPGA 0x07a
337 #define SVM_EXIT_IOIO 0x07b
338 #define SVM_EXIT_MSR 0x07c
339 #define SVM_EXIT_TASK_SWITCH 0x07d
340 #define SVM_EXIT_FERR_FREEZE 0x07e
341 #define SVM_EXIT_SHUTDOWN 0x07f
342 #define SVM_EXIT_VMRUN 0x080
343 #define SVM_EXIT_VMMCALL 0x081
344 #define SVM_EXIT_VMLOAD 0x082
345 #define SVM_EXIT_VMSAVE 0x083
346 #define SVM_EXIT_STGI 0x084
347 #define SVM_EXIT_CLGI 0x085
348 #define SVM_EXIT_SKINIT 0x086
349 #define SVM_EXIT_RDTSCP 0x087
350 #define SVM_EXIT_ICEBP 0x088
351 #define SVM_EXIT_WBINVD 0x089
352 #define SVM_EXIT_MONITOR 0x08a
353 #define SVM_EXIT_MWAIT 0x08b
354 #define SVM_EXIT_MWAIT_COND 0x08c
355 #define SVM_EXIT_NPF 0x400
356
357 #define SVM_EXIT_ERR -1
358
359 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
360
361 #define SVM_CR0_RESERVED_MASK 0xffffffff00000000U
362 #define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U
363 #define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U
364 #define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U
365 #define SVM_CR4_LEGACY_RESERVED_MASK 0xfe08e000U
366 #define SVM_CR4_RESERVED_MASK 0xfffffffffe08e000U
367 #define SVM_DR6_RESERVED_MASK 0xffffffffffff1ff0U
368 #define SVM_DR7_RESERVED_MASK 0xffffffff0000cc00U
369 #define SVM_EFER_RESERVED_MASK 0xffffffffffff0200U
370
371 #define MSR_BITMAP_SIZE 8192
372
373 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
374
375 struct svm_test {
376 const char *name;
377 bool (*supported)(void);
378 void (*prepare)(struct svm_test *test);
379 void (*prepare_gif_clear)(struct svm_test *test);
380 void (*guest_func)(struct svm_test *test);
381 bool (*finished)(struct svm_test *test);
382 bool (*succeeded)(struct svm_test *test);
383 int exits;
384 ulong scratch;
385 /* Alternative test interface. */
386 void (*v2)(void);
387 int on_vcpu;
388 bool on_vcpu_done;
389 };
390
391 struct regs {
392 u64 rax;
393 u64 rbx;
394 u64 rcx;
395 u64 rdx;
396 u64 cr2;
397 u64 rbp;
398 u64 rsi;
399 u64 rdi;
400 u64 r8;
401 u64 r9;
402 u64 r10;
403 u64 r11;
404 u64 r12;
405 u64 r13;
406 u64 r14;
407 u64 r15;
408 u64 rflags;
409 };
410
411 typedef void (*test_guest_func)(struct svm_test *);
412
413 int run_svm_tests(int ac, char **av, struct svm_test *svm_tests);
414 u64 *npt_get_pte(u64 address);
415 u64 *npt_get_pde(u64 address);
416 u64 *npt_get_pdpe(u64 address);
417 u64 *npt_get_pml4e(void);
418 bool smp_supported(void);
419 bool default_supported(void);
420 bool vgif_supported(void);
421 bool lbrv_supported(void);
422 bool tsc_scale_supported(void);
423 bool pause_filter_supported(void);
424 bool pause_threshold_supported(void);
425 void default_prepare(struct svm_test *test);
426 void default_prepare_gif_clear(struct svm_test *test);
427 bool default_finished(struct svm_test *test);
428 bool npt_supported(void);
429 bool vnmi_supported(void);
430 int get_test_stage(struct svm_test *test);
431 void set_test_stage(struct svm_test *test, int s);
432 void inc_test_stage(struct svm_test *test);
433 void vmcb_ident(struct vmcb *vmcb);
434 struct regs get_regs(void);
435 void vmmcall(void);
436 void svm_setup_vmrun(u64 rip);
437 int __svm_vmrun(u64 rip);
438 int svm_vmrun(void);
439 void test_set_guest(test_guest_func func);
440
441 extern struct vmcb *vmcb;
442
stgi(void)443 static inline void stgi(void)
444 {
445 asm volatile ("stgi");
446 }
447
clgi(void)448 static inline void clgi(void)
449 {
450 asm volatile ("clgi");
451 }
452
453
454
455 #define SAVE_GPR_C \
456 "xchg %%rbx, regs+0x8\n\t" \
457 "xchg %%rcx, regs+0x10\n\t" \
458 "xchg %%rdx, regs+0x18\n\t" \
459 "xchg %%rbp, regs+0x28\n\t" \
460 "xchg %%rsi, regs+0x30\n\t" \
461 "xchg %%rdi, regs+0x38\n\t" \
462 "xchg %%r8, regs+0x40\n\t" \
463 "xchg %%r9, regs+0x48\n\t" \
464 "xchg %%r10, regs+0x50\n\t" \
465 "xchg %%r11, regs+0x58\n\t" \
466 "xchg %%r12, regs+0x60\n\t" \
467 "xchg %%r13, regs+0x68\n\t" \
468 "xchg %%r14, regs+0x70\n\t" \
469 "xchg %%r15, regs+0x78\n\t"
470
471 #define LOAD_GPR_C SAVE_GPR_C
472
473 #define ASM_PRE_VMRUN_CMD \
474 "vmload %%rax\n\t" \
475 "mov regs+0x80, %%r15\n\t" \
476 "mov %%r15, 0x170(%%rax)\n\t" \
477 "mov regs, %%r15\n\t" \
478 "mov %%r15, 0x1f8(%%rax)\n\t" \
479 LOAD_GPR_C \
480
481 #define ASM_POST_VMRUN_CMD \
482 SAVE_GPR_C \
483 "mov 0x170(%%rax), %%r15\n\t" \
484 "mov %%r15, regs+0x80\n\t" \
485 "mov 0x1f8(%%rax), %%r15\n\t" \
486 "mov %%r15, regs\n\t" \
487 "vmsave %%rax\n\t" \
488
489
490
491 #define SVM_BARE_VMRUN \
492 asm volatile ( \
493 ASM_PRE_VMRUN_CMD \
494 "vmrun %%rax\n\t" \
495 ASM_POST_VMRUN_CMD \
496 : \
497 : "a" (virt_to_phys(vmcb)) \
498 : "memory", "r15") \
499
500 #endif
501