1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2022 Intel Corporation
4 */
5
6 #include <drm/drm_edid.h>
7 #include <drm/drm_eld.h>
8
9 #include "i915_drv.h"
10 #include "intel_crtc_state_dump.h"
11 #include "intel_display_types.h"
12 #include "intel_hdmi.h"
13 #include "intel_vblank.h"
14 #include "intel_vdsc.h"
15 #include "intel_vrr.h"
16
intel_dump_crtc_timings(struct drm_printer * p,const struct drm_display_mode * mode)17 static void intel_dump_crtc_timings(struct drm_printer *p,
18 const struct drm_display_mode *mode)
19 {
20 drm_printf(p, "crtc timings: clock=%d, "
21 "hd=%d hb=%d-%d hs=%d-%d ht=%d, "
22 "vd=%d vb=%d-%d vs=%d-%d vt=%d, "
23 "flags=0x%x\n",
24 mode->crtc_clock,
25 mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end,
26 mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal,
27 mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end,
28 mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal,
29 mode->flags);
30 }
31
32 static void
intel_dump_m_n_config(struct drm_printer * p,const struct intel_crtc_state * pipe_config,const char * id,unsigned int lane_count,const struct intel_link_m_n * m_n)33 intel_dump_m_n_config(struct drm_printer *p,
34 const struct intel_crtc_state *pipe_config,
35 const char *id, unsigned int lane_count,
36 const struct intel_link_m_n *m_n)
37 {
38 drm_printf(p, "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
39 id, lane_count,
40 m_n->data_m, m_n->data_n,
41 m_n->link_m, m_n->link_n, m_n->tu);
42 }
43
44 static void
intel_dump_infoframe(struct drm_i915_private * i915,const union hdmi_infoframe * frame)45 intel_dump_infoframe(struct drm_i915_private *i915,
46 const union hdmi_infoframe *frame)
47 {
48 if (!drm_debug_enabled(DRM_UT_KMS))
49 return;
50
51 hdmi_infoframe_log(KERN_DEBUG, i915->drm.dev, frame);
52 }
53
54 #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
55
56 static const char * const output_type_str[] = {
57 OUTPUT_TYPE(UNUSED),
58 OUTPUT_TYPE(ANALOG),
59 OUTPUT_TYPE(DVO),
60 OUTPUT_TYPE(SDVO),
61 OUTPUT_TYPE(LVDS),
62 OUTPUT_TYPE(TVOUT),
63 OUTPUT_TYPE(HDMI),
64 OUTPUT_TYPE(DP),
65 OUTPUT_TYPE(EDP),
66 OUTPUT_TYPE(DSI),
67 OUTPUT_TYPE(DDI),
68 OUTPUT_TYPE(DP_MST),
69 };
70
71 #undef OUTPUT_TYPE
72
snprintf_output_types(char * buf,size_t len,unsigned int output_types)73 static void snprintf_output_types(char *buf, size_t len,
74 unsigned int output_types)
75 {
76 char *str = buf;
77 int i;
78
79 str[0] = '\0';
80
81 for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
82 int r;
83
84 if ((output_types & BIT(i)) == 0)
85 continue;
86
87 r = snprintf(str, len, "%s%s",
88 str != buf ? "," : "", output_type_str[i]);
89 if (r >= len)
90 break;
91 str += r;
92 len -= r;
93
94 output_types &= ~BIT(i);
95 }
96
97 WARN_ON_ONCE(output_types != 0);
98 }
99
100 static const char * const output_format_str[] = {
101 [INTEL_OUTPUT_FORMAT_RGB] = "RGB",
102 [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
103 [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
104 };
105
intel_output_format_name(enum intel_output_format format)106 const char *intel_output_format_name(enum intel_output_format format)
107 {
108 if (format >= ARRAY_SIZE(output_format_str))
109 return "invalid";
110 return output_format_str[format];
111 }
112
intel_dump_plane_state(struct drm_printer * p,const struct intel_plane_state * plane_state)113 static void intel_dump_plane_state(struct drm_printer *p,
114 const struct intel_plane_state *plane_state)
115 {
116 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
117 const struct drm_framebuffer *fb = plane_state->hw.fb;
118
119 if (!fb) {
120 drm_printf(p, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
121 plane->base.base.id, plane->base.name,
122 str_yes_no(plane_state->uapi.visible));
123 return;
124 }
125
126 drm_printf(p, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
127 plane->base.base.id, plane->base.name,
128 fb->base.id, fb->width, fb->height, &fb->format->format,
129 fb->modifier, str_yes_no(plane_state->uapi.visible));
130 drm_printf(p, "\trotation: 0x%x, scaler: %d, scaling_filter: %d\n",
131 plane_state->hw.rotation, plane_state->scaler_id, plane_state->hw.scaling_filter);
132 if (plane_state->uapi.visible)
133 drm_printf(p, "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
134 DRM_RECT_FP_ARG(&plane_state->uapi.src),
135 DRM_RECT_ARG(&plane_state->uapi.dst));
136 }
137
138 static void
ilk_dump_csc(struct drm_i915_private * i915,struct drm_printer * p,const char * name,const struct intel_csc_matrix * csc)139 ilk_dump_csc(struct drm_i915_private *i915,
140 struct drm_printer *p,
141 const char *name,
142 const struct intel_csc_matrix *csc)
143 {
144 int i;
145
146 drm_printf(p, "%s: pre offsets: 0x%04x 0x%04x 0x%04x\n", name,
147 csc->preoff[0], csc->preoff[1], csc->preoff[2]);
148
149 for (i = 0; i < 3; i++)
150 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,
151 csc->coeff[3 * i + 0],
152 csc->coeff[3 * i + 1],
153 csc->coeff[3 * i + 2]);
154
155 if (DISPLAY_VER(i915) < 7)
156 return;
157
158 drm_printf(p, "%s: post offsets: 0x%04x 0x%04x 0x%04x\n", name,
159 csc->postoff[0], csc->postoff[1], csc->postoff[2]);
160 }
161
162 static void
vlv_dump_csc(struct drm_printer * p,const char * name,const struct intel_csc_matrix * csc)163 vlv_dump_csc(struct drm_printer *p, const char *name,
164 const struct intel_csc_matrix *csc)
165 {
166 int i;
167
168 for (i = 0; i < 3; i++)
169 drm_printf(p, "%s: coefficients: 0x%04x 0x%04x 0x%04x\n", name,
170 csc->coeff[3 * i + 0],
171 csc->coeff[3 * i + 1],
172 csc->coeff[3 * i + 2]);
173 }
174
intel_crtc_state_dump(const struct intel_crtc_state * pipe_config,struct intel_atomic_state * state,const char * context)175 void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
176 struct intel_atomic_state *state,
177 const char *context)
178 {
179 struct intel_display *display = to_intel_display(pipe_config);
180 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
181 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
182 const struct intel_plane_state *plane_state;
183 struct intel_plane *plane;
184 struct drm_printer p;
185 char buf[64];
186 int i;
187
188 if (!drm_debug_enabled(DRM_UT_KMS))
189 return;
190
191 p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);
192
193 drm_printf(&p, "[CRTC:%d:%s] enable: %s [%s]\n",
194 crtc->base.base.id, crtc->base.name,
195 str_yes_no(pipe_config->hw.enable), context);
196
197 if (!pipe_config->hw.enable)
198 goto dump_planes;
199
200 snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
201 drm_printf(&p, "active: %s, output_types: %s (0x%x), output format: %s, sink format: %s\n",
202 str_yes_no(pipe_config->hw.active),
203 buf, pipe_config->output_types,
204 intel_output_format_name(pipe_config->output_format),
205 intel_output_format_name(pipe_config->sink_format));
206
207 drm_printf(&p, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
208 transcoder_name(pipe_config->cpu_transcoder),
209 pipe_config->pipe_bpp, pipe_config->dither);
210
211 drm_printf(&p, "MST master transcoder: %s\n",
212 transcoder_name(pipe_config->mst_master_transcoder));
213
214 drm_printf(&p, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
215 transcoder_name(pipe_config->master_transcoder),
216 pipe_config->sync_mode_slaves_mask);
217
218 drm_printf(&p, "joiner: %s, pipes: 0x%x\n",
219 intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" :
220 intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no",
221 pipe_config->joiner_pipes);
222
223 drm_printf(&p, "splitter: %s, link count %d, overlap %d\n",
224 str_enabled_disabled(pipe_config->splitter.enable),
225 pipe_config->splitter.link_count,
226 pipe_config->splitter.pixel_overlap);
227
228 if (pipe_config->has_pch_encoder)
229 intel_dump_m_n_config(&p, pipe_config, "fdi",
230 pipe_config->fdi_lanes,
231 &pipe_config->fdi_m_n);
232
233 if (intel_crtc_has_dp_encoder(pipe_config)) {
234 intel_dump_m_n_config(&p, pipe_config, "dp m_n",
235 pipe_config->lane_count,
236 &pipe_config->dp_m_n);
237 intel_dump_m_n_config(&p, pipe_config, "dp m2_n2",
238 pipe_config->lane_count,
239 &pipe_config->dp_m2_n2);
240 drm_printf(&p, "fec: %s, enhanced framing: %s\n",
241 str_enabled_disabled(pipe_config->fec_enable),
242 str_enabled_disabled(pipe_config->enhanced_framing));
243
244 drm_printf(&p, "sdp split: %s\n",
245 str_enabled_disabled(pipe_config->sdp_split_enable));
246
247 drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n",
248 str_enabled_disabled(pipe_config->has_psr &&
249 !pipe_config->has_panel_replay),
250 str_enabled_disabled(pipe_config->has_sel_update),
251 str_enabled_disabled(pipe_config->has_panel_replay),
252 str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
253 drm_printf(&p, "minimum HBlank: %d\n", pipe_config->min_hblank);
254 }
255
256 drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
257 pipe_config->has_audio, pipe_config->has_infoframe,
258 pipe_config->infoframes.enable);
259
260 if (pipe_config->infoframes.enable &
261 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
262 drm_printf(&p, "GCP: 0x%x\n", pipe_config->infoframes.gcp);
263 if (pipe_config->infoframes.enable &
264 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
265 intel_dump_infoframe(i915, &pipe_config->infoframes.avi);
266 if (pipe_config->infoframes.enable &
267 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
268 intel_dump_infoframe(i915, &pipe_config->infoframes.spd);
269 if (pipe_config->infoframes.enable &
270 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
271 intel_dump_infoframe(i915, &pipe_config->infoframes.hdmi);
272 if (pipe_config->infoframes.enable &
273 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
274 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
275 if (pipe_config->infoframes.enable &
276 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
277 intel_dump_infoframe(i915, &pipe_config->infoframes.drm);
278 if (pipe_config->infoframes.enable &
279 intel_hdmi_infoframe_enable(DP_SDP_VSC))
280 drm_dp_vsc_sdp_log(&p, &pipe_config->infoframes.vsc);
281 if (pipe_config->infoframes.enable &
282 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
283 drm_dp_as_sdp_log(&p, &pipe_config->infoframes.as_sdp);
284
285 if (pipe_config->has_audio)
286 drm_print_hex_dump(&p, "ELD: ", pipe_config->eld,
287 drm_eld_size(pipe_config->eld));
288
289 drm_printf(&p, "scanline offset: %d\n",
290 intel_crtc_scanline_offset(pipe_config));
291
292 drm_printf(&p, "vblank delay: %d, framestart delay: %d, MSA timing delay: %d\n",
293 pipe_config->hw.adjusted_mode.crtc_vblank_start -
294 pipe_config->hw.adjusted_mode.crtc_vdisplay,
295 pipe_config->framestart_delay, pipe_config->msa_timing_delay);
296
297 drm_printf(&p, "vrr: %s, vmin: %d, vmax: %d, flipline: %d, pipeline full: %d, guardband: %d vsync start: %d, vsync end: %d\n",
298 str_yes_no(pipe_config->vrr.enable),
299 pipe_config->vrr.vmin, pipe_config->vrr.vmax, pipe_config->vrr.flipline,
300 pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
301 pipe_config->vrr.vsync_start, pipe_config->vrr.vsync_end);
302
303 drm_printf(&p, "vrr: vmin vblank: %d, vmax vblank: %d, vmin vtotal: %d, vmax vtotal: %d\n",
304 intel_vrr_vmin_vblank_start(pipe_config), intel_vrr_vmax_vblank_start(pipe_config),
305 intel_vrr_vmin_vtotal(pipe_config), intel_vrr_vmax_vtotal(pipe_config));
306
307 drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
308 DRM_MODE_ARG(&pipe_config->hw.mode));
309 drm_printf(&p, "adjusted mode: " DRM_MODE_FMT "\n",
310 DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
311 intel_dump_crtc_timings(&p, &pipe_config->hw.adjusted_mode);
312 drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n",
313 DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
314 intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode);
315 drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
316 pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
317 pipe_config->pixel_rate);
318
319 drm_printf(&p, "linetime: %d, ips linetime: %d\n",
320 pipe_config->linetime, pipe_config->ips_linetime);
321
322 if (DISPLAY_VER(i915) >= 9)
323 drm_printf(&p, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d, scaling_filter: %d\n",
324 crtc->num_scalers,
325 pipe_config->scaler_state.scaler_users,
326 pipe_config->scaler_state.scaler_id,
327 pipe_config->hw.scaling_filter);
328
329 if (HAS_GMCH(i915))
330 drm_printf(&p, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
331 pipe_config->gmch_pfit.control,
332 pipe_config->gmch_pfit.pgm_ratios,
333 pipe_config->gmch_pfit.lvds_border_bits);
334 else
335 drm_printf(&p, "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
336 DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
337 str_enabled_disabled(pipe_config->pch_pfit.enabled),
338 str_yes_no(pipe_config->pch_pfit.force_thru));
339
340 drm_printf(&p, "ips: %i, double wide: %i, drrs: %i\n",
341 pipe_config->ips_enabled, pipe_config->double_wide,
342 pipe_config->has_drrs);
343
344 intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);
345
346 if (IS_CHERRYVIEW(i915))
347 drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
348 pipe_config->cgm_mode, pipe_config->gamma_mode,
349 pipe_config->gamma_enable, pipe_config->csc_enable);
350 else
351 drm_printf(&p, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
352 pipe_config->csc_mode, pipe_config->gamma_mode,
353 pipe_config->gamma_enable, pipe_config->csc_enable);
354
355 drm_printf(&p, "pre csc lut: %s%d entries, post csc lut: %d entries\n",
356 pipe_config->pre_csc_lut && pipe_config->pre_csc_lut ==
357 i915->display.color.glk_linear_degamma_lut ? "(linear) " : "",
358 pipe_config->pre_csc_lut ?
359 drm_color_lut_size(pipe_config->pre_csc_lut) : 0,
360 pipe_config->post_csc_lut ?
361 drm_color_lut_size(pipe_config->post_csc_lut) : 0);
362
363 if (DISPLAY_VER(i915) >= 11)
364 ilk_dump_csc(i915, &p, "output csc", &pipe_config->output_csc);
365
366 if (!HAS_GMCH(i915))
367 ilk_dump_csc(i915, &p, "pipe csc", &pipe_config->csc);
368 else if (IS_CHERRYVIEW(i915))
369 vlv_dump_csc(&p, "cgm csc", &pipe_config->csc);
370 else if (IS_VALLEYVIEW(i915))
371 vlv_dump_csc(&p, "wgc csc", &pipe_config->csc);
372
373 intel_vdsc_state_dump(&p, 0, pipe_config);
374
375 dump_planes:
376 if (!state)
377 return;
378
379 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
380 if (plane->pipe == crtc->pipe)
381 intel_dump_plane_state(&p, plane_state);
382 }
383 }
384