1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 *
24 */
25
26 #include <drm/display/drm_dp_dual_mode_helper.h>
27 #include <drm/display/drm_hdmi_helper.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_edid.h>
30
31 #include "i915_reg.h"
32 #include "i915_utils.h"
33 #include "intel_de.h"
34 #include "intel_display_types.h"
35 #include "intel_dp.h"
36 #include "intel_hdmi.h"
37 #include "intel_lspcon.h"
38
39 /* LSPCON OUI Vendor ID(signatures) */
40 #define LSPCON_VENDOR_PARADE_OUI 0x001CF8
41 #define LSPCON_VENDOR_MCA_OUI 0x0060AD
42
43 #define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
44 #define DPCD_PARADE_LSPCON_HDR_STATUS 0x00511
45
46 /* AUX addresses to write MCA AVI IF */
47 #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
48 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF
49 #define LSPCON_MCA_AVI_IF_KICKOFF (1 << 0)
50 #define LSPCON_MCA_AVI_IF_HANDLED (1 << 1)
51
52 /* AUX addresses to write Parade AVI IF */
53 #define LSPCON_PARADE_AVI_IF_WRITE_OFFSET 0x516
54 #define LSPCON_PARADE_AVI_IF_CTRL 0x51E
55 #define LSPCON_PARADE_AVI_IF_KICKOFF (1 << 7)
56 #define LSPCON_PARADE_AVI_IF_DATA_SIZE 32
57
enc_to_intel_lspcon(struct intel_encoder * encoder)58 static struct intel_lspcon *enc_to_intel_lspcon(struct intel_encoder *encoder)
59 {
60 return &enc_to_dig_port(encoder)->lspcon;
61 }
62
lspcon_to_intel_dp(struct intel_lspcon * lspcon)63 static struct intel_dp *lspcon_to_intel_dp(struct intel_lspcon *lspcon)
64 {
65 struct intel_digital_port *dig_port =
66 container_of(lspcon, struct intel_digital_port, lspcon);
67
68 return &dig_port->dp;
69 }
70
lspcon_mode_name(enum drm_lspcon_mode mode)71 static const char *lspcon_mode_name(enum drm_lspcon_mode mode)
72 {
73 switch (mode) {
74 case DRM_LSPCON_MODE_PCON:
75 return "PCON";
76 case DRM_LSPCON_MODE_LS:
77 return "LS";
78 case DRM_LSPCON_MODE_INVALID:
79 return "INVALID";
80 default:
81 MISSING_CASE(mode);
82 return "INVALID";
83 }
84 }
85
lspcon_detect_vendor(struct intel_lspcon * lspcon)86 static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
87 {
88 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
89 struct intel_display *display = to_intel_display(intel_dp);
90 struct drm_dp_dpcd_ident *ident;
91 u32 vendor_oui;
92
93 if (drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd))) {
94 drm_err(display->drm, "Can't read description\n");
95 return false;
96 }
97
98 ident = &intel_dp->desc.ident;
99 vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) |
100 ident->oui[2];
101
102 switch (vendor_oui) {
103 case LSPCON_VENDOR_MCA_OUI:
104 lspcon->vendor = LSPCON_VENDOR_MCA;
105 drm_dbg_kms(display->drm, "Vendor: Mega Chips\n");
106 break;
107
108 case LSPCON_VENDOR_PARADE_OUI:
109 lspcon->vendor = LSPCON_VENDOR_PARADE;
110 drm_dbg_kms(display->drm, "Vendor: Parade Tech\n");
111 break;
112
113 default:
114 drm_err(display->drm, "Invalid/Unknown vendor OUI\n");
115 return false;
116 }
117
118 return true;
119 }
120
get_hdr_status_reg(struct intel_lspcon * lspcon)121 static u32 get_hdr_status_reg(struct intel_lspcon *lspcon)
122 {
123 if (lspcon->vendor == LSPCON_VENDOR_MCA)
124 return DPCD_MCA_LSPCON_HDR_STATUS;
125 else
126 return DPCD_PARADE_LSPCON_HDR_STATUS;
127 }
128
intel_lspcon_detect_hdr_capability(struct intel_digital_port * dig_port)129 bool intel_lspcon_detect_hdr_capability(struct intel_digital_port *dig_port)
130 {
131 struct intel_lspcon *lspcon = &dig_port->lspcon;
132 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
133 struct intel_display *display = to_intel_display(intel_dp);
134 u8 hdr_caps;
135 int ret;
136
137 ret = drm_dp_dpcd_read(&intel_dp->aux, get_hdr_status_reg(lspcon),
138 &hdr_caps, 1);
139
140 if (ret < 0) {
141 drm_dbg_kms(display->drm, "HDR capability detection failed\n");
142 lspcon->hdr_supported = false;
143 } else if (hdr_caps & 0x1) {
144 drm_dbg_kms(display->drm, "LSPCON capable of HDR\n");
145 lspcon->hdr_supported = true;
146 }
147
148 return lspcon->hdr_supported;
149 }
150
lspcon_get_current_mode(struct intel_lspcon * lspcon)151 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
152 {
153 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
154 struct intel_display *display = to_intel_display(intel_dp);
155 enum drm_lspcon_mode current_mode;
156 struct i2c_adapter *ddc = &intel_dp->aux.ddc;
157
158 if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, ¤t_mode)) {
159 drm_dbg_kms(display->drm, "Error reading LSPCON mode\n");
160 return DRM_LSPCON_MODE_INVALID;
161 }
162 return current_mode;
163 }
164
lspcon_get_mode_settle_timeout(struct intel_lspcon * lspcon)165 static int lspcon_get_mode_settle_timeout(struct intel_lspcon *lspcon)
166 {
167 /*
168 * On some CometLake-based device designs the Parade PS175 takes more
169 * than 400ms to settle in PCON mode. 100 reboot trials on one device
170 * resulted in a median settle time of 440ms and a maximum of 444ms.
171 * Even after increasing the timeout to 500ms, 2% of devices still had
172 * this error. So this sets the timeout to 800ms.
173 */
174 return lspcon->vendor == LSPCON_VENDOR_PARADE ? 800 : 400;
175 }
176
lspcon_wait_mode(struct intel_lspcon * lspcon,enum drm_lspcon_mode mode)177 static enum drm_lspcon_mode lspcon_wait_mode(struct intel_lspcon *lspcon,
178 enum drm_lspcon_mode mode)
179 {
180 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
181 struct intel_display *display = to_intel_display(intel_dp);
182 enum drm_lspcon_mode current_mode;
183
184 current_mode = lspcon_get_current_mode(lspcon);
185 if (current_mode == mode)
186 goto out;
187
188 drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n",
189 lspcon_mode_name(mode));
190
191 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode,
192 lspcon_get_mode_settle_timeout(lspcon));
193 if (current_mode != mode)
194 drm_err(display->drm, "LSPCON mode hasn't settled\n");
195
196 out:
197 drm_dbg_kms(display->drm, "Current LSPCON mode %s\n",
198 lspcon_mode_name(current_mode));
199
200 return current_mode;
201 }
202
lspcon_change_mode(struct intel_lspcon * lspcon,enum drm_lspcon_mode mode)203 static int lspcon_change_mode(struct intel_lspcon *lspcon,
204 enum drm_lspcon_mode mode)
205 {
206 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
207 struct intel_display *display = to_intel_display(intel_dp);
208 int err;
209 enum drm_lspcon_mode current_mode;
210 struct i2c_adapter *ddc = &intel_dp->aux.ddc;
211
212 err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, ¤t_mode);
213 if (err) {
214 drm_err(display->drm, "Error reading LSPCON mode\n");
215 return err;
216 }
217
218 if (current_mode == mode) {
219 drm_dbg_kms(display->drm, "Current mode = desired LSPCON mode\n");
220 return 0;
221 }
222
223 err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode,
224 lspcon_get_mode_settle_timeout(lspcon));
225 if (err < 0) {
226 drm_err(display->drm, "LSPCON mode change failed\n");
227 return err;
228 }
229
230 lspcon->mode = mode;
231 drm_dbg_kms(display->drm, "LSPCON mode changed done\n");
232 return 0;
233 }
234
lspcon_wake_native_aux_ch(struct intel_lspcon * lspcon)235 static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon)
236 {
237 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
238 struct intel_display *display = to_intel_display(intel_dp);
239 u8 rev;
240
241 if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
242 &rev) != 1) {
243 drm_dbg_kms(display->drm, "Native AUX CH down\n");
244 return false;
245 }
246
247 drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n",
248 rev >> 4, rev & 0xf);
249
250 return true;
251 }
252
lspcon_probe(struct intel_lspcon * lspcon)253 static bool lspcon_probe(struct intel_lspcon *lspcon)
254 {
255 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
256 struct intel_display *display = to_intel_display(intel_dp);
257 struct i2c_adapter *ddc = &intel_dp->aux.ddc;
258 enum drm_dp_dual_mode_type adaptor_type;
259 enum drm_lspcon_mode expected_mode;
260 int retry;
261
262 expected_mode = lspcon_wake_native_aux_ch(lspcon) ?
263 DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS;
264
265 /* Lets probe the adaptor and check its type */
266 for (retry = 0; retry < 6; retry++) {
267 if (retry)
268 usleep_range(500, 1000);
269
270 adaptor_type = drm_dp_dual_mode_detect(intel_dp->aux.drm_dev, ddc);
271 if (adaptor_type == DRM_DP_DUAL_MODE_LSPCON)
272 break;
273 }
274
275 if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) {
276 drm_dbg_kms(display->drm, "No LSPCON detected, found %s\n",
277 drm_dp_get_dual_mode_type_name(adaptor_type));
278 return false;
279 }
280
281 /* Yay ... got a LSPCON device */
282 drm_dbg_kms(display->drm, "LSPCON detected\n");
283 lspcon->mode = lspcon_wait_mode(lspcon, expected_mode);
284
285 /*
286 * In the SW state machine, lets Put LSPCON in PCON mode only.
287 * In this way, it will work with both HDMI 1.4 sinks as well as HDMI
288 * 2.0 sinks.
289 */
290 if (lspcon->mode != DRM_LSPCON_MODE_PCON) {
291 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) {
292 drm_err(display->drm, "LSPCON mode change to PCON failed\n");
293 return false;
294 }
295 }
296 return true;
297 }
298
lspcon_resume_in_pcon_wa(struct intel_lspcon * lspcon)299 static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon)
300 {
301 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon);
302 struct intel_display *display = to_intel_display(intel_dp);
303 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
304 unsigned long start = jiffies;
305
306 while (1) {
307 if (intel_digital_port_connected(&dig_port->base)) {
308 drm_dbg_kms(display->drm, "LSPCON recovering in PCON mode after %u ms\n",
309 jiffies_to_msecs(jiffies - start));
310 return;
311 }
312
313 if (time_after(jiffies, start + msecs_to_jiffies(1000)))
314 break;
315
316 usleep_range(10000, 15000);
317 }
318
319 drm_dbg_kms(display->drm, "LSPCON DP descriptor mismatch after resume\n");
320 }
321
lspcon_parade_fw_ready(struct drm_dp_aux * aux)322 static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux)
323 {
324 u8 avi_if_ctrl;
325 u8 retry;
326 ssize_t ret;
327
328 /* Check if LSPCON FW is ready for data */
329 for (retry = 0; retry < 5; retry++) {
330 if (retry)
331 usleep_range(200, 300);
332
333 ret = drm_dp_dpcd_read(aux, LSPCON_PARADE_AVI_IF_CTRL,
334 &avi_if_ctrl, 1);
335 if (ret < 0) {
336 drm_err(aux->drm_dev, "Failed to read AVI IF control\n");
337 return false;
338 }
339
340 if ((avi_if_ctrl & LSPCON_PARADE_AVI_IF_KICKOFF) == 0)
341 return true;
342 }
343
344 drm_err(aux->drm_dev, "Parade FW not ready to accept AVI IF\n");
345 return false;
346 }
347
_lspcon_parade_write_infoframe_blocks(struct drm_dp_aux * aux,u8 * avi_buf)348 static bool _lspcon_parade_write_infoframe_blocks(struct drm_dp_aux *aux,
349 u8 *avi_buf)
350 {
351 u8 avi_if_ctrl;
352 u8 block_count = 0;
353 u8 *data;
354 u16 reg;
355 ssize_t ret;
356
357 while (block_count < 4) {
358 if (!lspcon_parade_fw_ready(aux)) {
359 drm_dbg_kms(aux->drm_dev, "LSPCON FW not ready, block %d\n",
360 block_count);
361 return false;
362 }
363
364 reg = LSPCON_PARADE_AVI_IF_WRITE_OFFSET;
365 data = avi_buf + block_count * 8;
366 ret = drm_dp_dpcd_write(aux, reg, data, 8);
367 if (ret < 0) {
368 drm_err(aux->drm_dev, "Failed to write AVI IF block %d\n",
369 block_count);
370 return false;
371 }
372
373 /*
374 * Once a block of data is written, we have to inform the FW
375 * about this by writing into avi infoframe control register:
376 * - set the kickoff bit[7] to 1
377 * - write the block no. to bits[1:0]
378 */
379 reg = LSPCON_PARADE_AVI_IF_CTRL;
380 avi_if_ctrl = LSPCON_PARADE_AVI_IF_KICKOFF | block_count;
381 ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);
382 if (ret < 0) {
383 drm_err(aux->drm_dev, "Failed to update (0x%x), block %d\n",
384 reg, block_count);
385 return false;
386 }
387
388 block_count++;
389 }
390
391 drm_dbg_kms(aux->drm_dev, "Wrote AVI IF blocks successfully\n");
392 return true;
393 }
394
_lspcon_write_avi_infoframe_parade(struct drm_dp_aux * aux,const u8 * frame,ssize_t len)395 static bool _lspcon_write_avi_infoframe_parade(struct drm_dp_aux *aux,
396 const u8 *frame,
397 ssize_t len)
398 {
399 u8 avi_if[LSPCON_PARADE_AVI_IF_DATA_SIZE] = {1, };
400
401 /*
402 * Parade's frames contains 32 bytes of data, divided
403 * into 4 frames:
404 * Token byte (first byte of first frame, must be non-zero)
405 * HB0 to HB2 from AVI IF (3 bytes header)
406 * PB0 to PB27 from AVI IF (28 bytes data)
407 * So it should look like this
408 * first block: | <token> <HB0-HB2> <DB0-DB3> |
409 * next 3 blocks: |<DB4-DB11>|<DB12-DB19>|<DB20-DB28>|
410 */
411
412 if (len > LSPCON_PARADE_AVI_IF_DATA_SIZE - 1) {
413 drm_err(aux->drm_dev, "Invalid length of infoframes\n");
414 return false;
415 }
416
417 memcpy(&avi_if[1], frame, len);
418
419 if (!_lspcon_parade_write_infoframe_blocks(aux, avi_if)) {
420 drm_dbg_kms(aux->drm_dev, "Failed to write infoframe blocks\n");
421 return false;
422 }
423
424 return true;
425 }
426
_lspcon_write_avi_infoframe_mca(struct drm_dp_aux * aux,const u8 * buffer,ssize_t len)427 static bool _lspcon_write_avi_infoframe_mca(struct drm_dp_aux *aux,
428 const u8 *buffer, ssize_t len)
429 {
430 int ret;
431 u32 val = 0;
432 u32 retry;
433 u16 reg;
434 const u8 *data = buffer;
435
436 reg = LSPCON_MCA_AVI_IF_WRITE_OFFSET;
437 while (val < len) {
438 /* DPCD write for AVI IF can fail on a slow FW day, so retry */
439 for (retry = 0; retry < 5; retry++) {
440 ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1);
441 if (ret == 1) {
442 break;
443 } else if (retry < 4) {
444 mdelay(50);
445 continue;
446 } else {
447 drm_err(aux->drm_dev, "DPCD write failed at:0x%x\n", reg);
448 return false;
449 }
450 }
451 val++; reg++; data++;
452 }
453
454 val = 0;
455 reg = LSPCON_MCA_AVI_IF_CTRL;
456 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
457 if (ret < 0) {
458 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
459 return false;
460 }
461
462 /* Indicate LSPCON chip about infoframe, clear bit 1 and set bit 0 */
463 val &= ~LSPCON_MCA_AVI_IF_HANDLED;
464 val |= LSPCON_MCA_AVI_IF_KICKOFF;
465
466 ret = drm_dp_dpcd_write(aux, reg, &val, 1);
467 if (ret < 0) {
468 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
469 return false;
470 }
471
472 val = 0;
473 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
474 if (ret < 0) {
475 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
476 return false;
477 }
478
479 if (val == LSPCON_MCA_AVI_IF_HANDLED)
480 drm_dbg_kms(aux->drm_dev, "AVI IF handled by FW\n");
481
482 return true;
483 }
484
lspcon_write_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,const void * frame,ssize_t len)485 void lspcon_write_infoframe(struct intel_encoder *encoder,
486 const struct intel_crtc_state *crtc_state,
487 unsigned int type,
488 const void *frame, ssize_t len)
489 {
490 struct intel_display *display = to_intel_display(encoder);
491 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
492 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
493 bool ret = true;
494
495 switch (type) {
496 case HDMI_INFOFRAME_TYPE_AVI:
497 if (lspcon->vendor == LSPCON_VENDOR_MCA)
498 ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux,
499 frame, len);
500 else
501 ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux,
502 frame, len);
503 break;
504 case HDMI_PACKET_TYPE_GAMUT_METADATA:
505 drm_dbg_kms(display->drm, "Update HDR metadata for lspcon\n");
506 /* It uses the legacy hsw implementation for the same */
507 hsw_write_infoframe(encoder, crtc_state, type, frame, len);
508 break;
509 default:
510 return;
511 }
512
513 if (!ret) {
514 drm_err(display->drm, "Failed to write infoframes\n");
515 return;
516 }
517 }
518
lspcon_read_infoframe(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type,void * frame,ssize_t len)519 void lspcon_read_infoframe(struct intel_encoder *encoder,
520 const struct intel_crtc_state *crtc_state,
521 unsigned int type,
522 void *frame, ssize_t len)
523 {
524 /* FIXME implement for AVI Infoframe as well */
525 if (type == HDMI_PACKET_TYPE_GAMUT_METADATA)
526 hsw_read_infoframe(encoder, crtc_state, type,
527 frame, len);
528 }
529
lspcon_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)530 void lspcon_set_infoframes(struct intel_encoder *encoder,
531 bool enable,
532 const struct intel_crtc_state *crtc_state,
533 const struct drm_connector_state *conn_state)
534 {
535 struct intel_display *display = to_intel_display(encoder);
536 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
537 struct intel_lspcon *lspcon = &dig_port->lspcon;
538 const struct drm_display_mode *adjusted_mode =
539 &crtc_state->hw.adjusted_mode;
540 union hdmi_infoframe frame;
541 u8 buf[VIDEO_DIP_DATA_SIZE];
542 ssize_t ret;
543
544 if (!lspcon->active) {
545 drm_err(display->drm, "Writing infoframes while LSPCON disabled ?\n");
546 return;
547 }
548
549 /* FIXME precompute infoframes */
550
551 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
552 conn_state->connector,
553 adjusted_mode);
554 if (ret < 0) {
555 drm_err(display->drm, "couldn't fill AVI infoframe\n");
556 return;
557 }
558
559 /*
560 * Currently there is no interface defined to
561 * check user preference between RGB/YCBCR444
562 * or YCBCR420. So the only possible case for
563 * YCBCR444 usage is driving YCBCR420 output
564 * with LSPCON, when pipe is configured for
565 * YCBCR444 output and LSPCON takes care of
566 * downsampling it.
567 */
568 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
569 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
570 else
571 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
572
573 /* Set the Colorspace as per the HDMI spec */
574 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, conn_state);
575
576 /* nonsense combination */
577 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
578 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
579
580 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
581 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
582 conn_state->connector,
583 adjusted_mode,
584 crtc_state->limited_color_range ?
585 HDMI_QUANTIZATION_RANGE_LIMITED :
586 HDMI_QUANTIZATION_RANGE_FULL);
587 } else {
588 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
589 frame.avi.ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
590 }
591
592 drm_hdmi_avi_infoframe_content_type(&frame.avi, conn_state);
593
594 ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf));
595 if (ret < 0) {
596 drm_err(display->drm, "Failed to pack AVI IF\n");
597 return;
598 }
599
600 dig_port->write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI,
601 buf, ret);
602 }
603
_lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux * aux)604 static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux)
605 {
606 int ret;
607 u32 val = 0;
608 u16 reg = LSPCON_MCA_AVI_IF_CTRL;
609
610 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
611 if (ret < 0) {
612 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
613 return false;
614 }
615
616 return val & LSPCON_MCA_AVI_IF_KICKOFF;
617 }
618
_lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux * aux)619 static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux)
620 {
621 int ret;
622 u32 val = 0;
623 u16 reg = LSPCON_PARADE_AVI_IF_CTRL;
624
625 ret = drm_dp_dpcd_read(aux, reg, &val, 1);
626 if (ret < 0) {
627 drm_err(aux->drm_dev, "DPCD read failed, address 0x%x\n", reg);
628 return false;
629 }
630
631 return val & LSPCON_PARADE_AVI_IF_KICKOFF;
632 }
633
lspcon_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)634 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder,
635 const struct intel_crtc_state *pipe_config)
636 {
637 struct intel_display *display = to_intel_display(encoder);
638 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
639 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder);
640 bool infoframes_enabled;
641 u32 val = 0;
642 u32 mask, tmp;
643
644 if (lspcon->vendor == LSPCON_VENDOR_MCA)
645 infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux);
646 else
647 infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux);
648
649 if (infoframes_enabled)
650 val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
651
652 if (lspcon->hdr_supported) {
653 tmp = intel_de_read(display,
654 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
655 mask = VIDEO_DIP_ENABLE_GMP_HSW;
656
657 if (tmp & mask)
658 val |= intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
659 }
660
661 return val;
662 }
663
intel_lspcon_wait_pcon_mode(struct intel_digital_port * dig_port)664 void intel_lspcon_wait_pcon_mode(struct intel_digital_port *dig_port)
665 {
666 struct intel_lspcon *lspcon = &dig_port->lspcon;
667
668 lspcon_wait_mode(lspcon, DRM_LSPCON_MODE_PCON);
669 }
670
intel_lspcon_init(struct intel_digital_port * dig_port)671 bool intel_lspcon_init(struct intel_digital_port *dig_port)
672 {
673 struct intel_display *display = to_intel_display(dig_port);
674 struct intel_dp *intel_dp = &dig_port->dp;
675 struct intel_lspcon *lspcon = &dig_port->lspcon;
676 struct drm_connector *connector = &intel_dp->attached_connector->base;
677
678 lspcon->active = false;
679 lspcon->mode = DRM_LSPCON_MODE_INVALID;
680
681 if (!lspcon_probe(lspcon)) {
682 drm_err(display->drm, "Failed to probe lspcon\n");
683 return false;
684 }
685
686 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) {
687 drm_err(display->drm, "LSPCON DPCD read failed\n");
688 return false;
689 }
690
691 if (!lspcon_detect_vendor(lspcon)) {
692 drm_err(display->drm, "LSPCON vendor detection failed\n");
693 return false;
694 }
695
696 connector->ycbcr_420_allowed = true;
697 lspcon->active = true;
698 drm_dbg_kms(display->drm, "Success: LSPCON init\n");
699 return true;
700 }
701
intel_lspcon_active(struct intel_digital_port * dig_port)702 bool intel_lspcon_active(struct intel_digital_port *dig_port)
703 {
704 struct intel_lspcon *lspcon = &dig_port->lspcon;
705
706 return lspcon->active;
707 }
708
intel_lspcon_infoframes_enabled(struct intel_encoder * encoder,const struct intel_crtc_state * pipe_config)709 u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder,
710 const struct intel_crtc_state *pipe_config)
711 {
712 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
713
714 return dig_port->infoframes_enabled(encoder, pipe_config);
715 }
716
intel_lspcon_resume(struct intel_digital_port * dig_port)717 void intel_lspcon_resume(struct intel_digital_port *dig_port)
718 {
719 struct intel_display *display = to_intel_display(dig_port);
720 struct intel_lspcon *lspcon = &dig_port->lspcon;
721 enum drm_lspcon_mode expected_mode;
722
723 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
724 return;
725
726 if (!lspcon->active) {
727 if (!intel_lspcon_init(dig_port)) {
728 drm_err(display->drm, "LSPCON init failed on port %c\n",
729 port_name(dig_port->base.port));
730 return;
731 }
732 }
733
734 if (lspcon_wake_native_aux_ch(lspcon)) {
735 expected_mode = DRM_LSPCON_MODE_PCON;
736 lspcon_resume_in_pcon_wa(lspcon);
737 } else {
738 expected_mode = DRM_LSPCON_MODE_LS;
739 }
740
741 if (lspcon_wait_mode(lspcon, expected_mode) == DRM_LSPCON_MODE_PCON)
742 return;
743
744 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON))
745 drm_err(display->drm, "LSPCON resume failed\n");
746 else
747 drm_dbg_kms(display->drm, "LSPCON resume success\n");
748 }
749