1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include <drm/display/drm_dp.h>
40
41 #include "i915_drv.h"
42 #include "i915_reg.h"
43 #include "display/intel_display_regs.h"
44 #include "gvt.h"
45 #include "i915_pvinfo.h"
46 #include "intel_mchbar_regs.h"
47 #include "display/bxt_dpio_phy_regs.h"
48 #include "display/i9xx_plane_regs.h"
49 #include "display/intel_crt_regs.h"
50 #include "display/intel_cursor_regs.h"
51 #include "display/intel_display_core.h"
52 #include "display/intel_display_types.h"
53 #include "display/intel_dmc_regs.h"
54 #include "display/intel_dp_aux_regs.h"
55 #include "display/intel_dpio_phy.h"
56 #include "display/intel_fbc.h"
57 #include "display/intel_fdi_regs.h"
58 #include "display/intel_pps_regs.h"
59 #include "display/intel_psr_regs.h"
60 #include "display/intel_sbi_regs.h"
61 #include "display/intel_sprite_regs.h"
62 #include "display/intel_vga_regs.h"
63 #include "display/skl_universal_plane_regs.h"
64 #include "display/skl_watermark_regs.h"
65 #include "display/vlv_dsi_pll_regs.h"
66 #include "gt/intel_gt_regs.h"
67 #include <linux/vmalloc.h>
68
69 /* XXX FIXME i915 has changed PP_XXX definition */
70 #define PCH_PP_STATUS _MMIO(0xc7200)
71 #define PCH_PP_CONTROL _MMIO(0xc7204)
72 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
73 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
74 #define PCH_PP_DIVISOR _MMIO(0xc7210)
75
intel_gvt_get_device_type(struct intel_gvt * gvt)76 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
77 {
78 struct drm_i915_private *i915 = gvt->gt->i915;
79
80 if (IS_BROADWELL(i915))
81 return D_BDW;
82 else if (IS_SKYLAKE(i915))
83 return D_SKL;
84 else if (IS_KABYLAKE(i915))
85 return D_KBL;
86 else if (IS_BROXTON(i915))
87 return D_BXT;
88 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
89 return D_CFL;
90
91 return 0;
92 }
93
intel_gvt_match_device(struct intel_gvt * gvt,unsigned long device)94 static bool intel_gvt_match_device(struct intel_gvt *gvt,
95 unsigned long device)
96 {
97 return intel_gvt_get_device_type(gvt) & device;
98 }
99
read_vreg(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)100 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
101 void *p_data, unsigned int bytes)
102 {
103 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
104 }
105
write_vreg(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)106 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
107 void *p_data, unsigned int bytes)
108 {
109 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
110 }
111
intel_gvt_find_mmio_info(struct intel_gvt * gvt,unsigned int offset)112 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
113 unsigned int offset)
114 {
115 struct intel_gvt_mmio_info *e;
116
117 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
118 if (e->offset == offset)
119 return e;
120 }
121 return NULL;
122 }
123
setup_mmio_info(struct intel_gvt * gvt,u32 offset,u32 size,u16 flags,u32 addr_mask,u32 ro_mask,u32 device,gvt_mmio_func read,gvt_mmio_func write)124 static int setup_mmio_info(struct intel_gvt *gvt, u32 offset, u32 size,
125 u16 flags, u32 addr_mask, u32 ro_mask, u32 device,
126 gvt_mmio_func read, gvt_mmio_func write)
127 {
128 struct intel_gvt_mmio_info *p;
129 u32 start, end, i;
130
131 if (!intel_gvt_match_device(gvt, device))
132 return 0;
133
134 if (WARN_ON(!IS_ALIGNED(offset, 4)))
135 return -EINVAL;
136
137 start = offset;
138 end = offset + size;
139
140 for (i = start; i < end; i += 4) {
141 p = intel_gvt_find_mmio_info(gvt, i);
142 if (!p) {
143 WARN(1, "assign a handler to a non-tracked mmio %x\n",
144 i);
145 return -ENODEV;
146 }
147 p->ro_mask = ro_mask;
148 gvt->mmio.mmio_attribute[i / 4] = flags;
149 if (read)
150 p->read = read;
151 if (write)
152 p->write = write;
153 }
154 return 0;
155 }
156
157 /**
158 * intel_gvt_render_mmio_to_engine - convert a mmio offset into the engine
159 * @gvt: a GVT device
160 * @offset: register offset
161 *
162 * Returns:
163 * The engine containing the offset within its mmio page.
164 */
165 const struct intel_engine_cs *
intel_gvt_render_mmio_to_engine(struct intel_gvt * gvt,unsigned int offset)166 intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int offset)
167 {
168 struct intel_engine_cs *engine;
169 enum intel_engine_id id;
170
171 offset &= ~GENMASK(11, 0);
172 for_each_engine(engine, gvt->gt, id)
173 if (engine->mmio_base == offset)
174 return engine;
175
176 return NULL;
177 }
178
179 #define offset_to_fence_num(offset) \
180 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
181
182 #define fence_num_to_offset(num) \
183 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
184
185
enter_failsafe_mode(struct intel_vgpu * vgpu,int reason)186 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
187 {
188 switch (reason) {
189 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
190 pr_err("Detected your guest driver doesn't support GVT-g.\n");
191 break;
192 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
193 pr_err("Graphics resource is not enough for the guest\n");
194 break;
195 case GVT_FAILSAFE_GUEST_ERR:
196 pr_err("GVT Internal error for the guest\n");
197 break;
198 default:
199 break;
200 }
201 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
202 vgpu->failsafe = true;
203 }
204
sanitize_fence_mmio_access(struct intel_vgpu * vgpu,unsigned int fence_num,void * p_data,unsigned int bytes)205 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
206 unsigned int fence_num, void *p_data, unsigned int bytes)
207 {
208 unsigned int max_fence = vgpu_fence_sz(vgpu);
209
210 if (fence_num >= max_fence) {
211 gvt_vgpu_err("access oob fence reg %d/%d\n",
212 fence_num, max_fence);
213
214 /* When guest access oob fence regs without access
215 * pv_info first, we treat guest not supporting GVT,
216 * and we will let vgpu enter failsafe mode.
217 */
218 if (!vgpu->pv_notified)
219 enter_failsafe_mode(vgpu,
220 GVT_FAILSAFE_UNSUPPORTED_GUEST);
221
222 memset(p_data, 0, bytes);
223 return -EINVAL;
224 }
225 return 0;
226 }
227
gamw_echo_dev_rw_ia_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)228 static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu,
229 unsigned int offset, void *p_data, unsigned int bytes)
230 {
231 u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD;
232
233 if (GRAPHICS_VER(vgpu->gvt->gt->i915) <= 10) {
234 if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD)
235 gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id);
236 else if (!ips)
237 gvt_dbg_core("vgpu%d: ips disabled\n", vgpu->id);
238 else {
239 /* All engines must be enabled together for vGPU,
240 * since we don't know which engine the ppgtt will
241 * bind to when shadowing.
242 */
243 gvt_vgpu_err("Unsupported IPS setting %x, cannot enable 64K gtt.\n",
244 ips);
245 return -EINVAL;
246 }
247 }
248
249 write_vreg(vgpu, offset, p_data, bytes);
250 return 0;
251 }
252
fence_mmio_read(struct intel_vgpu * vgpu,unsigned int off,void * p_data,unsigned int bytes)253 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
254 void *p_data, unsigned int bytes)
255 {
256 int ret;
257
258 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
259 p_data, bytes);
260 if (ret)
261 return ret;
262 read_vreg(vgpu, off, p_data, bytes);
263 return 0;
264 }
265
fence_mmio_write(struct intel_vgpu * vgpu,unsigned int off,void * p_data,unsigned int bytes)266 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
267 void *p_data, unsigned int bytes)
268 {
269 struct intel_gvt *gvt = vgpu->gvt;
270 unsigned int fence_num = offset_to_fence_num(off);
271 intel_wakeref_t wakeref;
272 int ret;
273
274 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
275 if (ret)
276 return ret;
277 write_vreg(vgpu, off, p_data, bytes);
278
279 wakeref = mmio_hw_access_pre(gvt->gt);
280 intel_vgpu_write_fence(vgpu, fence_num,
281 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
282 mmio_hw_access_post(gvt->gt, wakeref);
283 return 0;
284 }
285
286 #define CALC_MODE_MASK_REG(old, new) \
287 (((new) & GENMASK(31, 16)) \
288 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
289 | ((new) & ((new) >> 16))))
290
mul_force_wake_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)291 static int mul_force_wake_write(struct intel_vgpu *vgpu,
292 unsigned int offset, void *p_data, unsigned int bytes)
293 {
294 u32 old, new;
295 u32 ack_reg_offset;
296
297 old = vgpu_vreg(vgpu, offset);
298 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
299
300 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) {
301 switch (offset) {
302 case FORCEWAKE_RENDER_GEN9_REG:
303 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
304 break;
305 case FORCEWAKE_GT_GEN9_REG:
306 ack_reg_offset = FORCEWAKE_ACK_GT_GEN9_REG;
307 break;
308 case FORCEWAKE_MEDIA_GEN9_REG:
309 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
310 break;
311 default:
312 /*should not hit here*/
313 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset);
314 return -EINVAL;
315 }
316 } else {
317 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
318 }
319
320 vgpu_vreg(vgpu, offset) = new;
321 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
322 return 0;
323 }
324
gdrst_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)325 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
326 void *p_data, unsigned int bytes)
327 {
328 intel_engine_mask_t engine_mask = 0;
329 u32 data;
330
331 write_vreg(vgpu, offset, p_data, bytes);
332 data = vgpu_vreg(vgpu, offset);
333
334 if (data & GEN6_GRDOM_FULL) {
335 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
336 engine_mask = ALL_ENGINES;
337 } else {
338 if (data & GEN6_GRDOM_RENDER) {
339 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
340 engine_mask |= BIT(RCS0);
341 }
342 if (data & GEN6_GRDOM_MEDIA) {
343 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
344 engine_mask |= BIT(VCS0);
345 }
346 if (data & GEN6_GRDOM_BLT) {
347 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
348 engine_mask |= BIT(BCS0);
349 }
350 if (data & GEN6_GRDOM_VECS) {
351 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
352 engine_mask |= BIT(VECS0);
353 }
354 if (data & GEN8_GRDOM_MEDIA2) {
355 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
356 engine_mask |= BIT(VCS1);
357 }
358 if (data & GEN9_GRDOM_GUC) {
359 gvt_dbg_mmio("vgpu%d: request GUC Reset\n", vgpu->id);
360 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
361 }
362 engine_mask &= vgpu->gvt->gt->info.engine_mask;
363 }
364
365 /* vgpu_lock already hold by emulate mmio r/w */
366 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
367
368 /* sw will wait for the device to ack the reset request */
369 vgpu_vreg(vgpu, offset) = 0;
370
371 return 0;
372 }
373
gmbus_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)374 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
375 void *p_data, unsigned int bytes)
376 {
377 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
378 }
379
gmbus_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)380 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
381 void *p_data, unsigned int bytes)
382 {
383 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
384 }
385
pch_pp_control_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)386 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
387 unsigned int offset, void *p_data, unsigned int bytes)
388 {
389 write_vreg(vgpu, offset, p_data, bytes);
390
391 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
392 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_ON;
393 vgpu_vreg_t(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
394 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
395 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
396
397 } else
398 vgpu_vreg_t(vgpu, PCH_PP_STATUS) &=
399 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
400 | PP_CYCLE_DELAY_ACTIVE);
401 return 0;
402 }
403
transconf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)404 static int transconf_mmio_write(struct intel_vgpu *vgpu,
405 unsigned int offset, void *p_data, unsigned int bytes)
406 {
407 write_vreg(vgpu, offset, p_data, bytes);
408
409 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
410 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
411 else
412 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
413 return 0;
414 }
415
lcpll_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)416 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
417 void *p_data, unsigned int bytes)
418 {
419 write_vreg(vgpu, offset, p_data, bytes);
420
421 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
422 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
423 else
424 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
425
426 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
427 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
428 else
429 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
430
431 return 0;
432 }
433
dpy_reg_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)434 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
435 void *p_data, unsigned int bytes)
436 {
437 switch (offset) {
438 case 0xe651c:
439 case 0xe661c:
440 case 0xe671c:
441 case 0xe681c:
442 vgpu_vreg(vgpu, offset) = 1 << 17;
443 break;
444 case 0xe6c04:
445 vgpu_vreg(vgpu, offset) = 0x3;
446 break;
447 case 0xe6e1c:
448 vgpu_vreg(vgpu, offset) = 0x2f << 16;
449 break;
450 default:
451 return -EINVAL;
452 }
453
454 read_vreg(vgpu, offset, p_data, bytes);
455 return 0;
456 }
457
458 /*
459 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to
460 * TRANSCODER_A in HW. DDI/PORT could be PORT_x depends on
461 * setup_virtual_dp_monitor().
462 * emulate_monitor_status_change() set up PLL for PORT_x as the initial enabled
463 * DPLL. Later guest driver may setup a different DPLLx when setting mode.
464 * So the correct sequence to find DP stream clock is:
465 * Check TRANS_DDI_FUNC_CTL on TRANSCODER_A to get PORT_x.
466 * Check correct PLLx for PORT_x to get PLL frequency and DP bitrate.
467 * Then Refresh rate then can be calculated based on follow equations:
468 * Pixel clock = h_total * v_total * refresh_rate
469 * stream clock = Pixel clock
470 * ls_clk = DP bitrate
471 * Link M/N = strm_clk / ls_clk
472 */
473
bdw_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)474 static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
475 {
476 u32 dp_br = 0;
477 u32 ddi_pll_sel = vgpu_vreg_t(vgpu, PORT_CLK_SEL(port));
478
479 switch (ddi_pll_sel) {
480 case PORT_CLK_SEL_LCPLL_2700:
481 dp_br = 270000 * 2;
482 break;
483 case PORT_CLK_SEL_LCPLL_1350:
484 dp_br = 135000 * 2;
485 break;
486 case PORT_CLK_SEL_LCPLL_810:
487 dp_br = 81000 * 2;
488 break;
489 case PORT_CLK_SEL_SPLL:
490 {
491 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) {
492 case SPLL_FREQ_810MHz:
493 dp_br = 81000 * 2;
494 break;
495 case SPLL_FREQ_1350MHz:
496 dp_br = 135000 * 2;
497 break;
498 case SPLL_FREQ_2700MHz:
499 dp_br = 270000 * 2;
500 break;
501 default:
502 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n",
503 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL));
504 break;
505 }
506 break;
507 }
508 case PORT_CLK_SEL_WRPLL1:
509 case PORT_CLK_SEL_WRPLL2:
510 {
511 u32 wrpll_ctl;
512 int refclk, n, p, r;
513
514 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1)
515 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL1));
516 else
517 wrpll_ctl = vgpu_vreg_t(vgpu, WRPLL_CTL(DPLL_ID_WRPLL2));
518
519 switch (wrpll_ctl & WRPLL_REF_MASK) {
520 case WRPLL_REF_PCH_SSC:
521 refclk = 135000;
522 break;
523 case WRPLL_REF_LCPLL:
524 refclk = 2700000;
525 break;
526 default:
527 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n",
528 vgpu->id, port_name(port), wrpll_ctl);
529 goto out;
530 }
531
532 r = wrpll_ctl & WRPLL_DIVIDER_REF_MASK;
533 p = (wrpll_ctl & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
534 n = (wrpll_ctl & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
535
536 dp_br = (refclk * n / 10) / (p * r) * 2;
537 break;
538 }
539 default:
540 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n",
541 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, PORT_CLK_SEL(port)));
542 break;
543 }
544
545 out:
546 return dp_br;
547 }
548
bxt_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)549 static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
550 {
551 u32 dp_br = 0;
552 int refclk = 100000;
553 enum dpio_phy phy = DPIO_PHY0;
554 enum dpio_channel ch = DPIO_CH0;
555 struct dpll clock = {};
556 u32 temp;
557
558 /* Port to PHY mapping is fixed, see bxt_ddi_phy_info{} */
559 switch (port) {
560 case PORT_A:
561 phy = DPIO_PHY1;
562 ch = DPIO_CH0;
563 break;
564 case PORT_B:
565 phy = DPIO_PHY0;
566 ch = DPIO_CH0;
567 break;
568 case PORT_C:
569 phy = DPIO_PHY0;
570 ch = DPIO_CH1;
571 break;
572 default:
573 gvt_dbg_dpy("vgpu-%d no PHY for PORT_%c\n", vgpu->id, port_name(port));
574 goto out;
575 }
576
577 temp = vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port));
578 if (!(temp & PORT_PLL_ENABLE) || !(temp & PORT_PLL_LOCK)) {
579 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n",
580 vgpu->id, port_name(port), temp);
581 goto out;
582 }
583
584 clock.m1 = 2;
585 clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK,
586 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22;
587 if (vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 3)) & PORT_PLL_M2_FRAC_ENABLE)
588 clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK,
589 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 2)));
590 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK,
591 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 1)));
592 clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK,
593 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
594 clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK,
595 vgpu_vreg_t(vgpu, BXT_PORT_PLL_EBB_0(phy, ch)));
596 clock.m = clock.m1 * clock.m2;
597 clock.p = clock.p1 * clock.p2 * 5;
598
599 if (clock.n == 0 || clock.p == 0) {
600 gvt_dbg_dpy("vgpu-%d PORT_%c PLL has invalid divider\n", vgpu->id, port_name(port));
601 goto out;
602 }
603
604 clock.vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock.m), clock.n << 22);
605 clock.dot = DIV_ROUND_CLOSEST(clock.vco, clock.p);
606
607 dp_br = clock.dot;
608
609 out:
610 return dp_br;
611 }
612
skl_vgpu_get_dp_bitrate(struct intel_vgpu * vgpu,enum port port)613 static u32 skl_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
614 {
615 u32 dp_br = 0;
616 enum intel_dpll_id dpll_id = DPLL_ID_SKL_DPLL0;
617
618 /* Find the enabled DPLL for the DDI/PORT */
619 if (!(vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port)) &&
620 (vgpu_vreg_t(vgpu, DPLL_CTRL2) & DPLL_CTRL2_DDI_SEL_OVERRIDE(port))) {
621 dpll_id += (vgpu_vreg_t(vgpu, DPLL_CTRL2) &
622 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
623 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
624 } else {
625 gvt_dbg_dpy("vgpu-%d DPLL for PORT_%c isn't turned on\n",
626 vgpu->id, port_name(port));
627 return dp_br;
628 }
629
630 /* Find PLL output frequency from correct DPLL, and get bir rate */
631 switch ((vgpu_vreg_t(vgpu, DPLL_CTRL1) &
632 DPLL_CTRL1_LINK_RATE_MASK(dpll_id)) >>
633 DPLL_CTRL1_LINK_RATE_SHIFT(dpll_id)) {
634 case DPLL_CTRL1_LINK_RATE_810:
635 dp_br = 81000 * 2;
636 break;
637 case DPLL_CTRL1_LINK_RATE_1080:
638 dp_br = 108000 * 2;
639 break;
640 case DPLL_CTRL1_LINK_RATE_1350:
641 dp_br = 135000 * 2;
642 break;
643 case DPLL_CTRL1_LINK_RATE_1620:
644 dp_br = 162000 * 2;
645 break;
646 case DPLL_CTRL1_LINK_RATE_2160:
647 dp_br = 216000 * 2;
648 break;
649 case DPLL_CTRL1_LINK_RATE_2700:
650 dp_br = 270000 * 2;
651 break;
652 default:
653 dp_br = 0;
654 gvt_dbg_dpy("vgpu-%d PORT_%c fail to get DPLL-%d freq\n",
655 vgpu->id, port_name(port), dpll_id);
656 }
657
658 return dp_br;
659 }
660
vgpu_update_refresh_rate(struct intel_vgpu * vgpu)661 static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
662 {
663 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
664 struct intel_display *display = dev_priv->display;
665 enum port port;
666 u32 dp_br, link_m, link_n, htotal, vtotal;
667
668 /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */
669 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &
670 TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
671 if (port != PORT_B && port != PORT_D) {
672 gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port));
673 return;
674 }
675
676 /* Calculate DP bitrate from PLL */
677 if (IS_BROADWELL(dev_priv))
678 dp_br = bdw_vgpu_get_dp_bitrate(vgpu, port);
679 else if (IS_BROXTON(dev_priv))
680 dp_br = bxt_vgpu_get_dp_bitrate(vgpu, port);
681 else
682 dp_br = skl_vgpu_get_dp_bitrate(vgpu, port);
683
684 /* Get DP link symbol clock M/N */
685 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A));
686 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A));
687
688 /* Get H/V total from transcoder timing */
689 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
690 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
691
692 if (dp_br && link_n && htotal && vtotal) {
693 u64 pixel_clk = 0;
694 u32 new_rate = 0;
695 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);
696
697 /* Calculate pixel clock by (ls_clk * M / N) */
698 pixel_clk = div_u64(mul_u32_u32(link_m, dp_br), link_n);
699 pixel_clk *= MSEC_PER_SEC;
700
701 /* Calculate refresh rate by (pixel_clk / (h_total * v_total)) */
702 new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal + 1, vtotal + 1));
703
704 if (*old_rate != new_rate)
705 *old_rate = new_rate;
706
707 gvt_dbg_dpy("vgpu-%d PIPE_%c refresh rate updated to %d\n",
708 vgpu->id, pipe_name(PIPE_A), new_rate);
709 }
710 }
711
pipeconf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)712 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
713 void *p_data, unsigned int bytes)
714 {
715 u32 data;
716
717 write_vreg(vgpu, offset, p_data, bytes);
718 data = vgpu_vreg(vgpu, offset);
719
720 if (data & TRANSCONF_ENABLE) {
721 vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
722 vgpu_update_refresh_rate(vgpu);
723 vgpu_update_vblank_emulation(vgpu, true);
724 } else {
725 vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
726 vgpu_update_vblank_emulation(vgpu, false);
727 }
728 return 0;
729 }
730
731 /* sorted in ascending order */
732 static i915_reg_t force_nonpriv_white_list[] = {
733 _MMIO(0xd80),
734 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
735 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
736 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
737 PS_INVOCATION_COUNT, //_MMIO(0x2348)
738 PS_DEPTH_COUNT, //_MMIO(0x2350)
739 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
740 _MMIO(0x2690),
741 _MMIO(0x2694),
742 _MMIO(0x2698),
743 _MMIO(0x2754),
744 _MMIO(0x28a0),
745 _MMIO(0x4de0),
746 _MMIO(0x4de4),
747 _MMIO(0x4dfc),
748 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
749 _MMIO(0x7014),
750 HDC_CHICKEN0,//_MMIO(0x7300)
751 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
752 _MMIO(0x7700),
753 _MMIO(0x7704),
754 _MMIO(0x7708),
755 _MMIO(0x770c),
756 _MMIO(0x83a8),
757 _MMIO(0xb110),
758 _MMIO(0xb118),
759 _MMIO(0xe100),
760 _MMIO(0xe18c),
761 _MMIO(0xe48c),
762 _MMIO(0xe5f4),
763 _MMIO(0x64844),
764 };
765
766 /* a simple bsearch */
in_whitelist(u32 reg)767 static inline bool in_whitelist(u32 reg)
768 {
769 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
770 i915_reg_t *array = force_nonpriv_white_list;
771
772 while (left < right) {
773 int mid = (left + right)/2;
774
775 if (reg > array[mid].reg)
776 left = mid + 1;
777 else if (reg < array[mid].reg)
778 right = mid;
779 else
780 return true;
781 }
782 return false;
783 }
784
force_nonpriv_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)785 static int force_nonpriv_write(struct intel_vgpu *vgpu,
786 unsigned int offset, void *p_data, unsigned int bytes)
787 {
788 u32 reg_nonpriv = (*(u32 *)p_data) & REG_GENMASK(25, 2);
789 const struct intel_engine_cs *engine =
790 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
791
792 if (bytes != 4 || !IS_ALIGNED(offset, bytes) || !engine) {
793 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
794 vgpu->id, offset, bytes);
795 return -EINVAL;
796 }
797
798 if (!in_whitelist(reg_nonpriv) &&
799 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) {
800 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x at offset %x\n",
801 vgpu->id, reg_nonpriv, offset);
802 } else
803 intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
804
805 return 0;
806 }
807
ddi_buf_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)808 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
809 void *p_data, unsigned int bytes)
810 {
811 write_vreg(vgpu, offset, p_data, bytes);
812
813 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
814 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
815 } else {
816 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
817 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
818 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E))
819 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
820 }
821 return 0;
822 }
823
fdi_rx_iir_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)824 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
825 unsigned int offset, void *p_data, unsigned int bytes)
826 {
827 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
828 return 0;
829 }
830
831 #define FDI_LINK_TRAIN_PATTERN1 0
832 #define FDI_LINK_TRAIN_PATTERN2 1
833
fdi_auto_training_started(struct intel_vgpu * vgpu)834 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
835 {
836 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E));
837 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
838 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E));
839
840 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
841 (rx_ctl & FDI_RX_ENABLE) &&
842 (rx_ctl & FDI_AUTO_TRAINING) &&
843 (tx_ctl & DP_TP_CTL_ENABLE) &&
844 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
845 return 1;
846 else
847 return 0;
848 }
849
check_fdi_rx_train_status(struct intel_vgpu * vgpu,enum pipe pipe,unsigned int train_pattern)850 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
851 enum pipe pipe, unsigned int train_pattern)
852 {
853 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
854 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
855 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
856 unsigned int fdi_iir_check_bits;
857
858 fdi_rx_imr = FDI_RX_IMR(pipe);
859 fdi_tx_ctl = FDI_TX_CTL(pipe);
860 fdi_rx_ctl = FDI_RX_CTL(pipe);
861
862 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
863 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
864 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
865 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
866 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
867 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
868 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
869 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
870 } else {
871 gvt_vgpu_err("Invalid train pattern %d\n", train_pattern);
872 return -EINVAL;
873 }
874
875 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
876 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
877
878 /* If imr bit has been masked */
879 if (vgpu_vreg_t(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
880 return 0;
881
882 if (((vgpu_vreg_t(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
883 == fdi_tx_check_bits)
884 && ((vgpu_vreg_t(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
885 == fdi_rx_check_bits))
886 return 1;
887 else
888 return 0;
889 }
890
891 #define INVALID_INDEX (~0U)
892
calc_index(unsigned int offset,i915_reg_t _start,i915_reg_t _next,i915_reg_t _end)893 static unsigned int calc_index(unsigned int offset, i915_reg_t _start,
894 i915_reg_t _next, i915_reg_t _end)
895 {
896 u32 start = i915_mmio_reg_offset(_start);
897 u32 next = i915_mmio_reg_offset(_next);
898 u32 end = i915_mmio_reg_offset(_end);
899 u32 stride = next - start;
900
901 if (offset < start || offset > end)
902 return INVALID_INDEX;
903 offset -= start;
904 return offset / stride;
905 }
906
907 #define FDI_RX_CTL_TO_PIPE(offset) \
908 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
909
910 #define FDI_TX_CTL_TO_PIPE(offset) \
911 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
912
913 #define FDI_RX_IMR_TO_PIPE(offset) \
914 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
915
update_fdi_rx_iir_status(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)916 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
917 unsigned int offset, void *p_data, unsigned int bytes)
918 {
919 i915_reg_t fdi_rx_iir;
920 unsigned int index;
921 int ret;
922
923 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
924 index = FDI_RX_CTL_TO_PIPE(offset);
925 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
926 index = FDI_TX_CTL_TO_PIPE(offset);
927 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
928 index = FDI_RX_IMR_TO_PIPE(offset);
929 else {
930 gvt_vgpu_err("Unsupported registers %x\n", offset);
931 return -EINVAL;
932 }
933
934 write_vreg(vgpu, offset, p_data, bytes);
935
936 fdi_rx_iir = FDI_RX_IIR(index);
937
938 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
939 if (ret < 0)
940 return ret;
941 if (ret)
942 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
943
944 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
945 if (ret < 0)
946 return ret;
947 if (ret)
948 vgpu_vreg_t(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
949
950 if (offset == _FDI_RXA_CTL)
951 if (fdi_auto_training_started(vgpu))
952 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |=
953 DP_TP_STATUS_AUTOTRAIN_DONE;
954 return 0;
955 }
956
957 #define DP_TP_CTL_TO_PORT(offset) \
958 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
959
dp_tp_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)960 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
961 void *p_data, unsigned int bytes)
962 {
963 i915_reg_t status_reg;
964 unsigned int index;
965 u32 data;
966
967 write_vreg(vgpu, offset, p_data, bytes);
968
969 index = DP_TP_CTL_TO_PORT(offset);
970 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
971 if (data == 0x2) {
972 status_reg = DP_TP_STATUS(index);
973 vgpu_vreg_t(vgpu, status_reg) |= (1 << 25);
974 }
975 return 0;
976 }
977
dp_tp_status_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)978 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
979 unsigned int offset, void *p_data, unsigned int bytes)
980 {
981 u32 reg_val;
982 u32 sticky_mask;
983
984 reg_val = *((u32 *)p_data);
985 sticky_mask = GENMASK(27, 26) | (1 << 24);
986
987 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
988 (vgpu_vreg(vgpu, offset) & sticky_mask);
989 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
990 return 0;
991 }
992
pch_adpa_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)993 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
994 unsigned int offset, void *p_data, unsigned int bytes)
995 {
996 u32 data;
997
998 write_vreg(vgpu, offset, p_data, bytes);
999 data = vgpu_vreg(vgpu, offset);
1000
1001 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
1002 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
1003 return 0;
1004 }
1005
south_chicken2_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1006 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
1007 unsigned int offset, void *p_data, unsigned int bytes)
1008 {
1009 u32 data;
1010
1011 write_vreg(vgpu, offset, p_data, bytes);
1012 data = vgpu_vreg(vgpu, offset);
1013
1014 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
1015 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
1016 else
1017 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
1018 return 0;
1019 }
1020
1021 #define DSPSURF_TO_PIPE(display, offset) \
1022 calc_index(offset, DSPSURF(display, PIPE_A), DSPSURF(display, PIPE_B), DSPSURF(display, PIPE_C))
1023
pri_surf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1024 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1025 void *p_data, unsigned int bytes)
1026 {
1027 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1028 struct intel_display *display = dev_priv->display;
1029 u32 pipe = DSPSURF_TO_PIPE(display, offset);
1030 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
1031
1032 write_vreg(vgpu, offset, p_data, bytes);
1033 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
1034
1035 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
1036
1037 if (vgpu_vreg_t(vgpu, DSPCNTR(display, pipe)) & PLANE_CTL_ASYNC_FLIP)
1038 intel_vgpu_trigger_virtual_event(vgpu, event);
1039 else
1040 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1041
1042 return 0;
1043 }
1044
1045 #define SPRSURF_TO_PIPE(offset) \
1046 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
1047
spr_surf_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1048 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1049 void *p_data, unsigned int bytes)
1050 {
1051 u32 pipe = SPRSURF_TO_PIPE(offset);
1052 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
1053
1054 write_vreg(vgpu, offset, p_data, bytes);
1055 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1056
1057 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
1058 intel_vgpu_trigger_virtual_event(vgpu, event);
1059 else
1060 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1061
1062 return 0;
1063 }
1064
reg50080_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1065 static int reg50080_mmio_write(struct intel_vgpu *vgpu,
1066 unsigned int offset, void *p_data,
1067 unsigned int bytes)
1068 {
1069 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1070 struct intel_display *display = dev_priv->display;
1071 enum pipe pipe = REG_50080_TO_PIPE(offset);
1072 enum plane_id plane = REG_50080_TO_PLANE(offset);
1073 int event = SKL_FLIP_EVENT(pipe, plane);
1074
1075 write_vreg(vgpu, offset, p_data, bytes);
1076 if (plane == PLANE_PRIMARY) {
1077 vgpu_vreg_t(vgpu, DSPSURFLIVE(display, pipe)) = vgpu_vreg(vgpu, offset);
1078 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, pipe))++;
1079 } else {
1080 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1081 }
1082
1083 if ((vgpu_vreg(vgpu, offset) & REG50080_FLIP_TYPE_MASK) == REG50080_FLIP_TYPE_ASYNC)
1084 intel_vgpu_trigger_virtual_event(vgpu, event);
1085 else
1086 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1087
1088 return 0;
1089 }
1090
trigger_aux_channel_interrupt(struct intel_vgpu * vgpu,unsigned int reg)1091 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
1092 unsigned int reg)
1093 {
1094 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1095 enum intel_gvt_event_type event;
1096
1097 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
1098 event = AUX_CHANNEL_A;
1099 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||
1100 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
1101 event = AUX_CHANNEL_B;
1102 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||
1103 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
1104 event = AUX_CHANNEL_C;
1105 else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||
1106 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
1107 event = AUX_CHANNEL_D;
1108 else {
1109 drm_WARN_ON(&dev_priv->drm, true);
1110 return -EINVAL;
1111 }
1112
1113 intel_vgpu_trigger_virtual_event(vgpu, event);
1114 return 0;
1115 }
1116
dp_aux_ch_ctl_trans_done(struct intel_vgpu * vgpu,u32 value,unsigned int reg,int len,bool data_valid)1117 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
1118 unsigned int reg, int len, bool data_valid)
1119 {
1120 /* mark transaction done */
1121 value |= DP_AUX_CH_CTL_DONE;
1122 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
1123 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
1124
1125 if (data_valid)
1126 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
1127 else
1128 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
1129
1130 /* message size */
1131 value &= ~(0xf << 20);
1132 value |= (len << 20);
1133 vgpu_vreg(vgpu, reg) = value;
1134
1135 if (value & DP_AUX_CH_CTL_INTERRUPT)
1136 return trigger_aux_channel_interrupt(vgpu, reg);
1137 return 0;
1138 }
1139
dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data * dpcd,u8 t)1140 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
1141 u8 t)
1142 {
1143 if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) {
1144 /* training pattern 1 for CR */
1145 /* set LANE0_CR_DONE, LANE1_CR_DONE */
1146 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CR_DONE |
1147 DP_LANE_CR_DONE << 4;
1148 /* set LANE2_CR_DONE, LANE3_CR_DONE */
1149 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CR_DONE |
1150 DP_LANE_CR_DONE << 4;
1151 } else if ((t & DP_TRAINING_PATTERN_MASK) ==
1152 DP_TRAINING_PATTERN_2) {
1153 /* training pattern 2 for EQ */
1154 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
1155 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1156 DP_LANE_CHANNEL_EQ_DONE << 4;
1157 dpcd->data[DP_LANE0_1_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1158 DP_LANE_SYMBOL_LOCKED << 4;
1159 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
1160 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_CHANNEL_EQ_DONE |
1161 DP_LANE_CHANNEL_EQ_DONE << 4;
1162 dpcd->data[DP_LANE2_3_STATUS] |= DP_LANE_SYMBOL_LOCKED |
1163 DP_LANE_SYMBOL_LOCKED << 4;
1164 /* set INTERLANE_ALIGN_DONE */
1165 dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |=
1166 DP_INTERLANE_ALIGN_DONE;
1167 } else if ((t & DP_TRAINING_PATTERN_MASK) ==
1168 DP_TRAINING_PATTERN_DISABLE) {
1169 /* finish link training */
1170 /* set sink status as synchronized */
1171 dpcd->data[DP_SINK_STATUS] = DP_RECEIVE_PORT_0_STATUS |
1172 DP_RECEIVE_PORT_1_STATUS;
1173 }
1174 }
1175
1176 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1177
1178 #define dpy_is_valid_port(port) \
1179 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
1180
dp_aux_ch_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1181 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
1182 unsigned int offset, void *p_data, unsigned int bytes)
1183 {
1184 struct intel_vgpu_display *display = &vgpu->display;
1185 int msg, addr, ctrl, op, len;
1186 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
1187 struct intel_vgpu_dpcd_data *dpcd = NULL;
1188 struct intel_vgpu_port *port = NULL;
1189 u32 data;
1190
1191 if (!dpy_is_valid_port(port_index)) {
1192 gvt_vgpu_err("Unsupported DP port access!\n");
1193 return 0;
1194 }
1195
1196 write_vreg(vgpu, offset, p_data, bytes);
1197 data = vgpu_vreg(vgpu, offset);
1198
1199 if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 &&
1200 offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {
1201 /* SKL DPB/C/D aux ctl register changed */
1202 return 0;
1203 } else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
1204 offset != i915_mmio_reg_offset(port_index ?
1205 PCH_DP_AUX_CH_CTL(port_index) :
1206 DP_AUX_CH_CTL(port_index))) {
1207 /* write to the data registers */
1208 return 0;
1209 }
1210
1211 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
1212 /* just want to clear the sticky bits */
1213 vgpu_vreg(vgpu, offset) = 0;
1214 return 0;
1215 }
1216
1217 port = &display->ports[port_index];
1218 dpcd = port->dpcd;
1219
1220 /* read out message from DATA1 register */
1221 msg = vgpu_vreg(vgpu, offset + 4);
1222 addr = (msg >> 8) & 0xffff;
1223 ctrl = (msg >> 24) & 0xff;
1224 len = msg & 0xff;
1225 op = ctrl >> 4;
1226
1227 if (op == DP_AUX_NATIVE_WRITE) {
1228 int t;
1229 u8 buf[16];
1230
1231 if ((addr + len + 1) >= DPCD_SIZE) {
1232 /*
1233 * Write request exceeds what we supported,
1234 * DCPD spec: When a Source Device is writing a DPCD
1235 * address not supported by the Sink Device, the Sink
1236 * Device shall reply with AUX NACK and “M” equal to
1237 * zero.
1238 */
1239
1240 /* NAK the write */
1241 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
1242 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
1243 return 0;
1244 }
1245
1246 /*
1247 * Write request format: Headr (command + address + size) occupies
1248 * 4 bytes, followed by (len + 1) bytes of data. See details at
1249 * intel_dp_aux_transfer().
1250 */
1251 if ((len + 1 + 4) > AUX_BURST_SIZE) {
1252 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1253 return -EINVAL;
1254 }
1255
1256 /* unpack data from vreg to buf */
1257 for (t = 0; t < 4; t++) {
1258 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
1259
1260 buf[t * 4] = (r >> 24) & 0xff;
1261 buf[t * 4 + 1] = (r >> 16) & 0xff;
1262 buf[t * 4 + 2] = (r >> 8) & 0xff;
1263 buf[t * 4 + 3] = r & 0xff;
1264 }
1265
1266 /* write to virtual DPCD */
1267 if (dpcd && dpcd->data_valid) {
1268 for (t = 0; t <= len; t++) {
1269 int p = addr + t;
1270
1271 dpcd->data[p] = buf[t];
1272 /* check for link training */
1273 if (p == DP_TRAINING_PATTERN_SET)
1274 dp_aux_ch_ctl_link_training(dpcd,
1275 buf[t]);
1276 }
1277 }
1278
1279 /* ACK the write */
1280 vgpu_vreg(vgpu, offset + 4) = 0;
1281 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1282 dpcd && dpcd->data_valid);
1283 return 0;
1284 }
1285
1286 if (op == DP_AUX_NATIVE_READ) {
1287 int idx, i, ret = 0;
1288
1289 if ((addr + len + 1) >= DPCD_SIZE) {
1290 /*
1291 * read request exceeds what we supported
1292 * DPCD spec: A Sink Device receiving a Native AUX CH
1293 * read request for an unsupported DPCD address must
1294 * reply with an AUX ACK and read data set equal to
1295 * zero instead of replying with AUX NACK.
1296 */
1297
1298 /* ACK the READ*/
1299 vgpu_vreg(vgpu, offset + 4) = 0;
1300 vgpu_vreg(vgpu, offset + 8) = 0;
1301 vgpu_vreg(vgpu, offset + 12) = 0;
1302 vgpu_vreg(vgpu, offset + 16) = 0;
1303 vgpu_vreg(vgpu, offset + 20) = 0;
1304
1305 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1306 true);
1307 return 0;
1308 }
1309
1310 for (idx = 1; idx <= 5; idx++) {
1311 /* clear the data registers */
1312 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
1313 }
1314
1315 /*
1316 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1317 */
1318 if ((len + 2) > AUX_BURST_SIZE) {
1319 gvt_vgpu_err("dp_aux_header: len %d is too large\n", len);
1320 return -EINVAL;
1321 }
1322
1323 /* read from virtual DPCD to vreg */
1324 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
1325 if (dpcd && dpcd->data_valid) {
1326 for (i = 1; i <= (len + 1); i++) {
1327 int t;
1328
1329 t = dpcd->data[addr + i - 1];
1330 t <<= (24 - 8 * (i % 4));
1331 ret |= t;
1332
1333 if ((i % 4 == 3) || (i == (len + 1))) {
1334 vgpu_vreg(vgpu, offset +
1335 (i / 4 + 1) * 4) = ret;
1336 ret = 0;
1337 }
1338 }
1339 }
1340 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1341 dpcd && dpcd->data_valid);
1342 return 0;
1343 }
1344
1345 /* i2c transaction starts */
1346 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
1347
1348 if (data & DP_AUX_CH_CTL_INTERRUPT)
1349 trigger_aux_channel_interrupt(vgpu, offset);
1350 return 0;
1351 }
1352
mbctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1353 static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1354 void *p_data, unsigned int bytes)
1355 {
1356 *(u32 *)p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
1357 write_vreg(vgpu, offset, p_data, bytes);
1358 return 0;
1359 }
1360
vga_control_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1361 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1362 void *p_data, unsigned int bytes)
1363 {
1364 bool vga_disable;
1365
1366 write_vreg(vgpu, offset, p_data, bytes);
1367 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
1368
1369 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
1370 vga_disable ? "Disable" : "Enable");
1371 return 0;
1372 }
1373
read_virtual_sbi_register(struct intel_vgpu * vgpu,unsigned int sbi_offset)1374 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
1375 unsigned int sbi_offset)
1376 {
1377 struct intel_vgpu_display *display = &vgpu->display;
1378 int num = display->sbi.number;
1379 int i;
1380
1381 for (i = 0; i < num; ++i)
1382 if (display->sbi.registers[i].offset == sbi_offset)
1383 break;
1384
1385 if (i == num)
1386 return 0;
1387
1388 return display->sbi.registers[i].value;
1389 }
1390
write_virtual_sbi_register(struct intel_vgpu * vgpu,unsigned int offset,u32 value)1391 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1392 unsigned int offset, u32 value)
1393 {
1394 struct intel_vgpu_display *display = &vgpu->display;
1395 int num = display->sbi.number;
1396 int i;
1397
1398 for (i = 0; i < num; ++i) {
1399 if (display->sbi.registers[i].offset == offset)
1400 break;
1401 }
1402
1403 if (i == num) {
1404 if (num == SBI_REG_MAX) {
1405 gvt_vgpu_err("SBI caching meets maximum limits\n");
1406 return;
1407 }
1408 display->sbi.number++;
1409 }
1410
1411 display->sbi.registers[i].offset = offset;
1412 display->sbi.registers[i].value = value;
1413 }
1414
sbi_data_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1415 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1416 void *p_data, unsigned int bytes)
1417 {
1418 if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRRD) {
1419 unsigned int sbi_offset;
1420
1421 sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));
1422
1423 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu, sbi_offset);
1424 }
1425 read_vreg(vgpu, offset, p_data, bytes);
1426 return 0;
1427 }
1428
sbi_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1429 static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1430 void *p_data, unsigned int bytes)
1431 {
1432 u32 data;
1433
1434 write_vreg(vgpu, offset, p_data, bytes);
1435 data = vgpu_vreg(vgpu, offset);
1436
1437 data &= ~SBI_STATUS_MASK;
1438 data |= SBI_STATUS_READY;
1439
1440 data &= ~SBI_RESPONSE_MASK;
1441 data |= SBI_RESPONSE_SUCCESS;
1442
1443 vgpu_vreg(vgpu, offset) = data;
1444
1445 if ((vgpu_vreg_t(vgpu, SBI_CTL_STAT) & SBI_CTL_OP_MASK) == SBI_CTL_OP_CRWR) {
1446 unsigned int sbi_offset;
1447
1448 sbi_offset = REG_FIELD_GET(SBI_ADDR_MASK, vgpu_vreg_t(vgpu, SBI_ADDR));
1449
1450 write_virtual_sbi_register(vgpu, sbi_offset, vgpu_vreg_t(vgpu, SBI_DATA));
1451 }
1452 return 0;
1453 }
1454
1455 #define _vgtif_reg(x) \
1456 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1457
pvinfo_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1458 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1459 void *p_data, unsigned int bytes)
1460 {
1461 bool invalid_read = false;
1462
1463 read_vreg(vgpu, offset, p_data, bytes);
1464
1465 switch (offset) {
1466 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1467 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1468 invalid_read = true;
1469 break;
1470 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1471 _vgtif_reg(avail_rs.fence_num):
1472 if (offset + bytes >
1473 _vgtif_reg(avail_rs.fence_num) + 4)
1474 invalid_read = true;
1475 break;
1476 case 0x78010: /* vgt_caps */
1477 case 0x7881c:
1478 break;
1479 default:
1480 invalid_read = true;
1481 break;
1482 }
1483 if (invalid_read)
1484 gvt_vgpu_err("invalid pvinfo read: [%x:%x] = %x\n",
1485 offset, bytes, *(u32 *)p_data);
1486 vgpu->pv_notified = true;
1487 return 0;
1488 }
1489
handle_g2v_notification(struct intel_vgpu * vgpu,int notification)1490 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1491 {
1492 enum intel_gvt_gtt_type root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1493 struct intel_vgpu_mm *mm;
1494 u64 *pdps;
1495
1496 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0]));
1497
1498 switch (notification) {
1499 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1500 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1501 fallthrough;
1502 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1503 mm = intel_vgpu_get_ppgtt_mm(vgpu, root_entry_type, pdps);
1504 return PTR_ERR_OR_ZERO(mm);
1505 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1506 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1507 return intel_vgpu_put_ppgtt_mm(vgpu, pdps);
1508 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1509 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1510 case 1: /* Remove this in guest driver. */
1511 break;
1512 default:
1513 gvt_vgpu_err("Invalid PV notification %d\n", notification);
1514 }
1515 return 0;
1516 }
1517
send_display_ready_uevent(struct intel_vgpu * vgpu,int ready)1518 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1519 {
1520 struct kobject *kobj = &vgpu->gvt->gt->i915->drm.primary->kdev->kobj;
1521 char *env[3] = {NULL, NULL, NULL};
1522 char vmid_str[20];
1523 char display_ready_str[20];
1524
1525 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
1526 env[0] = display_ready_str;
1527
1528 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1529 env[1] = vmid_str;
1530
1531 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1532 }
1533
pvinfo_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1534 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1535 void *p_data, unsigned int bytes)
1536 {
1537 u32 data = *(u32 *)p_data;
1538 bool invalid_write = false;
1539
1540 switch (offset) {
1541 case _vgtif_reg(display_ready):
1542 send_display_ready_uevent(vgpu, data ? 1 : 0);
1543 break;
1544 case _vgtif_reg(g2v_notify):
1545 handle_g2v_notification(vgpu, data);
1546 break;
1547 /* add xhot and yhot to handled list to avoid error log */
1548 case _vgtif_reg(cursor_x_hot):
1549 case _vgtif_reg(cursor_y_hot):
1550 case _vgtif_reg(pdp[0].lo):
1551 case _vgtif_reg(pdp[0].hi):
1552 case _vgtif_reg(pdp[1].lo):
1553 case _vgtif_reg(pdp[1].hi):
1554 case _vgtif_reg(pdp[2].lo):
1555 case _vgtif_reg(pdp[2].hi):
1556 case _vgtif_reg(pdp[3].lo):
1557 case _vgtif_reg(pdp[3].hi):
1558 case _vgtif_reg(execlist_context_descriptor_lo):
1559 case _vgtif_reg(execlist_context_descriptor_hi):
1560 break;
1561 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1562 invalid_write = true;
1563 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1564 break;
1565 default:
1566 invalid_write = true;
1567 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1568 offset, bytes, data);
1569 break;
1570 }
1571
1572 if (!invalid_write)
1573 write_vreg(vgpu, offset, p_data, bytes);
1574
1575 return 0;
1576 }
1577
pf_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1578 static int pf_write(struct intel_vgpu *vgpu,
1579 unsigned int offset, void *p_data, unsigned int bytes)
1580 {
1581 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1582 u32 val = *(u32 *)p_data;
1583
1584 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1585 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1586 offset == _PS_1C_CTRL) && (val & PS_BINDING_MASK) != PS_BINDING_PIPE) {
1587 drm_WARN_ONCE(&i915->drm, true,
1588 "VM(%d): guest is trying to scaling a plane\n",
1589 vgpu->id);
1590 return 0;
1591 }
1592
1593 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1594 }
1595
power_well_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1596 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1597 unsigned int offset, void *p_data, unsigned int bytes)
1598 {
1599 write_vreg(vgpu, offset, p_data, bytes);
1600
1601 if (vgpu_vreg(vgpu, offset) &
1602 HSW_PWR_WELL_CTL_REQ(HSW_PW_CTL_IDX_GLOBAL))
1603 vgpu_vreg(vgpu, offset) |=
1604 HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1605 else
1606 vgpu_vreg(vgpu, offset) &=
1607 ~HSW_PWR_WELL_CTL_STATE(HSW_PW_CTL_IDX_GLOBAL);
1608 return 0;
1609 }
1610
gen9_dbuf_ctl_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1611 static int gen9_dbuf_ctl_mmio_write(struct intel_vgpu *vgpu,
1612 unsigned int offset, void *p_data, unsigned int bytes)
1613 {
1614 write_vreg(vgpu, offset, p_data, bytes);
1615
1616 if (vgpu_vreg(vgpu, offset) & DBUF_POWER_REQUEST)
1617 vgpu_vreg(vgpu, offset) |= DBUF_POWER_STATE;
1618 else
1619 vgpu_vreg(vgpu, offset) &= ~DBUF_POWER_STATE;
1620
1621 return 0;
1622 }
1623
fpga_dbg_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1624 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1625 unsigned int offset, void *p_data, unsigned int bytes)
1626 {
1627 write_vreg(vgpu, offset, p_data, bytes);
1628
1629 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1630 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1631 return 0;
1632 }
1633
dma_ctrl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1634 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1635 void *p_data, unsigned int bytes)
1636 {
1637 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1638 u32 mode;
1639
1640 write_vreg(vgpu, offset, p_data, bytes);
1641 mode = vgpu_vreg(vgpu, offset);
1642
1643 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1644 drm_WARN_ONCE(&i915->drm, 1,
1645 "VM(%d): iGVT-g doesn't support GuC\n",
1646 vgpu->id);
1647 return 0;
1648 }
1649
1650 return 0;
1651 }
1652
gen9_trtte_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1653 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1654 void *p_data, unsigned int bytes)
1655 {
1656 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1657 u32 trtte = *(u32 *)p_data;
1658
1659 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1660 drm_WARN(&i915->drm, 1,
1661 "VM(%d): Use physical address for TRTT!\n",
1662 vgpu->id);
1663 return -EINVAL;
1664 }
1665 write_vreg(vgpu, offset, p_data, bytes);
1666
1667 return 0;
1668 }
1669
gen9_trtt_chicken_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1670 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1671 void *p_data, unsigned int bytes)
1672 {
1673 write_vreg(vgpu, offset, p_data, bytes);
1674 return 0;
1675 }
1676
dpll_status_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1677 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1678 void *p_data, unsigned int bytes)
1679 {
1680 u32 v = 0;
1681
1682 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1683 v |= (1 << 0);
1684
1685 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1686 v |= (1 << 8);
1687
1688 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1689 v |= (1 << 16);
1690
1691 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1692 v |= (1 << 24);
1693
1694 vgpu_vreg(vgpu, offset) = v;
1695
1696 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1697 }
1698
mailbox_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1699 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1700 void *p_data, unsigned int bytes)
1701 {
1702 u32 value = *(u32 *)p_data;
1703 u32 cmd = value & 0xff;
1704 u32 *data0 = &vgpu_vreg_t(vgpu, GEN6_PCODE_DATA);
1705
1706 switch (cmd) {
1707 case GEN9_PCODE_READ_MEM_LATENCY:
1708 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1709 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1710 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1711 IS_COMETLAKE(vgpu->gvt->gt->i915)) {
1712 /**
1713 * "Read memory latency" command on gen9.
1714 * Below memory latency values are read
1715 * from skylake platform.
1716 */
1717 if (!*data0)
1718 *data0 = 0x1e1a1100;
1719 else
1720 *data0 = 0x61514b3d;
1721 } else if (IS_BROXTON(vgpu->gvt->gt->i915)) {
1722 /**
1723 * "Read memory latency" command on gen9.
1724 * Below memory latency values are read
1725 * from Broxton MRB.
1726 */
1727 if (!*data0)
1728 *data0 = 0x16080707;
1729 else
1730 *data0 = 0x16161616;
1731 }
1732 break;
1733 case SKL_PCODE_CDCLK_CONTROL:
1734 if (IS_SKYLAKE(vgpu->gvt->gt->i915) ||
1735 IS_KABYLAKE(vgpu->gvt->gt->i915) ||
1736 IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
1737 IS_COMETLAKE(vgpu->gvt->gt->i915))
1738 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
1739 break;
1740 case GEN6_PCODE_READ_RC6VIDS:
1741 *data0 |= 0x1;
1742 break;
1743 }
1744
1745 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1746 vgpu->id, value, *data0);
1747 /**
1748 * PCODE_READY clear means ready for pcode read/write,
1749 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1750 * always emulate as pcode read/write success and ready for access
1751 * anytime, since we don't touch real physical registers here.
1752 */
1753 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1754 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1755 }
1756
hws_pga_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1757 static int hws_pga_write(struct intel_vgpu *vgpu, unsigned int offset,
1758 void *p_data, unsigned int bytes)
1759 {
1760 u32 value = *(u32 *)p_data;
1761 const struct intel_engine_cs *engine =
1762 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1763
1764 if (value != 0 &&
1765 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1766 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1767 offset, value);
1768 return -EINVAL;
1769 }
1770
1771 /*
1772 * Need to emulate all the HWSP register write to ensure host can
1773 * update the VM CSB status correctly. Here listed registers can
1774 * support BDW, SKL or other platforms with same HWSP registers.
1775 */
1776 if (unlikely(!engine)) {
1777 gvt_vgpu_err("access unknown hardware status page register:0x%x\n",
1778 offset);
1779 return -EINVAL;
1780 }
1781 vgpu->hws_pga[engine->id] = value;
1782 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n",
1783 vgpu->id, value, offset);
1784
1785 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1786 }
1787
skl_power_well_ctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1788 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1789 unsigned int offset, void *p_data, unsigned int bytes)
1790 {
1791 u32 v = *(u32 *)p_data;
1792
1793 if (IS_BROXTON(vgpu->gvt->gt->i915))
1794 v &= (1 << 31) | (1 << 29);
1795 else
1796 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1797 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1798 v |= (v >> 1);
1799
1800 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1801 }
1802
skl_lcpll_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1803 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1804 void *p_data, unsigned int bytes)
1805 {
1806 u32 v = *(u32 *)p_data;
1807
1808 /* other bits are MBZ. */
1809 v &= (1 << 31) | (1 << 30);
1810 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1811
1812 vgpu_vreg(vgpu, offset) = v;
1813
1814 return 0;
1815 }
1816
bxt_de_pll_enable_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1817 static int bxt_de_pll_enable_write(struct intel_vgpu *vgpu,
1818 unsigned int offset, void *p_data, unsigned int bytes)
1819 {
1820 u32 v = *(u32 *)p_data;
1821
1822 if (v & BXT_DE_PLL_PLL_ENABLE)
1823 v |= BXT_DE_PLL_LOCK;
1824
1825 vgpu_vreg(vgpu, offset) = v;
1826
1827 return 0;
1828 }
1829
bxt_port_pll_enable_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1830 static int bxt_port_pll_enable_write(struct intel_vgpu *vgpu,
1831 unsigned int offset, void *p_data, unsigned int bytes)
1832 {
1833 u32 v = *(u32 *)p_data;
1834
1835 if (v & PORT_PLL_ENABLE)
1836 v |= PORT_PLL_LOCK;
1837
1838 vgpu_vreg(vgpu, offset) = v;
1839
1840 return 0;
1841 }
1842
bxt_phy_ctl_family_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1843 static int bxt_phy_ctl_family_write(struct intel_vgpu *vgpu,
1844 unsigned int offset, void *p_data, unsigned int bytes)
1845 {
1846 u32 v = *(u32 *)p_data;
1847 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1848
1849 switch (offset) {
1850 case _PHY_CTL_FAMILY_EDP:
1851 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1852 break;
1853 case _PHY_CTL_FAMILY_DDI:
1854 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1855 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1856 break;
1857 }
1858
1859 vgpu_vreg(vgpu, offset) = v;
1860
1861 return 0;
1862 }
1863
bxt_port_tx_dw3_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1864 static int bxt_port_tx_dw3_read(struct intel_vgpu *vgpu,
1865 unsigned int offset, void *p_data, unsigned int bytes)
1866 {
1867 u32 v = vgpu_vreg(vgpu, offset);
1868
1869 v &= ~UNIQUE_TRANGE_EN_METHOD;
1870
1871 vgpu_vreg(vgpu, offset) = v;
1872
1873 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1874 }
1875
bxt_pcs_dw12_grp_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1876 static int bxt_pcs_dw12_grp_write(struct intel_vgpu *vgpu,
1877 unsigned int offset, void *p_data, unsigned int bytes)
1878 {
1879 u32 v = *(u32 *)p_data;
1880
1881 if (offset == _PORT_PCS_DW12_GRP_A || offset == _PORT_PCS_DW12_GRP_B) {
1882 vgpu_vreg(vgpu, offset - 0x600) = v;
1883 vgpu_vreg(vgpu, offset - 0x800) = v;
1884 } else {
1885 vgpu_vreg(vgpu, offset - 0x400) = v;
1886 vgpu_vreg(vgpu, offset - 0x600) = v;
1887 }
1888
1889 vgpu_vreg(vgpu, offset) = v;
1890
1891 return 0;
1892 }
1893
bxt_gt_disp_pwron_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1894 static int bxt_gt_disp_pwron_write(struct intel_vgpu *vgpu,
1895 unsigned int offset, void *p_data, unsigned int bytes)
1896 {
1897 u32 v = *(u32 *)p_data;
1898
1899 if (v & BIT(0)) {
1900 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
1901 ~PHY_RESERVED;
1902 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
1903 PHY_POWER_GOOD;
1904 }
1905
1906 if (v & BIT(1)) {
1907 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
1908 ~PHY_RESERVED;
1909 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
1910 PHY_POWER_GOOD;
1911 }
1912
1913
1914 vgpu_vreg(vgpu, offset) = v;
1915
1916 return 0;
1917 }
1918
edp_psr_imr_iir_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1919 static int edp_psr_imr_iir_write(struct intel_vgpu *vgpu,
1920 unsigned int offset, void *p_data, unsigned int bytes)
1921 {
1922 vgpu_vreg(vgpu, offset) = 0;
1923 return 0;
1924 }
1925
1926 /*
1927 * FixMe:
1928 * If guest fills non-priv batch buffer on ApolloLake/Broxton as Mesa i965 did:
1929 * 717e7539124d (i965: Use a WC map and memcpy for the batch instead of pwrite.)
1930 * Due to the missing flush of bb filled by VM vCPU, host GPU hangs on executing
1931 * these MI_BATCH_BUFFER.
1932 * Temporarily workaround this by setting SNOOP bit for PAT3 used by PPGTT
1933 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1934 * The performance is still expected to be low, will need further improvement.
1935 */
bxt_ppat_low_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1936 static int bxt_ppat_low_write(struct intel_vgpu *vgpu, unsigned int offset,
1937 void *p_data, unsigned int bytes)
1938 {
1939 u64 pat =
1940 GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1941 GEN8_PPAT(1, 0) |
1942 GEN8_PPAT(2, 0) |
1943 GEN8_PPAT(3, CHV_PPAT_SNOOP) |
1944 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1945 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1946 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1947 GEN8_PPAT(7, CHV_PPAT_SNOOP);
1948
1949 vgpu_vreg(vgpu, offset) = lower_32_bits(pat);
1950
1951 return 0;
1952 }
1953
guc_status_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1954 static int guc_status_read(struct intel_vgpu *vgpu,
1955 unsigned int offset, void *p_data,
1956 unsigned int bytes)
1957 {
1958 /* keep MIA_IN_RESET before clearing */
1959 read_vreg(vgpu, offset, p_data, bytes);
1960 vgpu_vreg(vgpu, offset) &= ~GS_MIA_IN_RESET;
1961 return 0;
1962 }
1963
mmio_read_from_hw(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1964 static int mmio_read_from_hw(struct intel_vgpu *vgpu,
1965 unsigned int offset, void *p_data, unsigned int bytes)
1966 {
1967 struct intel_gvt *gvt = vgpu->gvt;
1968 const struct intel_engine_cs *engine =
1969 intel_gvt_render_mmio_to_engine(gvt, offset);
1970
1971 /**
1972 * Read HW reg in following case
1973 * a. the offset isn't a ring mmio
1974 * b. the offset's ring is running on hw.
1975 * c. the offset is ring time stamp mmio
1976 */
1977
1978 if (!engine ||
1979 vgpu == gvt->scheduler.engine_owner[engine->id] ||
1980 offset == i915_mmio_reg_offset(RING_TIMESTAMP(engine->mmio_base)) ||
1981 offset == i915_mmio_reg_offset(RING_TIMESTAMP_UDW(engine->mmio_base))) {
1982 intel_wakeref_t wakeref;
1983
1984 wakeref = mmio_hw_access_pre(gvt->gt);
1985 vgpu_vreg(vgpu, offset) =
1986 intel_uncore_read(gvt->gt->uncore, _MMIO(offset));
1987 mmio_hw_access_post(gvt->gt, wakeref);
1988 }
1989
1990 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1991 }
1992
elsp_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)1993 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1994 void *p_data, unsigned int bytes)
1995 {
1996 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1997 const struct intel_engine_cs *engine = intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
1998 struct intel_vgpu_execlist *execlist;
1999 u32 data = *(u32 *)p_data;
2000 int ret = 0;
2001
2002 if (drm_WARN_ON(&i915->drm, !engine))
2003 return -EINVAL;
2004
2005 /*
2006 * Due to d3_entered is used to indicate skipping PPGTT invalidation on
2007 * vGPU reset, it's set on D0->D3 on PCI config write, and cleared after
2008 * vGPU reset if in resuming.
2009 * In S0ix exit, the device power state also transite from D3 to D0 as
2010 * S3 resume, but no vGPU reset (triggered by QEMU device model). After
2011 * S0ix exit, all engines continue to work. However the d3_entered
2012 * remains set which will break next vGPU reset logic (miss the expected
2013 * PPGTT invalidation).
2014 * Engines can only work in D0. Thus the 1st elsp write gives GVT a
2015 * chance to clear d3_entered.
2016 */
2017 if (vgpu->d3_entered)
2018 vgpu->d3_entered = false;
2019
2020 execlist = &vgpu->submission.execlist[engine->id];
2021
2022 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
2023 if (execlist->elsp_dwords.index == 3) {
2024 ret = intel_vgpu_submit_execlist(vgpu, engine);
2025 if(ret)
2026 gvt_vgpu_err("fail submit workload on ring %s\n",
2027 engine->name);
2028 }
2029
2030 ++execlist->elsp_dwords.index;
2031 execlist->elsp_dwords.index &= 0x3;
2032 return ret;
2033 }
2034
ring_mode_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2035 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2036 void *p_data, unsigned int bytes)
2037 {
2038 u32 data = *(u32 *)p_data;
2039 const struct intel_engine_cs *engine =
2040 intel_gvt_render_mmio_to_engine(vgpu->gvt, offset);
2041 bool enable_execlist;
2042 int ret;
2043
2044 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(1);
2045 if (IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2046 IS_COMETLAKE(vgpu->gvt->gt->i915))
2047 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(2);
2048 write_vreg(vgpu, offset, p_data, bytes);
2049
2050 if (IS_MASKED_BITS_ENABLED(data, 1)) {
2051 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2052 return 0;
2053 }
2054
2055 if ((IS_COFFEELAKE(vgpu->gvt->gt->i915) ||
2056 IS_COMETLAKE(vgpu->gvt->gt->i915)) &&
2057 IS_MASKED_BITS_ENABLED(data, 2)) {
2058 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2059 return 0;
2060 }
2061
2062 /* when PPGTT mode enabled, we will check if guest has called
2063 * pvinfo, if not, we will treat this guest as non-gvtg-aware
2064 * guest, and stop emulating its cfg space, mmio, gtt, etc.
2065 */
2066 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
2067 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
2068 !vgpu->pv_notified) {
2069 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2070 return 0;
2071 }
2072 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
2073 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
2074 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
2075
2076 gvt_dbg_core("EXECLIST %s on ring %s\n",
2077 (enable_execlist ? "enabling" : "disabling"),
2078 engine->name);
2079
2080 if (!enable_execlist)
2081 return 0;
2082
2083 ret = intel_vgpu_select_submission_ops(vgpu,
2084 engine->mask,
2085 INTEL_VGPU_EXECLIST_SUBMISSION);
2086 if (ret)
2087 return ret;
2088
2089 intel_vgpu_start_schedule(vgpu);
2090 }
2091 return 0;
2092 }
2093
gvt_reg_tlb_control_handler(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2094 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
2095 unsigned int offset, void *p_data, unsigned int bytes)
2096 {
2097 unsigned int id = 0;
2098
2099 write_vreg(vgpu, offset, p_data, bytes);
2100 vgpu_vreg(vgpu, offset) = 0;
2101
2102 switch (offset) {
2103 case 0x4260:
2104 id = RCS0;
2105 break;
2106 case 0x4264:
2107 id = VCS0;
2108 break;
2109 case 0x4268:
2110 id = VCS1;
2111 break;
2112 case 0x426c:
2113 id = BCS0;
2114 break;
2115 case 0x4270:
2116 id = VECS0;
2117 break;
2118 default:
2119 return -EINVAL;
2120 }
2121 set_bit(id, (void *)vgpu->submission.tlb_handle_pending);
2122
2123 return 0;
2124 }
2125
ring_reset_ctl_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2126 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
2127 unsigned int offset, void *p_data, unsigned int bytes)
2128 {
2129 u32 data;
2130
2131 write_vreg(vgpu, offset, p_data, bytes);
2132 data = vgpu_vreg(vgpu, offset);
2133
2134 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
2135 data |= RESET_CTL_READY_TO_RESET;
2136 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
2137 data &= ~RESET_CTL_READY_TO_RESET;
2138
2139 vgpu_vreg(vgpu, offset) = data;
2140 return 0;
2141 }
2142
csfe_chicken1_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)2143 static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
2144 unsigned int offset, void *p_data,
2145 unsigned int bytes)
2146 {
2147 u32 data = *(u32 *)p_data;
2148
2149 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18);
2150 write_vreg(vgpu, offset, p_data, bytes);
2151
2152 if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
2153 IS_MASKED_BITS_ENABLED(data, 0x8))
2154 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
2155
2156 return 0;
2157 }
2158
2159 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
2160 ret = setup_mmio_info(gvt, i915_mmio_reg_offset(reg), \
2161 s, f, am, rm, d, r, w); \
2162 if (ret) \
2163 return ret; \
2164 } while (0)
2165
2166 #define MMIO_DH(reg, d, r, w) \
2167 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2168
2169 #define MMIO_DFH(reg, d, f, r, w) \
2170 MMIO_F(reg, 4, f, 0, 0, d, r, w)
2171
2172 #define MMIO_GM(reg, d, r, w) \
2173 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2174
2175 #define MMIO_GM_RDR(reg, d, r, w) \
2176 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2177
2178 #define MMIO_RO(reg, d, f, rm, r, w) \
2179 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2180
2181 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
2182 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
2183 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
2184 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
2185 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
2186 if (HAS_ENGINE(gvt->gt, VCS1)) \
2187 MMIO_F(prefix(GEN8_BSD2_RING_BASE), s, f, am, rm, d, r, w); \
2188 } while (0)
2189
2190 #define MMIO_RING_DFH(prefix, d, f, r, w) \
2191 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2192
2193 #define MMIO_RING_GM(prefix, d, r, w) \
2194 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2195
2196 #define MMIO_RING_GM_RDR(prefix, d, r, w) \
2197 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2198
2199 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
2200 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2201
init_generic_mmio_info(struct intel_gvt * gvt)2202 static int init_generic_mmio_info(struct intel_gvt *gvt)
2203 {
2204 struct drm_i915_private *dev_priv = gvt->gt->i915;
2205 struct intel_display *display = dev_priv->display;
2206 int ret;
2207
2208 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,
2209 intel_vgpu_reg_imr_handler);
2210
2211 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
2212 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
2213 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
2214
2215 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);
2216
2217
2218 MMIO_DH(GEN8_GAMW_ECO_DEV_RW_IA, D_BDW_PLUS, NULL,
2219 gamw_echo_dev_rw_ia_write);
2220
2221 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2222 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2223 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
2224
2225 #define RING_REG(base) _MMIO((base) + 0x28)
2226 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2227 #undef RING_REG
2228
2229 #define RING_REG(base) _MMIO((base) + 0x134)
2230 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2231 #undef RING_REG
2232
2233 #define RING_REG(base) _MMIO((base) + 0x6c)
2234 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);
2235 #undef RING_REG
2236 MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
2237
2238 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
2239 MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
2240 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
2241
2242 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);
2243 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);
2244 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);
2245 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);
2246 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
2247
2248 /* RING MODE */
2249 #define RING_REG(base) _MMIO((base) + 0x29c)
2250 MMIO_RING_DFH(RING_REG, D_ALL,
2251 F_MODE_MASK | F_CMD_ACCESS | F_CMD_WRITE_PATCH, NULL,
2252 ring_mode_mmio_write);
2253 #undef RING_REG
2254
2255 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2256 NULL, NULL);
2257 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2258 NULL, NULL);
2259 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
2260 mmio_read_from_hw, NULL);
2261 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
2262 mmio_read_from_hw, NULL);
2263
2264 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2265 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2266 NULL, NULL);
2267 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2268 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2269 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2270
2271 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2272 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2273 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2274 MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,
2275 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2276 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2277 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
2278 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2279 NULL, NULL);
2280 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
2281 NULL, NULL);
2282 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);
2283 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);
2284 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);
2285 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);
2286 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);
2287 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
2288 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2289 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2290 MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2291 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2292
2293 /* display */
2294 MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,
2295 pipeconf_mmio_write);
2296 MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,
2297 pipeconf_mmio_write);
2298 MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,
2299 pipeconf_mmio_write);
2300 MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,
2301 pipeconf_mmio_write);
2302 MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
2303 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
2304 reg50080_mmio_write);
2305 MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
2306 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,
2307 reg50080_mmio_write);
2308 MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
2309 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,
2310 reg50080_mmio_write);
2311 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
2312 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,
2313 reg50080_mmio_write);
2314 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
2315 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,
2316 reg50080_mmio_write);
2317 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
2318 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,
2319 reg50080_mmio_write);
2320
2321 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
2322 gmbus_mmio_write);
2323 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
2324
2325 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2326 dp_aux_ch_ctl_mmio_write);
2327 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2328 dp_aux_ch_ctl_mmio_write);
2329 MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
2330 dp_aux_ch_ctl_mmio_write);
2331
2332 MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
2333
2334 MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);
2335 MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);
2336
2337 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
2338 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
2339 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
2340 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2341 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2342 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2343 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
2344 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
2345 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
2346 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
2347 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);
2348 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);
2349 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);
2350 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);
2351 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);
2352 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);
2353
2354 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
2355 PORTA_HOTPLUG_STATUS_MASK
2356 | PORTB_HOTPLUG_STATUS_MASK
2357 | PORTC_HOTPLUG_STATUS_MASK
2358 | PORTD_HOTPLUG_STATUS_MASK,
2359 NULL, NULL);
2360
2361 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
2362 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
2363 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2364 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2365 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
2366
2367 MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
2368 dp_aux_ch_ctl_mmio_write);
2369
2370 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2371 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2372 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2373 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2374 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2375
2376 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2377 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2378 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2379 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2380 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
2381
2382 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2383 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2384 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2385 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2386 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
2387
2388 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);
2389 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);
2390 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);
2391 MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);
2392
2393 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2394 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2395 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2396 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2397 MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);
2398 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2399 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2400 MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);
2401 MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);
2402 MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);
2403 MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);
2404 MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);
2405 MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);
2406
2407 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2408 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2409 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2410
2411 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2412 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2413
2414 MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
2415 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
2416
2417 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2418 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2419 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2420 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2421 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);
2422 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);
2423
2424 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2425 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2426 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2427 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2428
2429 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2430 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2431 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
2432
2433 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2434 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2435 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2436 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2437 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2438 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2439 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2440 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2441 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2442 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2443 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2444 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2445 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2446 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2447 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2448 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2449 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2450
2451 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2452 MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);
2453 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2454 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2455 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);
2456 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2457 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2458 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2459 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2460 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2461 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2462
2463 MMIO_DH(EDP_PSR_IMR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2464 MMIO_DH(EDP_PSR_IIR, D_BDW_PLUS, NULL, edp_psr_imr_iir_write);
2465 MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);
2466
2467 return 0;
2468 }
2469
init_bdw_mmio_info(struct intel_gvt * gvt)2470 static int init_bdw_mmio_info(struct intel_gvt *gvt)
2471 {
2472 int ret;
2473
2474 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2475 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2476 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2477
2478 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2479 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2480 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2481
2482 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2483 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2484 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2485
2486 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2487 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2488 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2489
2490 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2491 intel_vgpu_reg_imr_handler);
2492 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2493 intel_vgpu_reg_ier_handler);
2494 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2495 intel_vgpu_reg_iir_handler);
2496
2497 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2498 intel_vgpu_reg_imr_handler);
2499 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2500 intel_vgpu_reg_ier_handler);
2501 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2502 intel_vgpu_reg_iir_handler);
2503
2504 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2505 intel_vgpu_reg_imr_handler);
2506 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2507 intel_vgpu_reg_ier_handler);
2508 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2509 intel_vgpu_reg_iir_handler);
2510
2511 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2512 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2513 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2514
2515 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2516 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2517 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2518
2519 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2520 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2521 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2522
2523 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2524 intel_vgpu_reg_master_irq_handler);
2525
2526 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0,
2527 mmio_read_from_hw, NULL);
2528
2529 #define RING_REG(base) _MMIO((base) + 0xd0)
2530 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2531 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2532 ring_reset_ctl_write);
2533 #undef RING_REG
2534
2535 #define RING_REG(base) _MMIO((base) + 0x230)
2536 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2537 #undef RING_REG
2538
2539 #define RING_REG(base) _MMIO((base) + 0x234)
2540 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS,
2541 NULL, NULL);
2542 #undef RING_REG
2543
2544 #define RING_REG(base) _MMIO((base) + 0x244)
2545 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2546 #undef RING_REG
2547
2548 #define RING_REG(base) _MMIO((base) + 0x370)
2549 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2550 #undef RING_REG
2551
2552 #define RING_REG(base) _MMIO((base) + 0x3a0)
2553 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2554 #undef RING_REG
2555
2556 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2557
2558 #define RING_REG(base) _MMIO((base) + 0x270)
2559 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL);
2560 #undef RING_REG
2561
2562 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, hws_pga_write);
2563
2564 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2565
2566 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2567 NULL, NULL);
2568 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2569 NULL, NULL);
2570 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2571
2572 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2573 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
2574 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2575 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
2576 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
2577
2578 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0,
2579 D_BDW_PLUS, NULL, force_nonpriv_write);
2580
2581 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);
2582
2583 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);
2584
2585 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2586 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2587 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2588 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2589
2590 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
2591
2592 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2593 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2594 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2595 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2596 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2597 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2598 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2599 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2600 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2601 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2602 return 0;
2603 }
2604
init_skl_mmio_info(struct intel_gvt * gvt)2605 static int init_skl_mmio_info(struct intel_gvt *gvt)
2606 {
2607 int ret;
2608
2609 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2610 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2611 MMIO_DH(FORCEWAKE_GT_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2612 MMIO_DH(FORCEWAKE_ACK_GT_GEN9, D_SKL_PLUS, NULL, NULL);
2613 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2614 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2615
2616 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2617 dp_aux_ch_ctl_mmio_write);
2618 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2619 dp_aux_ch_ctl_mmio_write);
2620 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,
2621 dp_aux_ch_ctl_mmio_write);
2622
2623 MMIO_DH(HSW_PWR_WELL_CTL2, D_SKL_PLUS, NULL, skl_power_well_ctl_write);
2624
2625 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write);
2626
2627 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2628 MMIO_DFH(MMCD_MISC_CTRL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2629 MMIO_DH(CHICKEN_PAR1_1, D_SKL_PLUS, NULL, NULL);
2630 MMIO_DH(LCPLL1_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2631 MMIO_DH(LCPLL2_CTL, D_SKL_PLUS, NULL, skl_lcpll_write);
2632 MMIO_DH(DPLL_STATUS, D_SKL_PLUS, dpll_status_read, NULL);
2633
2634 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2635 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2636 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2637 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2638 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2639 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2640
2641 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2642 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2643 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2644 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2645 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2646 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2647
2648 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write);
2649 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL_PLUS, NULL, pf_write);
2650 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write);
2651 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL_PLUS, NULL, pf_write);
2652 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write);
2653 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL_PLUS, NULL, pf_write);
2654
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2656 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2657 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2658 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2659
2660 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2661 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2662 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2663 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2664
2665 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2666 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2667 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2668 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2669
2670 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL);
2671 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL);
2672 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL);
2673
2674 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2675 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2676 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2677
2678 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2679 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2680 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2681
2682 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2683 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2684 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2685
2686 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL_PLUS, NULL, NULL);
2687 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL_PLUS, NULL, NULL);
2688 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL_PLUS, NULL, NULL);
2689
2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2691 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2692 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2693 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2694
2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2696 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2697 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2698 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2699
2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2701 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2702 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2703 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2704
2705 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2706 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2707 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2708 MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2709
2710 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2711 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2712 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2713 MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2714
2715 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2716 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2717 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2718 MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2719
2720 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL);
2721 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL);
2722 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL);
2723 MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL);
2724
2725 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL);
2726 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL);
2727 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL);
2728 MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL);
2729
2730 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL);
2731 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL);
2732 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL);
2733 MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL);
2734
2735 MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2736
2737 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2738 NULL, NULL);
2739 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
2740 NULL, NULL);
2741
2742 MMIO_DFH(GEN7_FF_SLICE_CS_CHICKEN1, D_SKL_PLUS,
2743 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2744 MMIO_DFH(GEN9_CS_DEBUG_MODE1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2745 NULL, NULL);
2746
2747 /* TRTT */
2748 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2749 MMIO_DFH(TRVATTL3PTRDW(1), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2750 MMIO_DFH(TRVATTL3PTRDW(2), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2751 MMIO_DFH(TRVATTL3PTRDW(3), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2752 MMIO_DFH(TRVADR, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2753 MMIO_DFH(TRTTE, D_SKL_PLUS, F_CMD_ACCESS | F_PM_SAVE,
2754 NULL, gen9_trtte_write);
2755 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE,
2756 NULL, gen9_trtt_chicken_write);
2757
2758 MMIO_DFH(GEN8_GARBCNTL, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
2759 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2760
2761 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4)
2762 MMIO_RING_DFH(CSFE_CHICKEN1_REG, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2763 NULL, csfe_chicken1_mmio_write);
2764 #undef CSFE_CHICKEN1_REG
2765 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2766 NULL, NULL);
2767 MMIO_DFH(GEN9_WM_CHICKEN3, D_SKL_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2768 NULL, NULL);
2769
2770 MMIO_DFH(GAMT_CHKN_BIT_REG, D_KBL | D_CFL, F_CMD_ACCESS, NULL, NULL);
2771 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2772
2773 return 0;
2774 }
2775
init_bxt_mmio_info(struct intel_gvt * gvt)2776 static int init_bxt_mmio_info(struct intel_gvt *gvt)
2777 {
2778 int ret;
2779
2780 MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);
2781 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,
2782 NULL, bxt_phy_ctl_family_write);
2783 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,
2784 NULL, bxt_phy_ctl_family_write);
2785 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,
2786 NULL, bxt_port_pll_enable_write);
2787 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,
2788 NULL, bxt_port_pll_enable_write);
2789 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,
2790 bxt_port_pll_enable_write);
2791
2792 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
2793 NULL, bxt_pcs_dw12_grp_write);
2794 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
2795 bxt_port_tx_dw3_read, NULL);
2796 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
2797 NULL, bxt_pcs_dw12_grp_write);
2798 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
2799 bxt_port_tx_dw3_read, NULL);
2800 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
2801 NULL, bxt_pcs_dw12_grp_write);
2802 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
2803 bxt_port_tx_dw3_read, NULL);
2804 MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
2805 MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
2806 MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2807 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
2808 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2809 0, 0, D_BXT, NULL, NULL);
2810 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2811 0, 0, D_BXT, NULL, NULL);
2812 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2813 0, 0, D_BXT, NULL, NULL);
2814 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS,
2815 0, 0, D_BXT, NULL, NULL);
2816
2817 MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);
2818
2819 MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);
2820
2821 return 0;
2822 }
2823
find_mmio_block(struct intel_gvt * gvt,unsigned int offset)2824 static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
2825 unsigned int offset)
2826 {
2827 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2828 int num = gvt->mmio.num_mmio_block;
2829 int i;
2830
2831 for (i = 0; i < num; i++, block++) {
2832 if (offset >= i915_mmio_reg_offset(block->offset) &&
2833 offset < i915_mmio_reg_offset(block->offset) + block->size)
2834 return block;
2835 }
2836 return NULL;
2837 }
2838
2839 /**
2840 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2841 * @gvt: GVT device
2842 *
2843 * This function is called at the driver unloading stage, to clean up the MMIO
2844 * information table of GVT device
2845 *
2846 */
intel_gvt_clean_mmio_info(struct intel_gvt * gvt)2847 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2848 {
2849 struct hlist_node *tmp;
2850 struct intel_gvt_mmio_info *e;
2851 int i;
2852
2853 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2854 kfree(e);
2855
2856 kfree(gvt->mmio.mmio_block);
2857 gvt->mmio.mmio_block = NULL;
2858 gvt->mmio.num_mmio_block = 0;
2859
2860 vfree(gvt->mmio.mmio_attribute);
2861 gvt->mmio.mmio_attribute = NULL;
2862 }
2863
handle_mmio(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2864 static int handle_mmio(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2865 u32 size)
2866 {
2867 struct intel_gvt *gvt = iter->data;
2868 struct intel_gvt_mmio_info *info, *p;
2869 u32 start, end, i;
2870
2871 if (WARN_ON(!IS_ALIGNED(offset, 4)))
2872 return -EINVAL;
2873
2874 start = offset;
2875 end = offset + size;
2876
2877 for (i = start; i < end; i += 4) {
2878 p = intel_gvt_find_mmio_info(gvt, i);
2879 if (p) {
2880 WARN(1, "dup mmio definition offset %x\n", i);
2881
2882 /* We return -EEXIST here to make GVT-g load fail.
2883 * So duplicated MMIO can be found as soon as
2884 * possible.
2885 */
2886 return -EEXIST;
2887 }
2888
2889 info = kzalloc(sizeof(*info), GFP_KERNEL);
2890 if (!info)
2891 return -ENOMEM;
2892
2893 info->offset = i;
2894 info->read = intel_vgpu_default_mmio_read;
2895 info->write = intel_vgpu_default_mmio_write;
2896 INIT_HLIST_NODE(&info->node);
2897 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
2898 gvt->mmio.num_tracked_mmio++;
2899 }
2900 return 0;
2901 }
2902
handle_mmio_block(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2903 static int handle_mmio_block(struct intel_gvt_mmio_table_iter *iter,
2904 u32 offset, u32 size)
2905 {
2906 struct intel_gvt *gvt = iter->data;
2907 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
2908 void *ret;
2909
2910 ret = krealloc(block,
2911 (gvt->mmio.num_mmio_block + 1) * sizeof(*block),
2912 GFP_KERNEL);
2913 if (!ret)
2914 return -ENOMEM;
2915
2916 gvt->mmio.mmio_block = block = ret;
2917
2918 block += gvt->mmio.num_mmio_block;
2919
2920 memset(block, 0, sizeof(*block));
2921
2922 block->offset = _MMIO(offset);
2923 block->size = size;
2924
2925 gvt->mmio.num_mmio_block++;
2926
2927 return 0;
2928 }
2929
handle_mmio_cb(struct intel_gvt_mmio_table_iter * iter,u32 offset,u32 size)2930 static int handle_mmio_cb(struct intel_gvt_mmio_table_iter *iter, u32 offset,
2931 u32 size)
2932 {
2933 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0)))
2934 return handle_mmio(iter, offset, size);
2935 else
2936 return handle_mmio_block(iter, offset, size);
2937 }
2938
init_mmio_info(struct intel_gvt * gvt)2939 static int init_mmio_info(struct intel_gvt *gvt)
2940 {
2941 struct intel_gvt_mmio_table_iter iter = {
2942 .i915 = gvt->gt->i915,
2943 .data = gvt,
2944 .handle_mmio_cb = handle_mmio_cb,
2945 };
2946
2947 return intel_gvt_iterate_mmio_table(&iter);
2948 }
2949
init_mmio_block_handlers(struct intel_gvt * gvt)2950 static int init_mmio_block_handlers(struct intel_gvt *gvt)
2951 {
2952 struct gvt_mmio_block *block;
2953
2954 block = find_mmio_block(gvt, VGT_PVINFO_PAGE);
2955 if (!block) {
2956 WARN(1, "fail to assign handlers to mmio block %x\n",
2957 i915_mmio_reg_offset(gvt->mmio.mmio_block->offset));
2958 return -ENODEV;
2959 }
2960
2961 block->read = pvinfo_mmio_read;
2962 block->write = pvinfo_mmio_write;
2963
2964 return 0;
2965 }
2966
2967 /**
2968 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2969 * @gvt: GVT device
2970 *
2971 * This function is called at the initialization stage, to setup the MMIO
2972 * information table for GVT device
2973 *
2974 * Returns:
2975 * zero on success, negative if failed.
2976 */
intel_gvt_setup_mmio_info(struct intel_gvt * gvt)2977 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2978 {
2979 struct intel_gvt_device_info *info = &gvt->device_info;
2980 struct drm_i915_private *i915 = gvt->gt->i915;
2981 int size = info->mmio_size / 4 * sizeof(*gvt->mmio.mmio_attribute);
2982 int ret;
2983
2984 gvt->mmio.mmio_attribute = vzalloc(size);
2985 if (!gvt->mmio.mmio_attribute)
2986 return -ENOMEM;
2987
2988 ret = init_mmio_info(gvt);
2989 if (ret)
2990 goto err;
2991
2992 ret = init_mmio_block_handlers(gvt);
2993 if (ret)
2994 goto err;
2995
2996 ret = init_generic_mmio_info(gvt);
2997 if (ret)
2998 goto err;
2999
3000 if (IS_BROADWELL(i915)) {
3001 ret = init_bdw_mmio_info(gvt);
3002 if (ret)
3003 goto err;
3004 } else if (IS_SKYLAKE(i915) ||
3005 IS_KABYLAKE(i915) ||
3006 IS_COFFEELAKE(i915) ||
3007 IS_COMETLAKE(i915)) {
3008 ret = init_bdw_mmio_info(gvt);
3009 if (ret)
3010 goto err;
3011 ret = init_skl_mmio_info(gvt);
3012 if (ret)
3013 goto err;
3014 } else if (IS_BROXTON(i915)) {
3015 ret = init_bdw_mmio_info(gvt);
3016 if (ret)
3017 goto err;
3018 ret = init_skl_mmio_info(gvt);
3019 if (ret)
3020 goto err;
3021 ret = init_bxt_mmio_info(gvt);
3022 if (ret)
3023 goto err;
3024 }
3025
3026 return 0;
3027 err:
3028 intel_gvt_clean_mmio_info(gvt);
3029 return ret;
3030 }
3031
3032 /**
3033 * intel_gvt_for_each_tracked_mmio - iterate each tracked mmio
3034 * @gvt: a GVT device
3035 * @handler: the handler
3036 * @data: private data given to handler
3037 *
3038 * Returns:
3039 * Zero on success, negative error code if failed.
3040 */
intel_gvt_for_each_tracked_mmio(struct intel_gvt * gvt,int (* handler)(struct intel_gvt * gvt,u32 offset,void * data),void * data)3041 int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
3042 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3043 void *data)
3044 {
3045 struct gvt_mmio_block *block = gvt->mmio.mmio_block;
3046 struct intel_gvt_mmio_info *e;
3047 int i, j, ret;
3048
3049 hash_for_each(gvt->mmio.mmio_info_table, i, e, node) {
3050 ret = handler(gvt, e->offset, data);
3051 if (ret)
3052 return ret;
3053 }
3054
3055 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) {
3056 /* pvinfo data doesn't come from hw mmio */
3057 if (i915_mmio_reg_offset(block->offset) == VGT_PVINFO_PAGE)
3058 continue;
3059
3060 for (j = 0; j < block->size; j += 4) {
3061 ret = handler(gvt, i915_mmio_reg_offset(block->offset) + j, data);
3062 if (ret)
3063 return ret;
3064 }
3065 }
3066 return 0;
3067 }
3068
3069 /**
3070 * intel_vgpu_default_mmio_read - default MMIO read handler
3071 * @vgpu: a vGPU
3072 * @offset: access offset
3073 * @p_data: data return buffer
3074 * @bytes: access data length
3075 *
3076 * Returns:
3077 * Zero on success, negative error code if failed.
3078 */
intel_vgpu_default_mmio_read(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3079 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
3080 void *p_data, unsigned int bytes)
3081 {
3082 read_vreg(vgpu, offset, p_data, bytes);
3083 return 0;
3084 }
3085
3086 /**
3087 * intel_vgpu_default_mmio_write() - default MMIO write handler
3088 * @vgpu: a vGPU
3089 * @offset: access offset
3090 * @p_data: write data buffer
3091 * @bytes: access data length
3092 *
3093 * Returns:
3094 * Zero on success, negative error code if failed.
3095 */
intel_vgpu_default_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3096 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3097 void *p_data, unsigned int bytes)
3098 {
3099 write_vreg(vgpu, offset, p_data, bytes);
3100 return 0;
3101 }
3102
3103 /**
3104 * intel_vgpu_mask_mmio_write - write mask register
3105 * @vgpu: a vGPU
3106 * @offset: access offset
3107 * @p_data: write data buffer
3108 * @bytes: access data length
3109 *
3110 * Returns:
3111 * Zero on success, negative error code if failed.
3112 */
intel_vgpu_mask_mmio_write(struct intel_vgpu * vgpu,unsigned int offset,void * p_data,unsigned int bytes)3113 int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
3114 void *p_data, unsigned int bytes)
3115 {
3116 u32 mask, old_vreg;
3117
3118 old_vreg = vgpu_vreg(vgpu, offset);
3119 write_vreg(vgpu, offset, p_data, bytes);
3120 mask = vgpu_vreg(vgpu, offset) >> 16;
3121 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask) |
3122 (vgpu_vreg(vgpu, offset) & mask);
3123
3124 return 0;
3125 }
3126
3127 /**
3128 * intel_vgpu_mmio_reg_rw - emulate tracked mmio registers
3129 * @vgpu: a vGPU
3130 * @offset: register offset
3131 * @pdata: data buffer
3132 * @bytes: data length
3133 * @is_read: read or write
3134 *
3135 * Returns:
3136 * Zero on success, negative error code if failed.
3137 */
intel_vgpu_mmio_reg_rw(struct intel_vgpu * vgpu,unsigned int offset,void * pdata,unsigned int bytes,bool is_read)3138 int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
3139 void *pdata, unsigned int bytes, bool is_read)
3140 {
3141 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
3142 struct intel_gvt *gvt = vgpu->gvt;
3143 struct intel_gvt_mmio_info *mmio_info;
3144 struct gvt_mmio_block *mmio_block;
3145 gvt_mmio_func func;
3146 int ret;
3147
3148 if (drm_WARN_ON(&i915->drm, bytes > 8))
3149 return -EINVAL;
3150
3151 /*
3152 * Handle special MMIO blocks.
3153 */
3154 mmio_block = find_mmio_block(gvt, offset);
3155 if (mmio_block) {
3156 func = is_read ? mmio_block->read : mmio_block->write;
3157 if (func)
3158 return func(vgpu, offset, pdata, bytes);
3159 goto default_rw;
3160 }
3161
3162 /*
3163 * Normal tracked MMIOs.
3164 */
3165 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
3166 if (!mmio_info) {
3167 gvt_dbg_mmio("untracked MMIO %08x len %d\n", offset, bytes);
3168 goto default_rw;
3169 }
3170
3171 if (is_read)
3172 return mmio_info->read(vgpu, offset, pdata, bytes);
3173 else {
3174 u64 ro_mask = mmio_info->ro_mask;
3175 u32 old_vreg = 0;
3176 u64 data = 0;
3177
3178 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3179 old_vreg = vgpu_vreg(vgpu, offset);
3180 }
3181
3182 if (likely(!ro_mask))
3183 ret = mmio_info->write(vgpu, offset, pdata, bytes);
3184 else if (!~ro_mask) {
3185 gvt_vgpu_err("try to write RO reg %x\n", offset);
3186 return 0;
3187 } else {
3188 /* keep the RO bits in the virtual register */
3189 memcpy(&data, pdata, bytes);
3190 data &= ~ro_mask;
3191 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3192 ret = mmio_info->write(vgpu, offset, &data, bytes);
3193 }
3194
3195 /* higher 16bits of mode ctl regs are mask bits for change */
3196 if (intel_gvt_mmio_has_mode_mask(gvt, mmio_info->offset)) {
3197 u32 mask = vgpu_vreg(vgpu, offset) >> 16;
3198
3199 vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
3200 | (vgpu_vreg(vgpu, offset) & mask);
3201 }
3202 }
3203
3204 return ret;
3205
3206 default_rw:
3207 return is_read ?
3208 intel_vgpu_default_mmio_read(vgpu, offset, pdata, bytes) :
3209 intel_vgpu_default_mmio_write(vgpu, offset, pdata, bytes);
3210 }
3211
intel_gvt_restore_fence(struct intel_gvt * gvt)3212 void intel_gvt_restore_fence(struct intel_gvt *gvt)
3213 {
3214 struct intel_vgpu *vgpu;
3215 int i, id;
3216
3217 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3218 intel_wakeref_t wakeref;
3219
3220 wakeref = mmio_hw_access_pre(gvt->gt);
3221 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
3222 intel_vgpu_write_fence(vgpu, i, vgpu_vreg64(vgpu, fence_num_to_offset(i)));
3223 mmio_hw_access_post(gvt->gt, wakeref);
3224 }
3225 }
3226
mmio_pm_restore_handler(struct intel_gvt * gvt,u32 offset,void * data)3227 static int mmio_pm_restore_handler(struct intel_gvt *gvt, u32 offset, void *data)
3228 {
3229 struct intel_vgpu *vgpu = data;
3230 struct drm_i915_private *dev_priv = gvt->gt->i915;
3231
3232 if (gvt->mmio.mmio_attribute[offset >> 2] & F_PM_SAVE)
3233 intel_uncore_write(&dev_priv->uncore, _MMIO(offset), vgpu_vreg(vgpu, offset));
3234
3235 return 0;
3236 }
3237
intel_gvt_restore_mmio(struct intel_gvt * gvt)3238 void intel_gvt_restore_mmio(struct intel_gvt *gvt)
3239 {
3240 struct intel_vgpu *vgpu;
3241 int id;
3242
3243 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
3244 intel_wakeref_t wakeref;
3245
3246 wakeref = mmio_hw_access_pre(gvt->gt);
3247 intel_gvt_for_each_tracked_mmio(gvt, mmio_pm_restore_handler, vgpu);
3248 mmio_hw_access_post(gvt->gt, wakeref);
3249 }
3250 }
3251