1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Kevin Tian <kevin.tian@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
32 * Yulei Zhang <yulei.zhang@intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
34 *
35 */
36
37 #include <linux/slab.h>
38
39 #include "i915_drv.h"
40 #include "i915_reg.h"
41 #include "display/intel_display_regs.h"
42 #include "gt/intel_engine_regs.h"
43 #include "gt/intel_gpu_commands.h"
44 #include "gt/intel_gt_regs.h"
45 #include "gt/intel_lrc.h"
46 #include "gt/intel_ring.h"
47 #include "gt/intel_gt_requests.h"
48 #include "gt/shmem_utils.h"
49 #include "gvt.h"
50 #include "i915_pvinfo.h"
51 #include "trace.h"
52
53 #include "display/i9xx_plane_regs.h"
54 #include "display/intel_display_core.h"
55 #include "display/intel_sprite_regs.h"
56 #include "gem/i915_gem_context.h"
57 #include "gem/i915_gem_pm.h"
58 #include "gt/intel_context.h"
59
60 #define INVALID_OP (~0U)
61
62 #define OP_LEN_MI 9
63 #define OP_LEN_2D 10
64 #define OP_LEN_3D_MEDIA 16
65 #define OP_LEN_MFX_VC 16
66 #define OP_LEN_VEBOX 16
67
68 #define CMD_TYPE(cmd) (((cmd) >> 29) & 7)
69
70 struct sub_op_bits {
71 int hi;
72 int low;
73 };
74 struct decode_info {
75 const char *name;
76 int op_len;
77 int nr_sub_op;
78 const struct sub_op_bits *sub_op;
79 };
80
81 #define MAX_CMD_BUDGET 0x7fffffff
82 #define MI_WAIT_FOR_PLANE_C_FLIP_PENDING (1<<15)
83 #define MI_WAIT_FOR_PLANE_B_FLIP_PENDING (1<<9)
84 #define MI_WAIT_FOR_PLANE_A_FLIP_PENDING (1<<1)
85
86 #define MI_WAIT_FOR_SPRITE_C_FLIP_PENDING (1<<20)
87 #define MI_WAIT_FOR_SPRITE_B_FLIP_PENDING (1<<10)
88 #define MI_WAIT_FOR_SPRITE_A_FLIP_PENDING (1<<2)
89
90 /* Render Command Map */
91
92 /* MI_* command Opcode (28:23) */
93 #define OP_MI_NOOP 0x0
94 #define OP_MI_SET_PREDICATE 0x1 /* HSW+ */
95 #define OP_MI_USER_INTERRUPT 0x2
96 #define OP_MI_WAIT_FOR_EVENT 0x3
97 #define OP_MI_FLUSH 0x4
98 #define OP_MI_ARB_CHECK 0x5
99 #define OP_MI_RS_CONTROL 0x6 /* HSW+ */
100 #define OP_MI_REPORT_HEAD 0x7
101 #define OP_MI_ARB_ON_OFF 0x8
102 #define OP_MI_URB_ATOMIC_ALLOC 0x9 /* HSW+ */
103 #define OP_MI_BATCH_BUFFER_END 0xA
104 #define OP_MI_SUSPEND_FLUSH 0xB
105 #define OP_MI_PREDICATE 0xC /* IVB+ */
106 #define OP_MI_TOPOLOGY_FILTER 0xD /* IVB+ */
107 #define OP_MI_SET_APPID 0xE /* IVB+ */
108 #define OP_MI_RS_CONTEXT 0xF /* HSW+ */
109 #define OP_MI_LOAD_SCAN_LINES_INCL 0x12 /* HSW+ */
110 #define OP_MI_DISPLAY_FLIP 0x14
111 #define OP_MI_SEMAPHORE_MBOX 0x16
112 #define OP_MI_SET_CONTEXT 0x18
113 #define OP_MI_MATH 0x1A
114 #define OP_MI_URB_CLEAR 0x19
115 #define OP_MI_SEMAPHORE_SIGNAL 0x1B /* BDW+ */
116 #define OP_MI_SEMAPHORE_WAIT 0x1C /* BDW+ */
117
118 #define OP_MI_STORE_DATA_IMM 0x20
119 #define OP_MI_STORE_DATA_INDEX 0x21
120 #define OP_MI_LOAD_REGISTER_IMM 0x22
121 #define OP_MI_UPDATE_GTT 0x23
122 #define OP_MI_STORE_REGISTER_MEM 0x24
123 #define OP_MI_FLUSH_DW 0x26
124 #define OP_MI_CLFLUSH 0x27
125 #define OP_MI_REPORT_PERF_COUNT 0x28
126 #define OP_MI_LOAD_REGISTER_MEM 0x29 /* HSW+ */
127 #define OP_MI_LOAD_REGISTER_REG 0x2A /* HSW+ */
128 #define OP_MI_RS_STORE_DATA_IMM 0x2B /* HSW+ */
129 #define OP_MI_LOAD_URB_MEM 0x2C /* HSW+ */
130 #define OP_MI_STORE_URM_MEM 0x2D /* HSW+ */
131 #define OP_MI_2E 0x2E /* BDW+ */
132 #define OP_MI_2F 0x2F /* BDW+ */
133 #define OP_MI_BATCH_BUFFER_START 0x31
134
135 /* Bit definition for dword 0 */
136 #define _CMDBIT_BB_START_IN_PPGTT (1UL << 8)
137
138 #define OP_MI_CONDITIONAL_BATCH_BUFFER_END 0x36
139
140 #define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
141 #define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
142 #define BATCH_BUFFER_ADR_SPACE_BIT(x) (((x) >> 8) & 1U)
143 #define BATCH_BUFFER_2ND_LEVEL_BIT(x) ((x) >> 22 & 1U)
144
145 /* 2D command: Opcode (28:22) */
146 #define OP_2D(x) ((2<<7) | x)
147
148 #define OP_XY_SETUP_BLT OP_2D(0x1)
149 #define OP_XY_SETUP_CLIP_BLT OP_2D(0x3)
150 #define OP_XY_SETUP_MONO_PATTERN_SL_BLT OP_2D(0x11)
151 #define OP_XY_PIXEL_BLT OP_2D(0x24)
152 #define OP_XY_SCANLINES_BLT OP_2D(0x25)
153 #define OP_XY_TEXT_BLT OP_2D(0x26)
154 #define OP_XY_TEXT_IMMEDIATE_BLT OP_2D(0x31)
155 #define OP_XY_COLOR_BLT OP_2D(0x50)
156 #define OP_XY_PAT_BLT OP_2D(0x51)
157 #define OP_XY_MONO_PAT_BLT OP_2D(0x52)
158 #define OP_XY_SRC_COPY_BLT OP_2D(0x53)
159 #define OP_XY_MONO_SRC_COPY_BLT OP_2D(0x54)
160 #define OP_XY_FULL_BLT OP_2D(0x55)
161 #define OP_XY_FULL_MONO_SRC_BLT OP_2D(0x56)
162 #define OP_XY_FULL_MONO_PATTERN_BLT OP_2D(0x57)
163 #define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT OP_2D(0x58)
164 #define OP_XY_MONO_PAT_FIXED_BLT OP_2D(0x59)
165 #define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT OP_2D(0x71)
166 #define OP_XY_PAT_BLT_IMMEDIATE OP_2D(0x72)
167 #define OP_XY_SRC_COPY_CHROMA_BLT OP_2D(0x73)
168 #define OP_XY_FULL_IMMEDIATE_PATTERN_BLT OP_2D(0x74)
169 #define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT OP_2D(0x75)
170 #define OP_XY_PAT_CHROMA_BLT OP_2D(0x76)
171 #define OP_XY_PAT_CHROMA_BLT_IMMEDIATE OP_2D(0x77)
172
173 /* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
174 #define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
175 ((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
176
177 #define OP_STATE_PREFETCH OP_3D_MEDIA(0x0, 0x0, 0x03)
178
179 #define OP_STATE_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x01)
180 #define OP_STATE_SIP OP_3D_MEDIA(0x0, 0x1, 0x02)
181 #define OP_3D_MEDIA_0_1_4 OP_3D_MEDIA(0x0, 0x1, 0x04)
182 #define OP_SWTESS_BASE_ADDRESS OP_3D_MEDIA(0x0, 0x1, 0x03)
183
184 #define OP_3DSTATE_VF_STATISTICS_GM45 OP_3D_MEDIA(0x1, 0x0, 0x0B)
185
186 #define OP_PIPELINE_SELECT OP_3D_MEDIA(0x1, 0x1, 0x04)
187
188 #define OP_MEDIA_VFE_STATE OP_3D_MEDIA(0x2, 0x0, 0x0)
189 #define OP_MEDIA_CURBE_LOAD OP_3D_MEDIA(0x2, 0x0, 0x1)
190 #define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD OP_3D_MEDIA(0x2, 0x0, 0x2)
191 #define OP_MEDIA_GATEWAY_STATE OP_3D_MEDIA(0x2, 0x0, 0x3)
192 #define OP_MEDIA_STATE_FLUSH OP_3D_MEDIA(0x2, 0x0, 0x4)
193 #define OP_MEDIA_POOL_STATE OP_3D_MEDIA(0x2, 0x0, 0x5)
194
195 #define OP_MEDIA_OBJECT OP_3D_MEDIA(0x2, 0x1, 0x0)
196 #define OP_MEDIA_OBJECT_PRT OP_3D_MEDIA(0x2, 0x1, 0x2)
197 #define OP_MEDIA_OBJECT_WALKER OP_3D_MEDIA(0x2, 0x1, 0x3)
198 #define OP_GPGPU_WALKER OP_3D_MEDIA(0x2, 0x1, 0x5)
199
200 #define OP_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
201 #define OP_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
202 #define OP_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
203 #define OP_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
204 #define OP_3DSTATE_VERTEX_BUFFERS OP_3D_MEDIA(0x3, 0x0, 0x08)
205 #define OP_3DSTATE_VERTEX_ELEMENTS OP_3D_MEDIA(0x3, 0x0, 0x09)
206 #define OP_3DSTATE_INDEX_BUFFER OP_3D_MEDIA(0x3, 0x0, 0x0A)
207 #define OP_3DSTATE_VF_STATISTICS OP_3D_MEDIA(0x3, 0x0, 0x0B)
208 #define OP_3DSTATE_VF OP_3D_MEDIA(0x3, 0x0, 0x0C) /* HSW+ */
209 #define OP_3DSTATE_CC_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0E)
210 #define OP_3DSTATE_SCISSOR_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x0F)
211 #define OP_3DSTATE_VS OP_3D_MEDIA(0x3, 0x0, 0x10)
212 #define OP_3DSTATE_GS OP_3D_MEDIA(0x3, 0x0, 0x11)
213 #define OP_3DSTATE_CLIP OP_3D_MEDIA(0x3, 0x0, 0x12)
214 #define OP_3DSTATE_SF OP_3D_MEDIA(0x3, 0x0, 0x13)
215 #define OP_3DSTATE_WM OP_3D_MEDIA(0x3, 0x0, 0x14)
216 #define OP_3DSTATE_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x15)
217 #define OP_3DSTATE_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x16)
218 #define OP_3DSTATE_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x17)
219 #define OP_3DSTATE_SAMPLE_MASK OP_3D_MEDIA(0x3, 0x0, 0x18)
220 #define OP_3DSTATE_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
221 #define OP_3DSTATE_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
222 #define OP_3DSTATE_HS OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
223 #define OP_3DSTATE_TE OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
224 #define OP_3DSTATE_DS OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
225 #define OP_3DSTATE_STREAMOUT OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
226 #define OP_3DSTATE_SBE OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
227 #define OP_3DSTATE_PS OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
228 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
229 #define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
230 #define OP_3DSTATE_BLEND_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
231 #define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
232 #define OP_3DSTATE_BINDING_TABLE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
233 #define OP_3DSTATE_BINDING_TABLE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
234 #define OP_3DSTATE_BINDING_TABLE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
235 #define OP_3DSTATE_BINDING_TABLE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
236 #define OP_3DSTATE_BINDING_TABLE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
237 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
238 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
239 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
240 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
241 #define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
242 #define OP_3DSTATE_URB_VS OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
243 #define OP_3DSTATE_URB_HS OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
244 #define OP_3DSTATE_URB_DS OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
245 #define OP_3DSTATE_URB_GS OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
246 #define OP_3DSTATE_GATHER_CONSTANT_VS OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
247 #define OP_3DSTATE_GATHER_CONSTANT_GS OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
248 #define OP_3DSTATE_GATHER_CONSTANT_HS OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
249 #define OP_3DSTATE_GATHER_CONSTANT_DS OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
250 #define OP_3DSTATE_GATHER_CONSTANT_PS OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
251 #define OP_3DSTATE_DX9_CONSTANTF_VS OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
252 #define OP_3DSTATE_DX9_CONSTANTF_PS OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
253 #define OP_3DSTATE_DX9_CONSTANTI_VS OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
254 #define OP_3DSTATE_DX9_CONSTANTI_PS OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
255 #define OP_3DSTATE_DX9_CONSTANTB_VS OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
256 #define OP_3DSTATE_DX9_CONSTANTB_PS OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
257 #define OP_3DSTATE_DX9_LOCAL_VALID_VS OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
258 #define OP_3DSTATE_DX9_LOCAL_VALID_PS OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
259 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
260 #define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
261 #define OP_3DSTATE_BINDING_TABLE_EDIT_VS OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
262 #define OP_3DSTATE_BINDING_TABLE_EDIT_GS OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
263 #define OP_3DSTATE_BINDING_TABLE_EDIT_HS OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
264 #define OP_3DSTATE_BINDING_TABLE_EDIT_DS OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
265 #define OP_3DSTATE_BINDING_TABLE_EDIT_PS OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
266
267 #define OP_3DSTATE_VF_INSTANCING OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
268 #define OP_3DSTATE_VF_SGVS OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
269 #define OP_3DSTATE_VF_TOPOLOGY OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
270 #define OP_3DSTATE_WM_CHROMAKEY OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
271 #define OP_3DSTATE_PS_BLEND OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
272 #define OP_3DSTATE_WM_DEPTH_STENCIL OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
273 #define OP_3DSTATE_PS_EXTRA OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
274 #define OP_3DSTATE_RASTER OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
275 #define OP_3DSTATE_SBE_SWIZ OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
276 #define OP_3DSTATE_WM_HZ_OP OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
277 #define OP_3DSTATE_COMPONENT_PACKING OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
278
279 #define OP_3DSTATE_DRAWING_RECTANGLE OP_3D_MEDIA(0x3, 0x1, 0x00)
280 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD0 OP_3D_MEDIA(0x3, 0x1, 0x02)
281 #define OP_3DSTATE_CHROMA_KEY OP_3D_MEDIA(0x3, 0x1, 0x04)
282 #define OP_SNB_3DSTATE_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x05)
283 #define OP_3DSTATE_POLY_STIPPLE_OFFSET OP_3D_MEDIA(0x3, 0x1, 0x06)
284 #define OP_3DSTATE_POLY_STIPPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x07)
285 #define OP_3DSTATE_LINE_STIPPLE OP_3D_MEDIA(0x3, 0x1, 0x08)
286 #define OP_3DSTATE_AA_LINE_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x0A)
287 #define OP_3DSTATE_GS_SVB_INDEX OP_3D_MEDIA(0x3, 0x1, 0x0B)
288 #define OP_3DSTATE_SAMPLER_PALETTE_LOAD1 OP_3D_MEDIA(0x3, 0x1, 0x0C)
289 #define OP_3DSTATE_MULTISAMPLE_BDW OP_3D_MEDIA(0x3, 0x0, 0x0D)
290 #define OP_SNB_3DSTATE_STENCIL_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0E)
291 #define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x0F)
292 #define OP_SNB_3DSTATE_CLEAR_PARAMS OP_3D_MEDIA(0x3, 0x1, 0x10)
293 #define OP_3DSTATE_MONOFILTER_SIZE OP_3D_MEDIA(0x3, 0x1, 0x11)
294 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
295 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
296 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
297 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
298 #define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
299 #define OP_3DSTATE_SO_DECL_LIST OP_3D_MEDIA(0x3, 0x1, 0x17)
300 #define OP_3DSTATE_SO_BUFFER OP_3D_MEDIA(0x3, 0x1, 0x18)
301 #define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
302 #define OP_3DSTATE_GATHER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
303 #define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
304 #define OP_3DSTATE_SAMPLE_PATTERN OP_3D_MEDIA(0x3, 0x1, 0x1C)
305 #define OP_PIPE_CONTROL OP_3D_MEDIA(0x3, 0x2, 0x00)
306 #define OP_3DPRIMITIVE OP_3D_MEDIA(0x3, 0x3, 0x00)
307
308 /* VCCP Command Parser */
309
310 /*
311 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
312 * git://anongit.freedesktop.org/vaapi/intel-driver
313 * src/i965_defines.h
314 *
315 */
316
317 #define OP_MFX(pipeline, op, sub_opa, sub_opb) \
318 (3 << 13 | \
319 (pipeline) << 11 | \
320 (op) << 8 | \
321 (sub_opa) << 5 | \
322 (sub_opb))
323
324 #define OP_MFX_PIPE_MODE_SELECT OP_MFX(2, 0, 0, 0) /* ALL */
325 #define OP_MFX_SURFACE_STATE OP_MFX(2, 0, 0, 1) /* ALL */
326 #define OP_MFX_PIPE_BUF_ADDR_STATE OP_MFX(2, 0, 0, 2) /* ALL */
327 #define OP_MFX_IND_OBJ_BASE_ADDR_STATE OP_MFX(2, 0, 0, 3) /* ALL */
328 #define OP_MFX_BSP_BUF_BASE_ADDR_STATE OP_MFX(2, 0, 0, 4) /* ALL */
329 #define OP_2_0_0_5 OP_MFX(2, 0, 0, 5) /* ALL */
330 #define OP_MFX_STATE_POINTER OP_MFX(2, 0, 0, 6) /* ALL */
331 #define OP_MFX_QM_STATE OP_MFX(2, 0, 0, 7) /* IVB+ */
332 #define OP_MFX_FQM_STATE OP_MFX(2, 0, 0, 8) /* IVB+ */
333 #define OP_MFX_PAK_INSERT_OBJECT OP_MFX(2, 0, 2, 8) /* IVB+ */
334 #define OP_MFX_STITCH_OBJECT OP_MFX(2, 0, 2, 0xA) /* IVB+ */
335
336 #define OP_MFD_IT_OBJECT OP_MFX(2, 0, 1, 9) /* ALL */
337
338 #define OP_MFX_WAIT OP_MFX(1, 0, 0, 0) /* IVB+ */
339 #define OP_MFX_AVC_IMG_STATE OP_MFX(2, 1, 0, 0) /* ALL */
340 #define OP_MFX_AVC_QM_STATE OP_MFX(2, 1, 0, 1) /* ALL */
341 #define OP_MFX_AVC_DIRECTMODE_STATE OP_MFX(2, 1, 0, 2) /* ALL */
342 #define OP_MFX_AVC_SLICE_STATE OP_MFX(2, 1, 0, 3) /* ALL */
343 #define OP_MFX_AVC_REF_IDX_STATE OP_MFX(2, 1, 0, 4) /* ALL */
344 #define OP_MFX_AVC_WEIGHTOFFSET_STATE OP_MFX(2, 1, 0, 5) /* ALL */
345 #define OP_MFD_AVC_PICID_STATE OP_MFX(2, 1, 1, 5) /* HSW+ */
346 #define OP_MFD_AVC_DPB_STATE OP_MFX(2, 1, 1, 6) /* IVB+ */
347 #define OP_MFD_AVC_SLICEADDR OP_MFX(2, 1, 1, 7) /* IVB+ */
348 #define OP_MFD_AVC_BSD_OBJECT OP_MFX(2, 1, 1, 8) /* ALL */
349 #define OP_MFC_AVC_PAK_OBJECT OP_MFX(2, 1, 2, 9) /* ALL */
350
351 #define OP_MFX_VC1_PRED_PIPE_STATE OP_MFX(2, 2, 0, 1) /* ALL */
352 #define OP_MFX_VC1_DIRECTMODE_STATE OP_MFX(2, 2, 0, 2) /* ALL */
353 #define OP_MFD_VC1_SHORT_PIC_STATE OP_MFX(2, 2, 1, 0) /* IVB+ */
354 #define OP_MFD_VC1_LONG_PIC_STATE OP_MFX(2, 2, 1, 1) /* IVB+ */
355 #define OP_MFD_VC1_BSD_OBJECT OP_MFX(2, 2, 1, 8) /* ALL */
356
357 #define OP_MFX_MPEG2_PIC_STATE OP_MFX(2, 3, 0, 0) /* ALL */
358 #define OP_MFX_MPEG2_QM_STATE OP_MFX(2, 3, 0, 1) /* ALL */
359 #define OP_MFD_MPEG2_BSD_OBJECT OP_MFX(2, 3, 1, 8) /* ALL */
360 #define OP_MFC_MPEG2_SLICEGROUP_STATE OP_MFX(2, 3, 2, 3) /* ALL */
361 #define OP_MFC_MPEG2_PAK_OBJECT OP_MFX(2, 3, 2, 9) /* ALL */
362
363 #define OP_MFX_2_6_0_0 OP_MFX(2, 6, 0, 0) /* IVB+ */
364 #define OP_MFX_2_6_0_8 OP_MFX(2, 6, 0, 8) /* IVB+ */
365 #define OP_MFX_2_6_0_9 OP_MFX(2, 6, 0, 9) /* IVB+ */
366
367 #define OP_MFX_JPEG_PIC_STATE OP_MFX(2, 7, 0, 0)
368 #define OP_MFX_JPEG_HUFF_TABLE_STATE OP_MFX(2, 7, 0, 2)
369 #define OP_MFD_JPEG_BSD_OBJECT OP_MFX(2, 7, 1, 8)
370
371 #define OP_VEB(pipeline, op, sub_opa, sub_opb) \
372 (3 << 13 | \
373 (pipeline) << 11 | \
374 (op) << 8 | \
375 (sub_opa) << 5 | \
376 (sub_opb))
377
378 #define OP_VEB_SURFACE_STATE OP_VEB(2, 4, 0, 0)
379 #define OP_VEB_STATE OP_VEB(2, 4, 0, 2)
380 #define OP_VEB_DNDI_IECP_STATE OP_VEB(2, 4, 0, 3)
381
382 struct parser_exec_state;
383
384 typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
385
386 #define GVT_CMD_HASH_BITS 7
387
388 /* which DWords need address fix */
389 #define ADDR_FIX_1(x1) (1 << (x1))
390 #define ADDR_FIX_2(x1, x2) (ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
391 #define ADDR_FIX_3(x1, x2, x3) (ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
392 #define ADDR_FIX_4(x1, x2, x3, x4) (ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
393 #define ADDR_FIX_5(x1, x2, x3, x4, x5) (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
394
395 #define DWORD_FIELD(dword, end, start) \
396 FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
397
398 #define OP_LENGTH_BIAS 2
399 #define CMD_LEN(value) (value + OP_LENGTH_BIAS)
400
gvt_check_valid_cmd_length(int len,int valid_len)401 static int gvt_check_valid_cmd_length(int len, int valid_len)
402 {
403 if (valid_len != len) {
404 gvt_err("len is not valid: len=%u valid_len=%u\n",
405 len, valid_len);
406 return -EFAULT;
407 }
408 return 0;
409 }
410
411 struct cmd_info {
412 const char *name;
413 u32 opcode;
414
415 #define F_LEN_MASK 3U
416 #define F_LEN_CONST 1U
417 #define F_LEN_VAR 0U
418 /* value is const although LEN maybe variable */
419 #define F_LEN_VAR_FIXED (1<<1)
420
421 /*
422 * command has its own ip advance logic
423 * e.g. MI_BATCH_START, MI_BATCH_END
424 */
425 #define F_IP_ADVANCE_CUSTOM (1<<2)
426 u32 flag;
427
428 #define R_RCS BIT(RCS0)
429 #define R_VCS1 BIT(VCS0)
430 #define R_VCS2 BIT(VCS1)
431 #define R_VCS (R_VCS1 | R_VCS2)
432 #define R_BCS BIT(BCS0)
433 #define R_VECS BIT(VECS0)
434 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
435 /* rings that support this cmd: BLT/RCS/VCS/VECS */
436 intel_engine_mask_t rings;
437
438 /* devices that support this cmd: SNB/IVB/HSW/... */
439 u16 devices;
440
441 /* which DWords are address that need fix up.
442 * bit 0 means a 32-bit non address operand in command
443 * bit 1 means address operand, which could be 32-bit
444 * or 64-bit depending on different architectures.(
445 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
446 * No matter the address length, each address only takes
447 * one bit in the bitmap.
448 */
449 u16 addr_bitmap;
450
451 /* flag == F_LEN_CONST : command length
452 * flag == F_LEN_VAR : length bias bits
453 * Note: length is in DWord
454 */
455 u32 len;
456
457 parser_cmd_handler handler;
458
459 /* valid length in DWord */
460 u32 valid_len;
461 };
462
463 struct cmd_entry {
464 struct hlist_node hlist;
465 const struct cmd_info *info;
466 };
467
468 enum {
469 RING_BUFFER_INSTRUCTION,
470 BATCH_BUFFER_INSTRUCTION,
471 BATCH_BUFFER_2ND_LEVEL,
472 RING_BUFFER_CTX,
473 };
474
475 enum {
476 GTT_BUFFER,
477 PPGTT_BUFFER
478 };
479
480 struct parser_exec_state {
481 struct intel_vgpu *vgpu;
482 const struct intel_engine_cs *engine;
483
484 int buf_type;
485
486 /* batch buffer address type */
487 int buf_addr_type;
488
489 /* graphics memory address of ring buffer start */
490 unsigned long ring_start;
491 unsigned long ring_size;
492 unsigned long ring_head;
493 unsigned long ring_tail;
494
495 /* instruction graphics memory address */
496 unsigned long ip_gma;
497
498 /* mapped va of the instr_gma */
499 void *ip_va;
500 void *rb_va;
501
502 void *ret_bb_va;
503 /* next instruction when return from batch buffer to ring buffer */
504 unsigned long ret_ip_gma_ring;
505
506 /* next instruction when return from 2nd batch buffer to batch buffer */
507 unsigned long ret_ip_gma_bb;
508
509 /* batch buffer address type (GTT or PPGTT)
510 * used when ret from 2nd level batch buffer
511 */
512 int saved_buf_addr_type;
513 bool is_ctx_wa;
514 bool is_init_ctx;
515
516 const struct cmd_info *info;
517
518 struct intel_vgpu_workload *workload;
519 };
520
521 #define gmadr_dw_number(s) \
522 (s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
523
524 static unsigned long bypass_scan_mask = 0;
525
526 /* ring ALL, type = 0 */
527 static const struct sub_op_bits sub_op_mi[] = {
528 {31, 29},
529 {28, 23},
530 };
531
532 static const struct decode_info decode_info_mi = {
533 "MI",
534 OP_LEN_MI,
535 ARRAY_SIZE(sub_op_mi),
536 sub_op_mi,
537 };
538
539 /* ring RCS, command type 2 */
540 static const struct sub_op_bits sub_op_2d[] = {
541 {31, 29},
542 {28, 22},
543 };
544
545 static const struct decode_info decode_info_2d = {
546 "2D",
547 OP_LEN_2D,
548 ARRAY_SIZE(sub_op_2d),
549 sub_op_2d,
550 };
551
552 /* ring RCS, command type 3 */
553 static const struct sub_op_bits sub_op_3d_media[] = {
554 {31, 29},
555 {28, 27},
556 {26, 24},
557 {23, 16},
558 };
559
560 static const struct decode_info decode_info_3d_media = {
561 "3D_Media",
562 OP_LEN_3D_MEDIA,
563 ARRAY_SIZE(sub_op_3d_media),
564 sub_op_3d_media,
565 };
566
567 /* ring VCS, command type 3 */
568 static const struct sub_op_bits sub_op_mfx_vc[] = {
569 {31, 29},
570 {28, 27},
571 {26, 24},
572 {23, 21},
573 {20, 16},
574 };
575
576 static const struct decode_info decode_info_mfx_vc = {
577 "MFX_VC",
578 OP_LEN_MFX_VC,
579 ARRAY_SIZE(sub_op_mfx_vc),
580 sub_op_mfx_vc,
581 };
582
583 /* ring VECS, command type 3 */
584 static const struct sub_op_bits sub_op_vebox[] = {
585 {31, 29},
586 {28, 27},
587 {26, 24},
588 {23, 21},
589 {20, 16},
590 };
591
592 static const struct decode_info decode_info_vebox = {
593 "VEBOX",
594 OP_LEN_VEBOX,
595 ARRAY_SIZE(sub_op_vebox),
596 sub_op_vebox,
597 };
598
599 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
600 [RCS0] = {
601 &decode_info_mi,
602 NULL,
603 NULL,
604 &decode_info_3d_media,
605 NULL,
606 NULL,
607 NULL,
608 NULL,
609 },
610
611 [VCS0] = {
612 &decode_info_mi,
613 NULL,
614 NULL,
615 &decode_info_mfx_vc,
616 NULL,
617 NULL,
618 NULL,
619 NULL,
620 },
621
622 [BCS0] = {
623 &decode_info_mi,
624 NULL,
625 &decode_info_2d,
626 NULL,
627 NULL,
628 NULL,
629 NULL,
630 NULL,
631 },
632
633 [VECS0] = {
634 &decode_info_mi,
635 NULL,
636 NULL,
637 &decode_info_vebox,
638 NULL,
639 NULL,
640 NULL,
641 NULL,
642 },
643
644 [VCS1] = {
645 &decode_info_mi,
646 NULL,
647 NULL,
648 &decode_info_mfx_vc,
649 NULL,
650 NULL,
651 NULL,
652 NULL,
653 },
654 };
655
get_opcode(u32 cmd,const struct intel_engine_cs * engine)656 static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
657 {
658 const struct decode_info *d_info;
659
660 d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
661 if (d_info == NULL)
662 return INVALID_OP;
663
664 return cmd >> (32 - d_info->op_len);
665 }
666
667 static inline const struct cmd_info *
find_cmd_entry(struct intel_gvt * gvt,unsigned int opcode,const struct intel_engine_cs * engine)668 find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
669 const struct intel_engine_cs *engine)
670 {
671 struct cmd_entry *e;
672
673 hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
674 if (opcode == e->info->opcode &&
675 e->info->rings & engine->mask)
676 return e->info;
677 }
678 return NULL;
679 }
680
681 static inline const struct cmd_info *
get_cmd_info(struct intel_gvt * gvt,u32 cmd,const struct intel_engine_cs * engine)682 get_cmd_info(struct intel_gvt *gvt, u32 cmd,
683 const struct intel_engine_cs *engine)
684 {
685 u32 opcode;
686
687 opcode = get_opcode(cmd, engine);
688 if (opcode == INVALID_OP)
689 return NULL;
690
691 return find_cmd_entry(gvt, opcode, engine);
692 }
693
sub_op_val(u32 cmd,u32 hi,u32 low)694 static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
695 {
696 return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
697 }
698
print_opcode(u32 cmd,const struct intel_engine_cs * engine)699 static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
700 {
701 const struct decode_info *d_info;
702 int i;
703
704 d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
705 if (d_info == NULL)
706 return;
707
708 gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
709 cmd >> (32 - d_info->op_len), d_info->name);
710
711 for (i = 0; i < d_info->nr_sub_op; i++)
712 pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
713 d_info->sub_op[i].low));
714
715 pr_err("\n");
716 }
717
cmd_ptr(struct parser_exec_state * s,int index)718 static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
719 {
720 return s->ip_va + (index << 2);
721 }
722
cmd_val(struct parser_exec_state * s,int index)723 static inline u32 cmd_val(struct parser_exec_state *s, int index)
724 {
725 return *cmd_ptr(s, index);
726 }
727
is_init_ctx(struct parser_exec_state * s)728 static inline bool is_init_ctx(struct parser_exec_state *s)
729 {
730 return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
731 }
732
parser_exec_state_dump(struct parser_exec_state * s)733 static void parser_exec_state_dump(struct parser_exec_state *s)
734 {
735 int cnt = 0;
736 int i;
737
738 gvt_dbg_cmd(" vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
739 " ring_head(%08lx) ring_tail(%08lx)\n",
740 s->vgpu->id, s->engine->name,
741 s->ring_start, s->ring_start + s->ring_size,
742 s->ring_head, s->ring_tail);
743
744 gvt_dbg_cmd(" %s %s ip_gma(%08lx) ",
745 s->buf_type == RING_BUFFER_INSTRUCTION ?
746 "RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
747 "CTX_BUFFER" : "BATCH_BUFFER"),
748 s->buf_addr_type == GTT_BUFFER ?
749 "GTT" : "PPGTT", s->ip_gma);
750
751 if (s->ip_va == NULL) {
752 gvt_dbg_cmd(" ip_va(NULL)");
753 return;
754 }
755
756 gvt_dbg_cmd(" ip_va=%p: %08x %08x %08x %08x\n",
757 s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
758 cmd_val(s, 2), cmd_val(s, 3));
759
760 print_opcode(cmd_val(s, 0), s->engine);
761
762 s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
763
764 while (cnt < 1024) {
765 gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
766 for (i = 0; i < 8; i++)
767 gvt_dbg_cmd("%08x ", cmd_val(s, i));
768 gvt_dbg_cmd("\n");
769
770 s->ip_va += 8 * sizeof(u32);
771 cnt += 8;
772 }
773 }
774
update_ip_va(struct parser_exec_state * s)775 static inline void update_ip_va(struct parser_exec_state *s)
776 {
777 unsigned long len = 0;
778
779 if (WARN_ON(s->ring_head == s->ring_tail))
780 return;
781
782 if (s->buf_type == RING_BUFFER_INSTRUCTION ||
783 s->buf_type == RING_BUFFER_CTX) {
784 unsigned long ring_top = s->ring_start + s->ring_size;
785
786 if (s->ring_head > s->ring_tail) {
787 if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
788 len = (s->ip_gma - s->ring_head);
789 else if (s->ip_gma >= s->ring_start &&
790 s->ip_gma <= s->ring_tail)
791 len = (ring_top - s->ring_head) +
792 (s->ip_gma - s->ring_start);
793 } else
794 len = (s->ip_gma - s->ring_head);
795
796 s->ip_va = s->rb_va + len;
797 } else {/* shadow batch buffer */
798 s->ip_va = s->ret_bb_va;
799 }
800 }
801
ip_gma_set(struct parser_exec_state * s,unsigned long ip_gma)802 static inline int ip_gma_set(struct parser_exec_state *s,
803 unsigned long ip_gma)
804 {
805 WARN_ON(!IS_ALIGNED(ip_gma, 4));
806
807 s->ip_gma = ip_gma;
808 update_ip_va(s);
809 return 0;
810 }
811
ip_gma_advance(struct parser_exec_state * s,unsigned int dw_len)812 static inline int ip_gma_advance(struct parser_exec_state *s,
813 unsigned int dw_len)
814 {
815 s->ip_gma += (dw_len << 2);
816
817 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
818 if (s->ip_gma >= s->ring_start + s->ring_size)
819 s->ip_gma -= s->ring_size;
820 update_ip_va(s);
821 } else {
822 s->ip_va += (dw_len << 2);
823 }
824
825 return 0;
826 }
827
get_cmd_length(const struct cmd_info * info,u32 cmd)828 static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
829 {
830 if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
831 return info->len;
832 else
833 return (cmd & ((1U << info->len) - 1)) + 2;
834 return 0;
835 }
836
cmd_length(struct parser_exec_state * s)837 static inline int cmd_length(struct parser_exec_state *s)
838 {
839 return get_cmd_length(s->info, cmd_val(s, 0));
840 }
841
842 /* do not remove this, some platform may need clflush here */
843 #define patch_value(s, addr, val) do { \
844 *addr = val; \
845 } while (0)
846
is_mocs_mmio(unsigned int offset)847 static inline bool is_mocs_mmio(unsigned int offset)
848 {
849 return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
850 ((offset >= 0xb020) && (offset <= 0xb0a0));
851 }
852
is_cmd_update_pdps(unsigned int offset,struct parser_exec_state * s)853 static int is_cmd_update_pdps(unsigned int offset,
854 struct parser_exec_state *s)
855 {
856 u32 base = s->workload->engine->mmio_base;
857 return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
858 }
859
cmd_pdp_mmio_update_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index)860 static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
861 unsigned int offset, unsigned int index)
862 {
863 struct intel_vgpu *vgpu = s->vgpu;
864 struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
865 struct intel_vgpu_mm *mm;
866 u64 pdps[GEN8_3LVL_PDPES];
867
868 if (shadow_mm->ppgtt_mm.root_entry_type ==
869 GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
870 pdps[0] = (u64)cmd_val(s, 2) << 32;
871 pdps[0] |= cmd_val(s, 4);
872
873 mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
874 if (!mm) {
875 gvt_vgpu_err("failed to get the 4-level shadow vm\n");
876 return -EINVAL;
877 }
878 intel_vgpu_mm_get(mm);
879 list_add_tail(&mm->ppgtt_mm.link,
880 &s->workload->lri_shadow_mm);
881 *cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
882 *cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
883 } else {
884 /* Currently all guests use PML4 table and now can't
885 * have a guest with 3-level table but uses LRI for
886 * PPGTT update. So this is simply un-testable. */
887 GEM_BUG_ON(1);
888 gvt_vgpu_err("invalid shared shadow vm type\n");
889 return -EINVAL;
890 }
891 return 0;
892 }
893
cmd_reg_handler(struct parser_exec_state * s,unsigned int offset,unsigned int index,char * cmd)894 static int cmd_reg_handler(struct parser_exec_state *s,
895 unsigned int offset, unsigned int index, char *cmd)
896 {
897 struct intel_vgpu *vgpu = s->vgpu;
898 struct intel_gvt *gvt = vgpu->gvt;
899 u32 ctx_sr_ctl;
900 u32 *vreg, vreg_old;
901
902 if (offset + 4 > gvt->device_info.mmio_size) {
903 gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
904 cmd, offset);
905 return -EFAULT;
906 }
907
908 if (is_init_ctx(s)) {
909 struct intel_gvt_mmio_info *mmio_info;
910
911 intel_gvt_mmio_set_cmd_accessible(gvt, offset);
912 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
913 if (mmio_info && mmio_info->write)
914 intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
915 return 0;
916 }
917
918 if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
919 gvt_vgpu_err("%s access to non-render register (%x)\n",
920 cmd, offset);
921 return -EBADRQC;
922 }
923
924 if (!strncmp(cmd, "srm", 3) ||
925 !strncmp(cmd, "lrm", 3)) {
926 if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
927 offset == 0x21f0 ||
928 (IS_BROADWELL(gvt->gt->i915) &&
929 offset == i915_mmio_reg_offset(INSTPM)))
930 return 0;
931 else {
932 gvt_vgpu_err("%s access to register (%x)\n",
933 cmd, offset);
934 return -EPERM;
935 }
936 }
937
938 if (!strncmp(cmd, "lrr-src", 7) ||
939 !strncmp(cmd, "lrr-dst", 7)) {
940 if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
941 return 0;
942 else {
943 gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
944 return -EPERM;
945 }
946 }
947
948 if (!strncmp(cmd, "pipe_ctrl", 9)) {
949 /* TODO: add LRI POST logic here */
950 return 0;
951 }
952
953 if (strncmp(cmd, "lri", 3))
954 return -EPERM;
955
956 /* below are all lri handlers */
957 vreg = &vgpu_vreg(s->vgpu, offset);
958
959 if (is_cmd_update_pdps(offset, s) &&
960 cmd_pdp_mmio_update_handler(s, offset, index))
961 return -EINVAL;
962
963 if (offset == i915_mmio_reg_offset(DERRMR) ||
964 offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
965 /* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
966 patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
967 }
968
969 if (is_mocs_mmio(offset))
970 *vreg = cmd_val(s, index + 1);
971
972 vreg_old = *vreg;
973
974 if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
975 u32 cmdval_new, cmdval;
976 struct intel_gvt_mmio_info *mmio_info;
977
978 cmdval = cmd_val(s, index + 1);
979
980 mmio_info = intel_gvt_find_mmio_info(gvt, offset);
981 if (!mmio_info) {
982 cmdval_new = cmdval;
983 } else {
984 u64 ro_mask = mmio_info->ro_mask;
985 int ret;
986
987 if (likely(!ro_mask))
988 ret = mmio_info->write(s->vgpu, offset,
989 &cmdval, 4);
990 else {
991 gvt_vgpu_err("try to write RO reg %x\n",
992 offset);
993 ret = -EBADRQC;
994 }
995 if (ret)
996 return ret;
997 cmdval_new = *vreg;
998 }
999 if (cmdval_new != cmdval)
1000 patch_value(s, cmd_ptr(s, index+1), cmdval_new);
1001 }
1002
1003 /* only patch cmd. restore vreg value if changed in mmio write handler*/
1004 *vreg = vreg_old;
1005
1006 /* TODO
1007 * In order to let workload with inhibit context to generate
1008 * correct image data into memory, vregs values will be loaded to
1009 * hw via LRIs in the workload with inhibit context. But as
1010 * indirect context is loaded prior to LRIs in workload, we don't
1011 * want reg values specified in indirect context overwritten by
1012 * LRIs in workloads. So, when scanning an indirect context, we
1013 * update reg values in it into vregs, so LRIs in workload with
1014 * inhibit context will restore with correct values
1015 */
1016 if (GRAPHICS_VER(s->engine->i915) == 9 &&
1017 intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
1018 !strncmp(cmd, "lri", 3)) {
1019 intel_gvt_read_gpa(s->vgpu,
1020 s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
1021 /* check inhibit context */
1022 if (ctx_sr_ctl & 1) {
1023 u32 data = cmd_val(s, index + 1);
1024
1025 if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1026 intel_vgpu_mask_mmio_write(vgpu,
1027 offset, &data, 4);
1028 else
1029 vgpu_vreg(vgpu, offset) = data;
1030 }
1031 }
1032
1033 return 0;
1034 }
1035
1036 #define cmd_reg(s, i) \
1037 (cmd_val(s, i) & GENMASK(22, 2))
1038
1039 #define cmd_reg_inhibit(s, i) \
1040 (cmd_val(s, i) & GENMASK(22, 18))
1041
1042 #define cmd_gma(s, i) \
1043 (cmd_val(s, i) & GENMASK(31, 2))
1044
1045 #define cmd_gma_hi(s, i) \
1046 (cmd_val(s, i) & GENMASK(15, 0))
1047
cmd_handler_lri(struct parser_exec_state * s)1048 static int cmd_handler_lri(struct parser_exec_state *s)
1049 {
1050 int i, ret = 0;
1051 int cmd_len = cmd_length(s);
1052
1053 for (i = 1; i < cmd_len; i += 2) {
1054 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1055 if (s->engine->id == BCS0 &&
1056 cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1057 ret |= 0;
1058 else
1059 ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1060 }
1061 if (ret)
1062 break;
1063 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1064 if (ret)
1065 break;
1066 }
1067 return ret;
1068 }
1069
cmd_handler_lrr(struct parser_exec_state * s)1070 static int cmd_handler_lrr(struct parser_exec_state *s)
1071 {
1072 int i, ret = 0;
1073 int cmd_len = cmd_length(s);
1074
1075 for (i = 1; i < cmd_len; i += 2) {
1076 if (IS_BROADWELL(s->engine->i915))
1077 ret |= ((cmd_reg_inhibit(s, i) ||
1078 (cmd_reg_inhibit(s, i + 1)))) ?
1079 -EBADRQC : 0;
1080 if (ret)
1081 break;
1082 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1083 if (ret)
1084 break;
1085 ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1086 if (ret)
1087 break;
1088 }
1089 return ret;
1090 }
1091
1092 static inline int cmd_address_audit(struct parser_exec_state *s,
1093 unsigned long guest_gma, int op_size, bool index_mode);
1094
cmd_handler_lrm(struct parser_exec_state * s)1095 static int cmd_handler_lrm(struct parser_exec_state *s)
1096 {
1097 struct intel_gvt *gvt = s->vgpu->gvt;
1098 int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1099 unsigned long gma;
1100 int i, ret = 0;
1101 int cmd_len = cmd_length(s);
1102
1103 for (i = 1; i < cmd_len;) {
1104 if (IS_BROADWELL(s->engine->i915))
1105 ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1106 if (ret)
1107 break;
1108 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1109 if (ret)
1110 break;
1111 if (cmd_val(s, 0) & (1 << 22)) {
1112 gma = cmd_gma(s, i + 1);
1113 if (gmadr_bytes == 8)
1114 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1115 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1116 if (ret)
1117 break;
1118 }
1119 i += gmadr_dw_number(s) + 1;
1120 }
1121 return ret;
1122 }
1123
cmd_handler_srm(struct parser_exec_state * s)1124 static int cmd_handler_srm(struct parser_exec_state *s)
1125 {
1126 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1127 unsigned long gma;
1128 int i, ret = 0;
1129 int cmd_len = cmd_length(s);
1130
1131 for (i = 1; i < cmd_len;) {
1132 ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1133 if (ret)
1134 break;
1135 if (cmd_val(s, 0) & (1 << 22)) {
1136 gma = cmd_gma(s, i + 1);
1137 if (gmadr_bytes == 8)
1138 gma |= (cmd_gma_hi(s, i + 2)) << 32;
1139 ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1140 if (ret)
1141 break;
1142 }
1143 i += gmadr_dw_number(s) + 1;
1144 }
1145 return ret;
1146 }
1147
1148 struct cmd_interrupt_event {
1149 int pipe_control_notify;
1150 int mi_flush_dw;
1151 int mi_user_interrupt;
1152 };
1153
1154 static const struct cmd_interrupt_event cmd_interrupt_events[] = {
1155 [RCS0] = {
1156 .pipe_control_notify = RCS_PIPE_CONTROL,
1157 .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1158 .mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1159 },
1160 [BCS0] = {
1161 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1162 .mi_flush_dw = BCS_MI_FLUSH_DW,
1163 .mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1164 },
1165 [VCS0] = {
1166 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1167 .mi_flush_dw = VCS_MI_FLUSH_DW,
1168 .mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1169 },
1170 [VCS1] = {
1171 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1172 .mi_flush_dw = VCS2_MI_FLUSH_DW,
1173 .mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1174 },
1175 [VECS0] = {
1176 .pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1177 .mi_flush_dw = VECS_MI_FLUSH_DW,
1178 .mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1179 },
1180 };
1181
cmd_handler_pipe_control(struct parser_exec_state * s)1182 static int cmd_handler_pipe_control(struct parser_exec_state *s)
1183 {
1184 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1185 unsigned long gma;
1186 bool index_mode = false;
1187 unsigned int post_sync;
1188 int ret = 0;
1189 u32 hws_pga, val;
1190
1191 post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1192
1193 /* LRI post sync */
1194 if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1195 ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1196 /* post sync */
1197 else if (post_sync) {
1198 if (post_sync == 2)
1199 ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1200 else if (post_sync == 3)
1201 ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1202 else if (post_sync == 1) {
1203 /* check ggtt*/
1204 if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1205 gma = cmd_val(s, 2) & GENMASK(31, 3);
1206 if (gmadr_bytes == 8)
1207 gma |= (cmd_gma_hi(s, 3)) << 32;
1208 /* Store Data Index */
1209 if (cmd_val(s, 1) & (1 << 21))
1210 index_mode = true;
1211 ret |= cmd_address_audit(s, gma, sizeof(u64),
1212 index_mode);
1213 if (ret)
1214 return ret;
1215 if (index_mode) {
1216 hws_pga = s->vgpu->hws_pga[s->engine->id];
1217 gma = hws_pga + gma;
1218 patch_value(s, cmd_ptr(s, 2), gma);
1219 val = cmd_val(s, 1) & (~(1 << 21));
1220 patch_value(s, cmd_ptr(s, 1), val);
1221 }
1222 }
1223 }
1224 }
1225
1226 if (ret)
1227 return ret;
1228
1229 if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1230 set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1231 s->workload->pending_events);
1232 return 0;
1233 }
1234
cmd_handler_mi_user_interrupt(struct parser_exec_state * s)1235 static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1236 {
1237 set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1238 s->workload->pending_events);
1239 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1240 return 0;
1241 }
1242
cmd_advance_default(struct parser_exec_state * s)1243 static int cmd_advance_default(struct parser_exec_state *s)
1244 {
1245 return ip_gma_advance(s, cmd_length(s));
1246 }
1247
cmd_handler_mi_batch_buffer_end(struct parser_exec_state * s)1248 static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1249 {
1250 int ret;
1251
1252 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1253 s->buf_type = BATCH_BUFFER_INSTRUCTION;
1254 ret = ip_gma_set(s, s->ret_ip_gma_bb);
1255 s->buf_addr_type = s->saved_buf_addr_type;
1256 } else if (s->buf_type == RING_BUFFER_CTX) {
1257 ret = ip_gma_set(s, s->ring_tail);
1258 } else {
1259 s->buf_type = RING_BUFFER_INSTRUCTION;
1260 s->buf_addr_type = GTT_BUFFER;
1261 if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1262 s->ret_ip_gma_ring -= s->ring_size;
1263 ret = ip_gma_set(s, s->ret_ip_gma_ring);
1264 }
1265 return ret;
1266 }
1267
1268 struct mi_display_flip_command_info {
1269 int pipe;
1270 int plane;
1271 int event;
1272 i915_reg_t stride_reg;
1273 i915_reg_t ctrl_reg;
1274 i915_reg_t surf_reg;
1275 u64 stride_val;
1276 u64 tile_val;
1277 u64 surf_val;
1278 bool async_flip;
1279 };
1280
1281 struct plane_code_mapping {
1282 int pipe;
1283 int plane;
1284 int event;
1285 };
1286
gen8_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1287 static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1288 struct mi_display_flip_command_info *info)
1289 {
1290 struct drm_i915_private *dev_priv = s->engine->i915;
1291 struct intel_display *display = dev_priv->display;
1292 struct plane_code_mapping gen8_plane_code[] = {
1293 [0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1294 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1295 [2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1296 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1297 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1298 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1299 };
1300 u32 dword0, dword1, dword2;
1301 u32 v;
1302
1303 dword0 = cmd_val(s, 0);
1304 dword1 = cmd_val(s, 1);
1305 dword2 = cmd_val(s, 2);
1306
1307 v = (dword0 & GENMASK(21, 19)) >> 19;
1308 if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1309 return -EBADRQC;
1310
1311 info->pipe = gen8_plane_code[v].pipe;
1312 info->plane = gen8_plane_code[v].plane;
1313 info->event = gen8_plane_code[v].event;
1314 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1315 info->tile_val = (dword1 & 0x1);
1316 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1317 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1318
1319 if (info->plane == PLANE_A) {
1320 info->ctrl_reg = DSPCNTR(display, info->pipe);
1321 info->stride_reg = DSPSTRIDE(display, info->pipe);
1322 info->surf_reg = DSPSURF(display, info->pipe);
1323 } else if (info->plane == PLANE_B) {
1324 info->ctrl_reg = SPRCTL(info->pipe);
1325 info->stride_reg = SPRSTRIDE(info->pipe);
1326 info->surf_reg = SPRSURF(info->pipe);
1327 } else {
1328 drm_WARN_ON(&dev_priv->drm, 1);
1329 return -EBADRQC;
1330 }
1331 return 0;
1332 }
1333
skl_decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1334 static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1335 struct mi_display_flip_command_info *info)
1336 {
1337 struct drm_i915_private *dev_priv = s->engine->i915;
1338 struct intel_display *display = dev_priv->display;
1339 struct intel_vgpu *vgpu = s->vgpu;
1340 u32 dword0 = cmd_val(s, 0);
1341 u32 dword1 = cmd_val(s, 1);
1342 u32 dword2 = cmd_val(s, 2);
1343 u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1344
1345 info->plane = PRIMARY_PLANE;
1346
1347 switch (plane) {
1348 case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1349 info->pipe = PIPE_A;
1350 info->event = PRIMARY_A_FLIP_DONE;
1351 break;
1352 case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1353 info->pipe = PIPE_B;
1354 info->event = PRIMARY_B_FLIP_DONE;
1355 break;
1356 case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1357 info->pipe = PIPE_C;
1358 info->event = PRIMARY_C_FLIP_DONE;
1359 break;
1360
1361 case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1362 info->pipe = PIPE_A;
1363 info->event = SPRITE_A_FLIP_DONE;
1364 info->plane = SPRITE_PLANE;
1365 break;
1366 case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1367 info->pipe = PIPE_B;
1368 info->event = SPRITE_B_FLIP_DONE;
1369 info->plane = SPRITE_PLANE;
1370 break;
1371 case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1372 info->pipe = PIPE_C;
1373 info->event = SPRITE_C_FLIP_DONE;
1374 info->plane = SPRITE_PLANE;
1375 break;
1376
1377 default:
1378 gvt_vgpu_err("unknown plane code %d\n", plane);
1379 return -EBADRQC;
1380 }
1381
1382 info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1383 info->tile_val = (dword1 & GENMASK(2, 0));
1384 info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1385 info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1386
1387 info->ctrl_reg = DSPCNTR(display, info->pipe);
1388 info->stride_reg = DSPSTRIDE(display, info->pipe);
1389 info->surf_reg = DSPSURF(display, info->pipe);
1390
1391 return 0;
1392 }
1393
gen8_check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1394 static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1395 struct mi_display_flip_command_info *info)
1396 {
1397 u32 stride, tile;
1398
1399 if (!info->async_flip)
1400 return 0;
1401
1402 if (GRAPHICS_VER(s->engine->i915) >= 9) {
1403 stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1404 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1405 GENMASK(12, 10)) >> 10;
1406 } else {
1407 stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1408 GENMASK(15, 6)) >> 6;
1409 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1410 }
1411
1412 if (stride != info->stride_val)
1413 gvt_dbg_cmd("cannot change stride during async flip\n");
1414
1415 if (tile != info->tile_val)
1416 gvt_dbg_cmd("cannot change tile during async flip\n");
1417
1418 return 0;
1419 }
1420
gen8_update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1421 static int gen8_update_plane_mmio_from_mi_display_flip(
1422 struct parser_exec_state *s,
1423 struct mi_display_flip_command_info *info)
1424 {
1425 struct drm_i915_private *dev_priv = s->engine->i915;
1426 struct intel_display *display = dev_priv->display;
1427 struct intel_vgpu *vgpu = s->vgpu;
1428
1429 set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1430 info->surf_val << 12);
1431 if (GRAPHICS_VER(dev_priv) >= 9) {
1432 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1433 info->stride_val);
1434 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1435 info->tile_val << 10);
1436 } else {
1437 set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1438 info->stride_val << 6);
1439 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1440 info->tile_val << 10);
1441 }
1442
1443 if (info->plane == PLANE_PRIMARY)
1444 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(display, info->pipe))++;
1445
1446 if (info->async_flip)
1447 intel_vgpu_trigger_virtual_event(vgpu, info->event);
1448 else
1449 set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1450
1451 return 0;
1452 }
1453
decode_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1454 static int decode_mi_display_flip(struct parser_exec_state *s,
1455 struct mi_display_flip_command_info *info)
1456 {
1457 if (IS_BROADWELL(s->engine->i915))
1458 return gen8_decode_mi_display_flip(s, info);
1459 if (GRAPHICS_VER(s->engine->i915) >= 9)
1460 return skl_decode_mi_display_flip(s, info);
1461
1462 return -ENODEV;
1463 }
1464
check_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1465 static int check_mi_display_flip(struct parser_exec_state *s,
1466 struct mi_display_flip_command_info *info)
1467 {
1468 return gen8_check_mi_display_flip(s, info);
1469 }
1470
update_plane_mmio_from_mi_display_flip(struct parser_exec_state * s,struct mi_display_flip_command_info * info)1471 static int update_plane_mmio_from_mi_display_flip(
1472 struct parser_exec_state *s,
1473 struct mi_display_flip_command_info *info)
1474 {
1475 return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1476 }
1477
cmd_handler_mi_display_flip(struct parser_exec_state * s)1478 static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1479 {
1480 struct mi_display_flip_command_info info;
1481 struct intel_vgpu *vgpu = s->vgpu;
1482 int ret;
1483 int i;
1484 int len = cmd_length(s);
1485 u32 valid_len = CMD_LEN(1);
1486
1487 /* Flip Type == Stereo 3D Flip */
1488 if (DWORD_FIELD(2, 1, 0) == 2)
1489 valid_len++;
1490 ret = gvt_check_valid_cmd_length(cmd_length(s),
1491 valid_len);
1492 if (ret)
1493 return ret;
1494
1495 ret = decode_mi_display_flip(s, &info);
1496 if (ret) {
1497 gvt_vgpu_err("fail to decode MI display flip command\n");
1498 return ret;
1499 }
1500
1501 ret = check_mi_display_flip(s, &info);
1502 if (ret) {
1503 gvt_vgpu_err("invalid MI display flip command\n");
1504 return ret;
1505 }
1506
1507 ret = update_plane_mmio_from_mi_display_flip(s, &info);
1508 if (ret) {
1509 gvt_vgpu_err("fail to update plane mmio\n");
1510 return ret;
1511 }
1512
1513 for (i = 0; i < len; i++)
1514 patch_value(s, cmd_ptr(s, i), MI_NOOP);
1515 return 0;
1516 }
1517
is_wait_for_flip_pending(u32 cmd)1518 static bool is_wait_for_flip_pending(u32 cmd)
1519 {
1520 return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1521 MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1522 MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1523 MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1524 MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1525 MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1526 }
1527
cmd_handler_mi_wait_for_event(struct parser_exec_state * s)1528 static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1529 {
1530 u32 cmd = cmd_val(s, 0);
1531
1532 if (!is_wait_for_flip_pending(cmd))
1533 return 0;
1534
1535 patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1536 return 0;
1537 }
1538
get_gma_bb_from_cmd(struct parser_exec_state * s,int index)1539 static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1540 {
1541 unsigned long addr;
1542 unsigned long gma_high, gma_low;
1543 struct intel_vgpu *vgpu = s->vgpu;
1544 int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1545
1546 if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1547 gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1548 return INTEL_GVT_INVALID_ADDR;
1549 }
1550
1551 gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1552 if (gmadr_bytes == 4) {
1553 addr = gma_low;
1554 } else {
1555 gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1556 addr = (((unsigned long)gma_high) << 32) | gma_low;
1557 }
1558 return addr;
1559 }
1560
cmd_address_audit(struct parser_exec_state * s,unsigned long guest_gma,int op_size,bool index_mode)1561 static inline int cmd_address_audit(struct parser_exec_state *s,
1562 unsigned long guest_gma, int op_size, bool index_mode)
1563 {
1564 struct intel_vgpu *vgpu = s->vgpu;
1565 u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1566 int i;
1567 int ret;
1568
1569 if (op_size > max_surface_size) {
1570 gvt_vgpu_err("command address audit fail name %s\n",
1571 s->info->name);
1572 return -EFAULT;
1573 }
1574
1575 if (index_mode) {
1576 if (guest_gma >= I915_GTT_PAGE_SIZE) {
1577 ret = -EFAULT;
1578 goto err;
1579 }
1580 } else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1581 ret = -EFAULT;
1582 goto err;
1583 }
1584
1585 return 0;
1586
1587 err:
1588 gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1589 s->info->name, guest_gma, op_size);
1590
1591 pr_err("cmd dump: ");
1592 for (i = 0; i < cmd_length(s); i++) {
1593 if (!(i % 4))
1594 pr_err("\n%08x ", cmd_val(s, i));
1595 else
1596 pr_err("%08x ", cmd_val(s, i));
1597 }
1598 pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1599 vgpu->id,
1600 vgpu_aperture_gmadr_base(vgpu),
1601 vgpu_aperture_gmadr_end(vgpu),
1602 vgpu_hidden_gmadr_base(vgpu),
1603 vgpu_hidden_gmadr_end(vgpu));
1604 return ret;
1605 }
1606
cmd_handler_mi_store_data_imm(struct parser_exec_state * s)1607 static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1608 {
1609 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1610 int op_size = (cmd_length(s) - 3) * sizeof(u32);
1611 int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1612 unsigned long gma, gma_low, gma_high;
1613 u32 valid_len = CMD_LEN(2);
1614 int ret = 0;
1615
1616 /* check ppggt */
1617 if (!(cmd_val(s, 0) & (1 << 22)))
1618 return 0;
1619
1620 /* check if QWORD */
1621 if (DWORD_FIELD(0, 21, 21))
1622 valid_len++;
1623 ret = gvt_check_valid_cmd_length(cmd_length(s),
1624 valid_len);
1625 if (ret)
1626 return ret;
1627
1628 gma = cmd_val(s, 2) & GENMASK(31, 2);
1629
1630 if (gmadr_bytes == 8) {
1631 gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1632 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1633 gma = (gma_high << 32) | gma_low;
1634 core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1635 }
1636 ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1637 return ret;
1638 }
1639
unexpected_cmd(struct parser_exec_state * s)1640 static inline int unexpected_cmd(struct parser_exec_state *s)
1641 {
1642 struct intel_vgpu *vgpu = s->vgpu;
1643
1644 gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1645
1646 return -EBADRQC;
1647 }
1648
cmd_handler_mi_semaphore_wait(struct parser_exec_state * s)1649 static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1650 {
1651 return unexpected_cmd(s);
1652 }
1653
cmd_handler_mi_report_perf_count(struct parser_exec_state * s)1654 static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1655 {
1656 return unexpected_cmd(s);
1657 }
1658
cmd_handler_mi_op_2e(struct parser_exec_state * s)1659 static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1660 {
1661 return unexpected_cmd(s);
1662 }
1663
cmd_handler_mi_op_2f(struct parser_exec_state * s)1664 static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1665 {
1666 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1667 int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1668 sizeof(u32);
1669 unsigned long gma, gma_high;
1670 u32 valid_len = CMD_LEN(1);
1671 int ret = 0;
1672
1673 if (!(cmd_val(s, 0) & (1 << 22)))
1674 return ret;
1675
1676 /* check inline data */
1677 if (cmd_val(s, 0) & BIT(18))
1678 valid_len = CMD_LEN(9);
1679 ret = gvt_check_valid_cmd_length(cmd_length(s),
1680 valid_len);
1681 if (ret)
1682 return ret;
1683
1684 gma = cmd_val(s, 1) & GENMASK(31, 2);
1685 if (gmadr_bytes == 8) {
1686 gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1687 gma = (gma_high << 32) | gma;
1688 }
1689 ret = cmd_address_audit(s, gma, op_size, false);
1690 return ret;
1691 }
1692
cmd_handler_mi_store_data_index(struct parser_exec_state * s)1693 static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1694 {
1695 return unexpected_cmd(s);
1696 }
1697
cmd_handler_mi_clflush(struct parser_exec_state * s)1698 static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1699 {
1700 return unexpected_cmd(s);
1701 }
1702
cmd_handler_mi_conditional_batch_buffer_end(struct parser_exec_state * s)1703 static int cmd_handler_mi_conditional_batch_buffer_end(
1704 struct parser_exec_state *s)
1705 {
1706 return unexpected_cmd(s);
1707 }
1708
cmd_handler_mi_update_gtt(struct parser_exec_state * s)1709 static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1710 {
1711 return unexpected_cmd(s);
1712 }
1713
cmd_handler_mi_flush_dw(struct parser_exec_state * s)1714 static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1715 {
1716 int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1717 unsigned long gma;
1718 bool index_mode = false;
1719 int ret = 0;
1720 u32 hws_pga, val;
1721 u32 valid_len = CMD_LEN(2);
1722
1723 ret = gvt_check_valid_cmd_length(cmd_length(s),
1724 valid_len);
1725 if (ret) {
1726 /* Check again for Qword */
1727 ret = gvt_check_valid_cmd_length(cmd_length(s),
1728 ++valid_len);
1729 return ret;
1730 }
1731
1732 /* Check post-sync and ppgtt bit */
1733 if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1734 gma = cmd_val(s, 1) & GENMASK(31, 3);
1735 if (gmadr_bytes == 8)
1736 gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1737 /* Store Data Index */
1738 if (cmd_val(s, 0) & (1 << 21))
1739 index_mode = true;
1740 ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1741 if (ret)
1742 return ret;
1743 if (index_mode) {
1744 hws_pga = s->vgpu->hws_pga[s->engine->id];
1745 gma = hws_pga + gma;
1746 patch_value(s, cmd_ptr(s, 1), gma);
1747 val = cmd_val(s, 0) & (~(1 << 21));
1748 patch_value(s, cmd_ptr(s, 0), val);
1749 }
1750 }
1751 /* Check notify bit */
1752 if ((cmd_val(s, 0) & (1 << 8)))
1753 set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1754 s->workload->pending_events);
1755 return ret;
1756 }
1757
addr_type_update_snb(struct parser_exec_state * s)1758 static void addr_type_update_snb(struct parser_exec_state *s)
1759 {
1760 if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1761 (BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1762 s->buf_addr_type = PPGTT_BUFFER;
1763 }
1764 }
1765
1766
copy_gma_to_hva(struct intel_vgpu * vgpu,struct intel_vgpu_mm * mm,unsigned long gma,unsigned long end_gma,void * va)1767 static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1768 unsigned long gma, unsigned long end_gma, void *va)
1769 {
1770 unsigned long copy_len, offset;
1771 unsigned long len = 0;
1772 unsigned long gpa;
1773
1774 while (gma != end_gma) {
1775 gpa = intel_vgpu_gma_to_gpa(mm, gma);
1776 if (gpa == INTEL_GVT_INVALID_ADDR) {
1777 gvt_vgpu_err("invalid gma address: %lx\n", gma);
1778 return -EFAULT;
1779 }
1780
1781 offset = gma & (I915_GTT_PAGE_SIZE - 1);
1782
1783 copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1784 I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1785
1786 intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1787
1788 len += copy_len;
1789 gma += copy_len;
1790 }
1791 return len;
1792 }
1793
1794
1795 /*
1796 * Check whether a batch buffer needs to be scanned. Currently
1797 * the only criteria is based on privilege.
1798 */
batch_buffer_needs_scan(struct parser_exec_state * s)1799 static int batch_buffer_needs_scan(struct parser_exec_state *s)
1800 {
1801 /* Decide privilege based on address space */
1802 if (cmd_val(s, 0) & BIT(8) &&
1803 !(s->vgpu->scan_nonprivbb & s->engine->mask))
1804 return 0;
1805
1806 return 1;
1807 }
1808
repr_addr_type(unsigned int type)1809 static const char *repr_addr_type(unsigned int type)
1810 {
1811 return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1812 }
1813
find_bb_size(struct parser_exec_state * s,unsigned long * bb_size,unsigned long * bb_end_cmd_offset)1814 static int find_bb_size(struct parser_exec_state *s,
1815 unsigned long *bb_size,
1816 unsigned long *bb_end_cmd_offset)
1817 {
1818 unsigned long gma = 0;
1819 const struct cmd_info *info;
1820 u32 cmd_len = 0;
1821 bool bb_end = false;
1822 struct intel_vgpu *vgpu = s->vgpu;
1823 u32 cmd;
1824 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1825 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1826
1827 *bb_size = 0;
1828 *bb_end_cmd_offset = 0;
1829
1830 /* get the start gm address of the batch buffer */
1831 gma = get_gma_bb_from_cmd(s, 1);
1832 if (gma == INTEL_GVT_INVALID_ADDR)
1833 return -EFAULT;
1834
1835 cmd = cmd_val(s, 0);
1836 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1837 if (info == NULL) {
1838 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1839 cmd, get_opcode(cmd, s->engine),
1840 repr_addr_type(s->buf_addr_type),
1841 s->engine->name, s->workload);
1842 return -EBADRQC;
1843 }
1844 do {
1845 if (copy_gma_to_hva(s->vgpu, mm,
1846 gma, gma + 4, &cmd) < 0)
1847 return -EFAULT;
1848 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1849 if (info == NULL) {
1850 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1851 cmd, get_opcode(cmd, s->engine),
1852 repr_addr_type(s->buf_addr_type),
1853 s->engine->name, s->workload);
1854 return -EBADRQC;
1855 }
1856
1857 if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1858 bb_end = true;
1859 } else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1860 if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1861 /* chained batch buffer */
1862 bb_end = true;
1863 }
1864
1865 if (bb_end)
1866 *bb_end_cmd_offset = *bb_size;
1867
1868 cmd_len = get_cmd_length(info, cmd) << 2;
1869 *bb_size += cmd_len;
1870 gma += cmd_len;
1871 } while (!bb_end);
1872
1873 return 0;
1874 }
1875
audit_bb_end(struct parser_exec_state * s,void * va)1876 static int audit_bb_end(struct parser_exec_state *s, void *va)
1877 {
1878 struct intel_vgpu *vgpu = s->vgpu;
1879 u32 cmd = *(u32 *)va;
1880 const struct cmd_info *info;
1881
1882 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1883 if (info == NULL) {
1884 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1885 cmd, get_opcode(cmd, s->engine),
1886 repr_addr_type(s->buf_addr_type),
1887 s->engine->name, s->workload);
1888 return -EBADRQC;
1889 }
1890
1891 if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1892 ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1893 (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1894 return 0;
1895
1896 return -EBADRQC;
1897 }
1898
perform_bb_shadow(struct parser_exec_state * s)1899 static int perform_bb_shadow(struct parser_exec_state *s)
1900 {
1901 struct intel_vgpu *vgpu = s->vgpu;
1902 struct intel_vgpu_shadow_bb *bb;
1903 unsigned long gma = 0;
1904 unsigned long bb_size;
1905 unsigned long bb_end_cmd_offset;
1906 int ret = 0;
1907 struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1908 s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1909 unsigned long start_offset = 0;
1910
1911 /* Get the start gm address of the batch buffer */
1912 gma = get_gma_bb_from_cmd(s, 1);
1913 if (gma == INTEL_GVT_INVALID_ADDR)
1914 return -EFAULT;
1915
1916 ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1917 if (ret)
1918 return ret;
1919
1920 bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1921 if (!bb)
1922 return -ENOMEM;
1923
1924 bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1925
1926 /*
1927 * The start_offset stores the batch buffer's start gma's
1928 * offset relative to page boundary. So for non-privileged batch
1929 * buffer, the shadowed gem object holds exactly the same page
1930 * layout as original gem object. This is for the convenience of
1931 * replacing the whole non-privilged batch buffer page to this
1932 * shadowed one in PPGTT at the same gma address. (This replacing
1933 * action is not implemented yet now, but may be necessary in
1934 * future).
1935 * For prileged batch buffer, we just change start gma address to
1936 * that of shadowed page.
1937 */
1938 if (bb->ppgtt)
1939 start_offset = gma & ~I915_GTT_PAGE_MASK;
1940
1941 bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1942 round_up(bb_size + start_offset,
1943 PAGE_SIZE));
1944 if (IS_ERR(bb->obj)) {
1945 ret = PTR_ERR(bb->obj);
1946 goto err_free_bb;
1947 }
1948
1949 bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1950 if (IS_ERR(bb->va)) {
1951 ret = PTR_ERR(bb->va);
1952 goto err_free_obj;
1953 }
1954
1955 ret = copy_gma_to_hva(s->vgpu, mm,
1956 gma, gma + bb_size,
1957 bb->va + start_offset);
1958 if (ret < 0) {
1959 gvt_vgpu_err("fail to copy guest ring buffer\n");
1960 ret = -EFAULT;
1961 goto err_unmap;
1962 }
1963
1964 ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1965 if (ret)
1966 goto err_unmap;
1967
1968 i915_gem_object_unlock(bb->obj);
1969 INIT_LIST_HEAD(&bb->list);
1970 list_add(&bb->list, &s->workload->shadow_bb);
1971
1972 bb->bb_start_cmd_va = s->ip_va;
1973
1974 if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1975 bb->bb_offset = s->ip_va - s->rb_va;
1976 else
1977 bb->bb_offset = 0;
1978
1979 /*
1980 * ip_va saves the virtual address of the shadow batch buffer, while
1981 * ip_gma saves the graphics address of the original batch buffer.
1982 * As the shadow batch buffer is just a copy from the original one,
1983 * it should be right to use shadow batch buffer'va and original batch
1984 * buffer's gma in pair. After all, we don't want to pin the shadow
1985 * buffer here (too early).
1986 */
1987 s->ip_va = bb->va + start_offset;
1988 s->ip_gma = gma;
1989 return 0;
1990 err_unmap:
1991 i915_gem_object_unpin_map(bb->obj);
1992 err_free_obj:
1993 i915_gem_object_put(bb->obj);
1994 err_free_bb:
1995 kfree(bb);
1996 return ret;
1997 }
1998
cmd_handler_mi_batch_buffer_start(struct parser_exec_state * s)1999 static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
2000 {
2001 bool second_level;
2002 int ret = 0;
2003 struct intel_vgpu *vgpu = s->vgpu;
2004
2005 if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
2006 gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
2007 return -EFAULT;
2008 }
2009
2010 second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
2011 if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
2012 gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
2013 return -EFAULT;
2014 }
2015
2016 s->saved_buf_addr_type = s->buf_addr_type;
2017 addr_type_update_snb(s);
2018 if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2019 s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2020 s->buf_type = BATCH_BUFFER_INSTRUCTION;
2021 } else if (second_level) {
2022 s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2023 s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2024 s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2025 }
2026
2027 if (batch_buffer_needs_scan(s)) {
2028 ret = perform_bb_shadow(s);
2029 if (ret < 0)
2030 gvt_vgpu_err("invalid shadow batch buffer\n");
2031 } else {
2032 /* emulate a batch buffer end to do return right */
2033 ret = cmd_handler_mi_batch_buffer_end(s);
2034 if (ret < 0)
2035 return ret;
2036 }
2037 return ret;
2038 }
2039
2040 static int mi_noop_index;
2041
2042 static const struct cmd_info cmd_info[] = {
2043 {"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2044
2045 {"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2046 0, 1, NULL},
2047
2048 {"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2049 0, 1, cmd_handler_mi_user_interrupt},
2050
2051 {"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2052 D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2053
2054 {"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2055
2056 {"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2057 NULL},
2058
2059 {"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2060 NULL},
2061
2062 {"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2063 NULL},
2064
2065 {"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2066 NULL},
2067
2068 {"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2069 D_ALL, 0, 1, NULL},
2070
2071 {"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2072 F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2073 cmd_handler_mi_batch_buffer_end},
2074
2075 {"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2076 0, 1, NULL},
2077
2078 {"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2079 NULL},
2080
2081 {"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2082 D_ALL, 0, 1, NULL},
2083
2084 {"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2085 NULL},
2086
2087 {"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2088 NULL},
2089
2090 {"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2091 R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2092
2093 {"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2094 R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2095
2096 {"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2097
2098 {"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2099 D_ALL, 0, 8, NULL, CMD_LEN(0)},
2100
2101 {"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2102 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2103 NULL, CMD_LEN(0)},
2104
2105 {"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2106 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2107 8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2108
2109 {"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2110 ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2111
2112 {"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2113 0, 8, cmd_handler_mi_store_data_index},
2114
2115 {"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2116 D_ALL, 0, 8, cmd_handler_lri},
2117
2118 {"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2119 cmd_handler_mi_update_gtt},
2120
2121 {"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2122 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2123 cmd_handler_srm, CMD_LEN(2)},
2124
2125 {"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2126 cmd_handler_mi_flush_dw},
2127
2128 {"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2129 10, cmd_handler_mi_clflush},
2130
2131 {"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2132 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2133 cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2134
2135 {"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2136 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2137 cmd_handler_lrm, CMD_LEN(2)},
2138
2139 {"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2140 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2141 cmd_handler_lrr, CMD_LEN(1)},
2142
2143 {"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2144 F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2145 8, NULL, CMD_LEN(2)},
2146
2147 {"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2148 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2149
2150 {"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2151 ADDR_FIX_1(2), 8, NULL},
2152
2153 {"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2154 ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2155
2156 {"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2157 8, cmd_handler_mi_op_2f},
2158
2159 {"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2160 F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2161 cmd_handler_mi_batch_buffer_start},
2162
2163 {"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2164 F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2165 cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2166
2167 {"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2168 R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2169
2170 {"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2171 ADDR_FIX_2(4, 7), 8, NULL},
2172
2173 {"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2174 0, 8, NULL},
2175
2176 {"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2177 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2178
2179 {"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2180
2181 {"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2182 0, 8, NULL},
2183
2184 {"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2185 ADDR_FIX_1(3), 8, NULL},
2186
2187 {"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2188 D_ALL, 0, 8, NULL},
2189
2190 {"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2191 ADDR_FIX_1(4), 8, NULL},
2192
2193 {"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2194 ADDR_FIX_2(4, 5), 8, NULL},
2195
2196 {"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2197 ADDR_FIX_1(4), 8, NULL},
2198
2199 {"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2200 ADDR_FIX_2(4, 7), 8, NULL},
2201
2202 {"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2203 D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2204
2205 {"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2206
2207 {"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2208 D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2209
2210 {"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2211 R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2212
2213 {"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2214 OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2215 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2216
2217 {"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2218 D_ALL, ADDR_FIX_1(4), 8, NULL},
2219
2220 {"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2221 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2222
2223 {"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2224 D_ALL, ADDR_FIX_1(4), 8, NULL},
2225
2226 {"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2227 D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2228
2229 {"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2230 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2231
2232 {"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2233 OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2234 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2235
2236 {"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2237 ADDR_FIX_2(4, 5), 8, NULL},
2238
2239 {"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2240 F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2241
2242 {"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2243 OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2244 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246 {"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2247 OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2248 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2249
2250 {"3DSTATE_BLEND_STATE_POINTERS",
2251 OP_3DSTATE_BLEND_STATE_POINTERS,
2252 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2253
2254 {"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2255 OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2256 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2257
2258 {"3DSTATE_BINDING_TABLE_POINTERS_VS",
2259 OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2260 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2261
2262 {"3DSTATE_BINDING_TABLE_POINTERS_HS",
2263 OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2264 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2265
2266 {"3DSTATE_BINDING_TABLE_POINTERS_DS",
2267 OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2268 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270 {"3DSTATE_BINDING_TABLE_POINTERS_GS",
2271 OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2272 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2273
2274 {"3DSTATE_BINDING_TABLE_POINTERS_PS",
2275 OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2276 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278 {"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2279 OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2280 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281
2282 {"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2283 OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2284 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2285
2286 {"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2287 OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2288 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2289
2290 {"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2291 OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2292 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2293
2294 {"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2295 OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2296 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2297
2298 {"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2299 0, 8, NULL},
2300
2301 {"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2302 0, 8, NULL},
2303
2304 {"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2305 0, 8, NULL},
2306
2307 {"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2308 0, 8, NULL},
2309
2310 {"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2311 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2312
2313 {"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2314 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2315
2316 {"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2317 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2318
2319 {"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2320 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2321
2322 {"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2323 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2324
2325 {"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2326 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2327
2328 {"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2329 F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2330
2331 {"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2332 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2333
2334 {"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2335 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2336
2337 {"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2338 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2339
2340 {"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2341 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2342
2343 {"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2344 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2345
2346 {"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2347 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2348
2349 {"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2350 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2351
2352 {"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2353 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2354
2355 {"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2356 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2357
2358 {"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2359 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2360
2361 {"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2362 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2363
2364 {"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2365 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2366
2367 {"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2368 F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2369
2370 {"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2371 D_BDW_PLUS, 0, 8, NULL},
2372
2373 {"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2374 NULL},
2375
2376 {"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2377 D_BDW_PLUS, 0, 8, NULL},
2378
2379 {"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2380 D_BDW_PLUS, 0, 8, NULL},
2381
2382 {"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2383 8, NULL},
2384
2385 {"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2386 R_RCS, D_BDW_PLUS, 0, 8, NULL},
2387
2388 {"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2389 8, NULL},
2390
2391 {"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2392 NULL},
2393
2394 {"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2395 NULL},
2396
2397 {"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2398 NULL},
2399
2400 {"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2401 D_BDW_PLUS, 0, 8, NULL},
2402
2403 {"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2404 R_RCS, D_ALL, 0, 8, NULL},
2405
2406 {"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2407 D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2408
2409 {"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2410 R_RCS, D_ALL, 0, 1, NULL},
2411
2412 {"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2413
2414 {"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2415 R_RCS, D_ALL, 0, 8, NULL},
2416
2417 {"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2418 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2419
2420 {"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2421
2422 {"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2423
2424 {"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2425
2426 {"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2427 D_BDW_PLUS, 0, 8, NULL},
2428
2429 {"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2430 D_BDW_PLUS, 0, 8, NULL},
2431
2432 {"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2433 D_ALL, 0, 8, NULL},
2434
2435 {"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2436 D_BDW_PLUS, 0, 8, NULL},
2437
2438 {"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2439 D_BDW_PLUS, 0, 8, NULL},
2440
2441 {"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2442
2443 {"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2444
2445 {"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2446
2447 {"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2448 D_ALL, 0, 8, NULL},
2449
2450 {"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2451
2452 {"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2453
2454 {"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2455 R_RCS, D_ALL, 0, 8, NULL},
2456
2457 {"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2458 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2459
2460 {"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2461 0, 8, NULL},
2462
2463 {"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2464 D_ALL, ADDR_FIX_1(2), 8, NULL},
2465
2466 {"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2467 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2468
2469 {"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2470 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2471
2472 {"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2473 D_ALL, 0, 8, NULL},
2474
2475 {"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2476 D_ALL, 0, 8, NULL},
2477
2478 {"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2479 D_ALL, 0, 8, NULL},
2480
2481 {"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2482 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2483
2484 {"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2485 D_BDW_PLUS, 0, 8, NULL},
2486
2487 {"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2488 D_ALL, ADDR_FIX_1(2), 8, NULL},
2489
2490 {"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2491 R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2492
2493 {"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2494 R_RCS, D_ALL, 0, 8, NULL},
2495
2496 {"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2497 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2498
2499 {"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2500 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2501
2502 {"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2503 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2504
2505 {"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2506 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2507
2508 {"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2509 F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2510
2511 {"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2512 R_RCS, D_ALL, 0, 8, NULL},
2513
2514 {"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2515 D_ALL, 0, 9, NULL},
2516
2517 {"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2518 ADDR_FIX_2(2, 4), 8, NULL},
2519
2520 {"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2521 OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2522 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2523
2524 {"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2525 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2526
2527 {"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2528 OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2529 F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2530
2531 {"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2532 D_BDW_PLUS, 0, 8, NULL},
2533
2534 {"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2535 ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2536
2537 {"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2538
2539 {"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2540 1, NULL},
2541
2542 {"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2543 ADDR_FIX_1(1), 8, NULL},
2544
2545 {"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2546
2547 {"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2548 ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2549
2550 {"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2551 ADDR_FIX_1(1), 8, NULL},
2552
2553 {"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2554 F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2555
2556 {"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2557
2558 {"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2559
2560 {"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2561 0, 8, NULL},
2562
2563 {"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2564 D_SKL_PLUS, 0, 8, NULL},
2565
2566 {"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2567 F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2568
2569 {"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2570 0, 16, NULL},
2571
2572 {"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2573 0, 16, NULL},
2574
2575 {"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2576 0, 16, NULL},
2577
2578 {"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2579
2580 {"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2581 0, 16, NULL},
2582
2583 {"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2584 0, 16, NULL},
2585
2586 {"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2587 0, 16, NULL},
2588
2589 {"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2590 0, 8, NULL},
2591
2592 {"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2593 NULL},
2594
2595 {"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2596 F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2597
2598 {"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2599 R_VCS, D_ALL, 0, 12, NULL},
2600
2601 {"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2602 R_VCS, D_ALL, 0, 12, NULL},
2603
2604 {"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2605 R_VCS, D_BDW_PLUS, 0, 12, NULL},
2606
2607 {"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2608 F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2609
2610 {"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2611 F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2612
2613 {"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2614
2615 {"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2616 R_VCS, D_ALL, 0, 12, NULL},
2617
2618 {"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2619 R_VCS, D_ALL, 0, 12, NULL},
2620
2621 {"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2622 R_VCS, D_ALL, 0, 12, NULL},
2623
2624 {"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2625 R_VCS, D_ALL, 0, 12, NULL},
2626
2627 {"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2628 R_VCS, D_ALL, 0, 12, NULL},
2629
2630 {"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2631 R_VCS, D_ALL, 0, 12, NULL},
2632
2633 {"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2634 R_VCS, D_ALL, 0, 6, NULL},
2635
2636 {"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2637 R_VCS, D_ALL, 0, 12, NULL},
2638
2639 {"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2640 R_VCS, D_ALL, 0, 12, NULL},
2641
2642 {"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2643 R_VCS, D_ALL, 0, 12, NULL},
2644
2645 {"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2646 R_VCS, D_ALL, 0, 12, NULL},
2647
2648 {"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2649 R_VCS, D_ALL, 0, 12, NULL},
2650
2651 {"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2652 R_VCS, D_ALL, 0, 12, NULL},
2653
2654 {"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2655 R_VCS, D_ALL, 0, 12, NULL},
2656 {"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2657 R_VCS, D_ALL, 0, 12, NULL},
2658
2659 {"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2660 R_VCS, D_ALL, 0, 12, NULL},
2661
2662 {"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2663 R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2664
2665 {"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2666 R_VCS, D_ALL, 0, 12, NULL},
2667
2668 {"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2669 R_VCS, D_ALL, 0, 12, NULL},
2670
2671 {"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2672 R_VCS, D_ALL, 0, 12, NULL},
2673
2674 {"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2675 R_VCS, D_ALL, 0, 12, NULL},
2676
2677 {"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2678 R_VCS, D_ALL, 0, 12, NULL},
2679
2680 {"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2681 R_VCS, D_ALL, 0, 12, NULL},
2682
2683 {"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2684 R_VCS, D_ALL, 0, 12, NULL},
2685
2686 {"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2687 R_VCS, D_ALL, 0, 12, NULL},
2688
2689 {"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2690 R_VCS, D_ALL, 0, 12, NULL},
2691
2692 {"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2693 R_VCS, D_ALL, 0, 12, NULL},
2694
2695 {"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2696 R_VCS, D_ALL, 0, 12, NULL},
2697
2698 {"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2699 0, 16, NULL},
2700
2701 {"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2702
2703 {"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2704
2705 {"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2706 R_VCS, D_ALL, 0, 12, NULL},
2707
2708 {"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2709 R_VCS, D_ALL, 0, 12, NULL},
2710
2711 {"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2712 R_VCS, D_ALL, 0, 12, NULL},
2713
2714 {"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2715
2716 {"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2717 0, 12, NULL},
2718
2719 {"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2720 0, 12, NULL},
2721 };
2722
add_cmd_entry(struct intel_gvt * gvt,struct cmd_entry * e)2723 static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2724 {
2725 hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2726 }
2727
2728 /* call the cmd handler, and advance ip */
cmd_parser_exec(struct parser_exec_state * s)2729 static int cmd_parser_exec(struct parser_exec_state *s)
2730 {
2731 struct intel_vgpu *vgpu = s->vgpu;
2732 const struct cmd_info *info;
2733 u32 cmd;
2734 int ret = 0;
2735
2736 cmd = cmd_val(s, 0);
2737
2738 /* fastpath for MI_NOOP */
2739 if (cmd == MI_NOOP)
2740 info = &cmd_info[mi_noop_index];
2741 else
2742 info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2743
2744 if (info == NULL) {
2745 gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2746 cmd, get_opcode(cmd, s->engine),
2747 repr_addr_type(s->buf_addr_type),
2748 s->engine->name, s->workload);
2749 return -EBADRQC;
2750 }
2751
2752 s->info = info;
2753
2754 trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2755 cmd_length(s), s->buf_type, s->buf_addr_type,
2756 s->workload, info->name);
2757
2758 if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2759 ret = gvt_check_valid_cmd_length(cmd_length(s),
2760 info->valid_len);
2761 if (ret)
2762 return ret;
2763 }
2764
2765 if (info->handler) {
2766 ret = info->handler(s);
2767 if (ret < 0) {
2768 gvt_vgpu_err("%s handler error\n", info->name);
2769 return ret;
2770 }
2771 }
2772
2773 if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2774 ret = cmd_advance_default(s);
2775 if (ret) {
2776 gvt_vgpu_err("%s IP advance error\n", info->name);
2777 return ret;
2778 }
2779 }
2780 return 0;
2781 }
2782
gma_out_of_range(unsigned long gma,unsigned long gma_head,unsigned int gma_tail)2783 static inline bool gma_out_of_range(unsigned long gma,
2784 unsigned long gma_head, unsigned int gma_tail)
2785 {
2786 if (gma_tail >= gma_head)
2787 return (gma < gma_head) || (gma > gma_tail);
2788 else
2789 return (gma > gma_tail) && (gma < gma_head);
2790 }
2791
2792 /* Keep the consistent return type, e.g EBADRQC for unknown
2793 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2794 * works as the input of VM healthy status.
2795 */
command_scan(struct parser_exec_state * s,unsigned long rb_head,unsigned long rb_tail,unsigned long rb_start,unsigned long rb_len)2796 static int command_scan(struct parser_exec_state *s,
2797 unsigned long rb_head, unsigned long rb_tail,
2798 unsigned long rb_start, unsigned long rb_len)
2799 {
2800
2801 unsigned long gma_head, gma_tail, gma_bottom;
2802 int ret = 0;
2803 struct intel_vgpu *vgpu = s->vgpu;
2804
2805 gma_head = rb_start + rb_head;
2806 gma_tail = rb_start + rb_tail;
2807 gma_bottom = rb_start + rb_len;
2808
2809 while (s->ip_gma != gma_tail) {
2810 if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2811 s->buf_type == RING_BUFFER_CTX) {
2812 if (!(s->ip_gma >= rb_start) ||
2813 !(s->ip_gma < gma_bottom)) {
2814 gvt_vgpu_err("ip_gma %lx out of ring scope."
2815 "(base:0x%lx, bottom: 0x%lx)\n",
2816 s->ip_gma, rb_start,
2817 gma_bottom);
2818 parser_exec_state_dump(s);
2819 return -EFAULT;
2820 }
2821 if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2822 gvt_vgpu_err("ip_gma %lx out of range."
2823 "base 0x%lx head 0x%lx tail 0x%lx\n",
2824 s->ip_gma, rb_start,
2825 rb_head, rb_tail);
2826 parser_exec_state_dump(s);
2827 break;
2828 }
2829 }
2830 ret = cmd_parser_exec(s);
2831 if (ret) {
2832 gvt_vgpu_err("cmd parser error\n");
2833 parser_exec_state_dump(s);
2834 break;
2835 }
2836 }
2837
2838 return ret;
2839 }
2840
scan_workload(struct intel_vgpu_workload * workload)2841 static int scan_workload(struct intel_vgpu_workload *workload)
2842 {
2843 unsigned long gma_head, gma_tail;
2844 struct parser_exec_state s;
2845 int ret = 0;
2846
2847 /* ring base is page aligned */
2848 if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2849 return -EINVAL;
2850
2851 gma_head = workload->rb_start + workload->rb_head;
2852 gma_tail = workload->rb_start + workload->rb_tail;
2853
2854 s.buf_type = RING_BUFFER_INSTRUCTION;
2855 s.buf_addr_type = GTT_BUFFER;
2856 s.vgpu = workload->vgpu;
2857 s.engine = workload->engine;
2858 s.ring_start = workload->rb_start;
2859 s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2860 s.ring_head = gma_head;
2861 s.ring_tail = gma_tail;
2862 s.rb_va = workload->shadow_ring_buffer_va;
2863 s.workload = workload;
2864 s.is_ctx_wa = false;
2865
2866 if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2867 return 0;
2868
2869 ret = ip_gma_set(&s, gma_head);
2870 if (ret)
2871 goto out;
2872
2873 ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2874 workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2875
2876 out:
2877 return ret;
2878 }
2879
scan_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)2880 static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2881 {
2882
2883 unsigned long gma_head, gma_tail, ring_size, ring_tail;
2884 struct parser_exec_state s;
2885 int ret = 0;
2886 struct intel_vgpu_workload *workload = container_of(wa_ctx,
2887 struct intel_vgpu_workload,
2888 wa_ctx);
2889
2890 /* ring base is page aligned */
2891 if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2892 I915_GTT_PAGE_SIZE)))
2893 return -EINVAL;
2894
2895 ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2896 ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2897 PAGE_SIZE);
2898 gma_head = wa_ctx->indirect_ctx.guest_gma;
2899 gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2900
2901 s.buf_type = RING_BUFFER_INSTRUCTION;
2902 s.buf_addr_type = GTT_BUFFER;
2903 s.vgpu = workload->vgpu;
2904 s.engine = workload->engine;
2905 s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2906 s.ring_size = ring_size;
2907 s.ring_head = gma_head;
2908 s.ring_tail = gma_tail;
2909 s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2910 s.workload = workload;
2911 s.is_ctx_wa = true;
2912
2913 ret = ip_gma_set(&s, gma_head);
2914 if (ret)
2915 goto out;
2916
2917 ret = command_scan(&s, 0, ring_tail,
2918 wa_ctx->indirect_ctx.guest_gma, ring_size);
2919 out:
2920 return ret;
2921 }
2922
shadow_workload_ring_buffer(struct intel_vgpu_workload * workload)2923 static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2924 {
2925 struct intel_vgpu *vgpu = workload->vgpu;
2926 struct intel_vgpu_submission *s = &vgpu->submission;
2927 unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2928 void *shadow_ring_buffer_va;
2929 int ret;
2930
2931 guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2932
2933 /* calculate workload ring buffer size */
2934 workload->rb_len = (workload->rb_tail + guest_rb_size -
2935 workload->rb_head) % guest_rb_size;
2936
2937 gma_head = workload->rb_start + workload->rb_head;
2938 gma_tail = workload->rb_start + workload->rb_tail;
2939 gma_top = workload->rb_start + guest_rb_size;
2940
2941 if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2942 void *p;
2943
2944 /* realloc the new ring buffer if needed */
2945 p = krealloc(s->ring_scan_buffer[workload->engine->id],
2946 workload->rb_len, GFP_KERNEL);
2947 if (!p) {
2948 gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2949 return -ENOMEM;
2950 }
2951 s->ring_scan_buffer[workload->engine->id] = p;
2952 s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2953 }
2954
2955 shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2956
2957 /* get shadow ring buffer va */
2958 workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2959
2960 /* head > tail --> copy head <-> top */
2961 if (gma_head > gma_tail) {
2962 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2963 gma_head, gma_top, shadow_ring_buffer_va);
2964 if (ret < 0) {
2965 gvt_vgpu_err("fail to copy guest ring buffer\n");
2966 return ret;
2967 }
2968 shadow_ring_buffer_va += ret;
2969 gma_head = workload->rb_start;
2970 }
2971
2972 /* copy head or start <-> tail */
2973 ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2974 shadow_ring_buffer_va);
2975 if (ret < 0) {
2976 gvt_vgpu_err("fail to copy guest ring buffer\n");
2977 return ret;
2978 }
2979 return 0;
2980 }
2981
intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload * workload)2982 int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2983 {
2984 int ret;
2985 struct intel_vgpu *vgpu = workload->vgpu;
2986
2987 ret = shadow_workload_ring_buffer(workload);
2988 if (ret) {
2989 gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2990 return ret;
2991 }
2992
2993 ret = scan_workload(workload);
2994 if (ret) {
2995 gvt_vgpu_err("scan workload error\n");
2996 return ret;
2997 }
2998 return 0;
2999 }
3000
shadow_indirect_ctx(struct intel_shadow_wa_ctx * wa_ctx)3001 static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3002 {
3003 int ctx_size = wa_ctx->indirect_ctx.size;
3004 unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
3005 struct intel_vgpu_workload *workload = container_of(wa_ctx,
3006 struct intel_vgpu_workload,
3007 wa_ctx);
3008 struct intel_vgpu *vgpu = workload->vgpu;
3009 struct drm_i915_gem_object *obj;
3010 int ret = 0;
3011 void *map;
3012
3013 obj = i915_gem_object_create_shmem(workload->engine->i915,
3014 roundup(ctx_size + CACHELINE_BYTES,
3015 PAGE_SIZE));
3016 if (IS_ERR(obj))
3017 return PTR_ERR(obj);
3018
3019 /* get the va of the shadow batch buffer */
3020 map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3021 if (IS_ERR(map)) {
3022 gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3023 ret = PTR_ERR(map);
3024 goto put_obj;
3025 }
3026
3027 i915_gem_object_lock(obj, NULL);
3028 ret = i915_gem_object_set_to_cpu_domain(obj, false);
3029 i915_gem_object_unlock(obj);
3030 if (ret) {
3031 gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3032 goto unmap_src;
3033 }
3034
3035 ret = copy_gma_to_hva(workload->vgpu,
3036 workload->vgpu->gtt.ggtt_mm,
3037 guest_gma, guest_gma + ctx_size,
3038 map);
3039 if (ret < 0) {
3040 gvt_vgpu_err("fail to copy guest indirect ctx\n");
3041 goto unmap_src;
3042 }
3043
3044 wa_ctx->indirect_ctx.obj = obj;
3045 wa_ctx->indirect_ctx.shadow_va = map;
3046 return 0;
3047
3048 unmap_src:
3049 i915_gem_object_unpin_map(obj);
3050 put_obj:
3051 i915_gem_object_put(obj);
3052 return ret;
3053 }
3054
combine_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3055 static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3056 {
3057 u32 per_ctx_start[CACHELINE_DWORDS] = {};
3058 unsigned char *bb_start_sva;
3059
3060 if (!wa_ctx->per_ctx.valid)
3061 return 0;
3062
3063 per_ctx_start[0] = 0x18800001;
3064 per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3065
3066 bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3067 wa_ctx->indirect_ctx.size;
3068
3069 memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3070
3071 return 0;
3072 }
3073
intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx * wa_ctx)3074 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3075 {
3076 int ret;
3077 struct intel_vgpu_workload *workload = container_of(wa_ctx,
3078 struct intel_vgpu_workload,
3079 wa_ctx);
3080 struct intel_vgpu *vgpu = workload->vgpu;
3081
3082 if (wa_ctx->indirect_ctx.size == 0)
3083 return 0;
3084
3085 ret = shadow_indirect_ctx(wa_ctx);
3086 if (ret) {
3087 gvt_vgpu_err("fail to shadow indirect ctx\n");
3088 return ret;
3089 }
3090
3091 combine_wa_ctx(wa_ctx);
3092
3093 ret = scan_wa_ctx(wa_ctx);
3094 if (ret) {
3095 gvt_vgpu_err("scan wa ctx error\n");
3096 return ret;
3097 }
3098
3099 return 0;
3100 }
3101
3102 /* generate dummy contexts by sending empty requests to HW, and let
3103 * the HW to fill Engine Contexts. This dummy contexts are used for
3104 * initialization purpose (update reg whitelist), so referred to as
3105 * init context here
3106 */
intel_gvt_update_reg_whitelist(struct intel_vgpu * vgpu)3107 void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3108 {
3109 const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3110 struct intel_gvt *gvt = vgpu->gvt;
3111 struct intel_engine_cs *engine;
3112 enum intel_engine_id id;
3113
3114 if (gvt->is_reg_whitelist_updated)
3115 return;
3116
3117 /* scan init ctx to update cmd accessible list */
3118 for_each_engine(engine, gvt->gt, id) {
3119 struct parser_exec_state s;
3120 void *vaddr;
3121 int ret;
3122
3123 if (!engine->default_state)
3124 continue;
3125
3126 vaddr = shmem_pin_map(engine->default_state);
3127 if (!vaddr) {
3128 gvt_err("failed to map %s->default state\n",
3129 engine->name);
3130 return;
3131 }
3132
3133 s.buf_type = RING_BUFFER_CTX;
3134 s.buf_addr_type = GTT_BUFFER;
3135 s.vgpu = vgpu;
3136 s.engine = engine;
3137 s.ring_start = 0;
3138 s.ring_size = engine->context_size - start;
3139 s.ring_head = 0;
3140 s.ring_tail = s.ring_size;
3141 s.rb_va = vaddr + start;
3142 s.workload = NULL;
3143 s.is_ctx_wa = false;
3144 s.is_init_ctx = true;
3145
3146 /* skipping the first RING_CTX_SIZE(0x50) dwords */
3147 ret = ip_gma_set(&s, RING_CTX_SIZE);
3148 if (ret == 0) {
3149 ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3150 if (ret)
3151 gvt_err("Scan init ctx error\n");
3152 }
3153
3154 shmem_unpin_map(engine->default_state, vaddr);
3155 if (ret)
3156 return;
3157 }
3158
3159 gvt->is_reg_whitelist_updated = true;
3160 }
3161
intel_gvt_scan_engine_context(struct intel_vgpu_workload * workload)3162 int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
3163 {
3164 struct intel_vgpu *vgpu = workload->vgpu;
3165 unsigned long gma_head, gma_tail, gma_start, ctx_size;
3166 struct parser_exec_state s;
3167 int ring_id = workload->engine->id;
3168 struct intel_context *ce = vgpu->submission.shadow[ring_id];
3169 int ret;
3170
3171 GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
3172
3173 ctx_size = workload->engine->context_size - PAGE_SIZE;
3174
3175 /* Only ring contxt is loaded to HW for inhibit context, no need to
3176 * scan engine context
3177 */
3178 if (is_inhibit_context(ce))
3179 return 0;
3180
3181 gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
3182 gma_head = 0;
3183 gma_tail = ctx_size;
3184
3185 s.buf_type = RING_BUFFER_CTX;
3186 s.buf_addr_type = GTT_BUFFER;
3187 s.vgpu = workload->vgpu;
3188 s.engine = workload->engine;
3189 s.ring_start = gma_start;
3190 s.ring_size = ctx_size;
3191 s.ring_head = gma_start + gma_head;
3192 s.ring_tail = gma_start + gma_tail;
3193 s.rb_va = ce->lrc_reg_state;
3194 s.workload = workload;
3195 s.is_ctx_wa = false;
3196 s.is_init_ctx = false;
3197
3198 /* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
3199 * context
3200 */
3201 ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
3202 if (ret)
3203 goto out;
3204
3205 ret = command_scan(&s, gma_head, gma_tail,
3206 gma_start, ctx_size);
3207 out:
3208 if (ret)
3209 gvt_vgpu_err("scan shadow ctx error\n");
3210
3211 return ret;
3212 }
3213
init_cmd_table(struct intel_gvt * gvt)3214 static int init_cmd_table(struct intel_gvt *gvt)
3215 {
3216 unsigned int gen_type = intel_gvt_get_device_type(gvt);
3217 int i;
3218
3219 for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3220 struct cmd_entry *e;
3221
3222 if (!(cmd_info[i].devices & gen_type))
3223 continue;
3224
3225 e = kzalloc(sizeof(*e), GFP_KERNEL);
3226 if (!e)
3227 return -ENOMEM;
3228
3229 e->info = &cmd_info[i];
3230 if (cmd_info[i].opcode == OP_MI_NOOP)
3231 mi_noop_index = i;
3232
3233 INIT_HLIST_NODE(&e->hlist);
3234 add_cmd_entry(gvt, e);
3235 gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3236 e->info->name, e->info->opcode, e->info->flag,
3237 e->info->devices, e->info->rings);
3238 }
3239
3240 return 0;
3241 }
3242
clean_cmd_table(struct intel_gvt * gvt)3243 static void clean_cmd_table(struct intel_gvt *gvt)
3244 {
3245 struct hlist_node *tmp;
3246 struct cmd_entry *e;
3247 int i;
3248
3249 hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3250 kfree(e);
3251
3252 hash_init(gvt->cmd_table);
3253 }
3254
intel_gvt_clean_cmd_parser(struct intel_gvt * gvt)3255 void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3256 {
3257 clean_cmd_table(gvt);
3258 }
3259
intel_gvt_init_cmd_parser(struct intel_gvt * gvt)3260 int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3261 {
3262 int ret;
3263
3264 ret = init_cmd_table(gvt);
3265 if (ret) {
3266 intel_gvt_clean_cmd_parser(gvt);
3267 return ret;
3268 }
3269 return 0;
3270 }
3271