1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 /**
25 * DOC: Frame Buffer Compression (FBC)
26 *
27 * FBC tries to save memory bandwidth (and so power consumption) by
28 * compressing the amount of memory used by the display. It is total
29 * transparent to user space and completely handled in the kernel.
30 *
31 * The benefits of FBC are mostly visible with solid backgrounds and
32 * variation-less patterns. It comes from keeping the memory footprint small
33 * and having fewer memory pages opened and accessed for refreshing the display.
34 *
35 * i915 is responsible to reserve stolen memory for FBC and configure its
36 * offset on proper registers. The hardware takes care of all
37 * compress/decompress. However there are many known cases where we have to
38 * forcibly disable it to allow proper screen updates.
39 */
40
41 #include <linux/debugfs.h>
42 #include <linux/string_helpers.h>
43
44 #include <drm/drm_blend.h>
45 #include <drm/drm_fourcc.h>
46
47 #include "gem/i915_gem_stolen.h"
48 #include "gt/intel_gt_types.h"
49 #include "i915_drv.h"
50 #include "i915_reg.h"
51 #include "i915_utils.h"
52 #include "i915_vgpu.h"
53 #include "i915_vma.h"
54 #include "i9xx_plane_regs.h"
55 #include "intel_cdclk.h"
56 #include "intel_de.h"
57 #include "intel_display_device.h"
58 #include "intel_display_trace.h"
59 #include "intel_display_types.h"
60 #include "intel_display_wa.h"
61 #include "intel_fbc.h"
62 #include "intel_fbc_regs.h"
63 #include "intel_frontbuffer.h"
64
65 #define for_each_fbc_id(__display, __fbc_id) \
66 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
67 for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id))
68
69 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \
70 for_each_fbc_id((__display), (__fbc_id)) \
71 for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
72
73 struct intel_fbc_funcs {
74 void (*activate)(struct intel_fbc *fbc);
75 void (*deactivate)(struct intel_fbc *fbc);
76 bool (*is_active)(struct intel_fbc *fbc);
77 bool (*is_compressing)(struct intel_fbc *fbc);
78 void (*nuke)(struct intel_fbc *fbc);
79 void (*program_cfb)(struct intel_fbc *fbc);
80 void (*set_false_color)(struct intel_fbc *fbc, bool enable);
81 };
82
83 struct intel_fbc_state {
84 struct intel_plane *plane;
85 unsigned int cfb_stride;
86 unsigned int cfb_size;
87 unsigned int fence_y_offset;
88 u16 override_cfb_stride;
89 u16 interval;
90 s8 fence_id;
91 struct drm_rect dirty_rect;
92 };
93
94 struct intel_fbc {
95 struct intel_display *display;
96 const struct intel_fbc_funcs *funcs;
97
98 /*
99 * This is always the inner lock when overlapping with
100 * struct_mutex and it's the outer lock when overlapping
101 * with stolen_lock.
102 */
103 struct mutex lock;
104 unsigned int busy_bits;
105
106 struct i915_stolen_fb compressed_fb, compressed_llb;
107
108 enum intel_fbc_id id;
109
110 u8 limit;
111
112 bool false_color;
113
114 bool active;
115 bool activated;
116 bool flip_pending;
117
118 bool underrun_detected;
119 struct work_struct underrun_work;
120
121 /*
122 * This structure contains everything that's relevant to program the
123 * hardware registers. When we want to figure out if we need to disable
124 * and re-enable FBC for a new configuration we just check if there's
125 * something different in the struct. The genx_fbc_activate functions
126 * are supposed to read from it in order to program the registers.
127 */
128 struct intel_fbc_state state;
129 const char *no_fbc_reason;
130 };
131
132 /* plane stride in pixels */
intel_fbc_plane_stride(const struct intel_plane_state * plane_state)133 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state)
134 {
135 const struct drm_framebuffer *fb = plane_state->hw.fb;
136 unsigned int stride;
137
138 stride = plane_state->view.color_plane[0].mapping_stride;
139 if (!drm_rotation_90_or_270(plane_state->hw.rotation))
140 stride /= fb->format->cpp[0];
141
142 return stride;
143 }
144
intel_fbc_cfb_cpp(void)145 static unsigned int intel_fbc_cfb_cpp(void)
146 {
147 return 4; /* FBC always 4 bytes per pixel */
148 }
149
150 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
intel_fbc_plane_cfb_stride(const struct intel_plane_state * plane_state)151 static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state)
152 {
153 unsigned int cpp = intel_fbc_cfb_cpp();
154
155 return intel_fbc_plane_stride(plane_state) * cpp;
156 }
157
158 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */
skl_fbc_min_cfb_stride(struct intel_display * display,unsigned int cpp,unsigned int width)159 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display,
160 unsigned int cpp, unsigned int width)
161 {
162 unsigned int limit = 4; /* 1:4 compression limit is the worst case */
163 unsigned int height = 4; /* FBC segment is 4 lines */
164 unsigned int stride;
165
166 /* minimum segment stride we can use */
167 stride = width * cpp * height / limit;
168
169 /*
170 * Wa_16011863758: icl+
171 * Avoid some hardware segment address miscalculation.
172 */
173 if (DISPLAY_VER(display) >= 11)
174 stride += 64;
175
176 /*
177 * At least some of the platforms require each 4 line segment to
178 * be 512 byte aligned. Just do it always for simplicity.
179 */
180 stride = ALIGN(stride, 512);
181
182 /* convert back to single line equivalent with 1:1 compression limit */
183 return stride * limit / height;
184 }
185
186 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */
_intel_fbc_cfb_stride(struct intel_display * display,unsigned int cpp,unsigned int width,unsigned int stride)187 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display,
188 unsigned int cpp, unsigned int width,
189 unsigned int stride)
190 {
191 /*
192 * At least some of the platforms require each 4 line segment to
193 * be 512 byte aligned. Aligning each line to 512 bytes guarantees
194 * that regardless of the compression limit we choose later.
195 */
196 if (DISPLAY_VER(display) >= 9)
197 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width));
198 else
199 return stride;
200 }
201
intel_fbc_cfb_stride(const struct intel_plane_state * plane_state)202 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state)
203 {
204 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
205 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);
206 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
207 unsigned int cpp = intel_fbc_cfb_cpp();
208
209 return _intel_fbc_cfb_stride(display, cpp, width, stride);
210 }
211
212 /*
213 * Maximum height the hardware will compress, on HSW+
214 * additional lines (up to the actual plane height) will
215 * remain uncompressed.
216 */
intel_fbc_max_cfb_height(struct intel_display * display)217 static unsigned int intel_fbc_max_cfb_height(struct intel_display *display)
218 {
219 if (DISPLAY_VER(display) >= 8)
220 return 2560;
221 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
222 return 2048;
223 else
224 return 1536;
225 }
226
_intel_fbc_cfb_size(struct intel_display * display,unsigned int height,unsigned int stride)227 static unsigned int _intel_fbc_cfb_size(struct intel_display *display,
228 unsigned int height, unsigned int stride)
229 {
230 return min(height, intel_fbc_max_cfb_height(display)) * stride;
231 }
232
intel_fbc_cfb_size(const struct intel_plane_state * plane_state)233 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state)
234 {
235 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
236 unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16;
237
238 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state));
239 }
240
intel_fbc_override_cfb_stride(const struct intel_plane_state * plane_state)241 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state)
242 {
243 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
244 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state);
245 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);
246 const struct drm_framebuffer *fb = plane_state->hw.fb;
247
248 /*
249 * Override stride in 64 byte units per 4 line segment.
250 *
251 * Gen9 hw miscalculates cfb stride for linear as
252 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so
253 * we always need to use the override there.
254 */
255 if (stride != stride_aligned ||
256 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR))
257 return stride_aligned * 4 / 64;
258
259 return 0;
260 }
261
intel_fbc_has_fences(struct intel_display * display)262 static bool intel_fbc_has_fences(struct intel_display *display)
263 {
264 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm);
265
266 return intel_gt_support_legacy_fencing(to_gt(i915));
267 }
268
i8xx_fbc_ctl(struct intel_fbc * fbc)269 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc)
270 {
271 struct intel_display *display = fbc->display;
272 const struct intel_fbc_state *fbc_state = &fbc->state;
273 unsigned int cfb_stride;
274 u32 fbc_ctl;
275
276 cfb_stride = fbc_state->cfb_stride / fbc->limit;
277
278 /* FBC_CTL wants 32B or 64B units */
279 if (DISPLAY_VER(display) == 2)
280 cfb_stride = (cfb_stride / 32) - 1;
281 else
282 cfb_stride = (cfb_stride / 64) - 1;
283
284 fbc_ctl = FBC_CTL_PERIODIC |
285 FBC_CTL_INTERVAL(fbc_state->interval) |
286 FBC_CTL_STRIDE(cfb_stride);
287
288 if (display->platform.i945gm)
289 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
290
291 if (fbc_state->fence_id >= 0)
292 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id);
293
294 return fbc_ctl;
295 }
296
i965_fbc_ctl2(struct intel_fbc * fbc)297 static u32 i965_fbc_ctl2(struct intel_fbc *fbc)
298 {
299 const struct intel_fbc_state *fbc_state = &fbc->state;
300 u32 fbc_ctl2;
301
302 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM |
303 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane);
304
305 if (fbc_state->fence_id >= 0)
306 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN;
307
308 return fbc_ctl2;
309 }
310
i8xx_fbc_deactivate(struct intel_fbc * fbc)311 static void i8xx_fbc_deactivate(struct intel_fbc *fbc)
312 {
313 struct intel_display *display = fbc->display;
314 u32 fbc_ctl;
315
316 /* Disable compression */
317 fbc_ctl = intel_de_read(display, FBC_CONTROL);
318 if ((fbc_ctl & FBC_CTL_EN) == 0)
319 return;
320
321 fbc_ctl &= ~FBC_CTL_EN;
322 intel_de_write(display, FBC_CONTROL, fbc_ctl);
323
324 /* Wait for compressing bit to clear */
325 if (intel_de_wait_for_clear(display, FBC_STATUS,
326 FBC_STAT_COMPRESSING, 10)) {
327 drm_dbg_kms(display->drm, "FBC idle timed out\n");
328 return;
329 }
330 }
331
i8xx_fbc_activate(struct intel_fbc * fbc)332 static void i8xx_fbc_activate(struct intel_fbc *fbc)
333 {
334 struct intel_display *display = fbc->display;
335 const struct intel_fbc_state *fbc_state = &fbc->state;
336 int i;
337
338 /* Clear old tags */
339 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
340 intel_de_write(display, FBC_TAG(i), 0);
341
342 if (DISPLAY_VER(display) == 4) {
343 intel_de_write(display, FBC_CONTROL2,
344 i965_fbc_ctl2(fbc));
345 intel_de_write(display, FBC_FENCE_OFF,
346 fbc_state->fence_y_offset);
347 }
348
349 intel_de_write(display, FBC_CONTROL,
350 FBC_CTL_EN | i8xx_fbc_ctl(fbc));
351 }
352
i8xx_fbc_is_active(struct intel_fbc * fbc)353 static bool i8xx_fbc_is_active(struct intel_fbc *fbc)
354 {
355 return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN;
356 }
357
i8xx_fbc_is_compressing(struct intel_fbc * fbc)358 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc)
359 {
360 return intel_de_read(fbc->display, FBC_STATUS) &
361 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED);
362 }
363
i8xx_fbc_nuke(struct intel_fbc * fbc)364 static void i8xx_fbc_nuke(struct intel_fbc *fbc)
365 {
366 struct intel_display *display = fbc->display;
367 struct intel_fbc_state *fbc_state = &fbc->state;
368 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
369
370 intel_de_write_fw(display, DSPADDR(display, i9xx_plane),
371 intel_de_read_fw(display, DSPADDR(display, i9xx_plane)));
372 }
373
i8xx_fbc_program_cfb(struct intel_fbc * fbc)374 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
375 {
376 struct intel_display *display = fbc->display;
377 struct drm_i915_private *i915 = to_i915(display->drm);
378
379 drm_WARN_ON(display->drm,
380 range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
381 i915_gem_stolen_node_offset(&fbc->compressed_fb),
382 U32_MAX));
383 drm_WARN_ON(display->drm,
384 range_overflows_end_t(u64, i915_gem_stolen_area_address(i915),
385 i915_gem_stolen_node_offset(&fbc->compressed_llb),
386 U32_MAX));
387 intel_de_write(display, FBC_CFB_BASE,
388 i915_gem_stolen_node_address(i915, &fbc->compressed_fb));
389 intel_de_write(display, FBC_LL_BASE,
390 i915_gem_stolen_node_address(i915, &fbc->compressed_llb));
391 }
392
393 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
394 .activate = i8xx_fbc_activate,
395 .deactivate = i8xx_fbc_deactivate,
396 .is_active = i8xx_fbc_is_active,
397 .is_compressing = i8xx_fbc_is_compressing,
398 .nuke = i8xx_fbc_nuke,
399 .program_cfb = i8xx_fbc_program_cfb,
400 };
401
i965_fbc_nuke(struct intel_fbc * fbc)402 static void i965_fbc_nuke(struct intel_fbc *fbc)
403 {
404 struct intel_display *display = fbc->display;
405 struct intel_fbc_state *fbc_state = &fbc->state;
406 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane;
407
408 intel_de_write_fw(display, DSPSURF(display, i9xx_plane),
409 intel_de_read_fw(display, DSPSURF(display, i9xx_plane)));
410 }
411
412 static const struct intel_fbc_funcs i965_fbc_funcs = {
413 .activate = i8xx_fbc_activate,
414 .deactivate = i8xx_fbc_deactivate,
415 .is_active = i8xx_fbc_is_active,
416 .is_compressing = i8xx_fbc_is_compressing,
417 .nuke = i965_fbc_nuke,
418 .program_cfb = i8xx_fbc_program_cfb,
419 };
420
g4x_dpfc_ctl_limit(struct intel_fbc * fbc)421 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc)
422 {
423 switch (fbc->limit) {
424 default:
425 MISSING_CASE(fbc->limit);
426 fallthrough;
427 case 1:
428 return DPFC_CTL_LIMIT_1X;
429 case 2:
430 return DPFC_CTL_LIMIT_2X;
431 case 4:
432 return DPFC_CTL_LIMIT_4X;
433 }
434 }
435
g4x_dpfc_ctl(struct intel_fbc * fbc)436 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc)
437 {
438 struct intel_display *display = fbc->display;
439 const struct intel_fbc_state *fbc_state = &fbc->state;
440 u32 dpfc_ctl;
441
442 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) |
443 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane);
444
445 if (display->platform.g4x)
446 dpfc_ctl |= DPFC_CTL_SR_EN;
447
448 if (fbc_state->fence_id >= 0) {
449 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X;
450
451 if (DISPLAY_VER(display) < 6)
452 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id);
453 }
454
455 return dpfc_ctl;
456 }
457
g4x_fbc_activate(struct intel_fbc * fbc)458 static void g4x_fbc_activate(struct intel_fbc *fbc)
459 {
460 struct intel_display *display = fbc->display;
461 const struct intel_fbc_state *fbc_state = &fbc->state;
462
463 intel_de_write(display, DPFC_FENCE_YOFF,
464 fbc_state->fence_y_offset);
465
466 intel_de_write(display, DPFC_CONTROL,
467 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
468 }
469
g4x_fbc_deactivate(struct intel_fbc * fbc)470 static void g4x_fbc_deactivate(struct intel_fbc *fbc)
471 {
472 struct intel_display *display = fbc->display;
473 u32 dpfc_ctl;
474
475 /* Disable compression */
476 dpfc_ctl = intel_de_read(display, DPFC_CONTROL);
477 if (dpfc_ctl & DPFC_CTL_EN) {
478 dpfc_ctl &= ~DPFC_CTL_EN;
479 intel_de_write(display, DPFC_CONTROL, dpfc_ctl);
480 }
481 }
482
g4x_fbc_is_active(struct intel_fbc * fbc)483 static bool g4x_fbc_is_active(struct intel_fbc *fbc)
484 {
485 return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN;
486 }
487
g4x_fbc_is_compressing(struct intel_fbc * fbc)488 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc)
489 {
490 return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK;
491 }
492
g4x_fbc_program_cfb(struct intel_fbc * fbc)493 static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
494 {
495 struct intel_display *display = fbc->display;
496
497 intel_de_write(display, DPFC_CB_BASE,
498 i915_gem_stolen_node_offset(&fbc->compressed_fb));
499 }
500
501 static const struct intel_fbc_funcs g4x_fbc_funcs = {
502 .activate = g4x_fbc_activate,
503 .deactivate = g4x_fbc_deactivate,
504 .is_active = g4x_fbc_is_active,
505 .is_compressing = g4x_fbc_is_compressing,
506 .nuke = i965_fbc_nuke,
507 .program_cfb = g4x_fbc_program_cfb,
508 };
509
ilk_fbc_activate(struct intel_fbc * fbc)510 static void ilk_fbc_activate(struct intel_fbc *fbc)
511 {
512 struct intel_display *display = fbc->display;
513 struct intel_fbc_state *fbc_state = &fbc->state;
514
515 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id),
516 fbc_state->fence_y_offset);
517
518 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
519 DPFC_CTL_EN | g4x_dpfc_ctl(fbc));
520 }
521
ilk_fbc_deactivate(struct intel_fbc * fbc)522 static void ilk_fbc_deactivate(struct intel_fbc *fbc)
523 {
524 struct intel_display *display = fbc->display;
525 u32 dpfc_ctl;
526
527 if (HAS_FBC_DIRTY_RECT(display))
528 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0);
529
530 /* Disable compression */
531 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id));
532 if (dpfc_ctl & DPFC_CTL_EN) {
533 dpfc_ctl &= ~DPFC_CTL_EN;
534 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
535 }
536 }
537
ilk_fbc_is_active(struct intel_fbc * fbc)538 static bool ilk_fbc_is_active(struct intel_fbc *fbc)
539 {
540 return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN;
541 }
542
ilk_fbc_is_compressing(struct intel_fbc * fbc)543 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
544 {
545 return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
546 }
547
ilk_fbc_program_cfb(struct intel_fbc * fbc)548 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
549 {
550 struct intel_display *display = fbc->display;
551
552 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
553 i915_gem_stolen_node_offset(&fbc->compressed_fb));
554 }
555
556 static const struct intel_fbc_funcs ilk_fbc_funcs = {
557 .activate = ilk_fbc_activate,
558 .deactivate = ilk_fbc_deactivate,
559 .is_active = ilk_fbc_is_active,
560 .is_compressing = ilk_fbc_is_compressing,
561 .nuke = i965_fbc_nuke,
562 .program_cfb = ilk_fbc_program_cfb,
563 };
564
snb_fbc_program_fence(struct intel_fbc * fbc)565 static void snb_fbc_program_fence(struct intel_fbc *fbc)
566 {
567 struct intel_display *display = fbc->display;
568 const struct intel_fbc_state *fbc_state = &fbc->state;
569 u32 ctl = 0;
570
571 if (fbc_state->fence_id >= 0)
572 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id);
573
574 intel_de_write(display, SNB_DPFC_CTL_SA, ctl);
575 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset);
576 }
577
snb_fbc_activate(struct intel_fbc * fbc)578 static void snb_fbc_activate(struct intel_fbc *fbc)
579 {
580 snb_fbc_program_fence(fbc);
581
582 ilk_fbc_activate(fbc);
583 }
584
snb_fbc_nuke(struct intel_fbc * fbc)585 static void snb_fbc_nuke(struct intel_fbc *fbc)
586 {
587 struct intel_display *display = fbc->display;
588
589 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE);
590 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id));
591 }
592
593 static const struct intel_fbc_funcs snb_fbc_funcs = {
594 .activate = snb_fbc_activate,
595 .deactivate = ilk_fbc_deactivate,
596 .is_active = ilk_fbc_is_active,
597 .is_compressing = ilk_fbc_is_compressing,
598 .nuke = snb_fbc_nuke,
599 .program_cfb = ilk_fbc_program_cfb,
600 };
601
glk_fbc_program_cfb_stride(struct intel_fbc * fbc)602 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc)
603 {
604 struct intel_display *display = fbc->display;
605 const struct intel_fbc_state *fbc_state = &fbc->state;
606 u32 val = 0;
607
608 if (fbc_state->override_cfb_stride)
609 val |= FBC_STRIDE_OVERRIDE |
610 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
611
612 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val);
613 }
614
skl_fbc_program_cfb_stride(struct intel_fbc * fbc)615 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
616 {
617 struct intel_display *display = fbc->display;
618 const struct intel_fbc_state *fbc_state = &fbc->state;
619 u32 val = 0;
620
621 /* Display WA #0529: skl, kbl, bxt. */
622 if (fbc_state->override_cfb_stride)
623 val |= CHICKEN_FBC_STRIDE_OVERRIDE |
624 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit);
625
626 intel_de_rmw(display, CHICKEN_MISC_4,
627 CHICKEN_FBC_STRIDE_OVERRIDE |
628 CHICKEN_FBC_STRIDE_MASK, val);
629 }
630
ivb_dpfc_ctl(struct intel_fbc * fbc)631 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
632 {
633 struct intel_display *display = fbc->display;
634 const struct intel_fbc_state *fbc_state = &fbc->state;
635 u32 dpfc_ctl;
636
637 dpfc_ctl = g4x_dpfc_ctl_limit(fbc);
638
639 if (display->platform.ivybridge)
640 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane);
641
642 if (DISPLAY_VER(display) >= 20)
643 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id);
644
645 if (fbc_state->fence_id >= 0)
646 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB;
647
648 if (fbc->false_color)
649 dpfc_ctl |= DPFC_CTL_FALSE_COLOR;
650
651 return dpfc_ctl;
652 }
653
ivb_fbc_activate(struct intel_fbc * fbc)654 static void ivb_fbc_activate(struct intel_fbc *fbc)
655 {
656 struct intel_display *display = fbc->display;
657 u32 dpfc_ctl;
658
659 if (DISPLAY_VER(display) >= 10)
660 glk_fbc_program_cfb_stride(fbc);
661 else if (DISPLAY_VER(display) == 9)
662 skl_fbc_program_cfb_stride(fbc);
663
664 if (intel_fbc_has_fences(display))
665 snb_fbc_program_fence(fbc);
666
667 /* wa_14019417088 Alternative WA*/
668 dpfc_ctl = ivb_dpfc_ctl(fbc);
669 if (DISPLAY_VER(display) >= 20)
670 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl);
671
672 if (HAS_FBC_DIRTY_RECT(display))
673 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id),
674 FBC_DIRTY_RECT_EN);
675
676 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id),
677 DPFC_CTL_EN | dpfc_ctl);
678 }
679
ivb_fbc_is_compressing(struct intel_fbc * fbc)680 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc)
681 {
682 return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB;
683 }
684
ivb_fbc_set_false_color(struct intel_fbc * fbc,bool enable)685 static void ivb_fbc_set_false_color(struct intel_fbc *fbc,
686 bool enable)
687 {
688 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id),
689 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0);
690 }
691
692 static const struct intel_fbc_funcs ivb_fbc_funcs = {
693 .activate = ivb_fbc_activate,
694 .deactivate = ilk_fbc_deactivate,
695 .is_active = ilk_fbc_is_active,
696 .is_compressing = ivb_fbc_is_compressing,
697 .nuke = snb_fbc_nuke,
698 .program_cfb = ilk_fbc_program_cfb,
699 .set_false_color = ivb_fbc_set_false_color,
700 };
701
intel_fbc_hw_is_active(struct intel_fbc * fbc)702 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc)
703 {
704 return fbc->funcs->is_active(fbc);
705 }
706
intel_fbc_hw_activate(struct intel_fbc * fbc)707 static void intel_fbc_hw_activate(struct intel_fbc *fbc)
708 {
709 trace_intel_fbc_activate(fbc->state.plane);
710
711 fbc->active = true;
712 fbc->activated = true;
713
714 fbc->funcs->activate(fbc);
715 }
716
intel_fbc_hw_deactivate(struct intel_fbc * fbc)717 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc)
718 {
719 trace_intel_fbc_deactivate(fbc->state.plane);
720
721 fbc->active = false;
722
723 fbc->funcs->deactivate(fbc);
724 }
725
intel_fbc_is_compressing(struct intel_fbc * fbc)726 static bool intel_fbc_is_compressing(struct intel_fbc *fbc)
727 {
728 return fbc->funcs->is_compressing(fbc);
729 }
730
intel_fbc_nuke(struct intel_fbc * fbc)731 static void intel_fbc_nuke(struct intel_fbc *fbc)
732 {
733 struct intel_display *display = fbc->display;
734
735 lockdep_assert_held(&fbc->lock);
736 drm_WARN_ON(display->drm, fbc->flip_pending);
737
738 trace_intel_fbc_nuke(fbc->state.plane);
739
740 fbc->funcs->nuke(fbc);
741 }
742
intel_fbc_activate(struct intel_fbc * fbc)743 static void intel_fbc_activate(struct intel_fbc *fbc)
744 {
745 struct intel_display *display = fbc->display;
746
747 lockdep_assert_held(&fbc->lock);
748
749 /* only the fence can change for a flip nuke */
750 if (fbc->active && !intel_fbc_has_fences(display))
751 return;
752 /*
753 * In case of FBC dirt rect, any updates to the FBC registers will
754 * trigger the nuke.
755 */
756 drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));
757
758 intel_fbc_hw_activate(fbc);
759 intel_fbc_nuke(fbc);
760
761 fbc->no_fbc_reason = NULL;
762 }
763
intel_fbc_deactivate(struct intel_fbc * fbc,const char * reason)764 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason)
765 {
766 lockdep_assert_held(&fbc->lock);
767
768 if (fbc->active)
769 intel_fbc_hw_deactivate(fbc);
770
771 fbc->no_fbc_reason = reason;
772 }
773
intel_fbc_cfb_base_max(struct intel_display * display)774 static u64 intel_fbc_cfb_base_max(struct intel_display *display)
775 {
776 if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
777 return BIT_ULL(28);
778 else
779 return BIT_ULL(32);
780 }
781
intel_fbc_stolen_end(struct intel_display * display)782 static u64 intel_fbc_stolen_end(struct intel_display *display)
783 {
784 struct drm_i915_private __maybe_unused *i915 = to_i915(display->drm);
785 u64 end;
786
787 /* The FBC hardware for BDW/SKL doesn't have access to the stolen
788 * reserved range size, so it always assumes the maximum (8mb) is used.
789 * If we enable FBC using a CFB on that memory range we'll get FIFO
790 * underruns, even if that range is not reserved by the BIOS. */
791 if (display->platform.broadwell ||
792 (DISPLAY_VER(display) == 9 && !display->platform.broxton))
793 end = i915_gem_stolen_area_size(i915) - 8 * 1024 * 1024;
794 else
795 end = U64_MAX;
796
797 return min(end, intel_fbc_cfb_base_max(display));
798 }
799
intel_fbc_min_limit(const struct intel_plane_state * plane_state)800 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state)
801 {
802 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1;
803 }
804
intel_fbc_max_limit(struct intel_display * display)805 static int intel_fbc_max_limit(struct intel_display *display)
806 {
807 /* WaFbcOnly1to1Ratio:ctg */
808 if (display->platform.g4x)
809 return 1;
810
811 /*
812 * FBC2 can only do 1:1, 1:2, 1:4, we limit
813 * FBC1 to the same out of convenience.
814 */
815 return 4;
816 }
817
find_compression_limit(struct intel_fbc * fbc,unsigned int size,int min_limit)818 static int find_compression_limit(struct intel_fbc *fbc,
819 unsigned int size, int min_limit)
820 {
821 struct intel_display *display = fbc->display;
822 struct drm_i915_private *i915 = to_i915(display->drm);
823 u64 end = intel_fbc_stolen_end(display);
824 int ret, limit = min_limit;
825
826 size /= limit;
827
828 /* Try to over-allocate to reduce reallocations and fragmentation. */
829 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
830 size <<= 1, 4096, 0, end);
831 if (ret == 0)
832 return limit;
833
834 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) {
835 ret = i915_gem_stolen_insert_node_in_range(i915, &fbc->compressed_fb,
836 size >>= 1, 4096, 0, end);
837 if (ret == 0)
838 return limit;
839 }
840
841 return 0;
842 }
843
intel_fbc_alloc_cfb(struct intel_fbc * fbc,unsigned int size,int min_limit)844 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
845 unsigned int size, int min_limit)
846 {
847 struct intel_display *display = fbc->display;
848 struct drm_i915_private *i915 = to_i915(display->drm);
849 int ret;
850
851 drm_WARN_ON(display->drm,
852 i915_gem_stolen_node_allocated(&fbc->compressed_fb));
853 drm_WARN_ON(display->drm,
854 i915_gem_stolen_node_allocated(&fbc->compressed_llb));
855
856 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) {
857 ret = i915_gem_stolen_insert_node(i915, &fbc->compressed_llb,
858 4096, 4096);
859 if (ret)
860 goto err;
861 }
862
863 ret = find_compression_limit(fbc, size, min_limit);
864 if (!ret)
865 goto err_llb;
866 else if (ret > min_limit)
867 drm_info_once(display->drm,
868 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
869
870 fbc->limit = ret;
871
872 drm_dbg_kms(display->drm,
873 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n",
874 i915_gem_stolen_node_size(&fbc->compressed_fb), fbc->limit);
875 return 0;
876
877 err_llb:
878 if (i915_gem_stolen_node_allocated(&fbc->compressed_llb))
879 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
880 err:
881 if (i915_gem_stolen_initialized(i915))
882 drm_info_once(display->drm,
883 "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
884 return -ENOSPC;
885 }
886
intel_fbc_program_cfb(struct intel_fbc * fbc)887 static void intel_fbc_program_cfb(struct intel_fbc *fbc)
888 {
889 fbc->funcs->program_cfb(fbc);
890 }
891
intel_fbc_program_workarounds(struct intel_fbc * fbc)892 static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
893 {
894 struct intel_display *display = fbc->display;
895
896 if (display->platform.skylake || display->platform.broxton) {
897 /*
898 * WaFbcHighMemBwCorruptionAvoidance:skl,bxt
899 * Display WA #0883: skl,bxt
900 */
901 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
902 0, DPFC_DISABLE_DUMMY0);
903 }
904
905 if (display->platform.skylake || display->platform.kabylake ||
906 display->platform.coffeelake || display->platform.cometlake) {
907 /*
908 * WaFbcNukeOnHostModify:skl,kbl,cfl
909 * Display WA #0873: skl,kbl,cfl
910 */
911 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
912 0, DPFC_NUKE_ON_ANY_MODIFICATION);
913 }
914
915 /* Wa_1409120013:icl,jsl,tgl,dg1 */
916 if (IS_DISPLAY_VER(display, 11, 12))
917 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
918 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL);
919
920 /* Wa_22014263786:icl,jsl,tgl,dg1,rkl,adls,adlp,mtl */
921 if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
922 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id),
923 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION);
924 }
925
__intel_fbc_cleanup_cfb(struct intel_fbc * fbc)926 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
927 {
928 struct intel_display *display = fbc->display;
929 struct drm_i915_private *i915 = to_i915(display->drm);
930
931 if (WARN_ON(intel_fbc_hw_is_active(fbc)))
932 return;
933
934 if (i915_gem_stolen_node_allocated(&fbc->compressed_llb))
935 i915_gem_stolen_remove_node(i915, &fbc->compressed_llb);
936 if (i915_gem_stolen_node_allocated(&fbc->compressed_fb))
937 i915_gem_stolen_remove_node(i915, &fbc->compressed_fb);
938 }
939
intel_fbc_cleanup(struct intel_display * display)940 void intel_fbc_cleanup(struct intel_display *display)
941 {
942 struct intel_fbc *fbc;
943 enum intel_fbc_id fbc_id;
944
945 for_each_intel_fbc(display, fbc, fbc_id) {
946 mutex_lock(&fbc->lock);
947 __intel_fbc_cleanup_cfb(fbc);
948 mutex_unlock(&fbc->lock);
949
950 kfree(fbc);
951 }
952 }
953
i8xx_fbc_stride_is_valid(const struct intel_plane_state * plane_state)954 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
955 {
956 const struct drm_framebuffer *fb = plane_state->hw.fb;
957 unsigned int stride = intel_fbc_plane_stride(plane_state) *
958 fb->format->cpp[0];
959
960 return stride == 4096 || stride == 8192;
961 }
962
i965_fbc_stride_is_valid(const struct intel_plane_state * plane_state)963 static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
964 {
965 const struct drm_framebuffer *fb = plane_state->hw.fb;
966 unsigned int stride = intel_fbc_plane_stride(plane_state) *
967 fb->format->cpp[0];
968
969 return stride >= 2048 && stride <= 16384;
970 }
971
g4x_fbc_stride_is_valid(const struct intel_plane_state * plane_state)972 static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
973 {
974 return true;
975 }
976
skl_fbc_stride_is_valid(const struct intel_plane_state * plane_state)977 static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
978 {
979 const struct drm_framebuffer *fb = plane_state->hw.fb;
980 unsigned int stride = intel_fbc_plane_stride(plane_state) *
981 fb->format->cpp[0];
982
983 /* Display WA #1105: skl,bxt,kbl,cfl,glk */
984 if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511)
985 return false;
986
987 return true;
988 }
989
icl_fbc_stride_is_valid(const struct intel_plane_state * plane_state)990 static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
991 {
992 return true;
993 }
994
stride_is_valid(const struct intel_plane_state * plane_state)995 static bool stride_is_valid(const struct intel_plane_state *plane_state)
996 {
997 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
998
999 if (DISPLAY_VER(display) >= 11)
1000 return icl_fbc_stride_is_valid(plane_state);
1001 else if (DISPLAY_VER(display) >= 9)
1002 return skl_fbc_stride_is_valid(plane_state);
1003 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1004 return g4x_fbc_stride_is_valid(plane_state);
1005 else if (DISPLAY_VER(display) == 4)
1006 return i965_fbc_stride_is_valid(plane_state);
1007 else
1008 return i8xx_fbc_stride_is_valid(plane_state);
1009 }
1010
i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state * plane_state)1011 static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
1012 {
1013 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1014 const struct drm_framebuffer *fb = plane_state->hw.fb;
1015
1016 switch (fb->format->format) {
1017 case DRM_FORMAT_XRGB8888:
1018 case DRM_FORMAT_XBGR8888:
1019 return true;
1020 case DRM_FORMAT_XRGB1555:
1021 case DRM_FORMAT_RGB565:
1022 /* 16bpp not supported on gen2 */
1023 if (DISPLAY_VER(display) == 2)
1024 return false;
1025 return true;
1026 default:
1027 return false;
1028 }
1029 }
1030
g4x_fbc_pixel_format_is_valid(const struct intel_plane_state * plane_state)1031 static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
1032 {
1033 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1034 const struct drm_framebuffer *fb = plane_state->hw.fb;
1035
1036 switch (fb->format->format) {
1037 case DRM_FORMAT_XRGB8888:
1038 case DRM_FORMAT_XBGR8888:
1039 return true;
1040 case DRM_FORMAT_RGB565:
1041 /* WaFbcOnly1to1Ratio:ctg */
1042 if (display->platform.g4x)
1043 return false;
1044 return true;
1045 default:
1046 return false;
1047 }
1048 }
1049
lnl_fbc_pixel_format_is_valid(const struct intel_plane_state * plane_state)1050 static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
1051 {
1052 const struct drm_framebuffer *fb = plane_state->hw.fb;
1053
1054 switch (fb->format->format) {
1055 case DRM_FORMAT_XRGB8888:
1056 case DRM_FORMAT_XBGR8888:
1057 case DRM_FORMAT_ARGB8888:
1058 case DRM_FORMAT_ABGR8888:
1059 case DRM_FORMAT_RGB565:
1060 return true;
1061 default:
1062 return false;
1063 }
1064 }
1065
pixel_format_is_valid(const struct intel_plane_state * plane_state)1066 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
1067 {
1068 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1069
1070 if (DISPLAY_VER(display) >= 20)
1071 return lnl_fbc_pixel_format_is_valid(plane_state);
1072 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1073 return g4x_fbc_pixel_format_is_valid(plane_state);
1074 else
1075 return i8xx_fbc_pixel_format_is_valid(plane_state);
1076 }
1077
i8xx_fbc_rotation_is_valid(const struct intel_plane_state * plane_state)1078 static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
1079 {
1080 return plane_state->hw.rotation == DRM_MODE_ROTATE_0;
1081 }
1082
g4x_fbc_rotation_is_valid(const struct intel_plane_state * plane_state)1083 static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
1084 {
1085 return true;
1086 }
1087
skl_fbc_rotation_is_valid(const struct intel_plane_state * plane_state)1088 static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state)
1089 {
1090 const struct drm_framebuffer *fb = plane_state->hw.fb;
1091 unsigned int rotation = plane_state->hw.rotation;
1092
1093 if (fb->format->format == DRM_FORMAT_RGB565 &&
1094 drm_rotation_90_or_270(rotation))
1095 return false;
1096
1097 return true;
1098 }
1099
rotation_is_valid(const struct intel_plane_state * plane_state)1100 static bool rotation_is_valid(const struct intel_plane_state *plane_state)
1101 {
1102 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1103
1104 if (DISPLAY_VER(display) >= 9)
1105 return skl_fbc_rotation_is_valid(plane_state);
1106 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
1107 return g4x_fbc_rotation_is_valid(plane_state);
1108 else
1109 return i8xx_fbc_rotation_is_valid(plane_state);
1110 }
1111
intel_fbc_max_surface_size(struct intel_display * display,unsigned int * w,unsigned int * h)1112 static void intel_fbc_max_surface_size(struct intel_display *display,
1113 unsigned int *w, unsigned int *h)
1114 {
1115 if (DISPLAY_VER(display) >= 11) {
1116 *w = 8192;
1117 *h = 4096;
1118 } else if (DISPLAY_VER(display) >= 10) {
1119 *w = 5120;
1120 *h = 4096;
1121 } else if (DISPLAY_VER(display) >= 7) {
1122 *w = 4096;
1123 *h = 4096;
1124 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
1125 *w = 4096;
1126 *h = 2048;
1127 } else {
1128 *w = 2048;
1129 *h = 1536;
1130 }
1131 }
1132
1133 /*
1134 * For some reason, the hardware tracking starts looking at whatever we
1135 * programmed as the display plane base address register. It does not look at
1136 * the X and Y offset registers. That's why we include the src x/y offsets
1137 * instead of just looking at the plane size.
1138 */
intel_fbc_surface_size_ok(const struct intel_plane_state * plane_state)1139 static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state)
1140 {
1141 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1142 unsigned int effective_w, effective_h, max_w, max_h;
1143
1144 intel_fbc_max_surface_size(display, &max_w, &max_h);
1145
1146 effective_w = plane_state->view.color_plane[0].x +
1147 (drm_rect_width(&plane_state->uapi.src) >> 16);
1148 effective_h = plane_state->view.color_plane[0].y +
1149 (drm_rect_height(&plane_state->uapi.src) >> 16);
1150
1151 return effective_w <= max_w && effective_h <= max_h;
1152 }
1153
intel_fbc_max_plane_size(struct intel_display * display,unsigned int * w,unsigned int * h)1154 static void intel_fbc_max_plane_size(struct intel_display *display,
1155 unsigned int *w, unsigned int *h)
1156 {
1157 if (DISPLAY_VER(display) >= 10) {
1158 *w = 5120;
1159 *h = 4096;
1160 } else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) {
1161 *w = 4096;
1162 *h = 4096;
1163 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) {
1164 *w = 4096;
1165 *h = 2048;
1166 } else {
1167 *w = 2048;
1168 *h = 1536;
1169 }
1170 }
1171
intel_fbc_plane_size_valid(const struct intel_plane_state * plane_state)1172 static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state)
1173 {
1174 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1175 unsigned int w, h, max_w, max_h;
1176
1177 intel_fbc_max_plane_size(display, &max_w, &max_h);
1178
1179 w = drm_rect_width(&plane_state->uapi.src) >> 16;
1180 h = drm_rect_height(&plane_state->uapi.src) >> 16;
1181
1182 return w <= max_w && h <= max_h;
1183 }
1184
i8xx_fbc_tiling_valid(const struct intel_plane_state * plane_state)1185 static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state)
1186 {
1187 const struct drm_framebuffer *fb = plane_state->hw.fb;
1188
1189 return fb->modifier == I915_FORMAT_MOD_X_TILED;
1190 }
1191
skl_fbc_tiling_valid(const struct intel_plane_state * plane_state)1192 static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state)
1193 {
1194 return true;
1195 }
1196
tiling_is_valid(const struct intel_plane_state * plane_state)1197 static bool tiling_is_valid(const struct intel_plane_state *plane_state)
1198 {
1199 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1200
1201 if (DISPLAY_VER(display) >= 9)
1202 return skl_fbc_tiling_valid(plane_state);
1203 else
1204 return i8xx_fbc_tiling_valid(plane_state);
1205 }
1206
1207 static void
intel_fbc_invalidate_dirty_rect(struct intel_fbc * fbc)1208 intel_fbc_invalidate_dirty_rect(struct intel_fbc *fbc)
1209 {
1210 lockdep_assert_held(&fbc->lock);
1211
1212 fbc->state.dirty_rect = DRM_RECT_INIT(0, 0, 0, 0);
1213 }
1214
1215 static void
intel_fbc_program_dirty_rect(struct intel_dsb * dsb,struct intel_fbc * fbc,const struct drm_rect * fbc_dirty_rect)1216 intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_fbc *fbc,
1217 const struct drm_rect *fbc_dirty_rect)
1218 {
1219 struct intel_display *display = fbc->display;
1220
1221 drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0);
1222
1223 intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id),
1224 FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) |
1225 FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2 - 1));
1226 }
1227
1228 static void
intel_fbc_dirty_rect_update(struct intel_dsb * dsb,struct intel_fbc * fbc)1229 intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_fbc *fbc)
1230 {
1231 const struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect;
1232
1233 lockdep_assert_held(&fbc->lock);
1234
1235 if (!drm_rect_visible(fbc_dirty_rect))
1236 return;
1237
1238 intel_fbc_program_dirty_rect(dsb, fbc, fbc_dirty_rect);
1239 }
1240
1241 void
intel_fbc_dirty_rect_update_noarm(struct intel_dsb * dsb,struct intel_plane * plane)1242 intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
1243 struct intel_plane *plane)
1244 {
1245 struct intel_display *display = to_intel_display(plane);
1246 struct intel_fbc *fbc = plane->fbc;
1247
1248 if (!HAS_FBC_DIRTY_RECT(display))
1249 return;
1250
1251 mutex_lock(&fbc->lock);
1252
1253 if (fbc->state.plane == plane)
1254 intel_fbc_dirty_rect_update(dsb, fbc);
1255
1256 mutex_unlock(&fbc->lock);
1257 }
1258
1259 static void
intel_fbc_hw_intialize_dirty_rect(struct intel_fbc * fbc,const struct intel_plane_state * plane_state)1260 intel_fbc_hw_intialize_dirty_rect(struct intel_fbc *fbc,
1261 const struct intel_plane_state *plane_state)
1262 {
1263 struct drm_rect src;
1264
1265 /*
1266 * Initializing the FBC HW with the whole plane area as the dirty rect.
1267 * This is to ensure that we have valid coords be written to the
1268 * HW as dirty rect.
1269 */
1270 drm_rect_fp_to_int(&src, &plane_state->uapi.src);
1271
1272 intel_fbc_program_dirty_rect(NULL, fbc, &src);
1273 }
1274
intel_fbc_update_state(struct intel_atomic_state * state,struct intel_crtc * crtc,struct intel_plane * plane)1275 static void intel_fbc_update_state(struct intel_atomic_state *state,
1276 struct intel_crtc *crtc,
1277 struct intel_plane *plane)
1278 {
1279 struct intel_display *display = to_intel_display(state->base.dev);
1280 const struct intel_crtc_state *crtc_state =
1281 intel_atomic_get_new_crtc_state(state, crtc);
1282 const struct intel_plane_state *plane_state =
1283 intel_atomic_get_new_plane_state(state, plane);
1284 struct intel_fbc *fbc = plane->fbc;
1285 struct intel_fbc_state *fbc_state = &fbc->state;
1286
1287 WARN_ON(plane_state->no_fbc_reason);
1288 WARN_ON(fbc_state->plane && fbc_state->plane != plane);
1289
1290 fbc_state->plane = plane;
1291
1292 /* FBC1 compression interval: arbitrary choice of 1 second */
1293 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode);
1294
1295 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state);
1296
1297 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE &&
1298 !intel_fbc_has_fences(display));
1299
1300 if (plane_state->flags & PLANE_HAS_FENCE)
1301 fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma);
1302 else
1303 fbc_state->fence_id = -1;
1304
1305 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state);
1306 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state);
1307 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state);
1308 }
1309
intel_fbc_is_fence_ok(const struct intel_plane_state * plane_state)1310 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state)
1311 {
1312 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
1313
1314 /*
1315 * The use of a CPU fence is one of two ways to detect writes by the
1316 * CPU to the scanout and trigger updates to the FBC.
1317 *
1318 * The other method is by software tracking (see
1319 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke
1320 * the current compressed buffer and recompress it.
1321 *
1322 * Note that is possible for a tiled surface to be unmappable (and
1323 * so have no fence associated with it) due to aperture constraints
1324 * at the time of pinning.
1325 */
1326 return DISPLAY_VER(display) >= 9 ||
1327 (plane_state->flags & PLANE_HAS_FENCE &&
1328 i915_vma_fence_id(plane_state->ggtt_vma) != -1);
1329 }
1330
intel_fbc_is_cfb_ok(const struct intel_plane_state * plane_state)1331 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state)
1332 {
1333 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1334 struct intel_fbc *fbc = plane->fbc;
1335
1336 return intel_fbc_min_limit(plane_state) <= fbc->limit &&
1337 intel_fbc_cfb_size(plane_state) <= fbc->limit *
1338 i915_gem_stolen_node_size(&fbc->compressed_fb);
1339 }
1340
intel_fbc_is_ok(const struct intel_plane_state * plane_state)1341 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state)
1342 {
1343 return !plane_state->no_fbc_reason &&
1344 intel_fbc_is_fence_ok(plane_state) &&
1345 intel_fbc_is_cfb_ok(plane_state);
1346 }
1347
1348 static void
__intel_fbc_prepare_dirty_rect(const struct intel_plane_state * plane_state,const struct intel_crtc_state * crtc_state)1349 __intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state,
1350 const struct intel_crtc_state *crtc_state)
1351 {
1352 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1353 struct intel_fbc *fbc = plane->fbc;
1354 struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect;
1355 int width = drm_rect_width(&plane_state->uapi.src) >> 16;
1356 const struct drm_rect *damage = &plane_state->damage;
1357 int y_offset = plane_state->view.color_plane[0].y;
1358
1359 lockdep_assert_held(&fbc->lock);
1360
1361 if (intel_crtc_needs_modeset(crtc_state) ||
1362 !intel_fbc_is_ok(plane_state)) {
1363 intel_fbc_invalidate_dirty_rect(fbc);
1364 return;
1365 }
1366
1367 if (drm_rect_visible(damage))
1368 *fbc_dirty_rect = *damage;
1369 else
1370 /* dirty rect must cover at least one line */
1371 *fbc_dirty_rect = DRM_RECT_INIT(0, y_offset, width, 1);
1372 }
1373
1374 void
intel_fbc_prepare_dirty_rect(struct intel_atomic_state * state,struct intel_crtc * crtc)1375 intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
1376 struct intel_crtc *crtc)
1377 {
1378 struct intel_display *display = to_intel_display(state);
1379 const struct intel_crtc_state *crtc_state =
1380 intel_atomic_get_new_crtc_state(state, crtc);
1381 struct intel_plane_state *plane_state;
1382 struct intel_plane *plane;
1383 int i;
1384
1385 if (!HAS_FBC_DIRTY_RECT(display))
1386 return;
1387
1388 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1389 struct intel_fbc *fbc = plane->fbc;
1390
1391 if (!fbc || plane->pipe != crtc->pipe)
1392 continue;
1393
1394 mutex_lock(&fbc->lock);
1395
1396 if (fbc->state.plane == plane)
1397 __intel_fbc_prepare_dirty_rect(plane_state,
1398 crtc_state);
1399
1400 mutex_unlock(&fbc->lock);
1401 }
1402 }
1403
intel_fbc_check_plane(struct intel_atomic_state * state,struct intel_plane * plane)1404 static int intel_fbc_check_plane(struct intel_atomic_state *state,
1405 struct intel_plane *plane)
1406 {
1407 struct intel_display *display = to_intel_display(state->base.dev);
1408 struct drm_i915_private *i915 = to_i915(display->drm);
1409 struct intel_plane_state *plane_state =
1410 intel_atomic_get_new_plane_state(state, plane);
1411 const struct drm_framebuffer *fb = plane_state->hw.fb;
1412 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
1413 const struct intel_crtc_state *crtc_state;
1414 struct intel_fbc *fbc = plane->fbc;
1415
1416 if (!fbc)
1417 return 0;
1418
1419 if (!i915_gem_stolen_initialized(i915)) {
1420 plane_state->no_fbc_reason = "stolen memory not initialised";
1421 return 0;
1422 }
1423
1424 if (intel_vgpu_active(i915)) {
1425 plane_state->no_fbc_reason = "VGPU active";
1426 return 0;
1427 }
1428
1429 if (!display->params.enable_fbc) {
1430 plane_state->no_fbc_reason = "disabled per module param or by default";
1431 return 0;
1432 }
1433
1434 if (!plane_state->uapi.visible) {
1435 plane_state->no_fbc_reason = "plane not visible";
1436 return 0;
1437 }
1438
1439 if (intel_display_needs_wa_16023588340(i915)) {
1440 plane_state->no_fbc_reason = "Wa_16023588340";
1441 return 0;
1442 }
1443
1444 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1445 if (i915_vtd_active(i915) && (display->platform.skylake || display->platform.broxton)) {
1446 plane_state->no_fbc_reason = "VT-d enabled";
1447 return 0;
1448 }
1449
1450 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
1451
1452 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1453 plane_state->no_fbc_reason = "interlaced mode not supported";
1454 return 0;
1455 }
1456
1457 if (crtc_state->double_wide) {
1458 plane_state->no_fbc_reason = "double wide pipe not supported";
1459 return 0;
1460 }
1461
1462 /*
1463 * Display 12+ is not supporting FBC with PSR2.
1464 * Recommendation is to keep this combination disabled
1465 * Bspec: 50422 HSD: 14010260002
1466 *
1467 * In Xe3, PSR2 selective fetch and FBC dirty rect feature cannot
1468 * coexist. So if PSR2 selective fetch is supported then mark that
1469 * FBC is not supported.
1470 * TODO: Need a logic to decide between PSR2 and FBC Dirty rect
1471 */
1472 if ((IS_DISPLAY_VER(display, 12, 14) || HAS_FBC_DIRTY_RECT(display)) &&
1473 crtc_state->has_sel_update && !crtc_state->has_panel_replay) {
1474 plane_state->no_fbc_reason = "PSR2 enabled";
1475 return 0;
1476 }
1477
1478 /* Wa_14016291713 */
1479 if ((IS_DISPLAY_VER(display, 12, 13) ||
1480 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) &&
1481 crtc_state->has_psr && !crtc_state->has_panel_replay) {
1482 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
1483 return 0;
1484 }
1485
1486 if (!pixel_format_is_valid(plane_state)) {
1487 plane_state->no_fbc_reason = "pixel format not supported";
1488 return 0;
1489 }
1490
1491 if (!tiling_is_valid(plane_state)) {
1492 plane_state->no_fbc_reason = "tiling not supported";
1493 return 0;
1494 }
1495
1496 if (!rotation_is_valid(plane_state)) {
1497 plane_state->no_fbc_reason = "rotation not supported";
1498 return 0;
1499 }
1500
1501 if (!stride_is_valid(plane_state)) {
1502 plane_state->no_fbc_reason = "stride not supported";
1503 return 0;
1504 }
1505
1506 if (DISPLAY_VER(display) < 20 &&
1507 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
1508 fb->format->has_alpha) {
1509 plane_state->no_fbc_reason = "per-pixel alpha not supported";
1510 return 0;
1511 }
1512
1513 if (!intel_fbc_plane_size_valid(plane_state)) {
1514 plane_state->no_fbc_reason = "plane size too big";
1515 return 0;
1516 }
1517
1518 if (!intel_fbc_surface_size_ok(plane_state)) {
1519 plane_state->no_fbc_reason = "surface size too big";
1520 return 0;
1521 }
1522
1523 /*
1524 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
1525 * having a Y offset that isn't divisible by 4 causes FIFO underrun
1526 * and screen flicker.
1527 */
1528 if (DISPLAY_VER(display) >= 9 &&
1529 plane_state->view.color_plane[0].y & 3) {
1530 plane_state->no_fbc_reason = "plane start Y offset misaligned";
1531 return 0;
1532 }
1533
1534 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */
1535 if (DISPLAY_VER(display) >= 11 &&
1536 (plane_state->view.color_plane[0].y +
1537 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) {
1538 plane_state->no_fbc_reason = "plane end Y offset misaligned";
1539 return 0;
1540 }
1541
1542 /* WaFbcExceedCdClockThreshold:hsw,bdw */
1543 if (display->platform.haswell || display->platform.broadwell) {
1544 const struct intel_cdclk_state *cdclk_state;
1545
1546 cdclk_state = intel_atomic_get_cdclk_state(state);
1547 if (IS_ERR(cdclk_state))
1548 return PTR_ERR(cdclk_state);
1549
1550 if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
1551 plane_state->no_fbc_reason = "pixel rate too high";
1552 return 0;
1553 }
1554 }
1555
1556 plane_state->no_fbc_reason = NULL;
1557
1558 return 0;
1559 }
1560
1561
intel_fbc_can_flip_nuke(struct intel_atomic_state * state,struct intel_crtc * crtc,struct intel_plane * plane)1562 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
1563 struct intel_crtc *crtc,
1564 struct intel_plane *plane)
1565 {
1566 const struct intel_crtc_state *new_crtc_state =
1567 intel_atomic_get_new_crtc_state(state, crtc);
1568 const struct intel_plane_state *old_plane_state =
1569 intel_atomic_get_old_plane_state(state, plane);
1570 const struct intel_plane_state *new_plane_state =
1571 intel_atomic_get_new_plane_state(state, plane);
1572 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb;
1573 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb;
1574
1575 if (intel_crtc_needs_modeset(new_crtc_state))
1576 return false;
1577
1578 if (!intel_fbc_is_ok(old_plane_state) ||
1579 !intel_fbc_is_ok(new_plane_state))
1580 return false;
1581
1582 if (old_fb->format->format != new_fb->format->format)
1583 return false;
1584
1585 if (old_fb->modifier != new_fb->modifier)
1586 return false;
1587
1588 if (intel_fbc_plane_stride(old_plane_state) !=
1589 intel_fbc_plane_stride(new_plane_state))
1590 return false;
1591
1592 if (intel_fbc_cfb_stride(old_plane_state) !=
1593 intel_fbc_cfb_stride(new_plane_state))
1594 return false;
1595
1596 if (intel_fbc_cfb_size(old_plane_state) !=
1597 intel_fbc_cfb_size(new_plane_state))
1598 return false;
1599
1600 if (intel_fbc_override_cfb_stride(old_plane_state) !=
1601 intel_fbc_override_cfb_stride(new_plane_state))
1602 return false;
1603
1604 return true;
1605 }
1606
__intel_fbc_pre_update(struct intel_atomic_state * state,struct intel_crtc * crtc,struct intel_plane * plane)1607 static bool __intel_fbc_pre_update(struct intel_atomic_state *state,
1608 struct intel_crtc *crtc,
1609 struct intel_plane *plane)
1610 {
1611 struct intel_display *display = to_intel_display(state->base.dev);
1612 struct intel_fbc *fbc = plane->fbc;
1613 bool need_vblank_wait = false;
1614
1615 lockdep_assert_held(&fbc->lock);
1616
1617 fbc->flip_pending = true;
1618
1619 if (intel_fbc_can_flip_nuke(state, crtc, plane))
1620 return need_vblank_wait;
1621
1622 intel_fbc_deactivate(fbc, "update pending");
1623
1624 /*
1625 * Display WA #1198: glk+
1626 * Need an extra vblank wait between FBC disable and most plane
1627 * updates. Bspec says this is only needed for plane disable, but
1628 * that is not true. Touching most plane registers will cause the
1629 * corruption to appear. Also SKL/derivatives do not seem to be
1630 * affected.
1631 *
1632 * TODO: could optimize this a bit by sampling the frame
1633 * counter when we disable FBC (if it was already done earlier)
1634 * and skipping the extra vblank wait before the plane update
1635 * if at least one frame has already passed.
1636 */
1637 if (fbc->activated && DISPLAY_VER(display) >= 10)
1638 need_vblank_wait = true;
1639 fbc->activated = false;
1640
1641 return need_vblank_wait;
1642 }
1643
intel_fbc_pre_update(struct intel_atomic_state * state,struct intel_crtc * crtc)1644 bool intel_fbc_pre_update(struct intel_atomic_state *state,
1645 struct intel_crtc *crtc)
1646 {
1647 const struct intel_plane_state __maybe_unused *plane_state;
1648 bool need_vblank_wait = false;
1649 struct intel_plane *plane;
1650 int i;
1651
1652 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1653 struct intel_fbc *fbc = plane->fbc;
1654
1655 if (!fbc || plane->pipe != crtc->pipe)
1656 continue;
1657
1658 mutex_lock(&fbc->lock);
1659
1660 if (fbc->state.plane == plane)
1661 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane);
1662
1663 mutex_unlock(&fbc->lock);
1664 }
1665
1666 return need_vblank_wait;
1667 }
1668
__intel_fbc_disable(struct intel_fbc * fbc)1669 static void __intel_fbc_disable(struct intel_fbc *fbc)
1670 {
1671 struct intel_display *display = fbc->display;
1672 struct intel_plane *plane = fbc->state.plane;
1673
1674 lockdep_assert_held(&fbc->lock);
1675 drm_WARN_ON(display->drm, fbc->active);
1676
1677 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n",
1678 plane->base.base.id, plane->base.name);
1679
1680 intel_fbc_invalidate_dirty_rect(fbc);
1681
1682 __intel_fbc_cleanup_cfb(fbc);
1683
1684 fbc->state.plane = NULL;
1685 fbc->flip_pending = false;
1686 fbc->busy_bits = 0;
1687 }
1688
__intel_fbc_post_update(struct intel_fbc * fbc)1689 static void __intel_fbc_post_update(struct intel_fbc *fbc)
1690 {
1691 lockdep_assert_held(&fbc->lock);
1692
1693 fbc->flip_pending = false;
1694 fbc->busy_bits = 0;
1695
1696 intel_fbc_activate(fbc);
1697 }
1698
intel_fbc_post_update(struct intel_atomic_state * state,struct intel_crtc * crtc)1699 void intel_fbc_post_update(struct intel_atomic_state *state,
1700 struct intel_crtc *crtc)
1701 {
1702 const struct intel_plane_state __maybe_unused *plane_state;
1703 struct intel_plane *plane;
1704 int i;
1705
1706 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1707 struct intel_fbc *fbc = plane->fbc;
1708
1709 if (!fbc || plane->pipe != crtc->pipe)
1710 continue;
1711
1712 mutex_lock(&fbc->lock);
1713
1714 if (fbc->state.plane == plane)
1715 __intel_fbc_post_update(fbc);
1716
1717 mutex_unlock(&fbc->lock);
1718 }
1719 }
1720
intel_fbc_get_frontbuffer_bit(struct intel_fbc * fbc)1721 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
1722 {
1723 if (fbc->state.plane)
1724 return fbc->state.plane->frontbuffer_bit;
1725 else
1726 return 0;
1727 }
1728
__intel_fbc_invalidate(struct intel_fbc * fbc,unsigned int frontbuffer_bits,enum fb_op_origin origin)1729 static void __intel_fbc_invalidate(struct intel_fbc *fbc,
1730 unsigned int frontbuffer_bits,
1731 enum fb_op_origin origin)
1732 {
1733 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1734 return;
1735
1736 mutex_lock(&fbc->lock);
1737
1738 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1739 if (!frontbuffer_bits)
1740 goto out;
1741
1742 fbc->busy_bits |= frontbuffer_bits;
1743 intel_fbc_deactivate(fbc, "frontbuffer write");
1744
1745 out:
1746 mutex_unlock(&fbc->lock);
1747 }
1748
intel_fbc_invalidate(struct intel_display * display,unsigned int frontbuffer_bits,enum fb_op_origin origin)1749 void intel_fbc_invalidate(struct intel_display *display,
1750 unsigned int frontbuffer_bits,
1751 enum fb_op_origin origin)
1752 {
1753 struct intel_fbc *fbc;
1754 enum intel_fbc_id fbc_id;
1755
1756 for_each_intel_fbc(display, fbc, fbc_id)
1757 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin);
1758
1759 }
1760
__intel_fbc_flush(struct intel_fbc * fbc,unsigned int frontbuffer_bits,enum fb_op_origin origin)1761 static void __intel_fbc_flush(struct intel_fbc *fbc,
1762 unsigned int frontbuffer_bits,
1763 enum fb_op_origin origin)
1764 {
1765 mutex_lock(&fbc->lock);
1766
1767 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc);
1768 if (!frontbuffer_bits)
1769 goto out;
1770
1771 fbc->busy_bits &= ~frontbuffer_bits;
1772
1773 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE)
1774 goto out;
1775
1776 if (fbc->busy_bits || fbc->flip_pending)
1777 goto out;
1778
1779 if (fbc->active)
1780 intel_fbc_nuke(fbc);
1781 else
1782 intel_fbc_activate(fbc);
1783
1784 out:
1785 mutex_unlock(&fbc->lock);
1786 }
1787
intel_fbc_flush(struct intel_display * display,unsigned int frontbuffer_bits,enum fb_op_origin origin)1788 void intel_fbc_flush(struct intel_display *display,
1789 unsigned int frontbuffer_bits,
1790 enum fb_op_origin origin)
1791 {
1792 struct intel_fbc *fbc;
1793 enum intel_fbc_id fbc_id;
1794
1795 for_each_intel_fbc(display, fbc, fbc_id)
1796 __intel_fbc_flush(fbc, frontbuffer_bits, origin);
1797 }
1798
intel_fbc_atomic_check(struct intel_atomic_state * state)1799 int intel_fbc_atomic_check(struct intel_atomic_state *state)
1800 {
1801 struct intel_plane_state __maybe_unused *plane_state;
1802 struct intel_plane *plane;
1803 int i;
1804
1805 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1806 int ret;
1807
1808 ret = intel_fbc_check_plane(state, plane);
1809 if (ret)
1810 return ret;
1811 }
1812
1813 return 0;
1814 }
1815
__intel_fbc_enable(struct intel_atomic_state * state,struct intel_crtc * crtc,struct intel_plane * plane)1816 static void __intel_fbc_enable(struct intel_atomic_state *state,
1817 struct intel_crtc *crtc,
1818 struct intel_plane *plane)
1819 {
1820 struct intel_display *display = to_intel_display(state->base.dev);
1821 const struct intel_plane_state *plane_state =
1822 intel_atomic_get_new_plane_state(state, plane);
1823 struct intel_fbc *fbc = plane->fbc;
1824
1825 lockdep_assert_held(&fbc->lock);
1826
1827 if (fbc->state.plane) {
1828 if (fbc->state.plane != plane)
1829 return;
1830
1831 if (intel_fbc_is_ok(plane_state)) {
1832 intel_fbc_update_state(state, crtc, plane);
1833 return;
1834 }
1835
1836 __intel_fbc_disable(fbc);
1837 }
1838
1839 drm_WARN_ON(display->drm, fbc->active);
1840
1841 fbc->no_fbc_reason = plane_state->no_fbc_reason;
1842 if (fbc->no_fbc_reason)
1843 return;
1844
1845 if (!intel_fbc_is_fence_ok(plane_state)) {
1846 fbc->no_fbc_reason = "framebuffer not fenced";
1847 return;
1848 }
1849
1850 if (fbc->underrun_detected) {
1851 fbc->no_fbc_reason = "FIFO underrun";
1852 return;
1853 }
1854
1855 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state),
1856 intel_fbc_min_limit(plane_state))) {
1857 fbc->no_fbc_reason = "not enough stolen memory";
1858 return;
1859 }
1860
1861 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n",
1862 plane->base.base.id, plane->base.name);
1863 fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1864
1865 intel_fbc_update_state(state, crtc, plane);
1866
1867 if (HAS_FBC_DIRTY_RECT(display))
1868 intel_fbc_hw_intialize_dirty_rect(fbc, plane_state);
1869
1870 intel_fbc_program_workarounds(fbc);
1871 intel_fbc_program_cfb(fbc);
1872 }
1873
1874 /**
1875 * intel_fbc_disable - disable FBC if it's associated with crtc
1876 * @crtc: the CRTC
1877 *
1878 * This function disables FBC if it's associated with the provided CRTC.
1879 */
intel_fbc_disable(struct intel_crtc * crtc)1880 void intel_fbc_disable(struct intel_crtc *crtc)
1881 {
1882 struct intel_display *display = to_intel_display(crtc->base.dev);
1883 struct intel_plane *plane;
1884
1885 for_each_intel_plane(display->drm, plane) {
1886 struct intel_fbc *fbc = plane->fbc;
1887
1888 if (!fbc || plane->pipe != crtc->pipe)
1889 continue;
1890
1891 mutex_lock(&fbc->lock);
1892 if (fbc->state.plane == plane)
1893 __intel_fbc_disable(fbc);
1894 mutex_unlock(&fbc->lock);
1895 }
1896 }
1897
intel_fbc_update(struct intel_atomic_state * state,struct intel_crtc * crtc)1898 void intel_fbc_update(struct intel_atomic_state *state,
1899 struct intel_crtc *crtc)
1900 {
1901 const struct intel_crtc_state *crtc_state =
1902 intel_atomic_get_new_crtc_state(state, crtc);
1903 const struct intel_plane_state *plane_state;
1904 struct intel_plane *plane;
1905 int i;
1906
1907 for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1908 struct intel_fbc *fbc = plane->fbc;
1909
1910 if (!fbc || plane->pipe != crtc->pipe)
1911 continue;
1912
1913 mutex_lock(&fbc->lock);
1914
1915 if (intel_crtc_needs_fastset(crtc_state) &&
1916 plane_state->no_fbc_reason) {
1917 if (fbc->state.plane == plane)
1918 __intel_fbc_disable(fbc);
1919 } else {
1920 __intel_fbc_enable(state, crtc, plane);
1921 }
1922
1923 mutex_unlock(&fbc->lock);
1924 }
1925 }
1926
intel_fbc_underrun_work_fn(struct work_struct * work)1927 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1928 {
1929 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work);
1930 struct intel_display *display = fbc->display;
1931
1932 mutex_lock(&fbc->lock);
1933
1934 /* Maybe we were scheduled twice. */
1935 if (fbc->underrun_detected || !fbc->state.plane)
1936 goto out;
1937
1938 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n");
1939 fbc->underrun_detected = true;
1940
1941 intel_fbc_deactivate(fbc, "FIFO underrun");
1942 if (!fbc->flip_pending)
1943 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe));
1944 __intel_fbc_disable(fbc);
1945 out:
1946 mutex_unlock(&fbc->lock);
1947 }
1948
__intel_fbc_reset_underrun(struct intel_fbc * fbc)1949 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc)
1950 {
1951 struct intel_display *display = fbc->display;
1952
1953 cancel_work_sync(&fbc->underrun_work);
1954
1955 mutex_lock(&fbc->lock);
1956
1957 if (fbc->underrun_detected) {
1958 drm_dbg_kms(display->drm,
1959 "Re-allowing FBC after fifo underrun\n");
1960 fbc->no_fbc_reason = "FIFO underrun cleared";
1961 }
1962
1963 fbc->underrun_detected = false;
1964 mutex_unlock(&fbc->lock);
1965 }
1966
1967 /*
1968 * intel_fbc_reset_underrun - reset FBC fifo underrun status.
1969 * @display: display
1970 *
1971 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
1972 * want to re-enable FBC after an underrun to increase test coverage.
1973 */
intel_fbc_reset_underrun(struct intel_display * display)1974 void intel_fbc_reset_underrun(struct intel_display *display)
1975 {
1976 struct intel_fbc *fbc;
1977 enum intel_fbc_id fbc_id;
1978
1979 for_each_intel_fbc(display, fbc, fbc_id)
1980 __intel_fbc_reset_underrun(fbc);
1981 }
1982
__intel_fbc_handle_fifo_underrun_irq(struct intel_fbc * fbc)1983 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc)
1984 {
1985 struct drm_i915_private *i915 = to_i915(fbc->display->drm);
1986
1987 /*
1988 * There's no guarantee that underrun_detected won't be set to true
1989 * right after this check and before the work is scheduled, but that's
1990 * not a problem since we'll check it again under the work function
1991 * while FBC is locked. This check here is just to prevent us from
1992 * unnecessarily scheduling the work, and it relies on the fact that we
1993 * never switch underrun_detect back to false after it's true.
1994 */
1995 if (READ_ONCE(fbc->underrun_detected))
1996 return;
1997
1998 queue_work(i915->unordered_wq, &fbc->underrun_work);
1999 }
2000
2001 /**
2002 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
2003 * @display: display
2004 *
2005 * Without FBC, most underruns are harmless and don't really cause too many
2006 * problems, except for an annoying message on dmesg. With FBC, underruns can
2007 * become black screens or even worse, especially when paired with bad
2008 * watermarks. So in order for us to be on the safe side, completely disable FBC
2009 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
2010 * already suggests that watermarks may be bad, so try to be as safe as
2011 * possible.
2012 *
2013 * This function is called from the IRQ handler.
2014 */
intel_fbc_handle_fifo_underrun_irq(struct intel_display * display)2015 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display)
2016 {
2017 struct intel_fbc *fbc;
2018 enum intel_fbc_id fbc_id;
2019
2020 for_each_intel_fbc(display, fbc, fbc_id)
2021 __intel_fbc_handle_fifo_underrun_irq(fbc);
2022 }
2023
2024 /*
2025 * The DDX driver changes its behavior depending on the value it reads from
2026 * i915.enable_fbc, so sanitize it by translating the default value into either
2027 * 0 or 1 in order to allow it to know what's going on.
2028 *
2029 * Notice that this is done at driver initialization and we still allow user
2030 * space to change the value during runtime without sanitizing it again. IGT
2031 * relies on being able to change i915.enable_fbc at runtime.
2032 */
intel_sanitize_fbc_option(struct intel_display * display)2033 static int intel_sanitize_fbc_option(struct intel_display *display)
2034 {
2035 if (display->params.enable_fbc >= 0)
2036 return !!display->params.enable_fbc;
2037
2038 if (!HAS_FBC(display))
2039 return 0;
2040
2041 if (display->platform.broadwell || DISPLAY_VER(display) >= 9)
2042 return 1;
2043
2044 return 0;
2045 }
2046
intel_fbc_add_plane(struct intel_fbc * fbc,struct intel_plane * plane)2047 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
2048 {
2049 plane->fbc = fbc;
2050 }
2051
intel_fbc_create(struct intel_display * display,enum intel_fbc_id fbc_id)2052 static struct intel_fbc *intel_fbc_create(struct intel_display *display,
2053 enum intel_fbc_id fbc_id)
2054 {
2055 struct intel_fbc *fbc;
2056
2057 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL);
2058 if (!fbc)
2059 return NULL;
2060
2061 fbc->id = fbc_id;
2062 fbc->display = display;
2063 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
2064 mutex_init(&fbc->lock);
2065
2066 if (DISPLAY_VER(display) >= 7)
2067 fbc->funcs = &ivb_fbc_funcs;
2068 else if (DISPLAY_VER(display) == 6)
2069 fbc->funcs = &snb_fbc_funcs;
2070 else if (DISPLAY_VER(display) == 5)
2071 fbc->funcs = &ilk_fbc_funcs;
2072 else if (display->platform.g4x)
2073 fbc->funcs = &g4x_fbc_funcs;
2074 else if (DISPLAY_VER(display) == 4)
2075 fbc->funcs = &i965_fbc_funcs;
2076 else
2077 fbc->funcs = &i8xx_fbc_funcs;
2078
2079 return fbc;
2080 }
2081
2082 /**
2083 * intel_fbc_init - Initialize FBC
2084 * @display: display
2085 *
2086 * This function might be called during PM init process.
2087 */
intel_fbc_init(struct intel_display * display)2088 void intel_fbc_init(struct intel_display *display)
2089 {
2090 enum intel_fbc_id fbc_id;
2091
2092 display->params.enable_fbc = intel_sanitize_fbc_option(display);
2093 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n",
2094 display->params.enable_fbc);
2095
2096 for_each_fbc_id(display, fbc_id)
2097 display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
2098 }
2099
2100 /**
2101 * intel_fbc_sanitize - Sanitize FBC
2102 * @display: display
2103 *
2104 * Make sure FBC is initially disabled since we have no
2105 * idea eg. into which parts of stolen it might be scribbling
2106 * into.
2107 */
intel_fbc_sanitize(struct intel_display * display)2108 void intel_fbc_sanitize(struct intel_display *display)
2109 {
2110 struct intel_fbc *fbc;
2111 enum intel_fbc_id fbc_id;
2112
2113 for_each_intel_fbc(display, fbc, fbc_id) {
2114 if (intel_fbc_hw_is_active(fbc))
2115 intel_fbc_hw_deactivate(fbc);
2116 }
2117 }
2118
intel_fbc_debugfs_status_show(struct seq_file * m,void * unused)2119 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
2120 {
2121 struct intel_fbc *fbc = m->private;
2122 struct intel_display *display = fbc->display;
2123 struct drm_i915_private *i915 = to_i915(display->drm);
2124 struct intel_plane *plane;
2125 intel_wakeref_t wakeref;
2126
2127 drm_modeset_lock_all(display->drm);
2128
2129 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
2130 mutex_lock(&fbc->lock);
2131
2132 if (fbc->active) {
2133 seq_puts(m, "FBC enabled\n");
2134 seq_printf(m, "Compressing: %s\n",
2135 str_yes_no(intel_fbc_is_compressing(fbc)));
2136 } else {
2137 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason);
2138 }
2139
2140 for_each_intel_plane(display->drm, plane) {
2141 const struct intel_plane_state *plane_state =
2142 to_intel_plane_state(plane->base.state);
2143
2144 if (plane->fbc != fbc)
2145 continue;
2146
2147 seq_printf(m, "%c [PLANE:%d:%s]: %s\n",
2148 fbc->state.plane == plane ? '*' : ' ',
2149 plane->base.base.id, plane->base.name,
2150 plane_state->no_fbc_reason ?: "FBC possible");
2151 }
2152
2153 mutex_unlock(&fbc->lock);
2154 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
2155
2156 drm_modeset_unlock_all(display->drm);
2157
2158 return 0;
2159 }
2160
2161 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status);
2162
intel_fbc_debugfs_false_color_get(void * data,u64 * val)2163 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val)
2164 {
2165 struct intel_fbc *fbc = data;
2166
2167 *val = fbc->false_color;
2168
2169 return 0;
2170 }
2171
intel_fbc_debugfs_false_color_set(void * data,u64 val)2172 static int intel_fbc_debugfs_false_color_set(void *data, u64 val)
2173 {
2174 struct intel_fbc *fbc = data;
2175
2176 mutex_lock(&fbc->lock);
2177
2178 fbc->false_color = val;
2179
2180 if (fbc->active)
2181 fbc->funcs->set_false_color(fbc, fbc->false_color);
2182
2183 mutex_unlock(&fbc->lock);
2184
2185 return 0;
2186 }
2187
2188 DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops,
2189 intel_fbc_debugfs_false_color_get,
2190 intel_fbc_debugfs_false_color_set,
2191 "%llu\n");
2192
intel_fbc_debugfs_add(struct intel_fbc * fbc,struct dentry * parent)2193 static void intel_fbc_debugfs_add(struct intel_fbc *fbc,
2194 struct dentry *parent)
2195 {
2196 debugfs_create_file("i915_fbc_status", 0444, parent,
2197 fbc, &intel_fbc_debugfs_status_fops);
2198
2199 if (fbc->funcs->set_false_color)
2200 debugfs_create_file_unsafe("i915_fbc_false_color", 0644, parent,
2201 fbc, &intel_fbc_debugfs_false_color_fops);
2202 }
2203
intel_fbc_crtc_debugfs_add(struct intel_crtc * crtc)2204 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc)
2205 {
2206 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2207
2208 if (plane->fbc)
2209 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry);
2210 }
2211
2212 /* FIXME: remove this once igt is on board with per-crtc stuff */
intel_fbc_debugfs_register(struct intel_display * display)2213 void intel_fbc_debugfs_register(struct intel_display *display)
2214 {
2215 struct drm_minor *minor = display->drm->primary;
2216 struct intel_fbc *fbc;
2217
2218 fbc = display->fbc[INTEL_FBC_A];
2219 if (fbc)
2220 intel_fbc_debugfs_add(fbc, minor->debugfs_root);
2221 }
2222