1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2018 Intel Corporation
4 *
5 * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
6 * Manasi Navare <manasi.d.navare@intel.com>
7 */
8 #include <linux/limits.h>
9
10 #include <drm/display/drm_dsc_helper.h>
11 #include <drm/drm_fixed.h>
12 #include <drm/drm_print.h>
13
14 #include "intel_crtc.h"
15 #include "intel_de.h"
16 #include "intel_display_types.h"
17 #include "intel_display_utils.h"
18 #include "intel_dp.h"
19 #include "intel_dsi.h"
20 #include "intel_qp_tables.h"
21 #include "intel_vdsc.h"
22 #include "intel_vdsc_regs.h"
23
intel_dsc_source_support(const struct intel_crtc_state * crtc_state)24 bool intel_dsc_source_support(const struct intel_crtc_state *crtc_state)
25 {
26 struct intel_display *display = to_intel_display(crtc_state);
27 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
28
29 if (!HAS_DSC(display))
30 return false;
31
32 if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A)
33 return false;
34
35 return true;
36 }
37
intel_dsc_line_slice_count(const struct intel_dsc_slice_config * config)38 int intel_dsc_line_slice_count(const struct intel_dsc_slice_config *config)
39 {
40 return config->pipes_per_line * config->streams_per_pipe * config->slices_per_stream;
41 }
42
intel_dsc_get_slice_config(struct intel_display * display,int pipes_per_line,int slices_per_pipe,struct intel_dsc_slice_config * config)43 bool intel_dsc_get_slice_config(struct intel_display *display,
44 int pipes_per_line, int slices_per_pipe,
45 struct intel_dsc_slice_config *config)
46 {
47 int streams_per_pipe;
48
49 /* TODO: Add support for 8 slices per pipe on TGL+. */
50 switch (slices_per_pipe) {
51 case 3:
52 /*
53 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only
54 * with Ultrajoiner only for some platforms.
55 */
56 if (!HAS_DSC_3ENGINES(display) || pipes_per_line != 4)
57 return false;
58
59 streams_per_pipe = 3;
60 break;
61 case 4:
62 /* TODO: Consider using 1 DSC engine stream x 4 slices instead. */
63 case 2:
64 /* TODO: Consider using 1 DSC engine stream x 2 slices instead. */
65 streams_per_pipe = 2;
66 break;
67 case 1:
68 /*
69 * Bigjoiner needs small joiner to be enabled.
70 * So there should be at least 2 dsc slices per pipe,
71 * whenever bigjoiner is enabled.
72 */
73 if (pipes_per_line > 1)
74 return false;
75
76 streams_per_pipe = 1;
77 break;
78 default:
79 MISSING_CASE(slices_per_pipe);
80 return false;
81 }
82
83 config->pipes_per_line = pipes_per_line;
84 config->streams_per_pipe = streams_per_pipe;
85 config->slices_per_stream = slices_per_pipe / streams_per_pipe;
86
87 return true;
88 }
89
is_pipe_dsc(struct intel_crtc * crtc,enum transcoder cpu_transcoder)90 static bool is_pipe_dsc(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
91 {
92 struct intel_display *display = to_intel_display(crtc);
93
94 if (DISPLAY_VER(display) >= 12)
95 return true;
96
97 if (cpu_transcoder == TRANSCODER_EDP ||
98 cpu_transcoder == TRANSCODER_DSI_0 ||
99 cpu_transcoder == TRANSCODER_DSI_1)
100 return false;
101
102 /* There's no pipe A DSC engine on ICL */
103 drm_WARN_ON(display->drm, crtc->pipe == PIPE_A);
104
105 return true;
106 }
107
108 static void
intel_vdsc_set_min_max_qp(struct drm_dsc_config * vdsc_cfg,int buf,int bpp)109 intel_vdsc_set_min_max_qp(struct drm_dsc_config *vdsc_cfg, int buf,
110 int bpp)
111 {
112 int bpc = vdsc_cfg->bits_per_component;
113
114 /* Read range_minqp and range_max_qp from qp tables */
115 vdsc_cfg->rc_range_params[buf].range_min_qp =
116 intel_lookup_range_min_qp(bpc, buf, bpp, vdsc_cfg->native_420);
117 vdsc_cfg->rc_range_params[buf].range_max_qp =
118 intel_lookup_range_max_qp(bpc, buf, bpp, vdsc_cfg->native_420);
119 }
120
121 static int
get_range_bpg_offset(int bpp_low,int offset_low,int bpp_high,int offset_high,int bpp)122 get_range_bpg_offset(int bpp_low, int offset_low, int bpp_high, int offset_high, int bpp)
123 {
124 return offset_low + DIV_ROUND_UP((offset_high - offset_low) * (bpp - bpp_low),
125 (bpp_low - bpp_high));
126 }
127
128 /*
129 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
130 * Above method use a common formula to derive values for any combination of DSC
131 * variables. The formula approach may yield slight differences in the derived PPS
132 * parameters from the original parameter sets. These differences are not consequential
133 * to the coding performance because all parameter sets have been shown to produce
134 * visually lossless quality (provides the same PPS values as
135 * DSCParameterValuesVESA V1-2 spreadsheet).
136 */
137 static void
calculate_rc_params(struct drm_dsc_config * vdsc_cfg)138 calculate_rc_params(struct drm_dsc_config *vdsc_cfg)
139 {
140 int bpp = fxp_q4_to_int(vdsc_cfg->bits_per_pixel);
141 int bpc = vdsc_cfg->bits_per_component;
142 int qp_bpc_modifier = (bpc - 8) * 2;
143 int uncompressed_bpg_rate;
144 int first_line_bpg_offset;
145 u32 buf_i, bpp_i;
146
147 if (vdsc_cfg->slice_height >= 8)
148 first_line_bpg_offset =
149 12 + (9 * min(34, vdsc_cfg->slice_height - 8)) / 100;
150 else
151 first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
152
153 uncompressed_bpg_rate = (3 * bpc + (vdsc_cfg->convert_rgb ? 0 : 2)) * 3;
154 vdsc_cfg->first_line_bpg_offset = clamp(first_line_bpg_offset, 0,
155 uncompressed_bpg_rate - 3 * bpp);
156
157 /*
158 * According to DSC 1.2 spec in Section 4.1 if native_420 is set:
159 * -second_line_bpg_offset is 12 in general and equal to 2*(slice_height-1) if slice
160 * height < 8.
161 * -second_line_offset_adj is 512 as shown by empirical values to yield best chroma
162 * preservation in second line.
163 * -nsl_bpg_offset is calculated as second_line_offset/slice_height -1 then rounded
164 * up to 16 fractional bits, we left shift second line offset by 11 to preserve 11
165 * fractional bits.
166 */
167 if (vdsc_cfg->native_420) {
168 if (vdsc_cfg->slice_height >= 8)
169 vdsc_cfg->second_line_bpg_offset = 12;
170 else
171 vdsc_cfg->second_line_bpg_offset =
172 2 * (vdsc_cfg->slice_height - 1);
173
174 vdsc_cfg->second_line_offset_adj = 512;
175 vdsc_cfg->nsl_bpg_offset = DIV_ROUND_UP(vdsc_cfg->second_line_bpg_offset << 11,
176 vdsc_cfg->slice_height - 1);
177 }
178
179 if (bpp >= 12)
180 vdsc_cfg->initial_offset = 2048;
181 else if (bpp >= 10)
182 vdsc_cfg->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
183 else if (bpp >= 8)
184 vdsc_cfg->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
185 else
186 vdsc_cfg->initial_offset = 6144;
187
188 /* initial_xmit_delay = rc_model_size/2/compression_bpp */
189 vdsc_cfg->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
190
191 vdsc_cfg->flatness_min_qp = 3 + qp_bpc_modifier;
192 vdsc_cfg->flatness_max_qp = 12 + qp_bpc_modifier;
193
194 vdsc_cfg->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
195 vdsc_cfg->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
196
197 if (vdsc_cfg->native_420) {
198 static const s8 ofs_und4[] = {
199 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
200 };
201 static const s8 ofs_und5[] = {
202 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
203 };
204 static const s8 ofs_und6[] = {
205 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
206 };
207 static const s8 ofs_und8[] = {
208 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
209 };
210 /*
211 * For 420 format since bits_per_pixel (bpp) is set to target bpp * 2,
212 * QP table values for target bpp 4.0 to 4.4375 (rounded to 4.0) are
213 * actually for bpp 8 to 8.875 (rounded to 4.0 * 2 i.e 8).
214 * Similarly values for target bpp 4.5 to 4.8375 (rounded to 4.5)
215 * are for bpp 9 to 9.875 (rounded to 4.5 * 2 i.e 9), and so on.
216 */
217 bpp_i = bpp - 8;
218 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
219 u8 range_bpg_offset;
220
221 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
222
223 /* Calculate range_bpg_offset */
224 if (bpp <= 8)
225 range_bpg_offset = ofs_und4[buf_i];
226 else if (bpp <= 10)
227 range_bpg_offset = get_range_bpg_offset(8, ofs_und4[buf_i],
228 10, ofs_und5[buf_i], bpp);
229 else if (bpp <= 12)
230 range_bpg_offset = get_range_bpg_offset(10, ofs_und5[buf_i],
231 12, ofs_und6[buf_i], bpp);
232 else if (bpp <= 16)
233 range_bpg_offset = get_range_bpg_offset(12, ofs_und6[buf_i],
234 16, ofs_und8[buf_i], bpp);
235 else
236 range_bpg_offset = ofs_und8[buf_i];
237
238 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
239 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
240 }
241 } else {
242 /* fractional bpp part * 10000 (for precision up to 4 decimal places) */
243 int fractional_bits = fxp_q4_to_frac(vdsc_cfg->bits_per_pixel);
244
245 static const s8 ofs_und6[] = {
246 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
247 };
248 static const s8 ofs_und8[] = {
249 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
250 };
251 static const s8 ofs_und12[] = {
252 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
253 };
254 static const s8 ofs_und15[] = {
255 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12
256 };
257
258 /*
259 * QP table rows have values in increment of 0.5.
260 * So 6.0 bpp to 6.4375 will have index 0, 6.5 to 6.9375 will have index 1,
261 * and so on.
262 * 0.5 fractional part with 4 decimal precision becomes 5000
263 */
264 bpp_i = ((bpp - 6) + (fractional_bits < 5000 ? 0 : 1));
265
266 for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
267 u8 range_bpg_offset;
268
269 intel_vdsc_set_min_max_qp(vdsc_cfg, buf_i, bpp_i);
270
271 /* Calculate range_bpg_offset */
272 if (bpp <= 6)
273 range_bpg_offset = ofs_und6[buf_i];
274 else if (bpp <= 8)
275 range_bpg_offset = get_range_bpg_offset(6, ofs_und6[buf_i],
276 8, ofs_und8[buf_i], bpp);
277 else if (bpp <= 12)
278 range_bpg_offset = get_range_bpg_offset(8, ofs_und8[buf_i],
279 12, ofs_und12[buf_i], bpp);
280 else if (bpp <= 15)
281 range_bpg_offset = get_range_bpg_offset(12, ofs_und12[buf_i],
282 15, ofs_und15[buf_i], bpp);
283 else
284 range_bpg_offset = ofs_und15[buf_i];
285
286 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset =
287 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK;
288 }
289 }
290 }
291
intel_dsc_slice_dimensions_valid(struct intel_crtc_state * pipe_config,struct drm_dsc_config * vdsc_cfg)292 static int intel_dsc_slice_dimensions_valid(struct intel_crtc_state *pipe_config,
293 struct drm_dsc_config *vdsc_cfg)
294 {
295 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_RGB ||
296 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
297 if (vdsc_cfg->slice_height > 4095)
298 return -EINVAL;
299 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 15000)
300 return -EINVAL;
301 } else if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
302 if (vdsc_cfg->slice_width % 2)
303 return -EINVAL;
304 if (vdsc_cfg->slice_height % 2)
305 return -EINVAL;
306 if (vdsc_cfg->slice_height > 4094)
307 return -EINVAL;
308 if (vdsc_cfg->slice_height * vdsc_cfg->slice_width < 30000)
309 return -EINVAL;
310 }
311
312 return 0;
313 }
314
is_dsi_dsc_1_1(struct intel_crtc_state * crtc_state)315 static bool is_dsi_dsc_1_1(struct intel_crtc_state *crtc_state)
316 {
317 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
318
319 return vdsc_cfg->dsc_version_major == 1 &&
320 vdsc_cfg->dsc_version_minor == 1 &&
321 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI);
322 }
323
intel_dsc_compute_params(struct intel_crtc_state * pipe_config)324 int intel_dsc_compute_params(struct intel_crtc_state *pipe_config)
325 {
326 struct intel_display *display = to_intel_display(pipe_config);
327 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
328 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16);
329 int err;
330 int ret;
331
332 vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
333 vdsc_cfg->slice_width =
334 DIV_ROUND_UP(vdsc_cfg->pic_width,
335 intel_dsc_line_slice_count(&pipe_config->dsc.slice_config));
336
337 err = intel_dsc_slice_dimensions_valid(pipe_config, vdsc_cfg);
338
339 if (err) {
340 drm_dbg_kms(display->drm, "Slice dimension requirements not met\n");
341 return err;
342 }
343
344 /*
345 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0
346 * else 1
347 */
348 vdsc_cfg->convert_rgb = pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 &&
349 pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR444;
350
351 if (DISPLAY_VER(display) >= 14 &&
352 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
353 vdsc_cfg->native_420 = true;
354 /* We do not support YcBCr422 as of now */
355 vdsc_cfg->native_422 = false;
356 vdsc_cfg->simple_422 = false;
357 /* Gen 11 does not support VBR */
358 vdsc_cfg->vbr_enable = false;
359
360 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16;
361
362 /*
363 * According to DSC 1.2 specs in Section 4.1 if native_420 is set
364 * we need to double the current bpp.
365 */
366 if (vdsc_cfg->native_420)
367 vdsc_cfg->bits_per_pixel <<= 1;
368
369 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3;
370
371 if (vdsc_cfg->bits_per_component < 8) {
372 drm_dbg_kms(display->drm, "DSC bpc requirements not met bpc: %d\n",
373 vdsc_cfg->bits_per_component);
374 return -EINVAL;
375 }
376
377 drm_dsc_set_rc_buf_thresh(vdsc_cfg);
378
379 /*
380 * From XE_LPD onwards we supports compression bpps in steps of 1
381 * upto uncompressed bpp-1, hence add calculations for all the rc
382 * parameters
383 *
384 * We don't want to calculate all rc parameters when the panel
385 * is MIPI DSI and it's using DSC 1.1. The reason being that some
386 * DSI panels vendors have hardcoded PPS params in the VBT causing
387 * the parameters sent from the source which are derived through
388 * interpolation to differ from the params the panel expects.
389 * This causes a noise in the display.
390 * Furthermore for DSI panels we are currently using bits_per_pixel
391 * (compressed bpp) hardcoded from VBT, (unlike other encoders where we
392 * find the optimum compressed bpp) so dont need to rely on interpolation,
393 * as we can get the required rc parameters from the tables.
394 */
395 if (DISPLAY_VER(display) >= 13 && !is_dsi_dsc_1_1(pipe_config)) {
396 calculate_rc_params(vdsc_cfg);
397 } else {
398 if ((compressed_bpp == 8 ||
399 compressed_bpp == 12) &&
400 (vdsc_cfg->bits_per_component == 8 ||
401 vdsc_cfg->bits_per_component == 10 ||
402 vdsc_cfg->bits_per_component == 12))
403 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_1_PRE_SCR);
404 else
405 ret = drm_dsc_setup_rc_params(vdsc_cfg, DRM_DSC_1_2_444);
406
407 if (ret)
408 return ret;
409 }
410
411 /*
412 * BitsPerComponent value determines mux_word_size:
413 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
414 * 48 bits otherwise 64
415 */
416 if (vdsc_cfg->bits_per_component <= 10)
417 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
418 else
419 vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
420
421 /* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
422 vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
423 (vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
424
425 return 0;
426 }
427
intel_dsc_enable_on_crtc(struct intel_crtc_state * crtc_state)428 void intel_dsc_enable_on_crtc(struct intel_crtc_state *crtc_state)
429 {
430 crtc_state->dsc.compression_enabled_on_link = true;
431 crtc_state->dsc.compression_enable = true;
432 }
433
intel_dsc_enabled_on_link(const struct intel_crtc_state * crtc_state)434 bool intel_dsc_enabled_on_link(const struct intel_crtc_state *crtc_state)
435 {
436 struct intel_display *display = to_intel_display(crtc_state);
437
438 drm_WARN_ON(display->drm, crtc_state->dsc.compression_enable &&
439 !crtc_state->dsc.compression_enabled_on_link);
440
441 return crtc_state->dsc.compression_enabled_on_link;
442 }
443
444 enum intel_display_power_domain
intel_dsc_power_domain(struct intel_crtc * crtc,enum transcoder cpu_transcoder)445 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
446 {
447 struct intel_display *display = to_intel_display(crtc);
448 enum pipe pipe = crtc->pipe;
449
450 /*
451 * VDSC/joining uses a separate power well, PW2, and requires
452 * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases:
453 *
454 * - ICL eDP/DSI transcoder
455 * - Display version 12 (except RKL) pipe A
456 *
457 * For any other pipe, VDSC/joining uses the power well associated with
458 * the pipe in use. Hence another reference on the pipe power domain
459 * will suffice. (Except no VDSC/joining on ICL pipe A.)
460 */
461 if (DISPLAY_VER(display) == 12 && !display->platform.rocketlake &&
462 pipe == PIPE_A)
463 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
464 else if (is_pipe_dsc(crtc, cpu_transcoder))
465 return POWER_DOMAIN_PIPE(pipe);
466 else
467 return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
468 }
469
intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state * crtc_state)470 static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
471 {
472 return crtc_state->dsc.slice_config.streams_per_pipe;
473 }
474
intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state * crtc_state)475 int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
476 {
477 int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state);
478 int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
479
480 num_vdsc_instances *= num_joined_pipes;
481
482 return num_vdsc_instances;
483 }
484
intel_dsc_get_pps_reg(const struct intel_crtc_state * crtc_state,int pps,i915_reg_t * dsc_reg,int dsc_reg_num)485 static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
486 i915_reg_t *dsc_reg, int dsc_reg_num)
487 {
488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
489 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
490 enum pipe pipe = crtc->pipe;
491 bool pipe_dsc;
492
493 pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
494
495 if (dsc_reg_num >= 4)
496 MISSING_CASE(dsc_reg_num);
497 if (dsc_reg_num >= 3)
498 dsc_reg[2] = BMG_DSC2_PPS(pipe, pps);
499 if (dsc_reg_num >= 2)
500 dsc_reg[1] = pipe_dsc ? ICL_DSC1_PPS(pipe, pps) : DSCC_PPS(pps);
501 if (dsc_reg_num >= 1)
502 dsc_reg[0] = pipe_dsc ? ICL_DSC0_PPS(pipe, pps) : DSCA_PPS(pps);
503 }
504
intel_dsc_pps_write(const struct intel_crtc_state * crtc_state,int pps,u32 pps_val)505 static void intel_dsc_pps_write(const struct intel_crtc_state *crtc_state,
506 int pps, u32 pps_val)
507 {
508 struct intel_display *display = to_intel_display(crtc_state);
509 i915_reg_t dsc_reg[3];
510 int i, vdsc_per_pipe, dsc_reg_num;
511
512 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
513 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
514
515 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
516
517 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
518
519 for (i = 0; i < dsc_reg_num; i++)
520 intel_de_write(display, dsc_reg[i], pps_val);
521 }
522
intel_dsc_pps_configure(const struct intel_crtc_state * crtc_state)523 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
524 {
525 struct intel_display *display = to_intel_display(crtc_state);
526 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
527 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
528 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
529 enum pipe pipe = crtc->pipe;
530 u32 pps_val;
531 u32 rc_buf_thresh_dword[4];
532 u32 rc_range_params_dword[8];
533 int i = 0;
534 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
535 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
536
537 /* PPS 0 */
538 pps_val = DSC_PPS0_VER_MAJOR(1) |
539 DSC_PPS0_VER_MINOR(vdsc_cfg->dsc_version_minor) |
540 DSC_PPS0_BPC(vdsc_cfg->bits_per_component) |
541 DSC_PPS0_LINE_BUF_DEPTH(vdsc_cfg->line_buf_depth);
542 if (vdsc_cfg->dsc_version_minor == 2) {
543 pps_val |= DSC_PPS0_ALT_ICH_SEL;
544 if (vdsc_cfg->native_420)
545 pps_val |= DSC_PPS0_NATIVE_420_ENABLE;
546 if (vdsc_cfg->native_422)
547 pps_val |= DSC_PPS0_NATIVE_422_ENABLE;
548 }
549 if (vdsc_cfg->block_pred_enable)
550 pps_val |= DSC_PPS0_BLOCK_PREDICTION;
551 if (vdsc_cfg->convert_rgb)
552 pps_val |= DSC_PPS0_COLOR_SPACE_CONVERSION;
553 if (vdsc_cfg->simple_422)
554 pps_val |= DSC_PPS0_422_ENABLE;
555 if (vdsc_cfg->vbr_enable)
556 pps_val |= DSC_PPS0_VBR_ENABLE;
557 intel_dsc_pps_write(crtc_state, 0, pps_val);
558
559 /* PPS 1 */
560 pps_val = DSC_PPS1_BPP(vdsc_cfg->bits_per_pixel);
561 intel_dsc_pps_write(crtc_state, 1, pps_val);
562
563 /* PPS 2 */
564 pps_val = DSC_PPS2_PIC_HEIGHT(vdsc_cfg->pic_height) |
565 DSC_PPS2_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
566 intel_dsc_pps_write(crtc_state, 2, pps_val);
567
568 /* PPS 3 */
569 pps_val = DSC_PPS3_SLICE_HEIGHT(vdsc_cfg->slice_height) |
570 DSC_PPS3_SLICE_WIDTH(vdsc_cfg->slice_width);
571 intel_dsc_pps_write(crtc_state, 3, pps_val);
572
573 /* PPS 4 */
574 pps_val = DSC_PPS4_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
575 DSC_PPS4_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
576 intel_dsc_pps_write(crtc_state, 4, pps_val);
577
578 /* PPS 5 */
579 pps_val = DSC_PPS5_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
580 DSC_PPS5_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
581 intel_dsc_pps_write(crtc_state, 5, pps_val);
582
583 /* PPS 6 */
584 pps_val = DSC_PPS6_INITIAL_SCALE_VALUE(vdsc_cfg->initial_scale_value) |
585 DSC_PPS6_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) |
586 DSC_PPS6_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
587 DSC_PPS6_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
588 intel_dsc_pps_write(crtc_state, 6, pps_val);
589
590 /* PPS 7 */
591 pps_val = DSC_PPS7_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
592 DSC_PPS7_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
593 intel_dsc_pps_write(crtc_state, 7, pps_val);
594
595 /* PPS 8 */
596 pps_val = DSC_PPS8_FINAL_OFFSET(vdsc_cfg->final_offset) |
597 DSC_PPS8_INITIAL_OFFSET(vdsc_cfg->initial_offset);
598 intel_dsc_pps_write(crtc_state, 8, pps_val);
599
600 /* PPS 9 */
601 pps_val = DSC_PPS9_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
602 DSC_PPS9_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
603 intel_dsc_pps_write(crtc_state, 9, pps_val);
604
605 /* PPS 10 */
606 pps_val = DSC_PPS10_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
607 DSC_PPS10_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
608 DSC_PPS10_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
609 DSC_PPS10_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
610 intel_dsc_pps_write(crtc_state, 10, pps_val);
611
612 /* PPS 16 */
613 pps_val = DSC_PPS16_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) |
614 DSC_PPS16_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
615 vdsc_cfg->slice_width) |
616 DSC_PPS16_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
617 vdsc_cfg->slice_height);
618 intel_dsc_pps_write(crtc_state, 16, pps_val);
619
620 if (DISPLAY_VER(display) >= 14) {
621 /* PPS 17 */
622 pps_val = DSC_PPS17_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
623 intel_dsc_pps_write(crtc_state, 17, pps_val);
624
625 /* PPS 18 */
626 pps_val = DSC_PPS18_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
627 DSC_PPS18_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
628 intel_dsc_pps_write(crtc_state, 18, pps_val);
629 }
630
631 /* Populate the RC_BUF_THRESH registers */
632 memset(rc_buf_thresh_dword, 0, sizeof(rc_buf_thresh_dword));
633 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
634 rc_buf_thresh_dword[i / 4] |=
635 (u32)(vdsc_cfg->rc_buf_thresh[i] <<
636 BITS_PER_BYTE * (i % 4));
637 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
638 intel_de_write(display, DSCA_RC_BUF_THRESH_0,
639 rc_buf_thresh_dword[0]);
640 intel_de_write(display, DSCA_RC_BUF_THRESH_0_UDW,
641 rc_buf_thresh_dword[1]);
642 intel_de_write(display, DSCA_RC_BUF_THRESH_1,
643 rc_buf_thresh_dword[2]);
644 intel_de_write(display, DSCA_RC_BUF_THRESH_1_UDW,
645 rc_buf_thresh_dword[3]);
646 if (vdsc_instances_per_pipe > 1) {
647 intel_de_write(display, DSCC_RC_BUF_THRESH_0,
648 rc_buf_thresh_dword[0]);
649 intel_de_write(display, DSCC_RC_BUF_THRESH_0_UDW,
650 rc_buf_thresh_dword[1]);
651 intel_de_write(display, DSCC_RC_BUF_THRESH_1,
652 rc_buf_thresh_dword[2]);
653 intel_de_write(display, DSCC_RC_BUF_THRESH_1_UDW,
654 rc_buf_thresh_dword[3]);
655 }
656 } else {
657 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0(pipe),
658 rc_buf_thresh_dword[0]);
659 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe),
660 rc_buf_thresh_dword[1]);
661 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1(pipe),
662 rc_buf_thresh_dword[2]);
663 intel_de_write(display, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe),
664 rc_buf_thresh_dword[3]);
665 if (vdsc_instances_per_pipe > 1) {
666 intel_de_write(display,
667 ICL_DSC1_RC_BUF_THRESH_0(pipe),
668 rc_buf_thresh_dword[0]);
669 intel_de_write(display,
670 ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe),
671 rc_buf_thresh_dword[1]);
672 intel_de_write(display,
673 ICL_DSC1_RC_BUF_THRESH_1(pipe),
674 rc_buf_thresh_dword[2]);
675 intel_de_write(display,
676 ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe),
677 rc_buf_thresh_dword[3]);
678 }
679 }
680
681 /* Populate the RC_RANGE_PARAMETERS registers */
682 memset(rc_range_params_dword, 0, sizeof(rc_range_params_dword));
683 for (i = 0; i < DSC_NUM_BUF_RANGES; i++)
684 rc_range_params_dword[i / 2] |=
685 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
686 RC_BPG_OFFSET_SHIFT) |
687 (vdsc_cfg->rc_range_params[i].range_max_qp <<
688 RC_MAX_QP_SHIFT) |
689 (vdsc_cfg->rc_range_params[i].range_min_qp <<
690 RC_MIN_QP_SHIFT)) << 16 * (i % 2));
691 if (!is_pipe_dsc(crtc, cpu_transcoder)) {
692 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0,
693 rc_range_params_dword[0]);
694 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_0_UDW,
695 rc_range_params_dword[1]);
696 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1,
697 rc_range_params_dword[2]);
698 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_1_UDW,
699 rc_range_params_dword[3]);
700 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2,
701 rc_range_params_dword[4]);
702 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_2_UDW,
703 rc_range_params_dword[5]);
704 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3,
705 rc_range_params_dword[6]);
706 intel_de_write(display, DSCA_RC_RANGE_PARAMETERS_3_UDW,
707 rc_range_params_dword[7]);
708 if (vdsc_instances_per_pipe > 1) {
709 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_0,
710 rc_range_params_dword[0]);
711 intel_de_write(display,
712 DSCC_RC_RANGE_PARAMETERS_0_UDW,
713 rc_range_params_dword[1]);
714 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_1,
715 rc_range_params_dword[2]);
716 intel_de_write(display,
717 DSCC_RC_RANGE_PARAMETERS_1_UDW,
718 rc_range_params_dword[3]);
719 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_2,
720 rc_range_params_dword[4]);
721 intel_de_write(display,
722 DSCC_RC_RANGE_PARAMETERS_2_UDW,
723 rc_range_params_dword[5]);
724 intel_de_write(display, DSCC_RC_RANGE_PARAMETERS_3,
725 rc_range_params_dword[6]);
726 intel_de_write(display,
727 DSCC_RC_RANGE_PARAMETERS_3_UDW,
728 rc_range_params_dword[7]);
729 }
730 } else {
731 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe),
732 rc_range_params_dword[0]);
733 intel_de_write(display,
734 ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe),
735 rc_range_params_dword[1]);
736 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe),
737 rc_range_params_dword[2]);
738 intel_de_write(display,
739 ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe),
740 rc_range_params_dword[3]);
741 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe),
742 rc_range_params_dword[4]);
743 intel_de_write(display,
744 ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe),
745 rc_range_params_dword[5]);
746 intel_de_write(display, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe),
747 rc_range_params_dword[6]);
748 intel_de_write(display,
749 ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe),
750 rc_range_params_dword[7]);
751 if (vdsc_instances_per_pipe > 1) {
752 intel_de_write(display,
753 ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe),
754 rc_range_params_dword[0]);
755 intel_de_write(display,
756 ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe),
757 rc_range_params_dword[1]);
758 intel_de_write(display,
759 ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe),
760 rc_range_params_dword[2]);
761 intel_de_write(display,
762 ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe),
763 rc_range_params_dword[3]);
764 intel_de_write(display,
765 ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe),
766 rc_range_params_dword[4]);
767 intel_de_write(display,
768 ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe),
769 rc_range_params_dword[5]);
770 intel_de_write(display,
771 ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe),
772 rc_range_params_dword[6]);
773 intel_de_write(display,
774 ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe),
775 rc_range_params_dword[7]);
776 }
777 }
778 }
779
intel_dsc_dsi_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)780 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
781 const struct intel_crtc_state *crtc_state)
782 {
783 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
784 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
785 struct mipi_dsi_device *dsi;
786 struct drm_dsc_picture_parameter_set pps;
787 enum port port;
788
789 if (!crtc_state->dsc.compression_enable)
790 return;
791
792 drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
793
794 for_each_dsi_port(port, intel_dsi->ports) {
795 dsi = intel_dsi->dsi_hosts[port]->device;
796
797 mipi_dsi_picture_parameter_set(dsi, &pps);
798 mipi_dsi_compression_mode(dsi, true);
799 }
800 }
801
intel_dsc_dp_pps_write(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)802 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
803 const struct intel_crtc_state *crtc_state)
804 {
805 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
806 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
807 struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
808
809 if (!crtc_state->dsc.compression_enable)
810 return;
811
812 /* Prepare DP SDP PPS header as per DP 1.4 spec, Table 2-123 */
813 drm_dsc_dp_pps_header_init(&dp_dsc_pps_sdp.pps_header);
814
815 /* Fill the PPS payload bytes as per DSC spec 1.2 Table 4-1 */
816 drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
817
818 dig_port->write_infoframe(encoder, crtc_state,
819 DP_SDP_PPS, &dp_dsc_pps_sdp,
820 sizeof(dp_dsc_pps_sdp));
821 }
822
intel_dsc_su_et_parameters_configure(struct intel_dsb * dsb,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int su_lines)823 void intel_dsc_su_et_parameters_configure(struct intel_dsb *dsb, struct intel_encoder *encoder,
824 const struct intel_crtc_state *crtc_state, int su_lines)
825 {
826 struct intel_display *display = to_intel_display(crtc_state);
827 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
828 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
829 enum pipe pipe = crtc->pipe;
830 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
831 int slice_row_per_frame = su_lines / vdsc_cfg->slice_height;
832 u32 val;
833
834 drm_WARN_ON_ONCE(display->drm, su_lines % vdsc_cfg->slice_height);
835 drm_WARN_ON_ONCE(display->drm, vdsc_instances_per_pipe > 2);
836
837 val = DSC_SUPS0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame);
838 val |= DSC_SUPS0_SU_PIC_HEIGHT(su_lines);
839
840 intel_de_write_dsb(display, dsb, LNL_DSC0_SU_PARAMETER_SET_0(pipe), val);
841
842 if (vdsc_instances_per_pipe == 2)
843 intel_de_write_dsb(display, dsb, LNL_DSC1_SU_PARAMETER_SET_0(pipe), val);
844 }
845
dss_ctl1_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)846 static i915_reg_t dss_ctl1_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
847 {
848 return is_pipe_dsc(crtc, cpu_transcoder) ?
849 ICL_PIPE_DSS_CTL1(crtc->pipe) : DSS_CTL1;
850 }
851
dss_ctl2_reg(struct intel_crtc * crtc,enum transcoder cpu_transcoder)852 static i915_reg_t dss_ctl2_reg(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
853 {
854 return is_pipe_dsc(crtc, cpu_transcoder) ?
855 ICL_PIPE_DSS_CTL2(crtc->pipe) : DSS_CTL2;
856 }
857
intel_uncompressed_joiner_enable(const struct intel_crtc_state * crtc_state)858 void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
859 {
860 struct intel_display *display = to_intel_display(crtc_state);
861 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
862 u32 dss_ctl1_val = 0;
863
864 if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) {
865 if (intel_crtc_is_bigjoiner_secondary(crtc_state))
866 dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY;
867 else
868 dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY;
869
870 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder),
871 dss_ctl1_val);
872 }
873 }
874
intel_dsc_enable(const struct intel_crtc_state * crtc_state)875 void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
876 {
877 struct intel_display *display = to_intel_display(crtc_state);
878 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
879 u32 dss_ctl1_val = 0;
880 u32 dss_ctl2_val = 0;
881 int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
882
883 if (!crtc_state->dsc.compression_enable)
884 return;
885
886 intel_dsc_pps_configure(crtc_state);
887
888 dss_ctl2_val |= VDSC0_ENABLE;
889 if (vdsc_instances_per_pipe > 1) {
890 dss_ctl2_val |= VDSC1_ENABLE;
891 dss_ctl1_val |= JOINER_ENABLE;
892 }
893
894 if (vdsc_instances_per_pipe > 2) {
895 dss_ctl2_val |= VDSC2_ENABLE;
896 dss_ctl2_val |= SMALL_JOINER_CONFIG_3_ENGINES;
897 }
898
899 if (crtc_state->joiner_pipes) {
900 if (intel_crtc_ultrajoiner_enable_needed(crtc_state))
901 dss_ctl1_val |= ULTRA_JOINER_ENABLE;
902
903 if (intel_crtc_is_ultrajoiner_primary(crtc_state))
904 dss_ctl1_val |= PRIMARY_ULTRA_JOINER_ENABLE;
905
906 dss_ctl1_val |= BIG_JOINER_ENABLE;
907
908 if (intel_crtc_is_bigjoiner_primary(crtc_state))
909 dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
910 }
911 intel_de_write(display, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val);
912 intel_de_write(display, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val);
913 }
914
intel_dsc_disable(const struct intel_crtc_state * old_crtc_state)915 void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
916 {
917 struct intel_display *display = to_intel_display(old_crtc_state);
918 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
919
920 /* Disable only if either of them is enabled */
921 if (old_crtc_state->dsc.compression_enable ||
922 old_crtc_state->joiner_pipes) {
923 intel_de_write(display, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0);
924 intel_de_write(display, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0);
925 }
926 }
927
intel_dsc_pps_read(struct intel_crtc_state * crtc_state,int pps,bool * all_equal)928 static u32 intel_dsc_pps_read(struct intel_crtc_state *crtc_state, int pps,
929 bool *all_equal)
930 {
931 struct intel_display *display = to_intel_display(crtc_state);
932 i915_reg_t dsc_reg[3];
933 int i, vdsc_per_pipe, dsc_reg_num;
934 u32 val;
935
936 vdsc_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state);
937 dsc_reg_num = min_t(int, ARRAY_SIZE(dsc_reg), vdsc_per_pipe);
938
939 drm_WARN_ON_ONCE(display->drm, dsc_reg_num < vdsc_per_pipe);
940
941 intel_dsc_get_pps_reg(crtc_state, pps, dsc_reg, dsc_reg_num);
942
943 *all_equal = true;
944
945 val = intel_de_read(display, dsc_reg[0]);
946
947 for (i = 1; i < dsc_reg_num; i++) {
948 if (intel_de_read(display, dsc_reg[i]) != val) {
949 *all_equal = false;
950 break;
951 }
952 }
953
954 return val;
955 }
956
intel_dsc_pps_read_and_verify(struct intel_crtc_state * crtc_state,int pps)957 static u32 intel_dsc_pps_read_and_verify(struct intel_crtc_state *crtc_state, int pps)
958 {
959 struct intel_display *display = to_intel_display(crtc_state);
960 u32 val;
961 bool all_equal;
962
963 val = intel_dsc_pps_read(crtc_state, pps, &all_equal);
964 drm_WARN_ON(display->drm, !all_equal);
965
966 return val;
967 }
968
intel_dsc_get_pps_config(struct intel_crtc_state * crtc_state)969 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
970 {
971 struct intel_display *display = to_intel_display(crtc_state);
972 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
973 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
974 u32 pps_temp;
975
976 /* PPS 0 */
977 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 0);
978
979 vdsc_cfg->bits_per_component = REG_FIELD_GET(DSC_PPS0_BPC_MASK, pps_temp);
980 vdsc_cfg->line_buf_depth = REG_FIELD_GET(DSC_PPS0_LINE_BUF_DEPTH_MASK, pps_temp);
981 vdsc_cfg->block_pred_enable = pps_temp & DSC_PPS0_BLOCK_PREDICTION;
982 vdsc_cfg->convert_rgb = pps_temp & DSC_PPS0_COLOR_SPACE_CONVERSION;
983 vdsc_cfg->simple_422 = pps_temp & DSC_PPS0_422_ENABLE;
984 vdsc_cfg->native_422 = pps_temp & DSC_PPS0_NATIVE_422_ENABLE;
985 vdsc_cfg->native_420 = pps_temp & DSC_PPS0_NATIVE_420_ENABLE;
986 vdsc_cfg->vbr_enable = pps_temp & DSC_PPS0_VBR_ENABLE;
987
988 /* PPS 1 */
989 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 1);
990
991 vdsc_cfg->bits_per_pixel = REG_FIELD_GET(DSC_PPS1_BPP_MASK, pps_temp);
992
993 if (vdsc_cfg->native_420)
994 vdsc_cfg->bits_per_pixel >>= 1;
995
996 crtc_state->dsc.compressed_bpp_x16 = vdsc_cfg->bits_per_pixel;
997
998 /* PPS 2 */
999 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 2);
1000
1001 vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PPS2_PIC_WIDTH_MASK, pps_temp) * num_vdsc_instances;
1002 vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PPS2_PIC_HEIGHT_MASK, pps_temp);
1003
1004 /* PPS 3 */
1005 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 3);
1006
1007 vdsc_cfg->slice_width = REG_FIELD_GET(DSC_PPS3_SLICE_WIDTH_MASK, pps_temp);
1008 vdsc_cfg->slice_height = REG_FIELD_GET(DSC_PPS3_SLICE_HEIGHT_MASK, pps_temp);
1009
1010 /* PPS 4 */
1011 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 4);
1012
1013 vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_DEC_DELAY_MASK, pps_temp);
1014 vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_PPS4_INITIAL_XMIT_DELAY_MASK, pps_temp);
1015
1016 /* PPS 5 */
1017 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 5);
1018
1019 vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_PPS5_SCALE_DEC_INT_MASK, pps_temp);
1020 vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_PPS5_SCALE_INC_INT_MASK, pps_temp);
1021
1022 /* PPS 6 */
1023 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 6);
1024
1025 vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_PPS6_INITIAL_SCALE_VALUE_MASK, pps_temp);
1026 vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_PPS6_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
1027 vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MIN_QP_MASK, pps_temp);
1028 vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_PPS6_FLATNESS_MAX_QP_MASK, pps_temp);
1029
1030 /* PPS 7 */
1031 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 7);
1032
1033 vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_PPS7_NFL_BPG_OFFSET_MASK, pps_temp);
1034 vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_PPS7_SLICE_BPG_OFFSET_MASK, pps_temp);
1035
1036 /* PPS 8 */
1037 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 8);
1038
1039 vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_PPS8_INITIAL_OFFSET_MASK, pps_temp);
1040 vdsc_cfg->final_offset = REG_FIELD_GET(DSC_PPS8_FINAL_OFFSET_MASK, pps_temp);
1041
1042 /* PPS 9 */
1043 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 9);
1044
1045 vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_PPS9_RC_MODEL_SIZE_MASK, pps_temp);
1046
1047 /* PPS 10 */
1048 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 10);
1049
1050 vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
1051 vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_PPS10_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
1052
1053 /* PPS 16 */
1054 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 16);
1055
1056 vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_PPS16_SLICE_CHUNK_SIZE_MASK, pps_temp);
1057
1058 if (DISPLAY_VER(display) >= 14) {
1059 /* PPS 17 */
1060 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 17);
1061
1062 vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_PPS17_SL_BPG_OFFSET_MASK, pps_temp);
1063
1064 /* PPS 18 */
1065 pps_temp = intel_dsc_pps_read_and_verify(crtc_state, 18);
1066
1067 vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_PPS18_NSL_BPG_OFFSET_MASK, pps_temp);
1068 vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_PPS18_SL_OFFSET_ADJ_MASK, pps_temp);
1069 }
1070 }
1071
intel_dsc_get_config(struct intel_crtc_state * crtc_state)1072 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
1073 {
1074 struct intel_display *display = to_intel_display(crtc_state);
1075 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1076 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1077 enum intel_display_power_domain power_domain;
1078 struct ref_tracker *wakeref;
1079 u32 dss_ctl1, dss_ctl2;
1080
1081 if (!intel_dsc_source_support(crtc_state))
1082 return;
1083
1084 power_domain = intel_dsc_power_domain(crtc, cpu_transcoder);
1085
1086 wakeref = intel_display_power_get_if_enabled(display, power_domain);
1087 if (!wakeref)
1088 return;
1089
1090 dss_ctl1 = intel_de_read(display, dss_ctl1_reg(crtc, cpu_transcoder));
1091 dss_ctl2 = intel_de_read(display, dss_ctl2_reg(crtc, cpu_transcoder));
1092
1093 crtc_state->dsc.compression_enable = dss_ctl2 & VDSC0_ENABLE;
1094 if (!crtc_state->dsc.compression_enable)
1095 goto out;
1096
1097 /* TODO: Read out slice_config.pipes_per_line/slices_per_stream as well */
1098 if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & (VDSC2_ENABLE | SMALL_JOINER_CONFIG_3_ENGINES))
1099 crtc_state->dsc.slice_config.streams_per_pipe = 3;
1100 else if (dss_ctl1 & JOINER_ENABLE && dss_ctl2 & VDSC1_ENABLE)
1101 crtc_state->dsc.slice_config.streams_per_pipe = 2;
1102 else
1103 crtc_state->dsc.slice_config.streams_per_pipe = 1;
1104
1105 intel_dsc_get_pps_config(crtc_state);
1106 out:
1107 intel_display_power_put(display, power_domain, wakeref);
1108 }
1109
intel_vdsc_dump_state(struct drm_printer * p,int indent,const struct intel_crtc_state * crtc_state)1110 static void intel_vdsc_dump_state(struct drm_printer *p, int indent,
1111 const struct intel_crtc_state *crtc_state)
1112 {
1113 drm_printf_indent(p, indent,
1114 "dsc-dss: compressed-bpp:" FXP_Q4_FMT ", slice-count: %d, num_streams: %d\n",
1115 FXP_Q4_ARGS(crtc_state->dsc.compressed_bpp_x16),
1116 intel_dsc_line_slice_count(&crtc_state->dsc.slice_config),
1117 crtc_state->dsc.slice_config.streams_per_pipe);
1118 }
1119
intel_vdsc_state_dump(struct drm_printer * p,int indent,const struct intel_crtc_state * crtc_state)1120 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
1121 const struct intel_crtc_state *crtc_state)
1122 {
1123 if (!crtc_state->dsc.compression_enable)
1124 return;
1125
1126 intel_vdsc_dump_state(p, indent, crtc_state);
1127 drm_dsc_dump_config(p, indent, &crtc_state->dsc.config);
1128 }
1129
intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display * display,int pixel_rate,int htotal,int dsc_horizontal_slices)1130 int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
1131 int pixel_rate, int htotal,
1132 int dsc_horizontal_slices)
1133 {
1134 int dsc_slice_bubbles;
1135 u64 num;
1136
1137 if (drm_WARN_ON(display->drm, !htotal))
1138 return pixel_rate;
1139
1140 dsc_slice_bubbles = 14 * dsc_horizontal_slices;
1141 num = mul_u32_u32(pixel_rate, (htotal + dsc_slice_bubbles));
1142
1143 return DIV_ROUND_UP_ULL(num, htotal);
1144 }
1145
intel_vdsc_min_cdclk(const struct intel_crtc_state * crtc_state)1146 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
1147 {
1148 struct intel_display *display = to_intel_display(crtc_state);
1149 int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
1150 int htotal = crtc_state->hw.adjusted_mode.crtc_htotal;
1151 int dsc_slices = intel_dsc_line_slice_count(&crtc_state->dsc.slice_config);
1152 int pixel_rate;
1153 int min_cdclk;
1154
1155 if (!crtc_state->dsc.compression_enable)
1156 return 0;
1157
1158 pixel_rate = intel_dsc_get_pixel_rate_with_dsc_bubbles(display,
1159 crtc_state->pixel_rate,
1160 htotal,
1161 dsc_slices);
1162
1163 /*
1164 * When we decide to use only one VDSC engine, since
1165 * each VDSC operates with 1 ppc throughput, pixel clock
1166 * cannot be higher than the VDSC clock (cdclk)
1167 * If there 2 VDSC engines, then pixel clock can't be higher than
1168 * VDSC clock(cdclk) * 2 and so on.
1169 */
1170 min_cdclk = DIV_ROUND_UP(pixel_rate, num_vdsc_instances);
1171
1172 if (crtc_state->joiner_pipes) {
1173 int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock);
1174
1175 /*
1176 * According to Bigjoiner bw check:
1177 * compressed_bpp <= PPC * CDCLK * Big joiner Interface bits / Pixel clock
1178 *
1179 * We have already computed compressed_bpp, so now compute the min CDCLK that
1180 * is required to support this compressed_bpp.
1181 *
1182 * => CDCLK >= compressed_bpp * Pixel clock / (PPC * Bigjoiner Interface bits)
1183 *
1184 * Since PPC = 2 with bigjoiner
1185 * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits
1186 */
1187 int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24;
1188 int adjusted_pixel_rate =
1189 intel_dsc_get_pixel_rate_with_dsc_bubbles(display, pixel_clock,
1190 htotal, dsc_slices);
1191 int min_cdclk_bj = (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) *
1192 adjusted_pixel_rate) / (2 * bigjoiner_interface_bits);
1193
1194 min_cdclk = max(min_cdclk, min_cdclk_bj);
1195 }
1196
1197 return min_cdclk;
1198 }
1199
intel_vdsc_prefill_lines(const struct intel_crtc_state * crtc_state)1200 unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state)
1201 {
1202 if (!crtc_state->dsc.compression_enable)
1203 return 0;
1204
1205 return 0x18000; /* 1.5 */
1206 }
1207