1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/export.h>
29 #include <linux/i2c.h>
30 #include <linux/notifier.h>
31 #include <linux/seq_buf.h>
32 #include <linux/slab.h>
33 #include <linux/sort.h>
34 #include <linux/string_helpers.h>
35 #include <linux/timekeeping.h>
36 #include <linux/types.h>
37
38 #include <asm/byteorder.h>
39
40 #include <drm/display/drm_dp_helper.h>
41 #include <drm/display/drm_dp_tunnel.h>
42 #include <drm/display/drm_dsc_helper.h>
43 #include <drm/display/drm_hdmi_helper.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_crtc.h>
46 #include <drm/drm_edid.h>
47 #include <drm/drm_fixed.h>
48 #include <drm/drm_probe_helper.h>
49
50 #include "g4x_dp.h"
51 #include "i915_drv.h"
52 #include "i915_irq.h"
53 #include "i915_reg.h"
54 #include "intel_alpm.h"
55 #include "intel_atomic.h"
56 #include "intel_audio.h"
57 #include "intel_backlight.h"
58 #include "intel_combo_phy_regs.h"
59 #include "intel_connector.h"
60 #include "intel_crtc.h"
61 #include "intel_cx0_phy.h"
62 #include "intel_ddi.h"
63 #include "intel_de.h"
64 #include "intel_display_driver.h"
65 #include "intel_display_types.h"
66 #include "intel_dp.h"
67 #include "intel_dp_aux.h"
68 #include "intel_dp_hdcp.h"
69 #include "intel_dp_link_training.h"
70 #include "intel_dp_mst.h"
71 #include "intel_dp_test.h"
72 #include "intel_dp_tunnel.h"
73 #include "intel_dpio_phy.h"
74 #include "intel_dpll.h"
75 #include "intel_drrs.h"
76 #include "intel_encoder.h"
77 #include "intel_fifo_underrun.h"
78 #include "intel_hdcp.h"
79 #include "intel_hdmi.h"
80 #include "intel_hotplug.h"
81 #include "intel_hotplug_irq.h"
82 #include "intel_lspcon.h"
83 #include "intel_lvds.h"
84 #include "intel_modeset_lock.h"
85 #include "intel_panel.h"
86 #include "intel_pch_display.h"
87 #include "intel_pfit.h"
88 #include "intel_pps.h"
89 #include "intel_psr.h"
90 #include "intel_runtime_pm.h"
91 #include "intel_quirks.h"
92 #include "intel_tc.h"
93 #include "intel_vdsc.h"
94 #include "intel_vrr.h"
95 #include "intel_crtc_state_dump.h"
96
97 /* DP DSC throughput values used for slice count calculations KPixels/s */
98 #define DP_DSC_PEAK_PIXEL_RATE 2720000
99 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000
100 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000
101
102 /* Max DSC line buffer depth supported by HW. */
103 #define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
104
105 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
106 #define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
107
108 /* Constants for DP DSC configurations */
109 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
110
111 /*
112 * With Single pipe configuration, HW is capable of supporting maximum of:
113 * 2 slices per line for ICL, BMG
114 * 4 slices per line for other platforms.
115 * For now consider a max of 2 slices per line, which works for all platforms.
116 * With this we can have max of 4 DSC Slices per pipe.
117 *
118 * For higher resolutions where 12 slice support is required with
119 * ultrajoiner, only then each pipe can support 3 slices.
120 *
121 * #TODO Split this better to use 4 slices/dsc engine where supported.
122 */
123 static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};
124
125 /**
126 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
127 * @intel_dp: DP struct
128 *
129 * If a CPU or PCH DP output is attached to an eDP panel, this function
130 * will return true, and false otherwise.
131 *
132 * This function is not safe to use prior to encoder type being set.
133 */
intel_dp_is_edp(struct intel_dp * intel_dp)134 bool intel_dp_is_edp(struct intel_dp *intel_dp)
135 {
136 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
137
138 return dig_port->base.type == INTEL_OUTPUT_EDP;
139 }
140
141 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
142
143 /* Is link rate UHBR and thus 128b/132b? */
intel_dp_is_uhbr(const struct intel_crtc_state * crtc_state)144 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
145 {
146 return drm_dp_is_uhbr_rate(crtc_state->port_clock);
147 }
148
149 /**
150 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
151 * @rate: link rate in 10kbit/s units
152 *
153 * Returns the link symbol size in bits/symbol units depending on the link
154 * rate -> channel coding.
155 */
intel_dp_link_symbol_size(int rate)156 int intel_dp_link_symbol_size(int rate)
157 {
158 return drm_dp_is_uhbr_rate(rate) ? 32 : 10;
159 }
160
161 /**
162 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
163 * @rate: link rate in 10kbit/s units
164 *
165 * Returns the link symbol clock frequency in kHz units depending on the
166 * link rate and channel coding.
167 */
intel_dp_link_symbol_clock(int rate)168 int intel_dp_link_symbol_clock(int rate)
169 {
170 return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
171 }
172
max_dprx_rate(struct intel_dp * intel_dp)173 static int max_dprx_rate(struct intel_dp *intel_dp)
174 {
175 struct intel_display *display = to_intel_display(intel_dp);
176 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
177 int max_rate;
178
179 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
180 max_rate = drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);
181 else
182 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
183
184 /*
185 * Some broken eDP sinks illegally declare support for
186 * HBR3 without TPS4, and are unable to produce a stable
187 * output. Reject HBR3 when TPS4 is not available.
188 */
189 if (max_rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
190 drm_dbg_kms(display->drm,
191 "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
192 encoder->base.base.id, encoder->base.name);
193 max_rate = 540000;
194 }
195
196 return max_rate;
197 }
198
max_dprx_lane_count(struct intel_dp * intel_dp)199 static int max_dprx_lane_count(struct intel_dp *intel_dp)
200 {
201 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
202 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);
203
204 return drm_dp_max_lane_count(intel_dp->dpcd);
205 }
206
intel_dp_set_default_sink_rates(struct intel_dp * intel_dp)207 static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
208 {
209 intel_dp->sink_rates[0] = 162000;
210 intel_dp->num_sink_rates = 1;
211 }
212
213 /* update sink rates from dpcd */
intel_dp_set_dpcd_sink_rates(struct intel_dp * intel_dp)214 static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
215 {
216 static const int dp_rates[] = {
217 162000, 270000, 540000, 810000
218 };
219 int i, max_rate;
220 int max_lttpr_rate;
221
222 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
223 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
224 static const int quirk_rates[] = { 162000, 270000, 324000 };
225
226 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
227 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
228
229 return;
230 }
231
232 /*
233 * Sink rates for 8b/10b.
234 */
235 max_rate = max_dprx_rate(intel_dp);
236 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
237 if (max_lttpr_rate)
238 max_rate = min(max_rate, max_lttpr_rate);
239
240 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
241 if (dp_rates[i] > max_rate)
242 break;
243 intel_dp->sink_rates[i] = dp_rates[i];
244 }
245
246 /*
247 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
248 * rates and 10 Gbps.
249 */
250 if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
251 u8 uhbr_rates = 0;
252
253 BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
254
255 drm_dp_dpcd_readb(&intel_dp->aux,
256 DP_128B132B_SUPPORTED_LINK_RATES, &uhbr_rates);
257
258 if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {
259 /* We have a repeater */
260 if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
261 intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
262 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
263 DP_PHY_REPEATER_128B132B_SUPPORTED) {
264 /* Repeater supports 128b/132b, valid UHBR rates */
265 uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
266 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
267 } else {
268 /* Does not support 128b/132b */
269 uhbr_rates = 0;
270 }
271 }
272
273 if (uhbr_rates & DP_UHBR10)
274 intel_dp->sink_rates[i++] = 1000000;
275 if (uhbr_rates & DP_UHBR13_5)
276 intel_dp->sink_rates[i++] = 1350000;
277 if (uhbr_rates & DP_UHBR20)
278 intel_dp->sink_rates[i++] = 2000000;
279 }
280
281 intel_dp->num_sink_rates = i;
282 }
283
intel_dp_set_sink_rates(struct intel_dp * intel_dp)284 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
285 {
286 struct intel_display *display = to_intel_display(intel_dp);
287 struct intel_connector *connector = intel_dp->attached_connector;
288 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
289 struct intel_encoder *encoder = &intel_dig_port->base;
290
291 intel_dp_set_dpcd_sink_rates(intel_dp);
292
293 if (intel_dp->num_sink_rates)
294 return;
295
296 drm_err(display->drm,
297 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
298 connector->base.base.id, connector->base.name,
299 encoder->base.base.id, encoder->base.name);
300
301 intel_dp_set_default_sink_rates(intel_dp);
302 }
303
intel_dp_set_default_max_sink_lane_count(struct intel_dp * intel_dp)304 static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
305 {
306 intel_dp->max_sink_lane_count = 1;
307 }
308
intel_dp_set_max_sink_lane_count(struct intel_dp * intel_dp)309 static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
310 {
311 struct intel_display *display = to_intel_display(intel_dp);
312 struct intel_connector *connector = intel_dp->attached_connector;
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315
316 intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
317
318 switch (intel_dp->max_sink_lane_count) {
319 case 1:
320 case 2:
321 case 4:
322 return;
323 }
324
325 drm_err(display->drm,
326 "[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
327 connector->base.base.id, connector->base.name,
328 encoder->base.base.id, encoder->base.name,
329 intel_dp->max_sink_lane_count);
330
331 intel_dp_set_default_max_sink_lane_count(intel_dp);
332 }
333
334 /* Get length of rates array potentially limited by max_rate. */
intel_dp_rate_limit_len(const int * rates,int len,int max_rate)335 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
336 {
337 int i;
338
339 /* Limit results by potentially reduced max rate */
340 for (i = 0; i < len; i++) {
341 if (rates[len - i - 1] <= max_rate)
342 return len - i;
343 }
344
345 return 0;
346 }
347
348 /* Get length of common rates array potentially limited by max_rate. */
intel_dp_common_len_rate_limit(const struct intel_dp * intel_dp,int max_rate)349 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
350 int max_rate)
351 {
352 return intel_dp_rate_limit_len(intel_dp->common_rates,
353 intel_dp->num_common_rates, max_rate);
354 }
355
intel_dp_common_rate(struct intel_dp * intel_dp,int index)356 int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
357 {
358 struct intel_display *display = to_intel_display(intel_dp);
359
360 if (drm_WARN_ON(display->drm,
361 index < 0 || index >= intel_dp->num_common_rates))
362 return 162000;
363
364 return intel_dp->common_rates[index];
365 }
366
367 /* Theoretical max between source and sink */
intel_dp_max_common_rate(struct intel_dp * intel_dp)368 int intel_dp_max_common_rate(struct intel_dp *intel_dp)
369 {
370 return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
371 }
372
intel_dp_max_source_lane_count(struct intel_digital_port * dig_port)373 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
374 {
375 int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);
376 int max_lanes = dig_port->max_lanes;
377
378 if (vbt_max_lanes)
379 max_lanes = min(max_lanes, vbt_max_lanes);
380
381 return max_lanes;
382 }
383
384 /* Theoretical max between source and sink */
intel_dp_max_common_lane_count(struct intel_dp * intel_dp)385 int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
386 {
387 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
388 int source_max = intel_dp_max_source_lane_count(dig_port);
389 int sink_max = intel_dp->max_sink_lane_count;
390 int lane_max = intel_tc_port_max_lane_count(dig_port);
391 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
392
393 if (lttpr_max)
394 sink_max = min(sink_max, lttpr_max);
395
396 return min3(source_max, sink_max, lane_max);
397 }
398
forced_lane_count(struct intel_dp * intel_dp)399 static int forced_lane_count(struct intel_dp *intel_dp)
400 {
401 return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));
402 }
403
intel_dp_max_lane_count(struct intel_dp * intel_dp)404 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
405 {
406 int lane_count;
407
408 if (intel_dp->link.force_lane_count)
409 lane_count = forced_lane_count(intel_dp);
410 else
411 lane_count = intel_dp->link.max_lane_count;
412
413 switch (lane_count) {
414 case 1:
415 case 2:
416 case 4:
417 return lane_count;
418 default:
419 MISSING_CASE(lane_count);
420 return 1;
421 }
422 }
423
intel_dp_min_lane_count(struct intel_dp * intel_dp)424 static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
425 {
426 if (intel_dp->link.force_lane_count)
427 return forced_lane_count(intel_dp);
428
429 return 1;
430 }
431
432 /*
433 * The required data bandwidth for a mode with given pixel clock and bpp. This
434 * is the required net bandwidth independent of the data bandwidth efficiency.
435 *
436 * TODO: check if callers of this functions should use
437 * intel_dp_effective_data_rate() instead.
438 */
439 int
intel_dp_link_required(int pixel_clock,int bpp)440 intel_dp_link_required(int pixel_clock, int bpp)
441 {
442 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
443 return DIV_ROUND_UP(pixel_clock * bpp, 8);
444 }
445
446 /**
447 * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
448 * @pixel_clock: pixel clock in kHz
449 * @bpp_x16: bits per pixel .4 fixed point format
450 * @bw_overhead: BW allocation overhead in 1ppm units
451 *
452 * Return the effective pixel data rate in kB/sec units taking into account
453 * the provided SSC, FEC, DSC BW allocation overhead.
454 */
intel_dp_effective_data_rate(int pixel_clock,int bpp_x16,int bw_overhead)455 int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
456 int bw_overhead)
457 {
458 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
459 1000000 * 16 * 8);
460 }
461
462 /**
463 * intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
464 * @intel_dp: Intel DP object
465 * @max_dprx_rate: Maximum data rate of the DPRX
466 * @max_dprx_lanes: Maximum lane count of the DPRX
467 *
468 * Calculate the maximum data rate for the provided link parameters taking into
469 * account any BW limitations by a DP tunnel attached to @intel_dp.
470 *
471 * Returns the maximum data rate in kBps units.
472 */
intel_dp_max_link_data_rate(struct intel_dp * intel_dp,int max_dprx_rate,int max_dprx_lanes)473 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
474 int max_dprx_rate, int max_dprx_lanes)
475 {
476 int max_rate = drm_dp_max_dprx_data_rate(max_dprx_rate, max_dprx_lanes);
477
478 if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
479 max_rate = min(max_rate,
480 drm_dp_tunnel_available_bw(intel_dp->tunnel));
481
482 return max_rate;
483 }
484
intel_dp_has_joiner(struct intel_dp * intel_dp)485 bool intel_dp_has_joiner(struct intel_dp *intel_dp)
486 {
487 struct intel_display *display = to_intel_display(intel_dp);
488 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
489 struct intel_encoder *encoder = &intel_dig_port->base;
490
491 /* eDP MSO is not compatible with joiner */
492 if (intel_dp->mso_link_count)
493 return false;
494
495 return DISPLAY_VER(display) >= 12 ||
496 (DISPLAY_VER(display) == 11 &&
497 encoder->port != PORT_A);
498 }
499
dg2_max_source_rate(struct intel_dp * intel_dp)500 static int dg2_max_source_rate(struct intel_dp *intel_dp)
501 {
502 return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
503 }
504
icl_max_source_rate(struct intel_dp * intel_dp)505 static int icl_max_source_rate(struct intel_dp *intel_dp)
506 {
507 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
508
509 if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
510 return 540000;
511
512 return 810000;
513 }
514
ehl_max_source_rate(struct intel_dp * intel_dp)515 static int ehl_max_source_rate(struct intel_dp *intel_dp)
516 {
517 if (intel_dp_is_edp(intel_dp))
518 return 540000;
519
520 return 810000;
521 }
522
mtl_max_source_rate(struct intel_dp * intel_dp)523 static int mtl_max_source_rate(struct intel_dp *intel_dp)
524 {
525 struct intel_display *display = to_intel_display(intel_dp);
526 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
527
528 if (intel_encoder_is_c10phy(encoder))
529 return 810000;
530
531 if (DISPLAY_VERx100(display) == 1401)
532 return 1350000;
533
534 return 2000000;
535 }
536
vbt_max_link_rate(struct intel_dp * intel_dp)537 static int vbt_max_link_rate(struct intel_dp *intel_dp)
538 {
539 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
540 int max_rate;
541
542 max_rate = intel_bios_dp_max_link_rate(encoder->devdata);
543
544 if (intel_dp_is_edp(intel_dp)) {
545 struct intel_connector *connector = intel_dp->attached_connector;
546 int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
547
548 if (max_rate && edp_max_rate)
549 max_rate = min(max_rate, edp_max_rate);
550 else if (edp_max_rate)
551 max_rate = edp_max_rate;
552 }
553
554 return max_rate;
555 }
556
557 static void
intel_dp_set_source_rates(struct intel_dp * intel_dp)558 intel_dp_set_source_rates(struct intel_dp *intel_dp)
559 {
560 /* The values must be in increasing order */
561 static const int bmg_rates[] = {
562 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
563 810000, 1000000, 1350000,
564 };
565 static const int mtl_rates[] = {
566 162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
567 810000, 1000000, 2000000,
568 };
569 static const int icl_rates[] = {
570 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
571 1000000, 1350000,
572 };
573 static const int bxt_rates[] = {
574 162000, 216000, 243000, 270000, 324000, 432000, 540000
575 };
576 static const int skl_rates[] = {
577 162000, 216000, 270000, 324000, 432000, 540000
578 };
579 static const int hsw_rates[] = {
580 162000, 270000, 540000
581 };
582 static const int g4x_rates[] = {
583 162000, 270000
584 };
585 struct intel_display *display = to_intel_display(intel_dp);
586 const int *source_rates;
587 int size, max_rate = 0, vbt_max_rate;
588
589 /* This should only be done once */
590 drm_WARN_ON(display->drm,
591 intel_dp->source_rates || intel_dp->num_source_rates);
592
593 if (DISPLAY_VER(display) >= 14) {
594 if (display->platform.battlemage) {
595 source_rates = bmg_rates;
596 size = ARRAY_SIZE(bmg_rates);
597 } else {
598 source_rates = mtl_rates;
599 size = ARRAY_SIZE(mtl_rates);
600 }
601 max_rate = mtl_max_source_rate(intel_dp);
602 } else if (DISPLAY_VER(display) >= 11) {
603 source_rates = icl_rates;
604 size = ARRAY_SIZE(icl_rates);
605 if (display->platform.dg2)
606 max_rate = dg2_max_source_rate(intel_dp);
607 else if (display->platform.alderlake_p || display->platform.alderlake_s ||
608 display->platform.dg1 || display->platform.rocketlake)
609 max_rate = 810000;
610 else if (display->platform.jasperlake || display->platform.elkhartlake)
611 max_rate = ehl_max_source_rate(intel_dp);
612 else
613 max_rate = icl_max_source_rate(intel_dp);
614 } else if (display->platform.geminilake || display->platform.broxton) {
615 source_rates = bxt_rates;
616 size = ARRAY_SIZE(bxt_rates);
617 } else if (DISPLAY_VER(display) == 9) {
618 source_rates = skl_rates;
619 size = ARRAY_SIZE(skl_rates);
620 } else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
621 display->platform.broadwell) {
622 source_rates = hsw_rates;
623 size = ARRAY_SIZE(hsw_rates);
624 } else {
625 source_rates = g4x_rates;
626 size = ARRAY_SIZE(g4x_rates);
627 }
628
629 vbt_max_rate = vbt_max_link_rate(intel_dp);
630 if (max_rate && vbt_max_rate)
631 max_rate = min(max_rate, vbt_max_rate);
632 else if (vbt_max_rate)
633 max_rate = vbt_max_rate;
634
635 if (max_rate)
636 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
637
638 intel_dp->source_rates = source_rates;
639 intel_dp->num_source_rates = size;
640 }
641
intersect_rates(const int * source_rates,int source_len,const int * sink_rates,int sink_len,int * common_rates)642 static int intersect_rates(const int *source_rates, int source_len,
643 const int *sink_rates, int sink_len,
644 int *common_rates)
645 {
646 int i = 0, j = 0, k = 0;
647
648 while (i < source_len && j < sink_len) {
649 if (source_rates[i] == sink_rates[j]) {
650 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
651 return k;
652 common_rates[k] = source_rates[i];
653 ++k;
654 ++i;
655 ++j;
656 } else if (source_rates[i] < sink_rates[j]) {
657 ++i;
658 } else {
659 ++j;
660 }
661 }
662 return k;
663 }
664
665 /* return index of rate in rates array, or -1 if not found */
intel_dp_rate_index(const int * rates,int len,int rate)666 int intel_dp_rate_index(const int *rates, int len, int rate)
667 {
668 int i;
669
670 for (i = 0; i < len; i++)
671 if (rate == rates[i])
672 return i;
673
674 return -1;
675 }
676
intel_dp_link_config_rate(struct intel_dp * intel_dp,const struct intel_dp_link_config * lc)677 static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
678 const struct intel_dp_link_config *lc)
679 {
680 return intel_dp_common_rate(intel_dp, lc->link_rate_idx);
681 }
682
intel_dp_link_config_lane_count(const struct intel_dp_link_config * lc)683 static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
684 {
685 return 1 << lc->lane_count_exp;
686 }
687
intel_dp_link_config_bw(struct intel_dp * intel_dp,const struct intel_dp_link_config * lc)688 static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
689 const struct intel_dp_link_config *lc)
690 {
691 return drm_dp_max_dprx_data_rate(intel_dp_link_config_rate(intel_dp, lc),
692 intel_dp_link_config_lane_count(lc));
693 }
694
link_config_cmp_by_bw(const void * a,const void * b,const void * p)695 static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
696 {
697 struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */
698 const struct intel_dp_link_config *lc_a = a;
699 const struct intel_dp_link_config *lc_b = b;
700 int bw_a = intel_dp_link_config_bw(intel_dp, lc_a);
701 int bw_b = intel_dp_link_config_bw(intel_dp, lc_b);
702
703 if (bw_a != bw_b)
704 return bw_a - bw_b;
705
706 return intel_dp_link_config_rate(intel_dp, lc_a) -
707 intel_dp_link_config_rate(intel_dp, lc_b);
708 }
709
intel_dp_link_config_init(struct intel_dp * intel_dp)710 static void intel_dp_link_config_init(struct intel_dp *intel_dp)
711 {
712 struct intel_display *display = to_intel_display(intel_dp);
713 struct intel_dp_link_config *lc;
714 int num_common_lane_configs;
715 int i;
716 int j;
717
718 if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
719 return;
720
721 num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
722
723 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
724 ARRAY_SIZE(intel_dp->link.configs)))
725 return;
726
727 intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
728
729 lc = &intel_dp->link.configs[0];
730 for (i = 0; i < intel_dp->num_common_rates; i++) {
731 for (j = 0; j < num_common_lane_configs; j++) {
732 lc->lane_count_exp = j;
733 lc->link_rate_idx = i;
734
735 lc++;
736 }
737 }
738
739 sort_r(intel_dp->link.configs, intel_dp->link.num_configs,
740 sizeof(intel_dp->link.configs[0]),
741 link_config_cmp_by_bw, NULL,
742 intel_dp);
743 }
744
intel_dp_link_config_get(struct intel_dp * intel_dp,int idx,int * link_rate,int * lane_count)745 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
746 {
747 struct intel_display *display = to_intel_display(intel_dp);
748 const struct intel_dp_link_config *lc;
749
750 if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
751 idx = 0;
752
753 lc = &intel_dp->link.configs[idx];
754
755 *link_rate = intel_dp_link_config_rate(intel_dp, lc);
756 *lane_count = intel_dp_link_config_lane_count(lc);
757 }
758
intel_dp_link_config_index(struct intel_dp * intel_dp,int link_rate,int lane_count)759 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
760 {
761 int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,
762 link_rate);
763 int lane_count_exp = ilog2(lane_count);
764 int i;
765
766 for (i = 0; i < intel_dp->link.num_configs; i++) {
767 const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
768
769 if (lc->lane_count_exp == lane_count_exp &&
770 lc->link_rate_idx == link_rate_idx)
771 return i;
772 }
773
774 return -1;
775 }
776
intel_dp_set_common_rates(struct intel_dp * intel_dp)777 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
778 {
779 struct intel_display *display = to_intel_display(intel_dp);
780
781 drm_WARN_ON(display->drm,
782 !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
783
784 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
785 intel_dp->num_source_rates,
786 intel_dp->sink_rates,
787 intel_dp->num_sink_rates,
788 intel_dp->common_rates);
789
790 /* Paranoia, there should always be something in common. */
791 if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
792 intel_dp->common_rates[0] = 162000;
793 intel_dp->num_common_rates = 1;
794 }
795
796 intel_dp_link_config_init(intel_dp);
797 }
798
intel_dp_link_params_valid(struct intel_dp * intel_dp,int link_rate,u8 lane_count)799 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
800 u8 lane_count)
801 {
802 /*
803 * FIXME: we need to synchronize the current link parameters with
804 * hardware readout. Currently fast link training doesn't work on
805 * boot-up.
806 */
807 if (link_rate == 0 ||
808 link_rate > intel_dp->link.max_rate)
809 return false;
810
811 if (lane_count == 0 ||
812 lane_count > intel_dp_max_lane_count(intel_dp))
813 return false;
814
815 return true;
816 }
817
intel_dp_mode_to_fec_clock(u32 mode_clock)818 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
819 {
820 return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
821 1000000U);
822 }
823
intel_dp_bw_fec_overhead(bool fec_enabled)824 int intel_dp_bw_fec_overhead(bool fec_enabled)
825 {
826 /*
827 * TODO: Calculate the actual overhead for a given mode.
828 * The hard-coded 1/0.972261=2.853% overhead factor
829 * corresponds (for instance) to the 8b/10b DP FEC 2.4% +
830 * 0.453% DSC overhead. This is enough for a 3840 width mode,
831 * which has a DSC overhead of up to ~0.2%, but may not be
832 * enough for a 1024 width mode where this is ~0.8% (on a 4
833 * lane DP link, with 2 DSC slices and 8 bpp color depth).
834 */
835 return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
836 }
837
838 static int
small_joiner_ram_size_bits(struct intel_display * display)839 small_joiner_ram_size_bits(struct intel_display *display)
840 {
841 if (DISPLAY_VER(display) >= 13)
842 return 17280 * 8;
843 else if (DISPLAY_VER(display) >= 11)
844 return 7680 * 8;
845 else
846 return 6144 * 8;
847 }
848
intel_dp_dsc_nearest_valid_bpp(struct intel_display * display,u32 bpp,u32 pipe_bpp)849 u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
850 {
851 u32 bits_per_pixel = bpp;
852 int i;
853
854 /* Error out if the max bpp is less than smallest allowed valid bpp */
855 if (bits_per_pixel < valid_dsc_bpp[0]) {
856 drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",
857 bits_per_pixel, valid_dsc_bpp[0]);
858 return 0;
859 }
860
861 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
862 if (DISPLAY_VER(display) >= 13) {
863 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
864
865 /*
866 * According to BSpec, 27 is the max DSC output bpp,
867 * 8 is the min DSC output bpp.
868 * While we can still clamp higher bpp values to 27, saving bandwidth,
869 * if it is required to oompress up to bpp < 8, means we can't do
870 * that and probably means we can't fit the required mode, even with
871 * DSC enabled.
872 */
873 if (bits_per_pixel < 8) {
874 drm_dbg_kms(display->drm,
875 "Unsupported BPP %u, min 8\n",
876 bits_per_pixel);
877 return 0;
878 }
879 bits_per_pixel = min_t(u32, bits_per_pixel, 27);
880 } else {
881 /* Find the nearest match in the array of known BPPs from VESA */
882 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
883 if (bits_per_pixel < valid_dsc_bpp[i + 1])
884 break;
885 }
886 drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",
887 bits_per_pixel, valid_dsc_bpp[i]);
888
889 bits_per_pixel = valid_dsc_bpp[i];
890 }
891
892 return bits_per_pixel;
893 }
894
bigjoiner_interface_bits(struct intel_display * display)895 static int bigjoiner_interface_bits(struct intel_display *display)
896 {
897 return DISPLAY_VER(display) >= 14 ? 36 : 24;
898 }
899
bigjoiner_bw_max_bpp(struct intel_display * display,u32 mode_clock,int num_joined_pipes)900 static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
901 int num_joined_pipes)
902 {
903 u32 max_bpp;
904 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
905 int ppc = 2;
906 int num_big_joiners = num_joined_pipes / 2;
907
908 max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
909 intel_dp_mode_to_fec_clock(mode_clock);
910
911 max_bpp *= num_big_joiners;
912
913 return max_bpp;
914
915 }
916
small_joiner_ram_max_bpp(struct intel_display * display,u32 mode_hdisplay,int num_joined_pipes)917 static u32 small_joiner_ram_max_bpp(struct intel_display *display,
918 u32 mode_hdisplay,
919 int num_joined_pipes)
920 {
921 u32 max_bpp;
922
923 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
924 max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
925
926 max_bpp *= num_joined_pipes;
927
928 return max_bpp;
929 }
930
ultrajoiner_ram_bits(void)931 static int ultrajoiner_ram_bits(void)
932 {
933 return 4 * 72 * 512;
934 }
935
ultrajoiner_ram_max_bpp(u32 mode_hdisplay)936 static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)
937 {
938 return ultrajoiner_ram_bits() / mode_hdisplay;
939 }
940
941 static
get_max_compressed_bpp_with_joiner(struct intel_display * display,u32 mode_clock,u32 mode_hdisplay,int num_joined_pipes)942 u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
943 u32 mode_clock, u32 mode_hdisplay,
944 int num_joined_pipes)
945 {
946 u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
947
948 if (num_joined_pipes > 1)
949 max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
950 num_joined_pipes));
951 if (num_joined_pipes == 4)
952 max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay));
953
954 return max_bpp;
955 }
956
intel_dp_dsc_get_max_compressed_bpp(struct intel_display * display,u32 link_clock,u32 lane_count,u32 mode_clock,u32 mode_hdisplay,int num_joined_pipes,enum intel_output_format output_format,u32 pipe_bpp,u32 timeslots)957 u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
958 u32 link_clock, u32 lane_count,
959 u32 mode_clock, u32 mode_hdisplay,
960 int num_joined_pipes,
961 enum intel_output_format output_format,
962 u32 pipe_bpp,
963 u32 timeslots)
964 {
965 u32 bits_per_pixel, joiner_max_bpp;
966
967 /*
968 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
969 * (LinkSymbolClock)* 8 * (TimeSlots / 64)
970 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
971 * for MST -> TimeSlots has to be calculated, based on mode requirements
972 *
973 * Due to FEC overhead, the available bw is reduced to 97.2261%.
974 * To support the given mode:
975 * Bandwidth required should be <= Available link Bandwidth * FEC Overhead
976 * =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
977 * =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
978 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
979 * (ModeClock / FEC Overhead)
980 * =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
981 * (ModeClock / FEC Overhead * 8)
982 */
983 bits_per_pixel = ((link_clock * lane_count) * timeslots) /
984 (intel_dp_mode_to_fec_clock(mode_clock) * 8);
985
986 /* Bandwidth required for 420 is half, that of 444 format */
987 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
988 bits_per_pixel *= 2;
989
990 /*
991 * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
992 * supported PPS value can be 63.9375 and with the further
993 * mention that for 420, 422 formats, bpp should be programmed double
994 * the target bpp restricting our target bpp to be 31.9375 at max.
995 */
996 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
997 bits_per_pixel = min_t(u32, bits_per_pixel, 31);
998
999 drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "
1000 "total bw %u pixel clock %u\n",
1001 bits_per_pixel, timeslots,
1002 (link_clock * lane_count * 8),
1003 intel_dp_mode_to_fec_clock(mode_clock));
1004
1005 joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,
1006 mode_hdisplay, num_joined_pipes);
1007 bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
1008
1009 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bits_per_pixel, pipe_bpp);
1010
1011 return bits_per_pixel;
1012 }
1013
intel_dp_dsc_get_slice_count(const struct intel_connector * connector,int mode_clock,int mode_hdisplay,int num_joined_pipes)1014 u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
1015 int mode_clock, int mode_hdisplay,
1016 int num_joined_pipes)
1017 {
1018 struct intel_display *display = to_intel_display(connector);
1019 u8 min_slice_count, i;
1020 int max_slice_width;
1021
1022 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
1023 min_slice_count = DIV_ROUND_UP(mode_clock,
1024 DP_DSC_MAX_ENC_THROUGHPUT_0);
1025 else
1026 min_slice_count = DIV_ROUND_UP(mode_clock,
1027 DP_DSC_MAX_ENC_THROUGHPUT_1);
1028
1029 /*
1030 * Due to some DSC engine BW limitations, we need to enable second
1031 * slice and VDSC engine, whenever we approach close enough to max CDCLK
1032 */
1033 if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
1034 min_slice_count = max_t(u8, min_slice_count, 2);
1035
1036 max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);
1037 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1038 drm_dbg_kms(display->drm,
1039 "Unsupported slice width %d by DP DSC Sink device\n",
1040 max_slice_width);
1041 return 0;
1042 }
1043 /* Also take into account max slice width */
1044 min_slice_count = max_t(u8, min_slice_count,
1045 DIV_ROUND_UP(mode_hdisplay,
1046 max_slice_width));
1047
1048 /* Find the closest match to the valid slice count values */
1049 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
1050 u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
1051
1052 /*
1053 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only
1054 * with Ultrajoiner only for some platforms.
1055 */
1056 if (valid_dsc_slicecount[i] == 3 &&
1057 (!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4))
1058 continue;
1059
1060 if (test_slice_count >
1061 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))
1062 break;
1063
1064 /*
1065 * Bigjoiner needs small joiner to be enabled.
1066 * So there should be at least 2 dsc slices per pipe,
1067 * whenever bigjoiner is enabled.
1068 */
1069 if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
1070 continue;
1071
1072 if (mode_hdisplay % test_slice_count)
1073 continue;
1074
1075 if (min_slice_count <= test_slice_count)
1076 return test_slice_count;
1077 }
1078
1079 drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",
1080 min_slice_count);
1081 return 0;
1082 }
1083
source_can_output(struct intel_dp * intel_dp,enum intel_output_format format)1084 static bool source_can_output(struct intel_dp *intel_dp,
1085 enum intel_output_format format)
1086 {
1087 struct intel_display *display = to_intel_display(intel_dp);
1088
1089 switch (format) {
1090 case INTEL_OUTPUT_FORMAT_RGB:
1091 return true;
1092
1093 case INTEL_OUTPUT_FORMAT_YCBCR444:
1094 /*
1095 * No YCbCr output support on gmch platforms.
1096 * Also, ILK doesn't seem capable of DP YCbCr output.
1097 * The displayed image is severely corrupted. SNB+ is fine.
1098 */
1099 return !HAS_GMCH(display) && !display->platform.ironlake;
1100
1101 case INTEL_OUTPUT_FORMAT_YCBCR420:
1102 /* Platform < Gen 11 cannot output YCbCr420 format */
1103 return DISPLAY_VER(display) >= 11;
1104
1105 default:
1106 MISSING_CASE(format);
1107 return false;
1108 }
1109 }
1110
1111 static bool
dfp_can_convert_from_rgb(struct intel_dp * intel_dp,enum intel_output_format sink_format)1112 dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
1113 enum intel_output_format sink_format)
1114 {
1115 if (!drm_dp_is_branch(intel_dp->dpcd))
1116 return false;
1117
1118 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1119 return intel_dp->dfp.rgb_to_ycbcr;
1120
1121 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1122 return intel_dp->dfp.rgb_to_ycbcr &&
1123 intel_dp->dfp.ycbcr_444_to_420;
1124
1125 return false;
1126 }
1127
1128 static bool
dfp_can_convert_from_ycbcr444(struct intel_dp * intel_dp,enum intel_output_format sink_format)1129 dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
1130 enum intel_output_format sink_format)
1131 {
1132 if (!drm_dp_is_branch(intel_dp->dpcd))
1133 return false;
1134
1135 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1136 return intel_dp->dfp.ycbcr_444_to_420;
1137
1138 return false;
1139 }
1140
1141 static bool
dfp_can_convert(struct intel_dp * intel_dp,enum intel_output_format output_format,enum intel_output_format sink_format)1142 dfp_can_convert(struct intel_dp *intel_dp,
1143 enum intel_output_format output_format,
1144 enum intel_output_format sink_format)
1145 {
1146 switch (output_format) {
1147 case INTEL_OUTPUT_FORMAT_RGB:
1148 return dfp_can_convert_from_rgb(intel_dp, sink_format);
1149 case INTEL_OUTPUT_FORMAT_YCBCR444:
1150 return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1151 default:
1152 MISSING_CASE(output_format);
1153 return false;
1154 }
1155
1156 return false;
1157 }
1158
1159 static enum intel_output_format
intel_dp_output_format(struct intel_connector * connector,enum intel_output_format sink_format)1160 intel_dp_output_format(struct intel_connector *connector,
1161 enum intel_output_format sink_format)
1162 {
1163 struct intel_display *display = to_intel_display(connector);
1164 struct intel_dp *intel_dp = intel_attached_dp(connector);
1165 enum intel_output_format force_dsc_output_format =
1166 intel_dp->force_dsc_output_format;
1167 enum intel_output_format output_format;
1168 if (force_dsc_output_format) {
1169 if (source_can_output(intel_dp, force_dsc_output_format) &&
1170 (!drm_dp_is_branch(intel_dp->dpcd) ||
1171 sink_format != force_dsc_output_format ||
1172 dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))
1173 return force_dsc_output_format;
1174
1175 drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
1176 }
1177
1178 if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1179 dfp_can_convert_from_rgb(intel_dp, sink_format))
1180 output_format = INTEL_OUTPUT_FORMAT_RGB;
1181
1182 else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1183 dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1184 output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1185
1186 else
1187 output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1188
1189 drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
1190
1191 return output_format;
1192 }
1193
intel_dp_min_bpp(enum intel_output_format output_format)1194 int intel_dp_min_bpp(enum intel_output_format output_format)
1195 {
1196 if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1197 return 6 * 3;
1198 else
1199 return 8 * 3;
1200 }
1201
intel_dp_output_bpp(enum intel_output_format output_format,int bpp)1202 int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1203 {
1204 /*
1205 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1206 * format of the number of bytes per pixel will be half the number
1207 * of bytes of RGB pixel.
1208 */
1209 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1210 bpp /= 2;
1211
1212 return bpp;
1213 }
1214
1215 static enum intel_output_format
intel_dp_sink_format(struct intel_connector * connector,const struct drm_display_mode * mode)1216 intel_dp_sink_format(struct intel_connector *connector,
1217 const struct drm_display_mode *mode)
1218 {
1219 const struct drm_display_info *info = &connector->base.display_info;
1220
1221 if (drm_mode_is_420_only(info, mode))
1222 return INTEL_OUTPUT_FORMAT_YCBCR420;
1223
1224 return INTEL_OUTPUT_FORMAT_RGB;
1225 }
1226
1227 static int
intel_dp_mode_min_output_bpp(struct intel_connector * connector,const struct drm_display_mode * mode)1228 intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1229 const struct drm_display_mode *mode)
1230 {
1231 enum intel_output_format output_format, sink_format;
1232
1233 sink_format = intel_dp_sink_format(connector, mode);
1234
1235 output_format = intel_dp_output_format(connector, sink_format);
1236
1237 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
1238 }
1239
intel_dp_hdisplay_bad(struct intel_display * display,int hdisplay)1240 static bool intel_dp_hdisplay_bad(struct intel_display *display,
1241 int hdisplay)
1242 {
1243 /*
1244 * Older platforms don't like hdisplay==4096 with DP.
1245 *
1246 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1247 * and frame counter increment), but we don't get vblank interrupts,
1248 * and the pipe underruns immediately. The link also doesn't seem
1249 * to get trained properly.
1250 *
1251 * On CHV the vblank interrupts don't seem to disappear but
1252 * otherwise the symptoms are similar.
1253 *
1254 * TODO: confirm the behaviour on HSW+
1255 */
1256 return hdisplay == 4096 && !HAS_DDI(display);
1257 }
1258
intel_dp_max_tmds_clock(struct intel_dp * intel_dp)1259 static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1260 {
1261 struct intel_connector *connector = intel_dp->attached_connector;
1262 const struct drm_display_info *info = &connector->base.display_info;
1263 int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1264
1265 /* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1266 if (max_tmds_clock && info->max_tmds_clock)
1267 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1268
1269 return max_tmds_clock;
1270 }
1271
1272 static enum drm_mode_status
intel_dp_tmds_clock_valid(struct intel_dp * intel_dp,int clock,int bpc,enum intel_output_format sink_format,bool respect_downstream_limits)1273 intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1274 int clock, int bpc,
1275 enum intel_output_format sink_format,
1276 bool respect_downstream_limits)
1277 {
1278 int tmds_clock, min_tmds_clock, max_tmds_clock;
1279
1280 if (!respect_downstream_limits)
1281 return MODE_OK;
1282
1283 tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1284
1285 min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1286 max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1287
1288 if (min_tmds_clock && tmds_clock < min_tmds_clock)
1289 return MODE_CLOCK_LOW;
1290
1291 if (max_tmds_clock && tmds_clock > max_tmds_clock)
1292 return MODE_CLOCK_HIGH;
1293
1294 return MODE_OK;
1295 }
1296
1297 static enum drm_mode_status
intel_dp_mode_valid_downstream(struct intel_connector * connector,const struct drm_display_mode * mode,int target_clock)1298 intel_dp_mode_valid_downstream(struct intel_connector *connector,
1299 const struct drm_display_mode *mode,
1300 int target_clock)
1301 {
1302 struct intel_dp *intel_dp = intel_attached_dp(connector);
1303 const struct drm_display_info *info = &connector->base.display_info;
1304 enum drm_mode_status status;
1305 enum intel_output_format sink_format;
1306
1307 /* If PCON supports FRL MODE, check FRL bandwidth constraints */
1308 if (intel_dp->dfp.pcon_max_frl_bw) {
1309 int target_bw;
1310 int max_frl_bw;
1311 int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1312
1313 target_bw = bpp * target_clock;
1314
1315 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1316
1317 /* converting bw from Gbps to Kbps*/
1318 max_frl_bw = max_frl_bw * 1000000;
1319
1320 if (target_bw > max_frl_bw)
1321 return MODE_CLOCK_HIGH;
1322
1323 return MODE_OK;
1324 }
1325
1326 if (intel_dp->dfp.max_dotclock &&
1327 target_clock > intel_dp->dfp.max_dotclock)
1328 return MODE_CLOCK_HIGH;
1329
1330 sink_format = intel_dp_sink_format(connector, mode);
1331
1332 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1333 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1334 8, sink_format, true);
1335
1336 if (status != MODE_OK) {
1337 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1338 !connector->base.ycbcr_420_allowed ||
1339 !drm_mode_is_420_also(info, mode))
1340 return status;
1341 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1342 status = intel_dp_tmds_clock_valid(intel_dp, target_clock,
1343 8, sink_format, true);
1344 if (status != MODE_OK)
1345 return status;
1346 }
1347
1348 return MODE_OK;
1349 }
1350
1351 static
intel_dp_needs_joiner(struct intel_dp * intel_dp,struct intel_connector * connector,int hdisplay,int clock,int num_joined_pipes)1352 bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
1353 struct intel_connector *connector,
1354 int hdisplay, int clock,
1355 int num_joined_pipes)
1356 {
1357 struct intel_display *display = to_intel_display(intel_dp);
1358 int hdisplay_limit;
1359
1360 if (!intel_dp_has_joiner(intel_dp))
1361 return false;
1362
1363 num_joined_pipes /= 2;
1364
1365 hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
1366
1367 return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
1368 hdisplay > num_joined_pipes * hdisplay_limit;
1369 }
1370
intel_dp_num_joined_pipes(struct intel_dp * intel_dp,struct intel_connector * connector,int hdisplay,int clock)1371 int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
1372 struct intel_connector *connector,
1373 int hdisplay, int clock)
1374 {
1375 struct intel_display *display = to_intel_display(intel_dp);
1376
1377 if (connector->force_joined_pipes)
1378 return connector->force_joined_pipes;
1379
1380 if (HAS_ULTRAJOINER(display) &&
1381 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))
1382 return 4;
1383
1384 if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) &&
1385 intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))
1386 return 2;
1387
1388 return 1;
1389 }
1390
intel_dp_has_dsc(const struct intel_connector * connector)1391 bool intel_dp_has_dsc(const struct intel_connector *connector)
1392 {
1393 struct intel_display *display = to_intel_display(connector);
1394
1395 if (!HAS_DSC(display))
1396 return false;
1397
1398 if (connector->mst.dp && !HAS_DSC_MST(display))
1399 return false;
1400
1401 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1402 connector->panel.vbt.edp.dsc_disable)
1403 return false;
1404
1405 if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))
1406 return false;
1407
1408 return true;
1409 }
1410
1411 static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector * _connector,const struct drm_display_mode * mode)1412 intel_dp_mode_valid(struct drm_connector *_connector,
1413 const struct drm_display_mode *mode)
1414 {
1415 struct intel_display *display = to_intel_display(_connector->dev);
1416 struct intel_connector *connector = to_intel_connector(_connector);
1417 struct intel_dp *intel_dp = intel_attached_dp(connector);
1418 const struct drm_display_mode *fixed_mode;
1419 int target_clock = mode->clock;
1420 int max_rate, mode_rate, max_lanes, max_link_clock;
1421 int max_dotclk = display->cdclk.max_dotclk_freq;
1422 u16 dsc_max_compressed_bpp = 0;
1423 u8 dsc_slice_count = 0;
1424 enum drm_mode_status status;
1425 bool dsc = false;
1426 int num_joined_pipes;
1427
1428 status = intel_cpu_transcoder_mode_valid(display, mode);
1429 if (status != MODE_OK)
1430 return status;
1431
1432 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1433 return MODE_H_ILLEGAL;
1434
1435 if (mode->clock < 10000)
1436 return MODE_CLOCK_LOW;
1437
1438 fixed_mode = intel_panel_fixed_mode(connector, mode);
1439 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1440 status = intel_panel_mode_valid(connector, mode);
1441 if (status != MODE_OK)
1442 return status;
1443
1444 target_clock = fixed_mode->clock;
1445 }
1446
1447 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1448 mode->hdisplay, target_clock);
1449 max_dotclk *= num_joined_pipes;
1450
1451 if (target_clock > max_dotclk)
1452 return MODE_CLOCK_HIGH;
1453
1454 if (intel_dp_hdisplay_bad(display, mode->hdisplay))
1455 return MODE_H_ILLEGAL;
1456
1457 max_link_clock = intel_dp_max_link_rate(intel_dp);
1458 max_lanes = intel_dp_max_lane_count(intel_dp);
1459
1460 max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
1461
1462 mode_rate = intel_dp_link_required(target_clock,
1463 intel_dp_mode_min_output_bpp(connector, mode));
1464
1465 if (intel_dp_has_dsc(connector)) {
1466 enum intel_output_format sink_format, output_format;
1467 int pipe_bpp;
1468
1469 sink_format = intel_dp_sink_format(connector, mode);
1470 output_format = intel_dp_output_format(connector, sink_format);
1471 /*
1472 * TBD pass the connector BPC,
1473 * for now U8_MAX so that max BPC on that platform would be picked
1474 */
1475 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1476
1477 /*
1478 * Output bpp is stored in 6.4 format so right shift by 4 to get the
1479 * integer value since we support only integer values of bpp.
1480 */
1481 if (intel_dp_is_edp(intel_dp)) {
1482 dsc_max_compressed_bpp =
1483 drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;
1484 dsc_slice_count =
1485 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
1486 true);
1487 } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {
1488 dsc_max_compressed_bpp =
1489 intel_dp_dsc_get_max_compressed_bpp(display,
1490 max_link_clock,
1491 max_lanes,
1492 target_clock,
1493 mode->hdisplay,
1494 num_joined_pipes,
1495 output_format,
1496 pipe_bpp, 64);
1497 dsc_slice_count =
1498 intel_dp_dsc_get_slice_count(connector,
1499 target_clock,
1500 mode->hdisplay,
1501 num_joined_pipes);
1502 }
1503
1504 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1505 }
1506
1507 if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
1508 return MODE_CLOCK_HIGH;
1509
1510 if (mode_rate > max_rate && !dsc)
1511 return MODE_CLOCK_HIGH;
1512
1513 status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1514 if (status != MODE_OK)
1515 return status;
1516
1517 return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
1518 }
1519
intel_dp_source_supports_tps3(struct intel_display * display)1520 bool intel_dp_source_supports_tps3(struct intel_display *display)
1521 {
1522 return DISPLAY_VER(display) >= 9 ||
1523 display->platform.broadwell || display->platform.haswell;
1524 }
1525
intel_dp_source_supports_tps4(struct intel_display * display)1526 bool intel_dp_source_supports_tps4(struct intel_display *display)
1527 {
1528 return DISPLAY_VER(display) >= 10;
1529 }
1530
seq_buf_print_array(struct seq_buf * s,const int * array,int nelem)1531 static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem)
1532 {
1533 int i;
1534
1535 for (i = 0; i < nelem; i++)
1536 seq_buf_printf(s, "%s%d", i ? ", " : "", array[i]);
1537 }
1538
intel_dp_print_rates(struct intel_dp * intel_dp)1539 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1540 {
1541 struct intel_display *display = to_intel_display(intel_dp);
1542 DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */
1543
1544 if (!drm_debug_enabled(DRM_UT_KMS))
1545 return;
1546
1547 seq_buf_print_array(&s, intel_dp->source_rates, intel_dp->num_source_rates);
1548 drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));
1549
1550 seq_buf_clear(&s);
1551 seq_buf_print_array(&s, intel_dp->sink_rates, intel_dp->num_sink_rates);
1552 drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));
1553
1554 seq_buf_clear(&s);
1555 seq_buf_print_array(&s, intel_dp->common_rates, intel_dp->num_common_rates);
1556 drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
1557 }
1558
forced_link_rate(struct intel_dp * intel_dp)1559 static int forced_link_rate(struct intel_dp *intel_dp)
1560 {
1561 int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);
1562
1563 if (len == 0)
1564 return intel_dp_common_rate(intel_dp, 0);
1565
1566 return intel_dp_common_rate(intel_dp, len - 1);
1567 }
1568
1569 int
intel_dp_max_link_rate(struct intel_dp * intel_dp)1570 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1571 {
1572 int len;
1573
1574 if (intel_dp->link.force_rate)
1575 return forced_link_rate(intel_dp);
1576
1577 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);
1578
1579 return intel_dp_common_rate(intel_dp, len - 1);
1580 }
1581
1582 static int
intel_dp_min_link_rate(struct intel_dp * intel_dp)1583 intel_dp_min_link_rate(struct intel_dp *intel_dp)
1584 {
1585 if (intel_dp->link.force_rate)
1586 return forced_link_rate(intel_dp);
1587
1588 return intel_dp_common_rate(intel_dp, 0);
1589 }
1590
intel_dp_rate_select(struct intel_dp * intel_dp,int rate)1591 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1592 {
1593 struct intel_display *display = to_intel_display(intel_dp);
1594 int i = intel_dp_rate_index(intel_dp->sink_rates,
1595 intel_dp->num_sink_rates, rate);
1596
1597 if (drm_WARN_ON(display->drm, i < 0))
1598 i = 0;
1599
1600 return i;
1601 }
1602
intel_dp_compute_rate(struct intel_dp * intel_dp,int port_clock,u8 * link_bw,u8 * rate_select)1603 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1604 u8 *link_bw, u8 *rate_select)
1605 {
1606 /* eDP 1.4 rate select method. */
1607 if (intel_dp->use_rate_select) {
1608 *link_bw = 0;
1609 *rate_select =
1610 intel_dp_rate_select(intel_dp, port_clock);
1611 } else {
1612 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1613 *rate_select = 0;
1614 }
1615 }
1616
intel_dp_has_hdmi_sink(struct intel_dp * intel_dp)1617 bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1618 {
1619 struct intel_connector *connector = intel_dp->attached_connector;
1620
1621 return connector->base.display_info.is_hdmi;
1622 }
1623
intel_dp_source_supports_fec(struct intel_dp * intel_dp,const struct intel_crtc_state * pipe_config)1624 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1625 const struct intel_crtc_state *pipe_config)
1626 {
1627 struct intel_display *display = to_intel_display(intel_dp);
1628 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1629
1630 if (DISPLAY_VER(display) >= 12)
1631 return true;
1632
1633 if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
1634 !intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
1635 return true;
1636
1637 return false;
1638 }
1639
intel_dp_supports_fec(struct intel_dp * intel_dp,const struct intel_connector * connector,const struct intel_crtc_state * pipe_config)1640 bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1641 const struct intel_connector *connector,
1642 const struct intel_crtc_state *pipe_config)
1643 {
1644 return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1645 drm_dp_sink_supports_fec(connector->dp.fec_capability);
1646 }
1647
intel_dp_supports_dsc(struct intel_dp * intel_dp,const struct intel_connector * connector,const struct intel_crtc_state * crtc_state)1648 bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1649 const struct intel_connector *connector,
1650 const struct intel_crtc_state *crtc_state)
1651 {
1652 if (!intel_dp_has_dsc(connector))
1653 return false;
1654
1655 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) &&
1656 !intel_dp_supports_fec(intel_dp, connector, crtc_state))
1657 return false;
1658
1659 return intel_dsc_source_support(crtc_state);
1660 }
1661
intel_dp_hdmi_compute_bpc(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int bpc,bool respect_downstream_limits)1662 static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1663 const struct intel_crtc_state *crtc_state,
1664 int bpc, bool respect_downstream_limits)
1665 {
1666 int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1667
1668 /*
1669 * Current bpc could already be below 8bpc due to
1670 * FDI bandwidth constraints or other limits.
1671 * HDMI minimum is 8bpc however.
1672 */
1673 bpc = max(bpc, 8);
1674
1675 /*
1676 * We will never exceed downstream TMDS clock limits while
1677 * attempting deep color. If the user insists on forcing an
1678 * out of spec mode they will have to be satisfied with 8bpc.
1679 */
1680 if (!respect_downstream_limits)
1681 bpc = 8;
1682
1683 for (; bpc >= 8; bpc -= 2) {
1684 if (intel_hdmi_bpc_possible(crtc_state, bpc,
1685 intel_dp_has_hdmi_sink(intel_dp)) &&
1686 intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,
1687 respect_downstream_limits) == MODE_OK)
1688 return bpc;
1689 }
1690
1691 return -EINVAL;
1692 }
1693
intel_dp_max_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,bool respect_downstream_limits)1694 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1695 const struct intel_crtc_state *crtc_state,
1696 bool respect_downstream_limits)
1697 {
1698 struct intel_display *display = to_intel_display(intel_dp);
1699 struct intel_connector *connector = intel_dp->attached_connector;
1700 int bpp, bpc;
1701
1702 bpc = crtc_state->pipe_bpp / 3;
1703
1704 if (intel_dp->dfp.max_bpc)
1705 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1706
1707 if (intel_dp->dfp.min_tmds_clock) {
1708 int max_hdmi_bpc;
1709
1710 max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1711 respect_downstream_limits);
1712 if (max_hdmi_bpc < 0)
1713 return 0;
1714
1715 bpc = min(bpc, max_hdmi_bpc);
1716 }
1717
1718 bpp = bpc * 3;
1719 if (intel_dp_is_edp(intel_dp)) {
1720 /* Get bpp from vbt only for panels that dont have bpp in edid */
1721 if (connector->base.display_info.bpc == 0 &&
1722 connector->panel.vbt.edp.bpp &&
1723 connector->panel.vbt.edp.bpp < bpp) {
1724 drm_dbg_kms(display->drm,
1725 "clamping bpp for eDP panel to BIOS-provided %i\n",
1726 connector->panel.vbt.edp.bpp);
1727 bpp = connector->panel.vbt.edp.bpp;
1728 }
1729 }
1730
1731 return bpp;
1732 }
1733
has_seamless_m_n(struct intel_connector * connector)1734 static bool has_seamless_m_n(struct intel_connector *connector)
1735 {
1736 struct intel_display *display = to_intel_display(connector);
1737
1738 /*
1739 * Seamless M/N reprogramming only implemented
1740 * for BDW+ double buffered M/N registers so far.
1741 */
1742 return HAS_DOUBLE_BUFFERED_M_N(display) &&
1743 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1744 }
1745
intel_dp_mode_clock(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1746 static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1747 const struct drm_connector_state *conn_state)
1748 {
1749 struct intel_connector *connector = to_intel_connector(conn_state->connector);
1750 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1751
1752 /* FIXME a bit of a mess wrt clock vs. crtc_clock */
1753 if (has_seamless_m_n(connector))
1754 return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1755 else
1756 return adjusted_mode->crtc_clock;
1757 }
1758
1759 /* Optimize link config in order: max bpp, min clock, min lanes */
1760 static int
intel_dp_compute_link_config_wide(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,const struct drm_connector_state * conn_state,const struct link_config_limits * limits)1761 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1762 struct intel_crtc_state *pipe_config,
1763 const struct drm_connector_state *conn_state,
1764 const struct link_config_limits *limits)
1765 {
1766 int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
1767 int mode_rate, link_rate, link_avail;
1768
1769 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
1770 bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
1771 bpp -= 2 * 3) {
1772 int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
1773
1774 mode_rate = intel_dp_link_required(clock, link_bpp);
1775
1776 for (i = 0; i < intel_dp->num_common_rates; i++) {
1777 link_rate = intel_dp_common_rate(intel_dp, i);
1778 if (link_rate < limits->min_rate ||
1779 link_rate > limits->max_rate)
1780 continue;
1781
1782 for (lane_count = limits->min_lane_count;
1783 lane_count <= limits->max_lane_count;
1784 lane_count <<= 1) {
1785 link_avail = intel_dp_max_link_data_rate(intel_dp,
1786 link_rate,
1787 lane_count);
1788
1789
1790 if (mode_rate <= link_avail) {
1791 pipe_config->lane_count = lane_count;
1792 pipe_config->pipe_bpp = bpp;
1793 pipe_config->port_clock = link_rate;
1794
1795 return 0;
1796 }
1797 }
1798 }
1799 }
1800
1801 return -EINVAL;
1802 }
1803
intel_dp_dsc_max_src_input_bpc(struct intel_display * display)1804 int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
1805 {
1806 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1807 if (DISPLAY_VER(display) >= 12)
1808 return 12;
1809 if (DISPLAY_VER(display) == 11)
1810 return 10;
1811
1812 return intel_dp_dsc_min_src_input_bpc();
1813 }
1814
intel_dp_dsc_compute_max_bpp(const struct intel_connector * connector,u8 max_req_bpc)1815 int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1816 u8 max_req_bpc)
1817 {
1818 struct intel_display *display = to_intel_display(connector);
1819 int i, num_bpc;
1820 u8 dsc_bpc[3] = {};
1821 int dsc_max_bpc;
1822
1823 dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
1824
1825 if (!dsc_max_bpc)
1826 return dsc_max_bpc;
1827
1828 dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
1829
1830 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
1831 dsc_bpc);
1832 for (i = 0; i < num_bpc; i++) {
1833 if (dsc_max_bpc >= dsc_bpc[i])
1834 return dsc_bpc[i] * 3;
1835 }
1836
1837 return 0;
1838 }
1839
intel_dp_source_dsc_version_minor(struct intel_display * display)1840 static int intel_dp_source_dsc_version_minor(struct intel_display *display)
1841 {
1842 return DISPLAY_VER(display) >= 14 ? 2 : 1;
1843 }
1844
intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])1845 static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1846 {
1847 return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1848 DP_DSC_MINOR_SHIFT;
1849 }
1850
intel_dp_get_slice_height(int vactive)1851 static int intel_dp_get_slice_height(int vactive)
1852 {
1853 int slice_height;
1854
1855 /*
1856 * VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1857 * lines is an optimal slice height, but any size can be used as long as
1858 * vertical active integer multiple and maximum vertical slice count
1859 * requirements are met.
1860 */
1861 for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1862 if (vactive % slice_height == 0)
1863 return slice_height;
1864
1865 /*
1866 * Highly unlikely we reach here as most of the resolutions will end up
1867 * finding appropriate slice_height in above loop but returning
1868 * slice_height as 2 here as it should work with all resolutions.
1869 */
1870 return 2;
1871 }
1872
intel_dp_dsc_compute_params(const struct intel_connector * connector,struct intel_crtc_state * crtc_state)1873 static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1874 struct intel_crtc_state *crtc_state)
1875 {
1876 struct intel_display *display = to_intel_display(connector);
1877 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1878 int ret;
1879
1880 /*
1881 * RC_MODEL_SIZE is currently a constant across all configurations.
1882 *
1883 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1884 * DP_DSC_RC_BUF_SIZE for this.
1885 */
1886 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1887 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1888
1889 vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);
1890
1891 ret = intel_dsc_compute_params(crtc_state);
1892 if (ret)
1893 return ret;
1894
1895 vdsc_cfg->dsc_version_major =
1896 (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1897 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1898 vdsc_cfg->dsc_version_minor =
1899 min(intel_dp_source_dsc_version_minor(display),
1900 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1901 if (vdsc_cfg->convert_rgb)
1902 vdsc_cfg->convert_rgb =
1903 connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1904 DP_DSC_RGB;
1905
1906 vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1907 drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1908 if (!vdsc_cfg->line_buf_depth) {
1909 drm_dbg_kms(display->drm,
1910 "DSC Sink Line Buffer Depth invalid\n");
1911 return -EINVAL;
1912 }
1913
1914 vdsc_cfg->block_pred_enable =
1915 connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1916 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1917
1918 return drm_dsc_compute_rc_parameters(vdsc_cfg);
1919 }
1920
intel_dp_dsc_supports_format(const struct intel_connector * connector,enum intel_output_format output_format)1921 static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1922 enum intel_output_format output_format)
1923 {
1924 struct intel_display *display = to_intel_display(connector);
1925 u8 sink_dsc_format;
1926
1927 switch (output_format) {
1928 case INTEL_OUTPUT_FORMAT_RGB:
1929 sink_dsc_format = DP_DSC_RGB;
1930 break;
1931 case INTEL_OUTPUT_FORMAT_YCBCR444:
1932 sink_dsc_format = DP_DSC_YCbCr444;
1933 break;
1934 case INTEL_OUTPUT_FORMAT_YCBCR420:
1935 if (min(intel_dp_source_dsc_version_minor(display),
1936 intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1937 return false;
1938 sink_dsc_format = DP_DSC_YCbCr420_Native;
1939 break;
1940 default:
1941 return false;
1942 }
1943
1944 return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);
1945 }
1946
is_bw_sufficient_for_dsc_config(int dsc_bpp_x16,u32 link_clock,u32 lane_count,u32 mode_clock,enum intel_output_format output_format,int timeslots)1947 static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,
1948 u32 lane_count, u32 mode_clock,
1949 enum intel_output_format output_format,
1950 int timeslots)
1951 {
1952 u32 available_bw, required_bw;
1953
1954 available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1955 required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock));
1956
1957 return available_bw > required_bw;
1958 }
1959
dsc_compute_link_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,const struct link_config_limits * limits,int dsc_bpp_x16,int timeslots)1960 static int dsc_compute_link_config(struct intel_dp *intel_dp,
1961 struct intel_crtc_state *pipe_config,
1962 struct drm_connector_state *conn_state,
1963 const struct link_config_limits *limits,
1964 int dsc_bpp_x16,
1965 int timeslots)
1966 {
1967 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1968 int link_rate, lane_count;
1969 int i;
1970
1971 for (i = 0; i < intel_dp->num_common_rates; i++) {
1972 link_rate = intel_dp_common_rate(intel_dp, i);
1973 if (link_rate < limits->min_rate || link_rate > limits->max_rate)
1974 continue;
1975
1976 for (lane_count = limits->min_lane_count;
1977 lane_count <= limits->max_lane_count;
1978 lane_count <<= 1) {
1979
1980 /*
1981 * FIXME: intel_dp_mtp_tu_compute_config() requires
1982 * ->lane_count and ->port_clock set before we know
1983 * they'll work. If we end up failing altogether,
1984 * they'll remain in crtc state. This shouldn't matter,
1985 * as we'd then bail out from compute config, but it's
1986 * just ugly.
1987 */
1988 pipe_config->lane_count = lane_count;
1989 pipe_config->port_clock = link_rate;
1990
1991 if (drm_dp_is_uhbr_rate(link_rate)) {
1992 int ret;
1993
1994 ret = intel_dp_mtp_tu_compute_config(intel_dp,
1995 pipe_config,
1996 conn_state,
1997 dsc_bpp_x16,
1998 dsc_bpp_x16,
1999 0, true);
2000 if (ret)
2001 continue;
2002 } else {
2003 if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_rate,
2004 lane_count, adjusted_mode->clock,
2005 pipe_config->output_format,
2006 timeslots))
2007 continue;
2008 }
2009
2010 return 0;
2011 }
2012 }
2013
2014 return -EINVAL;
2015 }
2016
2017 static
intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector * connector,const struct intel_crtc_state * pipe_config,int bpc)2018 u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
2019 const struct intel_crtc_state *pipe_config,
2020 int bpc)
2021 {
2022 u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);
2023
2024 if (max_bppx16)
2025 return max_bppx16;
2026 /*
2027 * If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
2028 * values as given in spec Table 2-157 DP v2.0
2029 */
2030 switch (pipe_config->output_format) {
2031 case INTEL_OUTPUT_FORMAT_RGB:
2032 case INTEL_OUTPUT_FORMAT_YCBCR444:
2033 return (3 * bpc) << 4;
2034 case INTEL_OUTPUT_FORMAT_YCBCR420:
2035 return (3 * (bpc / 2)) << 4;
2036 default:
2037 MISSING_CASE(pipe_config->output_format);
2038 break;
2039 }
2040
2041 return 0;
2042 }
2043
intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state * pipe_config)2044 int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
2045 {
2046 /* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
2047 switch (pipe_config->output_format) {
2048 case INTEL_OUTPUT_FORMAT_RGB:
2049 case INTEL_OUTPUT_FORMAT_YCBCR444:
2050 return 8;
2051 case INTEL_OUTPUT_FORMAT_YCBCR420:
2052 return 6;
2053 default:
2054 MISSING_CASE(pipe_config->output_format);
2055 break;
2056 }
2057
2058 return 0;
2059 }
2060
intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector * connector,const struct intel_crtc_state * pipe_config,int bpc)2061 int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2062 const struct intel_crtc_state *pipe_config,
2063 int bpc)
2064 {
2065 return intel_dp_dsc_max_sink_compressed_bppx16(connector,
2066 pipe_config, bpc) >> 4;
2067 }
2068
dsc_src_min_compressed_bpp(void)2069 static int dsc_src_min_compressed_bpp(void)
2070 {
2071 /* Min Compressed bpp supported by source is 8 */
2072 return 8;
2073 }
2074
dsc_src_max_compressed_bpp(struct intel_dp * intel_dp)2075 static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2076 {
2077 struct intel_display *display = to_intel_display(intel_dp);
2078
2079 /*
2080 * Forcing DSC and using the platform's max compressed bpp is seen to cause
2081 * underruns. Since DSC isn't needed in these cases, limit the
2082 * max compressed bpp to 18, which is a safe value across platforms with different
2083 * pipe bpps.
2084 */
2085 if (intel_dp->force_dsc_en)
2086 return 18;
2087
2088 /*
2089 * Max Compressed bpp for Gen 13+ is 27bpp.
2090 * For earlier platform is 23bpp. (Bspec:49259).
2091 */
2092 if (DISPLAY_VER(display) < 13)
2093 return 23;
2094 else
2095 return 27;
2096 }
2097
2098 /*
2099 * Note: for pre-13 display you still need to check the validity of each step.
2100 */
intel_dp_dsc_bpp_step_x16(const struct intel_connector * connector)2101 static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector)
2102 {
2103 struct intel_display *display = to_intel_display(connector);
2104 u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);
2105
2106 if (DISPLAY_VER(display) < 14 || !incr)
2107 return fxp_q4_from_int(1);
2108
2109 /* fxp q4 */
2110 return fxp_q4_from_int(1) / incr;
2111 }
2112
2113 /* Note: This is not universally usable! */
intel_dp_dsc_valid_bpp(struct intel_dp * intel_dp,int bpp_x16)2114 static bool intel_dp_dsc_valid_bpp(struct intel_dp *intel_dp, int bpp_x16)
2115 {
2116 struct intel_display *display = to_intel_display(intel_dp);
2117 int i;
2118
2119 if (DISPLAY_VER(display) >= 13) {
2120 if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(bpp_x16))
2121 return false;
2122
2123 return true;
2124 }
2125
2126 if (fxp_q4_to_frac(bpp_x16))
2127 return false;
2128
2129 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
2130 if (fxp_q4_to_int(bpp_x16) == valid_dsc_bpp[i])
2131 return true;
2132 }
2133
2134 return false;
2135 }
2136
2137 /*
2138 * Find the max compressed BPP we can find a link configuration for. The BPPs to
2139 * try depend on the source (platform) and sink.
2140 */
dsc_compute_compressed_bpp(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,const struct link_config_limits * limits,int pipe_bpp,int timeslots)2141 static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
2142 struct intel_crtc_state *pipe_config,
2143 struct drm_connector_state *conn_state,
2144 const struct link_config_limits *limits,
2145 int pipe_bpp,
2146 int timeslots)
2147 {
2148 struct intel_display *display = to_intel_display(intel_dp);
2149 const struct intel_connector *connector = to_intel_connector(conn_state->connector);
2150 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2151 int output_bpp;
2152 int dsc_min_bpp;
2153 int dsc_max_bpp;
2154 int min_bpp_x16, max_bpp_x16, bpp_step_x16;
2155 int dsc_joiner_max_bpp;
2156 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2157 int bpp_x16;
2158 int ret;
2159
2160 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
2161
2162 dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, adjusted_mode->clock,
2163 adjusted_mode->hdisplay,
2164 num_joined_pipes);
2165 dsc_max_bpp = min(dsc_joiner_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));
2166
2167 /* FIXME: remove the round trip via integers */
2168 min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
2169 max_bpp_x16 = fxp_q4_from_int(dsc_max_bpp);
2170
2171 bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector);
2172
2173 /* Compressed BPP should be less than the Input DSC bpp */
2174 output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp);
2175 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16);
2176
2177 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) {
2178 if (!intel_dp_dsc_valid_bpp(intel_dp, bpp_x16))
2179 continue;
2180
2181 ret = dsc_compute_link_config(intel_dp,
2182 pipe_config,
2183 conn_state,
2184 limits,
2185 bpp_x16,
2186 timeslots);
2187 if (ret == 0) {
2188 pipe_config->dsc.compressed_bpp_x16 = bpp_x16;
2189 if (intel_dp->force_dsc_fractional_bpp_en &&
2190 fxp_q4_to_frac(bpp_x16))
2191 drm_dbg_kms(display->drm,
2192 "Forcing DSC fractional bpp\n");
2193
2194 return 0;
2195 }
2196 }
2197
2198 return -EINVAL;
2199 }
2200
intel_dp_dsc_min_src_input_bpc(void)2201 int intel_dp_dsc_min_src_input_bpc(void)
2202 {
2203 /* Min DSC Input BPC for ICL+ is 8 */
2204 return 8;
2205 }
2206
2207 static
is_dsc_pipe_bpp_sufficient(const struct link_config_limits * limits,int pipe_bpp)2208 bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits,
2209 int pipe_bpp)
2210 {
2211 return pipe_bpp >= limits->pipe.min_bpp &&
2212 pipe_bpp <= limits->pipe.max_bpp;
2213 }
2214
2215 static
intel_dp_force_dsc_pipe_bpp(struct intel_dp * intel_dp,const struct link_config_limits * limits)2216 int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2217 const struct link_config_limits *limits)
2218 {
2219 struct intel_display *display = to_intel_display(intel_dp);
2220 int forced_bpp;
2221
2222 if (!intel_dp->force_dsc_bpc)
2223 return 0;
2224
2225 forced_bpp = intel_dp->force_dsc_bpc * 3;
2226
2227 if (is_dsc_pipe_bpp_sufficient(limits, forced_bpp)) {
2228 drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
2229 intel_dp->force_dsc_bpc);
2230 return forced_bpp;
2231 }
2232
2233 drm_dbg_kms(display->drm,
2234 "Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2235 intel_dp->force_dsc_bpc);
2236
2237 return 0;
2238 }
2239
intel_dp_dsc_compute_pipe_bpp(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,const struct link_config_limits * limits,int timeslots)2240 static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2241 struct intel_crtc_state *pipe_config,
2242 struct drm_connector_state *conn_state,
2243 const struct link_config_limits *limits,
2244 int timeslots)
2245 {
2246 const struct intel_connector *connector =
2247 to_intel_connector(conn_state->connector);
2248 u8 dsc_bpc[3] = {};
2249 int forced_bpp, pipe_bpp;
2250 int num_bpc, i, ret;
2251
2252 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2253
2254 if (forced_bpp) {
2255 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,
2256 limits, forced_bpp, timeslots);
2257 if (ret == 0) {
2258 pipe_config->pipe_bpp = forced_bpp;
2259 return 0;
2260 }
2261 }
2262
2263 /*
2264 * Get the maximum DSC bpc that will be supported by any valid
2265 * link configuration and compressed bpp.
2266 */
2267 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);
2268 for (i = 0; i < num_bpc; i++) {
2269 pipe_bpp = dsc_bpc[i] * 3;
2270 if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp)
2271 continue;
2272
2273 ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,
2274 limits, pipe_bpp, timeslots);
2275 if (ret == 0) {
2276 pipe_config->pipe_bpp = pipe_bpp;
2277 return 0;
2278 }
2279 }
2280
2281 return -EINVAL;
2282 }
2283
intel_edp_dsc_compute_pipe_bpp(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,const struct link_config_limits * limits)2284 static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2285 struct intel_crtc_state *pipe_config,
2286 struct drm_connector_state *conn_state,
2287 const struct link_config_limits *limits)
2288 {
2289 struct intel_display *display = to_intel_display(intel_dp);
2290 struct intel_connector *connector =
2291 to_intel_connector(conn_state->connector);
2292 int pipe_bpp, forced_bpp;
2293 int dsc_min_bpp;
2294 int dsc_max_bpp;
2295
2296 forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2297
2298 if (forced_bpp) {
2299 pipe_bpp = forced_bpp;
2300 } else {
2301 int max_bpc = limits->pipe.max_bpp / 3;
2302
2303 /* For eDP use max bpp that can be supported with DSC. */
2304 pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);
2305 if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
2306 drm_dbg_kms(display->drm,
2307 "Computed BPC is not in DSC BPC limits\n");
2308 return -EINVAL;
2309 }
2310 }
2311 pipe_config->port_clock = limits->max_rate;
2312 pipe_config->lane_count = limits->max_lane_count;
2313
2314 dsc_min_bpp = fxp_q4_to_int_roundup(limits->link.min_bpp_x16);
2315
2316 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
2317
2318 /* Compressed BPP should be less than the Input DSC bpp */
2319 dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2320
2321 pipe_config->dsc.compressed_bpp_x16 =
2322 fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
2323
2324 pipe_config->pipe_bpp = pipe_bpp;
2325
2326 return 0;
2327 }
2328
intel_dp_fec_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)2329 static void intel_dp_fec_compute_config(struct intel_dp *intel_dp,
2330 struct intel_crtc_state *crtc_state)
2331 {
2332 if (crtc_state->fec_enable)
2333 return;
2334
2335 /*
2336 * Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2337 * Since, FEC is a bandwidth overhead, continue to not enable it for
2338 * eDP. Until, there is a good reason to do so.
2339 */
2340 if (intel_dp_is_edp(intel_dp))
2341 return;
2342
2343 if (intel_dp_is_uhbr(crtc_state))
2344 return;
2345
2346 crtc_state->fec_enable = true;
2347 }
2348
intel_dp_dsc_compute_config(struct intel_dp * intel_dp,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,const struct link_config_limits * limits,int timeslots)2349 int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2350 struct intel_crtc_state *pipe_config,
2351 struct drm_connector_state *conn_state,
2352 const struct link_config_limits *limits,
2353 int timeslots)
2354 {
2355 struct intel_display *display = to_intel_display(intel_dp);
2356 const struct intel_connector *connector =
2357 to_intel_connector(conn_state->connector);
2358 const struct drm_display_mode *adjusted_mode =
2359 &pipe_config->hw.adjusted_mode;
2360 int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);
2361 bool is_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST);
2362 int ret;
2363
2364 intel_dp_fec_compute_config(intel_dp, pipe_config);
2365
2366 if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))
2367 return -EINVAL;
2368
2369 /*
2370 * Link parameters, pipe bpp and compressed bpp have already been
2371 * figured out for DP MST DSC.
2372 */
2373 if (!is_mst) {
2374 if (intel_dp_is_edp(intel_dp))
2375 ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2376 conn_state, limits);
2377 else
2378 ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2379 conn_state, limits, timeslots);
2380 if (ret) {
2381 drm_dbg_kms(display->drm,
2382 "No Valid pipe bpp for given mode ret = %d\n", ret);
2383 return ret;
2384 }
2385 }
2386
2387 /* Calculate Slice count */
2388 if (intel_dp_is_edp(intel_dp)) {
2389 pipe_config->dsc.slice_count =
2390 drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,
2391 true);
2392 if (!pipe_config->dsc.slice_count) {
2393 drm_dbg_kms(display->drm,
2394 "Unsupported Slice Count %d\n",
2395 pipe_config->dsc.slice_count);
2396 return -EINVAL;
2397 }
2398 } else {
2399 u8 dsc_dp_slice_count;
2400
2401 dsc_dp_slice_count =
2402 intel_dp_dsc_get_slice_count(connector,
2403 adjusted_mode->crtc_clock,
2404 adjusted_mode->crtc_hdisplay,
2405 num_joined_pipes);
2406 if (!dsc_dp_slice_count) {
2407 drm_dbg_kms(display->drm,
2408 "Compressed Slice Count not supported\n");
2409 return -EINVAL;
2410 }
2411
2412 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2413 }
2414 /*
2415 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2416 * is greater than the maximum Cdclock and if slice count is even
2417 * then we need to use 2 VDSC instances.
2418 * In case of Ultrajoiner along with 12 slices we need to use 3
2419 * VDSC instances.
2420 */
2421 if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
2422 pipe_config->dsc.slice_count == 12)
2423 pipe_config->dsc.num_streams = 3;
2424 else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
2425 pipe_config->dsc.num_streams = 2;
2426 else
2427 pipe_config->dsc.num_streams = 1;
2428
2429 ret = intel_dp_dsc_compute_params(connector, pipe_config);
2430 if (ret < 0) {
2431 drm_dbg_kms(display->drm,
2432 "Cannot compute valid DSC parameters for Input Bpp = %d"
2433 "Compressed BPP = " FXP_Q4_FMT "\n",
2434 pipe_config->pipe_bpp,
2435 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
2436 return ret;
2437 }
2438
2439 pipe_config->dsc.compression_enable = true;
2440 drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
2441 "Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2442 pipe_config->pipe_bpp,
2443 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2444 pipe_config->dsc.slice_count);
2445
2446 return 0;
2447 }
2448
2449 /*
2450 * Calculate the output link min, max bpp values in limits based on the pipe bpp
2451 * range, crtc_state and dsc mode. Return true on success.
2452 */
2453 static bool
intel_dp_compute_config_link_bpp_limits(struct intel_dp * intel_dp,const struct intel_connector * connector,const struct intel_crtc_state * crtc_state,bool dsc,struct link_config_limits * limits)2454 intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2455 const struct intel_connector *connector,
2456 const struct intel_crtc_state *crtc_state,
2457 bool dsc,
2458 struct link_config_limits *limits)
2459 {
2460 struct intel_display *display = to_intel_display(intel_dp);
2461 const struct drm_display_mode *adjusted_mode =
2462 &crtc_state->hw.adjusted_mode;
2463 const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2464 const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2465 int max_link_bpp_x16;
2466
2467 max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2468 fxp_q4_from_int(limits->pipe.max_bpp));
2469
2470 if (!dsc) {
2471 max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
2472
2473 if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))
2474 return false;
2475
2476 limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);
2477 } else {
2478 int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2479 int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2480
2481 dsc_src_min_bpp = dsc_src_min_compressed_bpp();
2482 dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
2483 dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2484 limits->link.min_bpp_x16 = fxp_q4_from_int(dsc_min_bpp);
2485
2486 dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2487 dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2488 crtc_state,
2489 limits->pipe.max_bpp / 3);
2490 dsc_max_bpp = dsc_sink_max_bpp ?
2491 min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2492
2493 max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2494 }
2495
2496 limits->link.max_bpp_x16 = max_link_bpp_x16;
2497
2498 drm_dbg_kms(display->drm,
2499 "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2500 encoder->base.base.id, encoder->base.name,
2501 crtc->base.base.id, crtc->base.name,
2502 adjusted_mode->crtc_clock,
2503 str_on_off(dsc),
2504 limits->max_lane_count,
2505 limits->max_rate,
2506 limits->pipe.max_bpp,
2507 FXP_Q4_ARGS(limits->link.max_bpp_x16));
2508
2509 return true;
2510 }
2511
2512 static void
intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp * intel_dp,struct link_config_limits * limits)2513 intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp,
2514 struct link_config_limits *limits)
2515 {
2516 struct intel_display *display = to_intel_display(intel_dp);
2517 int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc();
2518 int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
2519
2520 limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2521 limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2522 }
2523
2524 bool
intel_dp_compute_config_limits(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,bool respect_downstream_limits,bool dsc,struct link_config_limits * limits)2525 intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2526 struct intel_crtc_state *crtc_state,
2527 bool respect_downstream_limits,
2528 bool dsc,
2529 struct link_config_limits *limits)
2530 {
2531 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2532
2533 limits->min_rate = intel_dp_min_link_rate(intel_dp);
2534 limits->max_rate = intel_dp_max_link_rate(intel_dp);
2535
2536 limits->min_rate = min(limits->min_rate, limits->max_rate);
2537
2538 limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2539 limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2540
2541 limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
2542 if (is_mst) {
2543 /*
2544 * FIXME: If all the streams can't fit into the link with their
2545 * current pipe_bpp we should reduce pipe_bpp across the board
2546 * until things start to fit. Until then we limit to <= 8bpc
2547 * since that's what was hardcoded for all MST streams
2548 * previously. This hack should be removed once we have the
2549 * proper retry logic in place.
2550 */
2551 limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
2552 } else {
2553 limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2554 respect_downstream_limits);
2555 }
2556
2557 if (dsc)
2558 intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits);
2559
2560 if (is_mst || intel_dp->use_max_params) {
2561 /*
2562 * For MST we always configure max link bw - the spec doesn't
2563 * seem to suggest we should do otherwise.
2564 *
2565 * Use the maximum clock and number of lanes the eDP panel
2566 * advertizes being capable of in case the initial fast
2567 * optimal params failed us. The panels are generally
2568 * designed to support only a single clock and lane
2569 * configuration, and typically on older panels these
2570 * values correspond to the native resolution of the panel.
2571 */
2572 limits->min_lane_count = limits->max_lane_count;
2573 limits->min_rate = limits->max_rate;
2574 }
2575
2576 intel_dp_test_compute_config(intel_dp, crtc_state, limits);
2577
2578 return intel_dp_compute_config_link_bpp_limits(intel_dp,
2579 intel_dp->attached_connector,
2580 crtc_state,
2581 dsc,
2582 limits);
2583 }
2584
intel_dp_config_required_rate(const struct intel_crtc_state * crtc_state)2585 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2586 {
2587 const struct drm_display_mode *adjusted_mode =
2588 &crtc_state->hw.adjusted_mode;
2589 int bpp = crtc_state->dsc.compression_enable ?
2590 fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :
2591 crtc_state->pipe_bpp;
2592
2593 return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);
2594 }
2595
intel_dp_joiner_needs_dsc(struct intel_display * display,int num_joined_pipes)2596 bool intel_dp_joiner_needs_dsc(struct intel_display *display,
2597 int num_joined_pipes)
2598 {
2599 /*
2600 * Pipe joiner needs compression up to display 12 due to bandwidth
2601 * limitation. DG2 onwards pipe joiner can be enabled without
2602 * compression.
2603 * Ultrajoiner always needs compression.
2604 */
2605 return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
2606 num_joined_pipes == 4;
2607 }
2608
2609 static int
intel_dp_compute_link_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state,bool respect_downstream_limits)2610 intel_dp_compute_link_config(struct intel_encoder *encoder,
2611 struct intel_crtc_state *pipe_config,
2612 struct drm_connector_state *conn_state,
2613 bool respect_downstream_limits)
2614 {
2615 struct intel_display *display = to_intel_display(encoder);
2616 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2617 struct intel_connector *connector =
2618 to_intel_connector(conn_state->connector);
2619 const struct drm_display_mode *adjusted_mode =
2620 &pipe_config->hw.adjusted_mode;
2621 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2622 struct link_config_limits limits;
2623 bool dsc_needed, joiner_needs_dsc;
2624 int num_joined_pipes;
2625 int ret = 0;
2626
2627 if (pipe_config->fec_enable &&
2628 !intel_dp_supports_fec(intel_dp, connector, pipe_config))
2629 return -EINVAL;
2630
2631 num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
2632 adjusted_mode->crtc_hdisplay,
2633 adjusted_mode->crtc_clock);
2634 if (num_joined_pipes > 1)
2635 pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2636
2637 joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2638
2639 dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2640 !intel_dp_compute_config_limits(intel_dp, pipe_config,
2641 respect_downstream_limits,
2642 false,
2643 &limits);
2644
2645 if (!dsc_needed) {
2646 /*
2647 * Optimize for slow and wide for everything, because there are some
2648 * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2649 */
2650 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2651 conn_state, &limits);
2652 if (!ret && intel_dp_is_uhbr(pipe_config))
2653 ret = intel_dp_mtp_tu_compute_config(intel_dp,
2654 pipe_config,
2655 conn_state,
2656 fxp_q4_from_int(pipe_config->pipe_bpp),
2657 fxp_q4_from_int(pipe_config->pipe_bpp),
2658 0, false);
2659 if (ret)
2660 dsc_needed = true;
2661 }
2662
2663 if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, pipe_config)) {
2664 drm_dbg_kms(display->drm, "DSC required but not available\n");
2665 return -EINVAL;
2666 }
2667
2668 if (dsc_needed) {
2669 drm_dbg_kms(display->drm,
2670 "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2671 str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2672 str_yes_no(intel_dp->force_dsc_en));
2673
2674 if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
2675 respect_downstream_limits,
2676 true,
2677 &limits))
2678 return -EINVAL;
2679
2680 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2681 conn_state, &limits, 64);
2682 if (ret < 0)
2683 return ret;
2684 }
2685
2686 drm_dbg_kms(display->drm,
2687 "DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2688 pipe_config->lane_count, pipe_config->port_clock,
2689 pipe_config->pipe_bpp,
2690 FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2691 intel_dp_config_required_rate(pipe_config),
2692 intel_dp_max_link_data_rate(intel_dp,
2693 pipe_config->port_clock,
2694 pipe_config->lane_count));
2695
2696 return 0;
2697 }
2698
intel_dp_limited_color_range(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2699 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2700 const struct drm_connector_state *conn_state)
2701 {
2702 const struct intel_digital_connector_state *intel_conn_state =
2703 to_intel_digital_connector_state(conn_state);
2704 const struct drm_display_mode *adjusted_mode =
2705 &crtc_state->hw.adjusted_mode;
2706
2707 /*
2708 * Our YCbCr output is always limited range.
2709 * crtc_state->limited_color_range only applies to RGB,
2710 * and it must never be set for YCbCr or we risk setting
2711 * some conflicting bits in TRANSCONF which will mess up
2712 * the colors on the monitor.
2713 */
2714 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2715 return false;
2716
2717 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2718 /*
2719 * See:
2720 * CEA-861-E - 5.1 Default Encoding Parameters
2721 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2722 */
2723 return crtc_state->pipe_bpp != 18 &&
2724 drm_default_rgb_quant_range(adjusted_mode) ==
2725 HDMI_QUANTIZATION_RANGE_LIMITED;
2726 } else {
2727 return intel_conn_state->broadcast_rgb ==
2728 INTEL_BROADCAST_RGB_LIMITED;
2729 }
2730 }
2731
intel_dp_port_has_audio(struct intel_display * display,enum port port)2732 static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
2733 {
2734 if (display->platform.g4x)
2735 return false;
2736 if (DISPLAY_VER(display) < 12 && port == PORT_A)
2737 return false;
2738
2739 return true;
2740 }
2741
intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state,struct drm_dp_vsc_sdp * vsc)2742 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2743 const struct drm_connector_state *conn_state,
2744 struct drm_dp_vsc_sdp *vsc)
2745 {
2746 struct intel_display *display = to_intel_display(crtc_state);
2747
2748 if (crtc_state->has_panel_replay) {
2749 /*
2750 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2751 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2752 * Encoding/Colorimetry Format indication.
2753 */
2754 vsc->revision = 0x7;
2755 } else {
2756 /*
2757 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2758 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2759 * Colorimetry Format indication.
2760 */
2761 vsc->revision = 0x5;
2762 }
2763
2764 vsc->length = 0x13;
2765
2766 /* DP 1.4a spec, Table 2-120 */
2767 switch (crtc_state->output_format) {
2768 case INTEL_OUTPUT_FORMAT_YCBCR444:
2769 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2770 break;
2771 case INTEL_OUTPUT_FORMAT_YCBCR420:
2772 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2773 break;
2774 case INTEL_OUTPUT_FORMAT_RGB:
2775 default:
2776 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2777 }
2778
2779 switch (conn_state->colorspace) {
2780 case DRM_MODE_COLORIMETRY_BT709_YCC:
2781 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2782 break;
2783 case DRM_MODE_COLORIMETRY_XVYCC_601:
2784 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2785 break;
2786 case DRM_MODE_COLORIMETRY_XVYCC_709:
2787 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2788 break;
2789 case DRM_MODE_COLORIMETRY_SYCC_601:
2790 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2791 break;
2792 case DRM_MODE_COLORIMETRY_OPYCC_601:
2793 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2794 break;
2795 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2796 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2797 break;
2798 case DRM_MODE_COLORIMETRY_BT2020_RGB:
2799 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2800 break;
2801 case DRM_MODE_COLORIMETRY_BT2020_YCC:
2802 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2803 break;
2804 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2805 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2806 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2807 break;
2808 default:
2809 /*
2810 * RGB->YCBCR color conversion uses the BT.709
2811 * color space.
2812 */
2813 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2814 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2815 else
2816 vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2817 break;
2818 }
2819
2820 vsc->bpc = crtc_state->pipe_bpp / 3;
2821
2822 /* only RGB pixelformat supports 6 bpc */
2823 drm_WARN_ON(display->drm,
2824 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2825
2826 /* all YCbCr are always limited range */
2827 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2828 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2829 }
2830
intel_dp_compute_as_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state)2831 static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2832 struct intel_crtc_state *crtc_state)
2833 {
2834 struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2835 const struct drm_display_mode *adjusted_mode =
2836 &crtc_state->hw.adjusted_mode;
2837
2838 if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
2839 return;
2840
2841 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2842
2843 as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2844 as_sdp->length = 0x9;
2845 as_sdp->duration_incr_ms = 0;
2846 as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
2847
2848 if (crtc_state->cmrr.enable) {
2849 as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
2850 as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
2851 as_sdp->target_rr_divider = true;
2852 } else {
2853 as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
2854 as_sdp->target_rr = 0;
2855 }
2856 }
2857
intel_dp_compute_vsc_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2858 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2859 struct intel_crtc_state *crtc_state,
2860 const struct drm_connector_state *conn_state)
2861 {
2862 struct drm_dp_vsc_sdp *vsc;
2863
2864 if ((!intel_dp->colorimetry_support ||
2865 !intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2866 !crtc_state->has_psr)
2867 return;
2868
2869 vsc = &crtc_state->infoframes.vsc;
2870
2871 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2872 vsc->sdp_type = DP_SDP_VSC;
2873
2874 /* Needs colorimetry */
2875 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2876 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2877 vsc);
2878 } else if (crtc_state->has_panel_replay) {
2879 /*
2880 * [Panel Replay without colorimetry info]
2881 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2882 * VSC SDP supporting 3D stereo + Panel Replay.
2883 */
2884 vsc->revision = 0x6;
2885 vsc->length = 0x10;
2886 } else if (crtc_state->has_sel_update) {
2887 /*
2888 * [PSR2 without colorimetry]
2889 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2890 * 3D stereo + PSR/PSR2 + Y-coordinate.
2891 */
2892 vsc->revision = 0x4;
2893 vsc->length = 0xe;
2894 } else {
2895 /*
2896 * [PSR1]
2897 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2898 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2899 * higher).
2900 */
2901 vsc->revision = 0x2;
2902 vsc->length = 0x8;
2903 }
2904 }
2905
2906 static void
intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp * intel_dp,struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)2907 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2908 struct intel_crtc_state *crtc_state,
2909 const struct drm_connector_state *conn_state)
2910 {
2911 struct intel_display *display = to_intel_display(intel_dp);
2912 int ret;
2913 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2914
2915 if (!conn_state->hdr_output_metadata)
2916 return;
2917
2918 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2919
2920 if (ret) {
2921 drm_dbg_kms(display->drm,
2922 "couldn't set HDR metadata in infoframe\n");
2923 return;
2924 }
2925
2926 crtc_state->infoframes.enable |=
2927 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2928 }
2929
can_enable_drrs(struct intel_connector * connector,const struct intel_crtc_state * pipe_config,const struct drm_display_mode * downclock_mode)2930 static bool can_enable_drrs(struct intel_connector *connector,
2931 const struct intel_crtc_state *pipe_config,
2932 const struct drm_display_mode *downclock_mode)
2933 {
2934 struct intel_display *display = to_intel_display(connector);
2935
2936 if (pipe_config->vrr.enable)
2937 return false;
2938
2939 /*
2940 * DRRS and PSR can't be enable together, so giving preference to PSR
2941 * as it allows more power-savings by complete shutting down display,
2942 * so to guarantee this, intel_drrs_compute_config() must be called
2943 * after intel_psr_compute_config().
2944 */
2945 if (pipe_config->has_psr)
2946 return false;
2947
2948 /* FIXME missing FDI M2/N2 etc. */
2949 if (pipe_config->has_pch_encoder)
2950 return false;
2951
2952 if (!intel_cpu_transcoder_has_drrs(display, pipe_config->cpu_transcoder))
2953 return false;
2954
2955 return downclock_mode &&
2956 intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
2957 }
2958
2959 static void
intel_dp_drrs_compute_config(struct intel_connector * connector,struct intel_crtc_state * pipe_config,int link_bpp_x16)2960 intel_dp_drrs_compute_config(struct intel_connector *connector,
2961 struct intel_crtc_state *pipe_config,
2962 int link_bpp_x16)
2963 {
2964 struct intel_display *display = to_intel_display(connector);
2965 const struct drm_display_mode *downclock_mode =
2966 intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2967 int pixel_clock;
2968
2969 /*
2970 * FIXME all joined pipes share the same transcoder.
2971 * Need to account for that when updating M/N live.
2972 */
2973 if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
2974 pipe_config->update_m_n = true;
2975
2976 if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
2977 if (intel_cpu_transcoder_has_m2_n2(display, pipe_config->cpu_transcoder))
2978 intel_zero_m_n(&pipe_config->dp_m2_n2);
2979 return;
2980 }
2981
2982 if (display->platform.ironlake || display->platform.sandybridge ||
2983 display->platform.ivybridge)
2984 pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
2985
2986 pipe_config->has_drrs = true;
2987
2988 pixel_clock = downclock_mode->clock;
2989 if (pipe_config->splitter.enable)
2990 pixel_clock /= pipe_config->splitter.link_count;
2991
2992 intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,
2993 pipe_config->port_clock,
2994 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
2995 &pipe_config->dp_m2_n2);
2996
2997 /* FIXME: abstract this better */
2998 if (pipe_config->splitter.enable)
2999 pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
3000 }
3001
intel_dp_has_audio(struct intel_encoder * encoder,const struct drm_connector_state * conn_state)3002 static bool intel_dp_has_audio(struct intel_encoder *encoder,
3003 const struct drm_connector_state *conn_state)
3004 {
3005 struct intel_display *display = to_intel_display(encoder);
3006 const struct intel_digital_connector_state *intel_conn_state =
3007 to_intel_digital_connector_state(conn_state);
3008 struct intel_connector *connector =
3009 to_intel_connector(conn_state->connector);
3010
3011 if (!intel_dp_port_has_audio(display, encoder->port))
3012 return false;
3013
3014 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
3015 return connector->base.display_info.has_audio;
3016 else
3017 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
3018 }
3019
3020 static int
intel_dp_compute_output_format(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state,bool respect_downstream_limits)3021 intel_dp_compute_output_format(struct intel_encoder *encoder,
3022 struct intel_crtc_state *crtc_state,
3023 struct drm_connector_state *conn_state,
3024 bool respect_downstream_limits)
3025 {
3026 struct intel_display *display = to_intel_display(encoder);
3027 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3028 struct intel_connector *connector = intel_dp->attached_connector;
3029 const struct drm_display_info *info = &connector->base.display_info;
3030 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3031 bool ycbcr_420_only;
3032 int ret;
3033
3034 ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
3035
3036 if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
3037 drm_dbg_kms(display->drm,
3038 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3039 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
3040 } else {
3041 crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);
3042 }
3043
3044 crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);
3045
3046 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
3047 respect_downstream_limits);
3048 if (ret) {
3049 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3050 !connector->base.ycbcr_420_allowed ||
3051 !drm_mode_is_420_also(info, adjusted_mode))
3052 return ret;
3053
3054 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
3055 crtc_state->output_format = intel_dp_output_format(connector,
3056 crtc_state->sink_format);
3057 ret = intel_dp_compute_link_config(encoder, crtc_state, conn_state,
3058 respect_downstream_limits);
3059 }
3060
3061 return ret;
3062 }
3063
3064 void
intel_dp_audio_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)3065 intel_dp_audio_compute_config(struct intel_encoder *encoder,
3066 struct intel_crtc_state *pipe_config,
3067 struct drm_connector_state *conn_state)
3068 {
3069 pipe_config->has_audio =
3070 intel_dp_has_audio(encoder, conn_state) &&
3071 intel_audio_compute_config(encoder, pipe_config, conn_state);
3072
3073 pipe_config->sdp_split_enable = pipe_config->has_audio &&
3074 intel_dp_is_uhbr(pipe_config);
3075 }
3076
3077 void
intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3078 intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
3079 struct intel_encoder *encoder,
3080 const struct intel_crtc_state *crtc_state)
3081 {
3082 struct intel_connector *connector;
3083 struct intel_digital_connector_state *conn_state;
3084 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3085 int i;
3086
3087 if (intel_dp->needs_modeset_retry)
3088 return;
3089
3090 intel_dp->needs_modeset_retry = true;
3091
3092 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3093 intel_connector_queue_modeset_retry_work(intel_dp->attached_connector);
3094
3095 return;
3096 }
3097
3098 for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
3099 if (!conn_state->base.crtc)
3100 continue;
3101
3102 if (connector->mst.dp == intel_dp)
3103 intel_connector_queue_modeset_retry_work(connector);
3104 }
3105 }
3106
3107 int
intel_dp_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)3108 intel_dp_compute_config(struct intel_encoder *encoder,
3109 struct intel_crtc_state *pipe_config,
3110 struct drm_connector_state *conn_state)
3111 {
3112 struct intel_display *display = to_intel_display(encoder);
3113 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3114 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3115 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3116 const struct drm_display_mode *fixed_mode;
3117 struct intel_connector *connector = intel_dp->attached_connector;
3118 int ret = 0, link_bpp_x16;
3119
3120 fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);
3121 if (intel_dp_is_edp(intel_dp) && fixed_mode) {
3122 ret = intel_panel_compute_config(connector, adjusted_mode);
3123 if (ret)
3124 return ret;
3125 }
3126
3127 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
3128 return -EINVAL;
3129
3130 if (!connector->base.interlace_allowed &&
3131 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
3132 return -EINVAL;
3133
3134 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3135 return -EINVAL;
3136
3137 if (intel_dp_hdisplay_bad(display, adjusted_mode->crtc_hdisplay))
3138 return -EINVAL;
3139
3140 /*
3141 * Try to respect downstream TMDS clock limits first, if
3142 * that fails assume the user might know something we don't.
3143 */
3144 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, true);
3145 if (ret)
3146 ret = intel_dp_compute_output_format(encoder, pipe_config, conn_state, false);
3147 if (ret)
3148 return ret;
3149
3150 if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
3151 pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3152 ret = intel_pfit_compute_config(pipe_config, conn_state);
3153 if (ret)
3154 return ret;
3155 }
3156
3157 pipe_config->limited_color_range =
3158 intel_dp_limited_color_range(pipe_config, conn_state);
3159
3160 if (intel_dp_is_uhbr(pipe_config)) {
3161 /* 128b/132b SST also needs this */
3162 pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
3163 } else {
3164 pipe_config->enhanced_framing =
3165 drm_dp_enhanced_frame_cap(intel_dp->dpcd);
3166 }
3167
3168 if (pipe_config->dsc.compression_enable)
3169 link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
3170 else
3171 link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,
3172 pipe_config->pipe_bpp));
3173
3174 if (intel_dp->mso_link_count) {
3175 int n = intel_dp->mso_link_count;
3176 int overlap = intel_dp->mso_pixel_overlap;
3177
3178 pipe_config->splitter.enable = true;
3179 pipe_config->splitter.link_count = n;
3180 pipe_config->splitter.pixel_overlap = overlap;
3181
3182 drm_dbg_kms(display->drm,
3183 "MSO link count %d, pixel overlap %d\n",
3184 n, overlap);
3185
3186 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
3187 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
3188 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
3189 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
3190 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
3191 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
3192 adjusted_mode->crtc_clock /= n;
3193 }
3194
3195 intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3196
3197 if (!intel_dp_is_uhbr(pipe_config)) {
3198 intel_link_compute_m_n(link_bpp_x16,
3199 pipe_config->lane_count,
3200 adjusted_mode->crtc_clock,
3201 pipe_config->port_clock,
3202 intel_dp_bw_fec_overhead(pipe_config->fec_enable),
3203 &pipe_config->dp_m_n);
3204 }
3205
3206 /* FIXME: abstract this better */
3207 if (pipe_config->splitter.enable)
3208 pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
3209
3210 intel_vrr_compute_config(pipe_config, conn_state);
3211 intel_dp_compute_as_sdp(intel_dp, pipe_config);
3212 intel_psr_compute_config(intel_dp, pipe_config, conn_state);
3213 intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
3214 intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3215 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
3216 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
3217
3218 return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3219 pipe_config);
3220 }
3221
intel_dp_set_link_params(struct intel_dp * intel_dp,int link_rate,int lane_count)3222 void intel_dp_set_link_params(struct intel_dp *intel_dp,
3223 int link_rate, int lane_count)
3224 {
3225 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3226 intel_dp->link_trained = false;
3227 intel_dp->needs_modeset_retry = false;
3228 intel_dp->link_rate = link_rate;
3229 intel_dp->lane_count = lane_count;
3230 }
3231
intel_dp_reset_link_params(struct intel_dp * intel_dp)3232 void intel_dp_reset_link_params(struct intel_dp *intel_dp)
3233 {
3234 intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
3235 intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
3236 intel_dp->link.mst_probed_lane_count = 0;
3237 intel_dp->link.mst_probed_rate = 0;
3238 intel_dp->link.retrain_disabled = false;
3239 intel_dp->link.seq_train_failures = 0;
3240 }
3241
3242 /* Enable backlight PWM and backlight PP control. */
intel_edp_backlight_on(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3243 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3244 const struct drm_connector_state *conn_state)
3245 {
3246 struct intel_display *display = to_intel_display(crtc_state);
3247 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3248
3249 if (!intel_dp_is_edp(intel_dp))
3250 return;
3251
3252 drm_dbg_kms(display->drm, "\n");
3253
3254 intel_backlight_enable(crtc_state, conn_state);
3255 intel_pps_backlight_on(intel_dp);
3256 }
3257
3258 /* Disable backlight PP control and backlight PWM. */
intel_edp_backlight_off(const struct drm_connector_state * old_conn_state)3259 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3260 {
3261 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3262 struct intel_display *display = to_intel_display(intel_dp);
3263
3264 if (!intel_dp_is_edp(intel_dp))
3265 return;
3266
3267 drm_dbg_kms(display->drm, "\n");
3268
3269 intel_pps_backlight_off(intel_dp);
3270 intel_backlight_disable(old_conn_state);
3271 }
3272
downstream_hpd_needs_d0(struct intel_dp * intel_dp)3273 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3274 {
3275 /*
3276 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3277 * be capable of signalling downstream hpd with a long pulse.
3278 * Whether or not that means D3 is safe to use is not clear,
3279 * but let's assume so until proven otherwise.
3280 *
3281 * FIXME should really check all downstream ports...
3282 */
3283 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3284 drm_dp_is_branch(intel_dp->dpcd) &&
3285 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3286 }
3287
3288 static int
write_dsc_decompression_flag(struct drm_dp_aux * aux,u8 flag,bool set)3289 write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3290 {
3291 int err;
3292 u8 val;
3293
3294 err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);
3295 if (err < 0)
3296 return err;
3297
3298 if (set)
3299 val |= flag;
3300 else
3301 val &= ~flag;
3302
3303 return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);
3304 }
3305
3306 static void
intel_dp_sink_set_dsc_decompression(struct intel_connector * connector,bool enable)3307 intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3308 bool enable)
3309 {
3310 struct intel_display *display = to_intel_display(connector);
3311
3312 if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,
3313 DP_DECOMPRESSION_EN, enable) < 0)
3314 drm_dbg_kms(display->drm,
3315 "Failed to %s sink decompression state\n",
3316 str_enable_disable(enable));
3317 }
3318
3319 static void
intel_dp_sink_set_dsc_passthrough(const struct intel_connector * connector,bool enable)3320 intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3321 bool enable)
3322 {
3323 struct intel_display *display = to_intel_display(connector);
3324 struct drm_dp_aux *aux = connector->mst.port ?
3325 connector->mst.port->passthrough_aux : NULL;
3326
3327 if (!aux)
3328 return;
3329
3330 if (write_dsc_decompression_flag(aux,
3331 DP_DSC_PASSTHROUGH_EN, enable) < 0)
3332 drm_dbg_kms(display->drm,
3333 "Failed to %s sink compression passthrough state\n",
3334 str_enable_disable(enable));
3335 }
3336
intel_dp_dsc_aux_ref_count(struct intel_atomic_state * state,const struct intel_connector * connector,bool for_get_ref)3337 static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3338 const struct intel_connector *connector,
3339 bool for_get_ref)
3340 {
3341 struct intel_display *display = to_intel_display(state);
3342 struct drm_connector *_connector_iter;
3343 struct drm_connector_state *old_conn_state;
3344 struct drm_connector_state *new_conn_state;
3345 int ref_count = 0;
3346 int i;
3347
3348 /*
3349 * On SST the decompression AUX device won't be shared, each connector
3350 * uses for this its own AUX targeting the sink device.
3351 */
3352 if (!connector->mst.dp)
3353 return connector->dp.dsc_decompression_enabled ? 1 : 0;
3354
3355 for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3356 old_conn_state, new_conn_state, i) {
3357 const struct intel_connector *
3358 connector_iter = to_intel_connector(_connector_iter);
3359
3360 if (connector_iter->mst.dp != connector->mst.dp)
3361 continue;
3362
3363 if (!connector_iter->dp.dsc_decompression_enabled)
3364 continue;
3365
3366 drm_WARN_ON(display->drm,
3367 (for_get_ref && !new_conn_state->crtc) ||
3368 (!for_get_ref && !old_conn_state->crtc));
3369
3370 if (connector_iter->dp.dsc_decompression_aux ==
3371 connector->dp.dsc_decompression_aux)
3372 ref_count++;
3373 }
3374
3375 return ref_count;
3376 }
3377
intel_dp_dsc_aux_get_ref(struct intel_atomic_state * state,struct intel_connector * connector)3378 static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3379 struct intel_connector *connector)
3380 {
3381 bool ret = intel_dp_dsc_aux_ref_count(state, connector, true) == 0;
3382
3383 connector->dp.dsc_decompression_enabled = true;
3384
3385 return ret;
3386 }
3387
intel_dp_dsc_aux_put_ref(struct intel_atomic_state * state,struct intel_connector * connector)3388 static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3389 struct intel_connector *connector)
3390 {
3391 connector->dp.dsc_decompression_enabled = false;
3392
3393 return intel_dp_dsc_aux_ref_count(state, connector, false) == 0;
3394 }
3395
3396 /**
3397 * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3398 * @state: atomic state
3399 * @connector: connector to enable the decompression for
3400 * @new_crtc_state: new state for the CRTC driving @connector
3401 *
3402 * Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3403 * register of the appropriate sink/branch device. On SST this is always the
3404 * sink device, whereas on MST based on each device's DSC capabilities it's
3405 * either the last branch device (enabling decompression in it) or both the
3406 * last branch device (enabling passthrough in it) and the sink device
3407 * (enabling decompression in it).
3408 */
intel_dp_sink_enable_decompression(struct intel_atomic_state * state,struct intel_connector * connector,const struct intel_crtc_state * new_crtc_state)3409 void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3410 struct intel_connector *connector,
3411 const struct intel_crtc_state *new_crtc_state)
3412 {
3413 struct intel_display *display = to_intel_display(state);
3414
3415 if (!new_crtc_state->dsc.compression_enable)
3416 return;
3417
3418 if (drm_WARN_ON(display->drm,
3419 !connector->dp.dsc_decompression_aux ||
3420 connector->dp.dsc_decompression_enabled))
3421 return;
3422
3423 if (!intel_dp_dsc_aux_get_ref(state, connector))
3424 return;
3425
3426 intel_dp_sink_set_dsc_passthrough(connector, true);
3427 intel_dp_sink_set_dsc_decompression(connector, true);
3428 }
3429
3430 /**
3431 * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3432 * @state: atomic state
3433 * @connector: connector to disable the decompression for
3434 * @old_crtc_state: old state for the CRTC driving @connector
3435 *
3436 * Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3437 * register of the appropriate sink/branch device, corresponding to the
3438 * sequence in intel_dp_sink_enable_decompression().
3439 */
intel_dp_sink_disable_decompression(struct intel_atomic_state * state,struct intel_connector * connector,const struct intel_crtc_state * old_crtc_state)3440 void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3441 struct intel_connector *connector,
3442 const struct intel_crtc_state *old_crtc_state)
3443 {
3444 struct intel_display *display = to_intel_display(state);
3445
3446 if (!old_crtc_state->dsc.compression_enable)
3447 return;
3448
3449 if (drm_WARN_ON(display->drm,
3450 !connector->dp.dsc_decompression_aux ||
3451 !connector->dp.dsc_decompression_enabled))
3452 return;
3453
3454 if (!intel_dp_dsc_aux_put_ref(state, connector))
3455 return;
3456
3457 intel_dp_sink_set_dsc_decompression(connector, false);
3458 intel_dp_sink_set_dsc_passthrough(connector, false);
3459 }
3460
3461 static void
intel_dp_init_source_oui(struct intel_dp * intel_dp)3462 intel_dp_init_source_oui(struct intel_dp *intel_dp)
3463 {
3464 struct intel_display *display = to_intel_display(intel_dp);
3465 u8 oui[] = { 0x00, 0xaa, 0x01 };
3466 u8 buf[3] = {};
3467
3468 if (READ_ONCE(intel_dp->oui_valid))
3469 return;
3470
3471 WRITE_ONCE(intel_dp->oui_valid, true);
3472
3473 /*
3474 * During driver init, we want to be careful and avoid changing the source OUI if it's
3475 * already set to what we want, so as to avoid clearing any state by accident
3476 */
3477 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)
3478 drm_dbg_kms(display->drm, "Failed to read source OUI\n");
3479
3480 if (memcmp(oui, buf, sizeof(oui)) == 0) {
3481 /* Assume the OUI was written now. */
3482 intel_dp->last_oui_write = jiffies;
3483 return;
3484 }
3485
3486 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {
3487 drm_dbg_kms(display->drm, "Failed to write source OUI\n");
3488 WRITE_ONCE(intel_dp->oui_valid, false);
3489 }
3490
3491 intel_dp->last_oui_write = jiffies;
3492 }
3493
intel_dp_invalidate_source_oui(struct intel_dp * intel_dp)3494 void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3495 {
3496 WRITE_ONCE(intel_dp->oui_valid, false);
3497 }
3498
intel_dp_wait_source_oui(struct intel_dp * intel_dp)3499 void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3500 {
3501 struct intel_display *display = to_intel_display(intel_dp);
3502 struct intel_connector *connector = intel_dp->attached_connector;
3503
3504 drm_dbg_kms(display->drm,
3505 "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3506 connector->base.base.id, connector->base.name,
3507 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3508
3509 wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,
3510 connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3511 }
3512
3513 /* If the device supports it, try to set the power state appropriately */
intel_dp_set_power(struct intel_dp * intel_dp,u8 mode)3514 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3515 {
3516 struct intel_display *display = to_intel_display(intel_dp);
3517 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3518 int ret, i;
3519
3520 /* Should have a valid DPCD by this point */
3521 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3522 return;
3523
3524 if (mode != DP_SET_POWER_D0) {
3525 if (downstream_hpd_needs_d0(intel_dp))
3526 return;
3527
3528 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3529 } else {
3530 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3531
3532 intel_lspcon_resume(dig_port);
3533
3534 /* Write the source OUI as early as possible */
3535 intel_dp_init_source_oui(intel_dp);
3536
3537 /*
3538 * When turning on, we need to retry for 1ms to give the sink
3539 * time to wake up.
3540 */
3541 for (i = 0; i < 3; i++) {
3542 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3543 if (ret == 1)
3544 break;
3545 msleep(1);
3546 }
3547
3548 if (ret == 1 && intel_lspcon_active(dig_port))
3549 intel_lspcon_wait_pcon_mode(dig_port);
3550 }
3551
3552 if (ret != 1)
3553 drm_dbg_kms(display->drm,
3554 "[ENCODER:%d:%s] Set power to %s failed\n",
3555 encoder->base.base.id, encoder->base.name,
3556 mode == DP_SET_POWER_D0 ? "D0" : "D3");
3557 }
3558
3559 static bool
3560 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3561
3562 /**
3563 * intel_dp_sync_state - sync the encoder state during init/resume
3564 * @encoder: intel encoder to sync
3565 * @crtc_state: state for the CRTC connected to the encoder
3566 *
3567 * Sync any state stored in the encoder wrt. HW state during driver init
3568 * and system resume.
3569 */
intel_dp_sync_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3570 void intel_dp_sync_state(struct intel_encoder *encoder,
3571 const struct intel_crtc_state *crtc_state)
3572 {
3573 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3574 bool dpcd_updated = false;
3575
3576 /*
3577 * Don't clobber DPCD if it's been already read out during output
3578 * setup (eDP) or detect.
3579 */
3580 if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3581 intel_dp_get_dpcd(intel_dp);
3582 dpcd_updated = true;
3583 }
3584
3585 intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3586
3587 if (crtc_state) {
3588 intel_dp_reset_link_params(intel_dp);
3589 intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
3590 intel_dp->link_trained = true;
3591 }
3592 }
3593
intel_dp_initial_fastset_check(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)3594 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3595 struct intel_crtc_state *crtc_state)
3596 {
3597 struct intel_display *display = to_intel_display(encoder);
3598 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3599 bool fastset = true;
3600
3601 /*
3602 * If BIOS has set an unsupported or non-standard link rate for some
3603 * reason force an encoder recompute and full modeset.
3604 */
3605 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3606 crtc_state->port_clock) < 0) {
3607 drm_dbg_kms(display->drm,
3608 "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3609 encoder->base.base.id, encoder->base.name);
3610 crtc_state->uapi.connectors_changed = true;
3611 fastset = false;
3612 }
3613
3614 /*
3615 * FIXME hack to force full modeset when DSC is being used.
3616 *
3617 * As long as we do not have full state readout and config comparison
3618 * of crtc_state->dsc, we have no way to ensure reliable fastset.
3619 * Remove once we have readout for DSC.
3620 */
3621 if (crtc_state->dsc.compression_enable) {
3622 drm_dbg_kms(display->drm,
3623 "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3624 encoder->base.base.id, encoder->base.name);
3625 crtc_state->uapi.mode_changed = true;
3626 fastset = false;
3627 }
3628
3629 if (CAN_PANEL_REPLAY(intel_dp)) {
3630 drm_dbg_kms(display->drm,
3631 "[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3632 encoder->base.base.id, encoder->base.name);
3633 crtc_state->uapi.mode_changed = true;
3634 fastset = false;
3635 }
3636
3637 return fastset;
3638 }
3639
intel_dp_get_pcon_dsc_cap(struct intel_dp * intel_dp)3640 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3641 {
3642 struct intel_display *display = to_intel_display(intel_dp);
3643
3644 /* Clear the cached register set to avoid using stale values */
3645
3646 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3647
3648 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,
3649 intel_dp->pcon_dsc_dpcd,
3650 sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3651 drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
3652 DP_PCON_DSC_ENCODER);
3653
3654 drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3655 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3656 }
3657
intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)3658 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3659 {
3660 static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3661 int i;
3662
3663 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3664 if (frl_bw_mask & (1 << i))
3665 return bw_gbps[i];
3666 }
3667 return 0;
3668 }
3669
intel_dp_pcon_set_frl_mask(int max_frl)3670 static int intel_dp_pcon_set_frl_mask(int max_frl)
3671 {
3672 switch (max_frl) {
3673 case 48:
3674 return DP_PCON_FRL_BW_MASK_48GBPS;
3675 case 40:
3676 return DP_PCON_FRL_BW_MASK_40GBPS;
3677 case 32:
3678 return DP_PCON_FRL_BW_MASK_32GBPS;
3679 case 24:
3680 return DP_PCON_FRL_BW_MASK_24GBPS;
3681 case 18:
3682 return DP_PCON_FRL_BW_MASK_18GBPS;
3683 case 9:
3684 return DP_PCON_FRL_BW_MASK_9GBPS;
3685 }
3686
3687 return 0;
3688 }
3689
intel_dp_hdmi_sink_max_frl(struct intel_dp * intel_dp)3690 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3691 {
3692 struct intel_connector *connector = intel_dp->attached_connector;
3693 const struct drm_display_info *info = &connector->base.display_info;
3694 int max_frl_rate;
3695 int max_lanes, rate_per_lane;
3696 int max_dsc_lanes, dsc_rate_per_lane;
3697
3698 max_lanes = info->hdmi.max_lanes;
3699 rate_per_lane = info->hdmi.max_frl_rate_per_lane;
3700 max_frl_rate = max_lanes * rate_per_lane;
3701
3702 if (info->hdmi.dsc_cap.v_1p2) {
3703 max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
3704 dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
3705 if (max_dsc_lanes && dsc_rate_per_lane)
3706 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3707 }
3708
3709 return max_frl_rate;
3710 }
3711
3712 static bool
intel_dp_pcon_is_frl_trained(struct intel_dp * intel_dp,u8 max_frl_bw_mask,u8 * frl_trained_mask)3713 intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3714 u8 max_frl_bw_mask, u8 *frl_trained_mask)
3715 {
3716 if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
3717 drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3718 *frl_trained_mask >= max_frl_bw_mask)
3719 return true;
3720
3721 return false;
3722 }
3723
intel_dp_pcon_start_frl_training(struct intel_dp * intel_dp)3724 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3725 {
3726 struct intel_display *display = to_intel_display(intel_dp);
3727 #define TIMEOUT_FRL_READY_MS 500
3728 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3729 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3730 u8 max_frl_bw_mask = 0, frl_trained_mask;
3731 bool is_active;
3732
3733 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3734 drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3735
3736 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3737 drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
3738 max_edid_frl_bw);
3739
3740 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3741
3742 if (max_frl_bw <= 0)
3743 return -EINVAL;
3744
3745 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
3746 drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3747
3748 if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))
3749 goto frl_trained;
3750
3751 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
3752 if (ret < 0)
3753 return ret;
3754 /* Wait for PCON to be FRL Ready */
3755 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);
3756
3757 if (!is_active)
3758 return -ETIMEDOUT;
3759
3760 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
3761 DP_PCON_ENABLE_SEQUENTIAL_LINK);
3762 if (ret < 0)
3763 return ret;
3764 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,
3765 DP_PCON_FRL_LINK_TRAIN_NORMAL);
3766 if (ret < 0)
3767 return ret;
3768 ret = drm_dp_pcon_frl_enable(&intel_dp->aux);
3769 if (ret < 0)
3770 return ret;
3771 /*
3772 * Wait for FRL to be completed
3773 * Check if the HDMI Link is up and active.
3774 */
3775 wait_for(is_active =
3776 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3777 TIMEOUT_HDMI_LINK_ACTIVE_MS);
3778
3779 if (!is_active)
3780 return -ETIMEDOUT;
3781
3782 frl_trained:
3783 drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3784 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);
3785 intel_dp->frl.is_trained = true;
3786 drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
3787 intel_dp->frl.trained_rate_gbps);
3788
3789 return 0;
3790 }
3791
intel_dp_is_hdmi_2_1_sink(struct intel_dp * intel_dp)3792 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
3793 {
3794 if (drm_dp_is_branch(intel_dp->dpcd) &&
3795 intel_dp_has_hdmi_sink(intel_dp) &&
3796 intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
3797 return true;
3798
3799 return false;
3800 }
3801
3802 static
intel_dp_pcon_set_tmds_mode(struct intel_dp * intel_dp)3803 int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
3804 {
3805 int ret;
3806 u8 buf = 0;
3807
3808 /* Set PCON source control mode */
3809 buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
3810
3811 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3812 if (ret < 0)
3813 return ret;
3814
3815 /* Set HDMI LINK ENABLE */
3816 buf |= DP_PCON_ENABLE_HDMI_LINK;
3817 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3818 if (ret < 0)
3819 return ret;
3820
3821 return 0;
3822 }
3823
intel_dp_check_frl_training(struct intel_dp * intel_dp)3824 void intel_dp_check_frl_training(struct intel_dp *intel_dp)
3825 {
3826 struct intel_display *display = to_intel_display(intel_dp);
3827
3828 /*
3829 * Always go for FRL training if:
3830 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
3831 * -sink is HDMI2.1
3832 */
3833 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
3834 !intel_dp_is_hdmi_2_1_sink(intel_dp) ||
3835 intel_dp->frl.is_trained)
3836 return;
3837
3838 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
3839 int ret, mode;
3840
3841 drm_dbg(display->drm,
3842 "Couldn't set FRL mode, continuing with TMDS mode\n");
3843 ret = intel_dp_pcon_set_tmds_mode(intel_dp);
3844 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);
3845
3846 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
3847 drm_dbg(display->drm,
3848 "Issue with PCON, cannot set TMDS mode\n");
3849 } else {
3850 drm_dbg(display->drm, "FRL training Completed\n");
3851 }
3852 }
3853
3854 static int
intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state * crtc_state)3855 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
3856 {
3857 int vactive = crtc_state->hw.adjusted_mode.vdisplay;
3858
3859 return intel_hdmi_dsc_get_slice_height(vactive);
3860 }
3861
3862 static int
intel_dp_pcon_dsc_enc_slices(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3863 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
3864 const struct intel_crtc_state *crtc_state)
3865 {
3866 struct intel_connector *connector = intel_dp->attached_connector;
3867 const struct drm_display_info *info = &connector->base.display_info;
3868 int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;
3869 int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;
3870 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);
3871 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);
3872
3873 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices,
3874 pcon_max_slice_width,
3875 hdmi_max_slices, hdmi_throughput);
3876 }
3877
3878 static int
intel_dp_pcon_dsc_enc_bpp(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state,int num_slices,int slice_width)3879 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
3880 const struct intel_crtc_state *crtc_state,
3881 int num_slices, int slice_width)
3882 {
3883 struct intel_connector *connector = intel_dp->attached_connector;
3884 const struct drm_display_info *info = &connector->base.display_info;
3885 int output_format = crtc_state->output_format;
3886 bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;
3887 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);
3888 int hdmi_max_chunk_bytes =
3889 info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
3890
3891 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,
3892 num_slices, output_format, hdmi_all_bpp,
3893 hdmi_max_chunk_bytes);
3894 }
3895
3896 void
intel_dp_pcon_dsc_configure(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3897 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
3898 const struct intel_crtc_state *crtc_state)
3899 {
3900 struct intel_display *display = to_intel_display(intel_dp);
3901 struct intel_connector *connector = intel_dp->attached_connector;
3902 const struct drm_display_info *info;
3903 u8 pps_param[6];
3904 int slice_height;
3905 int slice_width;
3906 int num_slices;
3907 int bits_per_pixel;
3908 int ret;
3909 bool hdmi_is_dsc_1_2;
3910
3911 if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
3912 return;
3913
3914 if (!connector)
3915 return;
3916
3917 info = &connector->base.display_info;
3918
3919 hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;
3920
3921 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||
3922 !hdmi_is_dsc_1_2)
3923 return;
3924
3925 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
3926 if (!slice_height)
3927 return;
3928
3929 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
3930 if (!num_slices)
3931 return;
3932
3933 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
3934 num_slices);
3935
3936 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
3937 num_slices, slice_width);
3938 if (!bits_per_pixel)
3939 return;
3940
3941 pps_param[0] = slice_height & 0xFF;
3942 pps_param[1] = slice_height >> 8;
3943 pps_param[2] = slice_width & 0xFF;
3944 pps_param[3] = slice_width >> 8;
3945 pps_param[4] = bits_per_pixel & 0xFF;
3946 pps_param[5] = (bits_per_pixel >> 8) & 0x3;
3947
3948 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);
3949 if (ret < 0)
3950 drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
3951 }
3952
intel_dp_configure_protocol_converter(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3953 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
3954 const struct intel_crtc_state *crtc_state)
3955 {
3956 struct intel_display *display = to_intel_display(intel_dp);
3957 bool ycbcr444_to_420 = false;
3958 bool rgb_to_ycbcr = false;
3959 u8 tmp;
3960
3961 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
3962 return;
3963
3964 if (!drm_dp_is_branch(intel_dp->dpcd))
3965 return;
3966
3967 tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
3968
3969 if (drm_dp_dpcd_writeb(&intel_dp->aux,
3970 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
3971 drm_dbg_kms(display->drm,
3972 "Failed to %s protocol converter HDMI mode\n",
3973 str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
3974
3975 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3976 switch (crtc_state->output_format) {
3977 case INTEL_OUTPUT_FORMAT_YCBCR420:
3978 break;
3979 case INTEL_OUTPUT_FORMAT_YCBCR444:
3980 ycbcr444_to_420 = true;
3981 break;
3982 case INTEL_OUTPUT_FORMAT_RGB:
3983 rgb_to_ycbcr = true;
3984 ycbcr444_to_420 = true;
3985 break;
3986 default:
3987 MISSING_CASE(crtc_state->output_format);
3988 break;
3989 }
3990 } else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
3991 switch (crtc_state->output_format) {
3992 case INTEL_OUTPUT_FORMAT_YCBCR444:
3993 break;
3994 case INTEL_OUTPUT_FORMAT_RGB:
3995 rgb_to_ycbcr = true;
3996 break;
3997 default:
3998 MISSING_CASE(crtc_state->output_format);
3999 break;
4000 }
4001 }
4002
4003 tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4004
4005 if (drm_dp_dpcd_writeb(&intel_dp->aux,
4006 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4007 drm_dbg_kms(display->drm,
4008 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
4009 str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
4010
4011 tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
4012
4013 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)
4014 drm_dbg_kms(display->drm,
4015 "Failed to %s protocol converter RGB->YCbCr conversion mode\n",
4016 str_enable_disable(tmp));
4017 }
4018
intel_dp_get_colorimetry_status(struct intel_dp * intel_dp)4019 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4020 {
4021 u8 dprx = 0;
4022
4023 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4024 &dprx) != 1)
4025 return false;
4026 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4027 }
4028
intel_dp_read_dsc_dpcd(struct drm_dp_aux * aux,u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])4029 static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
4030 u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
4031 {
4032 if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd,
4033 DP_DSC_RECEIVER_CAP_SIZE) < 0) {
4034 drm_err(aux->drm_dev,
4035 "Failed to read DPCD register 0x%x\n",
4036 DP_DSC_SUPPORT);
4037 return;
4038 }
4039
4040 drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
4041 DP_DSC_RECEIVER_CAP_SIZE,
4042 dsc_dpcd);
4043 }
4044
intel_dp_get_dsc_sink_cap(u8 dpcd_rev,struct intel_connector * connector)4045 void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)
4046 {
4047 struct intel_display *display = to_intel_display(connector);
4048
4049 /*
4050 * Clear the cached register set to avoid using stale values
4051 * for the sinks that do not support DSC.
4052 */
4053 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
4054
4055 /* Clear fec_capable to avoid using stale values */
4056 connector->dp.fec_capability = 0;
4057
4058 if (dpcd_rev < DP_DPCD_REV_14)
4059 return;
4060
4061 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,
4062 connector->dp.dsc_dpcd);
4063
4064 if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4065 &connector->dp.fec_capability) < 0) {
4066 drm_err(display->drm, "Failed to read FEC DPCD register\n");
4067 return;
4068 }
4069
4070 drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
4071 connector->dp.fec_capability);
4072 }
4073
intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev,struct intel_connector * connector)4074 static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
4075 {
4076 if (edp_dpcd_rev < DP_EDP_14)
4077 return;
4078
4079 intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);
4080 }
4081
4082 static void
intel_dp_detect_dsc_caps(struct intel_dp * intel_dp,struct intel_connector * connector)4083 intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4084 {
4085 struct intel_display *display = to_intel_display(intel_dp);
4086
4087 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4088 if (!HAS_DSC(display))
4089 return;
4090
4091 if (intel_dp_is_edp(intel_dp))
4092 intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],
4093 connector);
4094 else
4095 intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],
4096 connector);
4097 }
4098
intel_edp_mso_mode_fixup(struct intel_connector * connector,struct drm_display_mode * mode)4099 static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4100 struct drm_display_mode *mode)
4101 {
4102 struct intel_display *display = to_intel_display(connector);
4103 struct intel_dp *intel_dp = intel_attached_dp(connector);
4104 int n = intel_dp->mso_link_count;
4105 int overlap = intel_dp->mso_pixel_overlap;
4106
4107 if (!mode || !n)
4108 return;
4109
4110 mode->hdisplay = (mode->hdisplay - overlap) * n;
4111 mode->hsync_start = (mode->hsync_start - overlap) * n;
4112 mode->hsync_end = (mode->hsync_end - overlap) * n;
4113 mode->htotal = (mode->htotal - overlap) * n;
4114 mode->clock *= n;
4115
4116 drm_mode_set_name(mode);
4117
4118 drm_dbg_kms(display->drm,
4119 "[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4120 connector->base.base.id, connector->base.name,
4121 DRM_MODE_ARG(mode));
4122 }
4123
intel_edp_fixup_vbt_bpp(struct intel_encoder * encoder,int pipe_bpp)4124 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4125 {
4126 struct intel_display *display = to_intel_display(encoder);
4127 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4128 struct intel_connector *connector = intel_dp->attached_connector;
4129
4130 if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
4131 /*
4132 * This is a big fat ugly hack.
4133 *
4134 * Some machines in UEFI boot mode provide us a VBT that has 18
4135 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4136 * unknown we fail to light up. Yet the same BIOS boots up with
4137 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4138 * max, not what it tells us to use.
4139 *
4140 * Note: This will still be broken if the eDP panel is not lit
4141 * up by the BIOS, and thus we can't get the mode at module
4142 * load.
4143 */
4144 drm_dbg_kms(display->drm,
4145 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4146 pipe_bpp, connector->panel.vbt.edp.bpp);
4147 connector->panel.vbt.edp.bpp = pipe_bpp;
4148 }
4149 }
4150
intel_edp_mso_init(struct intel_dp * intel_dp)4151 static void intel_edp_mso_init(struct intel_dp *intel_dp)
4152 {
4153 struct intel_display *display = to_intel_display(intel_dp);
4154 struct intel_connector *connector = intel_dp->attached_connector;
4155 struct drm_display_info *info = &connector->base.display_info;
4156 u8 mso;
4157
4158 if (intel_dp->edp_dpcd[0] < DP_EDP_14)
4159 return;
4160
4161 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {
4162 drm_err(display->drm, "Failed to read MSO cap\n");
4163 return;
4164 }
4165
4166 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4167 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4168 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {
4169 drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
4170 mso = 0;
4171 }
4172
4173 if (mso) {
4174 drm_dbg_kms(display->drm,
4175 "Sink MSO %ux%u configuration, pixel overlap %u\n",
4176 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4177 info->mso_pixel_overlap);
4178 if (!HAS_MSO(display)) {
4179 drm_err(display->drm,
4180 "No source MSO support, disabling\n");
4181 mso = 0;
4182 }
4183 }
4184
4185 intel_dp->mso_link_count = mso;
4186 intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
4187 }
4188
4189 static void
intel_edp_set_sink_rates(struct intel_dp * intel_dp)4190 intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4191 {
4192 struct intel_display *display = to_intel_display(intel_dp);
4193 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4194
4195 intel_dp->num_sink_rates = 0;
4196
4197 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4198 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4199 int i;
4200
4201 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4202 sink_rates, sizeof(sink_rates));
4203
4204 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4205 int rate;
4206
4207 /* Value read multiplied by 200kHz gives the per-lane
4208 * link rate in kHz. The source rates are, however,
4209 * stored in terms of LS_Clk kHz. The full conversion
4210 * back to symbols is
4211 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4212 */
4213 rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
4214
4215 if (rate == 0)
4216 break;
4217
4218 /*
4219 * Some broken eDP sinks illegally declare support for
4220 * HBR3 without TPS4, and are unable to produce a stable
4221 * output. Reject HBR3 when TPS4 is not available.
4222 */
4223 if (rate >= 810000 && !drm_dp_tps4_supported(intel_dp->dpcd)) {
4224 drm_dbg_kms(display->drm,
4225 "[ENCODER:%d:%s] Rejecting HBR3 due to missing TPS4 support\n",
4226 encoder->base.base.id, encoder->base.name);
4227 break;
4228 }
4229
4230 intel_dp->sink_rates[i] = rate;
4231 }
4232 intel_dp->num_sink_rates = i;
4233 }
4234
4235 /*
4236 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4237 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4238 */
4239 if (intel_dp->num_sink_rates)
4240 intel_dp->use_rate_select = true;
4241 else
4242 intel_dp_set_sink_rates(intel_dp);
4243 }
4244
4245 static bool
intel_edp_init_dpcd(struct intel_dp * intel_dp,struct intel_connector * connector)4246 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4247 {
4248 struct intel_display *display = to_intel_display(intel_dp);
4249
4250 /* this function is meant to be called only once */
4251 drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4252
4253 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4254 return false;
4255
4256 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4257 drm_dp_is_branch(intel_dp->dpcd));
4258 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4259
4260 intel_dp->colorimetry_support =
4261 intel_dp_get_colorimetry_status(intel_dp);
4262
4263 /*
4264 * Read the eDP display control registers.
4265 *
4266 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4267 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4268 * set, but require eDP 1.4+ detection (e.g. for supported link rates
4269 * method). The display control registers should read zero if they're
4270 * not supported anyway.
4271 */
4272 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4273 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4274 sizeof(intel_dp->edp_dpcd)) {
4275 drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
4276 (int)sizeof(intel_dp->edp_dpcd),
4277 intel_dp->edp_dpcd);
4278
4279 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
4280 }
4281
4282 /*
4283 * If needed, program our source OUI so we can make various Intel-specific AUX services
4284 * available (such as HDR backlight controls)
4285 */
4286 intel_dp_init_source_oui(intel_dp);
4287
4288 /*
4289 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4290 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4291 */
4292 intel_psr_init_dpcd(intel_dp);
4293
4294 intel_edp_set_sink_rates(intel_dp);
4295 intel_dp_set_max_sink_lane_count(intel_dp);
4296
4297 /* Read the eDP DSC DPCD registers */
4298 intel_dp_detect_dsc_caps(intel_dp, connector);
4299
4300 return true;
4301 }
4302
4303 static bool
intel_dp_has_sink_count(struct intel_dp * intel_dp)4304 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4305 {
4306 if (!intel_dp->attached_connector)
4307 return false;
4308
4309 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4310 intel_dp->dpcd,
4311 &intel_dp->desc);
4312 }
4313
intel_dp_update_sink_caps(struct intel_dp * intel_dp)4314 void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4315 {
4316 intel_dp_set_sink_rates(intel_dp);
4317 intel_dp_set_max_sink_lane_count(intel_dp);
4318 intel_dp_set_common_rates(intel_dp);
4319 }
4320
4321 static bool
intel_dp_get_dpcd(struct intel_dp * intel_dp)4322 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4323 {
4324 int ret;
4325
4326 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4327 return false;
4328
4329 /*
4330 * Don't clobber cached eDP rates. Also skip re-reading
4331 * the OUI/ID since we know it won't change.
4332 */
4333 if (!intel_dp_is_edp(intel_dp)) {
4334 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4335 drm_dp_is_branch(intel_dp->dpcd));
4336
4337 intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);
4338
4339 intel_dp->colorimetry_support =
4340 intel_dp_get_colorimetry_status(intel_dp);
4341
4342 intel_dp_update_sink_caps(intel_dp);
4343 }
4344
4345 if (intel_dp_has_sink_count(intel_dp)) {
4346 ret = drm_dp_read_sink_count(&intel_dp->aux);
4347 if (ret < 0)
4348 return false;
4349
4350 /*
4351 * Sink count can change between short pulse hpd hence
4352 * a member variable in intel_dp will track any changes
4353 * between short pulse interrupts.
4354 */
4355 intel_dp->sink_count = ret;
4356
4357 /*
4358 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4359 * a dongle is present but no display. Unless we require to know
4360 * if a dongle is present or not, we don't need to update
4361 * downstream port information. So, an early return here saves
4362 * time from performing other operations which are not required.
4363 */
4364 if (!intel_dp->sink_count)
4365 return false;
4366 }
4367
4368 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4369 intel_dp->downstream_ports) == 0;
4370 }
4371
intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)4372 static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4373 {
4374 if (mst_mode == DRM_DP_MST)
4375 return "MST";
4376 else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4377 return "SST w/ sideband messaging";
4378 else
4379 return "SST";
4380 }
4381
4382 static enum drm_dp_mst_mode
intel_dp_mst_mode_choose(struct intel_dp * intel_dp,enum drm_dp_mst_mode sink_mst_mode)4383 intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4384 enum drm_dp_mst_mode sink_mst_mode)
4385 {
4386 struct intel_display *display = to_intel_display(intel_dp);
4387
4388 if (!display->params.enable_dp_mst)
4389 return DRM_DP_SST;
4390
4391 if (!intel_dp_mst_source_support(intel_dp))
4392 return DRM_DP_SST;
4393
4394 if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4395 !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4396 return DRM_DP_SST;
4397
4398 return sink_mst_mode;
4399 }
4400
4401 static enum drm_dp_mst_mode
intel_dp_mst_detect(struct intel_dp * intel_dp)4402 intel_dp_mst_detect(struct intel_dp *intel_dp)
4403 {
4404 struct intel_display *display = to_intel_display(intel_dp);
4405 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4406 enum drm_dp_mst_mode sink_mst_mode;
4407 enum drm_dp_mst_mode mst_detect;
4408
4409 sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4410
4411 mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4412
4413 drm_dbg_kms(display->drm,
4414 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4415 encoder->base.base.id, encoder->base.name,
4416 str_yes_no(intel_dp_mst_source_support(intel_dp)),
4417 intel_dp_mst_mode_str(sink_mst_mode),
4418 str_yes_no(display->params.enable_dp_mst),
4419 intel_dp_mst_mode_str(mst_detect));
4420
4421 return mst_detect;
4422 }
4423
4424 static void
intel_dp_mst_configure(struct intel_dp * intel_dp)4425 intel_dp_mst_configure(struct intel_dp *intel_dp)
4426 {
4427 if (!intel_dp_mst_source_support(intel_dp))
4428 return;
4429
4430 intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4431
4432 if (intel_dp->is_mst)
4433 intel_dp_mst_prepare_probe(intel_dp);
4434
4435 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);
4436
4437 /* Avoid stale info on the next detect cycle. */
4438 intel_dp->mst_detect = DRM_DP_SST;
4439 }
4440
4441 static void
intel_dp_mst_disconnect(struct intel_dp * intel_dp)4442 intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4443 {
4444 struct intel_display *display = to_intel_display(intel_dp);
4445
4446 if (!intel_dp->is_mst)
4447 return;
4448
4449 drm_dbg_kms(display->drm,
4450 "MST device may have disappeared %d vs %d\n",
4451 intel_dp->is_mst, intel_dp->mst.mgr.mst_state);
4452 intel_dp->is_mst = false;
4453 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, intel_dp->is_mst);
4454 }
4455
4456 static bool
intel_dp_get_sink_irq_esi(struct intel_dp * intel_dp,u8 * esi)4457 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4458 {
4459 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;
4460 }
4461
intel_dp_ack_sink_irq_esi(struct intel_dp * intel_dp,u8 esi[4])4462 static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4463 {
4464 int retry;
4465
4466 for (retry = 0; retry < 3; retry++) {
4467 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4468 &esi[1], 3) == 3)
4469 return true;
4470 }
4471
4472 return false;
4473 }
4474
4475 bool
intel_dp_needs_vsc_sdp(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4476 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4477 const struct drm_connector_state *conn_state)
4478 {
4479 /*
4480 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4481 * of Color Encoding Format and Content Color Gamut], in order to
4482 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4483 */
4484 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4485 return true;
4486
4487 switch (conn_state->colorspace) {
4488 case DRM_MODE_COLORIMETRY_SYCC_601:
4489 case DRM_MODE_COLORIMETRY_OPYCC_601:
4490 case DRM_MODE_COLORIMETRY_BT2020_YCC:
4491 case DRM_MODE_COLORIMETRY_BT2020_RGB:
4492 case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4493 return true;
4494 default:
4495 break;
4496 }
4497
4498 return false;
4499 }
4500
intel_dp_as_sdp_pack(const struct drm_dp_as_sdp * as_sdp,struct dp_sdp * sdp,size_t size)4501 static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4502 struct dp_sdp *sdp, size_t size)
4503 {
4504 size_t length = sizeof(struct dp_sdp);
4505
4506 if (size < length)
4507 return -ENOSPC;
4508
4509 memset(sdp, 0, size);
4510
4511 /* Prepare AS (Adaptive Sync) SDP Header */
4512 sdp->sdp_header.HB0 = 0;
4513 sdp->sdp_header.HB1 = as_sdp->sdp_type;
4514 sdp->sdp_header.HB2 = 0x02;
4515 sdp->sdp_header.HB3 = as_sdp->length;
4516
4517 /* Fill AS (Adaptive Sync) SDP Payload */
4518 sdp->db[0] = as_sdp->mode;
4519 sdp->db[1] = as_sdp->vtotal & 0xFF;
4520 sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4521 sdp->db[3] = as_sdp->target_rr & 0xFF;
4522 sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4523
4524 if (as_sdp->target_rr_divider)
4525 sdp->db[4] |= 0x20;
4526
4527 return length;
4528 }
4529
4530 static ssize_t
intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display * display,const struct hdmi_drm_infoframe * drm_infoframe,struct dp_sdp * sdp,size_t size)4531 intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
4532 const struct hdmi_drm_infoframe *drm_infoframe,
4533 struct dp_sdp *sdp,
4534 size_t size)
4535 {
4536 size_t length = sizeof(struct dp_sdp);
4537 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4538 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4539 ssize_t len;
4540
4541 if (size < length)
4542 return -ENOSPC;
4543
4544 memset(sdp, 0, size);
4545
4546 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
4547 if (len < 0) {
4548 drm_dbg_kms(display->drm,
4549 "buffer size is smaller than hdr metadata infoframe\n");
4550 return -ENOSPC;
4551 }
4552
4553 if (len != infoframe_size) {
4554 drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
4555 return -ENOSPC;
4556 }
4557
4558 /*
4559 * Set up the infoframe sdp packet for HDR static metadata.
4560 * Prepare VSC Header for SU as per DP 1.4a spec,
4561 * Table 2-100 and Table 2-101
4562 */
4563
4564 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4565 sdp->sdp_header.HB0 = 0;
4566 /*
4567 * Packet Type 80h + Non-audio INFOFRAME Type value
4568 * HDMI_INFOFRAME_TYPE_DRM: 0x87
4569 * - 80h + Non-audio INFOFRAME Type value
4570 * - InfoFrame Type: 0x07
4571 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4572 */
4573 sdp->sdp_header.HB1 = drm_infoframe->type;
4574 /*
4575 * Least Significant Eight Bits of (Data Byte Count – 1)
4576 * infoframe_size - 1
4577 */
4578 sdp->sdp_header.HB2 = 0x1D;
4579 /* INFOFRAME SDP Version Number */
4580 sdp->sdp_header.HB3 = (0x13 << 2);
4581 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4582 sdp->db[0] = drm_infoframe->version;
4583 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4584 sdp->db[1] = drm_infoframe->length;
4585 /*
4586 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4587 * HDMI_INFOFRAME_HEADER_SIZE
4588 */
4589 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4590 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4591 HDMI_DRM_INFOFRAME_SIZE);
4592
4593 /*
4594 * Size of DP infoframe sdp packet for HDR static metadata consists of
4595 * - DP SDP Header(struct dp_sdp_header): 4 bytes
4596 * - Two Data Blocks: 2 bytes
4597 * CTA Header Byte2 (INFOFRAME Version Number)
4598 * CTA Header Byte3 (Length of INFOFRAME)
4599 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4600 *
4601 * Prior to GEN11's GMP register size is identical to DP HDR static metadata
4602 * infoframe size. But GEN11+ has larger than that size, write_infoframe
4603 * will pad rest of the size.
4604 */
4605 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4606 }
4607
intel_write_dp_sdp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,unsigned int type)4608 static void intel_write_dp_sdp(struct intel_encoder *encoder,
4609 const struct intel_crtc_state *crtc_state,
4610 unsigned int type)
4611 {
4612 struct intel_display *display = to_intel_display(encoder);
4613 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4614 struct dp_sdp sdp = {};
4615 ssize_t len;
4616
4617 if ((crtc_state->infoframes.enable &
4618 intel_hdmi_infoframe_enable(type)) == 0)
4619 return;
4620
4621 switch (type) {
4622 case DP_SDP_VSC:
4623 len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);
4624 break;
4625 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4626 len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
4627 &crtc_state->infoframes.drm.drm,
4628 &sdp, sizeof(sdp));
4629 break;
4630 case DP_SDP_ADAPTIVE_SYNC:
4631 len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,
4632 sizeof(sdp));
4633 break;
4634 default:
4635 MISSING_CASE(type);
4636 return;
4637 }
4638
4639 if (drm_WARN_ON(display->drm, len < 0))
4640 return;
4641
4642 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4643 }
4644
intel_dp_set_infoframes(struct intel_encoder * encoder,bool enable,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4645 void intel_dp_set_infoframes(struct intel_encoder *encoder,
4646 bool enable,
4647 const struct intel_crtc_state *crtc_state,
4648 const struct drm_connector_state *conn_state)
4649 {
4650 struct intel_display *display = to_intel_display(encoder);
4651 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
4652 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4653 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4654 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4655
4656 if (HAS_AS_SDP(display))
4657 dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4658
4659 u32 val = intel_de_read(display, reg) & ~dip_enable;
4660
4661 /* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4662 if (!enable && HAS_DSC(display))
4663 val &= ~VDIP_ENABLE_PPS;
4664
4665 /*
4666 * This routine disables VSC DIP if the function is called
4667 * to disable SDP or if it does not have PSR
4668 */
4669 if (!enable || !crtc_state->has_psr)
4670 val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4671
4672 intel_de_write(display, reg, val);
4673 intel_de_posting_read(display, reg);
4674
4675 if (!enable)
4676 return;
4677
4678 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4679 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4680
4681 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
4682 }
4683
4684 static
intel_dp_as_sdp_unpack(struct drm_dp_as_sdp * as_sdp,const void * buffer,size_t size)4685 int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4686 const void *buffer, size_t size)
4687 {
4688 const struct dp_sdp *sdp = buffer;
4689
4690 if (size < sizeof(struct dp_sdp))
4691 return -EINVAL;
4692
4693 memset(as_sdp, 0, sizeof(*as_sdp));
4694
4695 if (sdp->sdp_header.HB0 != 0)
4696 return -EINVAL;
4697
4698 if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4699 return -EINVAL;
4700
4701 if (sdp->sdp_header.HB2 != 0x02)
4702 return -EINVAL;
4703
4704 if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4705 return -EINVAL;
4706
4707 as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4708 as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4709 as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
4710 as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
4711 as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
4712
4713 return 0;
4714 }
4715
intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp * vsc,const void * buffer,size_t size)4716 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
4717 const void *buffer, size_t size)
4718 {
4719 const struct dp_sdp *sdp = buffer;
4720
4721 if (size < sizeof(struct dp_sdp))
4722 return -EINVAL;
4723
4724 memset(vsc, 0, sizeof(*vsc));
4725
4726 if (sdp->sdp_header.HB0 != 0)
4727 return -EINVAL;
4728
4729 if (sdp->sdp_header.HB1 != DP_SDP_VSC)
4730 return -EINVAL;
4731
4732 vsc->sdp_type = sdp->sdp_header.HB1;
4733 vsc->revision = sdp->sdp_header.HB2;
4734 vsc->length = sdp->sdp_header.HB3;
4735
4736 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
4737 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
4738 (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
4739 /*
4740 * - HB2 = 0x2, HB3 = 0x8
4741 * VSC SDP supporting 3D stereo + PSR
4742 * - HB2 = 0x4, HB3 = 0xe
4743 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
4744 * first scan line of the SU region (applies to eDP v1.4b
4745 * and higher).
4746 * - HB2 = 0x6, HB3 = 0x10
4747 * VSC SDP supporting 3D stereo + Panel Replay.
4748 */
4749 return 0;
4750 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
4751 /*
4752 * - HB2 = 0x5, HB3 = 0x13
4753 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
4754 * Format.
4755 */
4756 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
4757 vsc->colorimetry = sdp->db[16] & 0xf;
4758 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
4759
4760 switch (sdp->db[17] & 0x7) {
4761 case 0x0:
4762 vsc->bpc = 6;
4763 break;
4764 case 0x1:
4765 vsc->bpc = 8;
4766 break;
4767 case 0x2:
4768 vsc->bpc = 10;
4769 break;
4770 case 0x3:
4771 vsc->bpc = 12;
4772 break;
4773 case 0x4:
4774 vsc->bpc = 16;
4775 break;
4776 default:
4777 MISSING_CASE(sdp->db[17] & 0x7);
4778 return -EINVAL;
4779 }
4780
4781 vsc->content_type = sdp->db[18] & 0x7;
4782 } else {
4783 return -EINVAL;
4784 }
4785
4786 return 0;
4787 }
4788
4789 static void
intel_read_dp_as_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_as_sdp * as_sdp)4790 intel_read_dp_as_sdp(struct intel_encoder *encoder,
4791 struct intel_crtc_state *crtc_state,
4792 struct drm_dp_as_sdp *as_sdp)
4793 {
4794 struct intel_display *display = to_intel_display(encoder);
4795 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4796 unsigned int type = DP_SDP_ADAPTIVE_SYNC;
4797 struct dp_sdp sdp = {};
4798 int ret;
4799
4800 if ((crtc_state->infoframes.enable &
4801 intel_hdmi_infoframe_enable(type)) == 0)
4802 return;
4803
4804 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4805 sizeof(sdp));
4806
4807 ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));
4808 if (ret)
4809 drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
4810 }
4811
4812 static int
intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe * drm_infoframe,const void * buffer,size_t size)4813 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
4814 const void *buffer, size_t size)
4815 {
4816 int ret;
4817
4818 const struct dp_sdp *sdp = buffer;
4819
4820 if (size < sizeof(struct dp_sdp))
4821 return -EINVAL;
4822
4823 if (sdp->sdp_header.HB0 != 0)
4824 return -EINVAL;
4825
4826 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
4827 return -EINVAL;
4828
4829 /*
4830 * Least Significant Eight Bits of (Data Byte Count – 1)
4831 * 1Dh (i.e., Data Byte Count = 30 bytes).
4832 */
4833 if (sdp->sdp_header.HB2 != 0x1D)
4834 return -EINVAL;
4835
4836 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
4837 if ((sdp->sdp_header.HB3 & 0x3) != 0)
4838 return -EINVAL;
4839
4840 /* INFOFRAME SDP Version Number */
4841 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
4842 return -EINVAL;
4843
4844 /* CTA Header Byte 2 (INFOFRAME Version Number) */
4845 if (sdp->db[0] != 1)
4846 return -EINVAL;
4847
4848 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4849 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
4850 return -EINVAL;
4851
4852 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
4853 HDMI_DRM_INFOFRAME_SIZE);
4854
4855 return ret;
4856 }
4857
intel_read_dp_vsc_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_dp_vsc_sdp * vsc)4858 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
4859 struct intel_crtc_state *crtc_state,
4860 struct drm_dp_vsc_sdp *vsc)
4861 {
4862 struct intel_display *display = to_intel_display(encoder);
4863 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4864 unsigned int type = DP_SDP_VSC;
4865 struct dp_sdp sdp = {};
4866 int ret;
4867
4868 if ((crtc_state->infoframes.enable &
4869 intel_hdmi_infoframe_enable(type)) == 0)
4870 return;
4871
4872 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
4873
4874 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
4875
4876 if (ret)
4877 drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
4878 }
4879
intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct hdmi_drm_infoframe * drm_infoframe)4880 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
4881 struct intel_crtc_state *crtc_state,
4882 struct hdmi_drm_infoframe *drm_infoframe)
4883 {
4884 struct intel_display *display = to_intel_display(encoder);
4885 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4886 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
4887 struct dp_sdp sdp = {};
4888 int ret;
4889
4890 if ((crtc_state->infoframes.enable &
4891 intel_hdmi_infoframe_enable(type)) == 0)
4892 return;
4893
4894 dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
4895 sizeof(sdp));
4896
4897 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
4898 sizeof(sdp));
4899
4900 if (ret)
4901 drm_dbg_kms(display->drm,
4902 "Failed to unpack DP HDR Metadata Infoframe SDP\n");
4903 }
4904
intel_read_dp_sdp(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,unsigned int type)4905 void intel_read_dp_sdp(struct intel_encoder *encoder,
4906 struct intel_crtc_state *crtc_state,
4907 unsigned int type)
4908 {
4909 switch (type) {
4910 case DP_SDP_VSC:
4911 intel_read_dp_vsc_sdp(encoder, crtc_state,
4912 &crtc_state->infoframes.vsc);
4913 break;
4914 case HDMI_PACKET_TYPE_GAMUT_METADATA:
4915 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
4916 &crtc_state->infoframes.drm.drm);
4917 break;
4918 case DP_SDP_ADAPTIVE_SYNC:
4919 intel_read_dp_as_sdp(encoder, crtc_state,
4920 &crtc_state->infoframes.as_sdp);
4921 break;
4922 default:
4923 MISSING_CASE(type);
4924 break;
4925 }
4926 }
4927
intel_dp_link_ok(struct intel_dp * intel_dp,u8 link_status[DP_LINK_STATUS_SIZE])4928 static bool intel_dp_link_ok(struct intel_dp *intel_dp,
4929 u8 link_status[DP_LINK_STATUS_SIZE])
4930 {
4931 struct intel_display *display = to_intel_display(intel_dp);
4932 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4933 bool uhbr = intel_dp->link_rate >= 1000000;
4934 bool ok;
4935
4936 if (uhbr)
4937 ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
4938 intel_dp->lane_count);
4939 else
4940 ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4941
4942 if (ok)
4943 return true;
4944
4945 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
4946 drm_dbg_kms(display->drm,
4947 "[ENCODER:%d:%s] %s link not ok, retraining\n",
4948 encoder->base.base.id, encoder->base.name,
4949 uhbr ? "128b/132b" : "8b/10b");
4950
4951 return false;
4952 }
4953
4954 static void
intel_dp_mst_hpd_irq(struct intel_dp * intel_dp,u8 * esi,u8 * ack)4955 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
4956 {
4957 bool handled = false;
4958
4959 drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst.mgr, esi, ack, &handled);
4960
4961 if (esi[1] & DP_CP_IRQ) {
4962 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
4963 ack[1] |= DP_CP_IRQ;
4964 }
4965 }
4966
intel_dp_mst_link_status(struct intel_dp * intel_dp)4967 static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
4968 {
4969 struct intel_display *display = to_intel_display(intel_dp);
4970 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4971 u8 link_status[DP_LINK_STATUS_SIZE] = {};
4972 const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
4973
4974 if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,
4975 esi_link_status_size) != esi_link_status_size) {
4976 drm_err(display->drm,
4977 "[ENCODER:%d:%s] Failed to read link status\n",
4978 encoder->base.base.id, encoder->base.name);
4979 return false;
4980 }
4981
4982 return intel_dp_link_ok(intel_dp, link_status);
4983 }
4984
4985 /**
4986 * intel_dp_check_mst_status - service any pending MST interrupts, check link status
4987 * @intel_dp: Intel DP struct
4988 *
4989 * Read any pending MST interrupts, call MST core to handle these and ack the
4990 * interrupts. Check if the main and AUX link state is ok.
4991 *
4992 * Returns:
4993 * - %true if pending interrupts were serviced (or no interrupts were
4994 * pending) w/o detecting an error condition.
4995 * - %false if an error condition - like AUX failure or a loss of link - is
4996 * detected, or another condition - like a DP tunnel BW state change - needs
4997 * servicing from the hotplug work.
4998 */
4999 static bool
intel_dp_check_mst_status(struct intel_dp * intel_dp)5000 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5001 {
5002 struct intel_display *display = to_intel_display(intel_dp);
5003 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5004 struct intel_encoder *encoder = &dig_port->base;
5005 bool link_ok = true;
5006 bool reprobe_needed = false;
5007
5008 drm_WARN_ON_ONCE(display->drm, intel_dp->mst.active_links < 0);
5009
5010 for (;;) {
5011 u8 esi[4] = {};
5012 u8 ack[4] = {};
5013
5014 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5015 drm_dbg_kms(display->drm,
5016 "failed to get ESI - device may have failed\n");
5017 link_ok = false;
5018
5019 break;
5020 }
5021
5022 drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
5023
5024 if (intel_dp->mst.active_links > 0 && link_ok &&
5025 esi[3] & LINK_STATUS_CHANGED) {
5026 if (!intel_dp_mst_link_status(intel_dp))
5027 link_ok = false;
5028 ack[3] |= LINK_STATUS_CHANGED;
5029 }
5030
5031 intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5032
5033 if (esi[3] & DP_TUNNELING_IRQ) {
5034 if (drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5035 &intel_dp->aux))
5036 reprobe_needed = true;
5037 ack[3] |= DP_TUNNELING_IRQ;
5038 }
5039
5040 if (mem_is_zero(ack, sizeof(ack)))
5041 break;
5042
5043 if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))
5044 drm_dbg_kms(display->drm, "Failed to ack ESI\n");
5045
5046 if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5047 drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst.mgr);
5048 }
5049
5050 if (!link_ok || intel_dp->link.force_retrain)
5051 intel_encoder_link_check_queue_work(encoder, 0);
5052
5053 return !reprobe_needed;
5054 }
5055
5056 static void
intel_dp_handle_hdmi_link_status_change(struct intel_dp * intel_dp)5057 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
5058 {
5059 bool is_active;
5060 u8 buf = 0;
5061
5062 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);
5063 if (intel_dp->frl.is_trained && !is_active) {
5064 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)
5065 return;
5066
5067 buf &= ~DP_PCON_ENABLE_HDMI_LINK;
5068 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)
5069 return;
5070
5071 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);
5072
5073 intel_dp->frl.is_trained = false;
5074
5075 /* Restart FRL training or fall back to TMDS mode */
5076 intel_dp_check_frl_training(intel_dp);
5077 }
5078 }
5079
5080 static bool
intel_dp_needs_link_retrain(struct intel_dp * intel_dp)5081 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5082 {
5083 u8 link_status[DP_LINK_STATUS_SIZE];
5084
5085 if (!intel_dp->link_trained)
5086 return false;
5087
5088 /*
5089 * While PSR source HW is enabled, it will control main-link sending
5090 * frames, enabling and disabling it so trying to do a retrain will fail
5091 * as the link would or not be on or it could mix training patterns
5092 * and frame data at the same time causing retrain to fail.
5093 * Also when exiting PSR, HW will retrain the link anyways fixing
5094 * any link status error.
5095 */
5096 if (intel_psr_enabled(intel_dp))
5097 return false;
5098
5099 if (intel_dp->link.force_retrain)
5100 return true;
5101
5102 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5103 link_status) < 0)
5104 return false;
5105
5106 /*
5107 * Validate the cached values of intel_dp->link_rate and
5108 * intel_dp->lane_count before attempting to retrain.
5109 *
5110 * FIXME would be nice to user the crtc state here, but since
5111 * we need to call this from the short HPD handler that seems
5112 * a bit hard.
5113 */
5114 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5115 intel_dp->lane_count))
5116 return false;
5117
5118 if (intel_dp->link.retrain_disabled)
5119 return false;
5120
5121 if (intel_dp->link.seq_train_failures)
5122 return true;
5123
5124 /* Retrain if link not ok */
5125 return !intel_dp_link_ok(intel_dp, link_status) &&
5126 !intel_psr_link_ok(intel_dp);
5127 }
5128
intel_dp_has_connector(struct intel_dp * intel_dp,const struct drm_connector_state * conn_state)5129 bool intel_dp_has_connector(struct intel_dp *intel_dp,
5130 const struct drm_connector_state *conn_state)
5131 {
5132 struct intel_display *display = to_intel_display(intel_dp);
5133 struct intel_encoder *encoder;
5134 enum pipe pipe;
5135
5136 if (!conn_state->best_encoder)
5137 return false;
5138
5139 /* SST */
5140 encoder = &dp_to_dig_port(intel_dp)->base;
5141 if (conn_state->best_encoder == &encoder->base)
5142 return true;
5143
5144 /* MST */
5145 for_each_pipe(display, pipe) {
5146 encoder = &intel_dp->mst.stream_encoders[pipe]->base;
5147 if (conn_state->best_encoder == &encoder->base)
5148 return true;
5149 }
5150
5151 return false;
5152 }
5153
wait_for_connector_hw_done(const struct drm_connector_state * conn_state)5154 static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5155 {
5156 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5157 struct intel_display *display = to_intel_display(connector);
5158
5159 drm_modeset_lock_assert_held(&display->drm->mode_config.connection_mutex);
5160
5161 if (!conn_state->commit)
5162 return;
5163
5164 drm_WARN_ON(display->drm,
5165 !wait_for_completion_timeout(&conn_state->commit->hw_done,
5166 msecs_to_jiffies(5000)));
5167 }
5168
intel_dp_get_active_pipes(struct intel_dp * intel_dp,struct drm_modeset_acquire_ctx * ctx,u8 * pipe_mask)5169 int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5170 struct drm_modeset_acquire_ctx *ctx,
5171 u8 *pipe_mask)
5172 {
5173 struct intel_display *display = to_intel_display(intel_dp);
5174 struct drm_connector_list_iter conn_iter;
5175 struct intel_connector *connector;
5176 int ret = 0;
5177
5178 *pipe_mask = 0;
5179
5180 drm_connector_list_iter_begin(display->drm, &conn_iter);
5181 for_each_intel_connector_iter(connector, &conn_iter) {
5182 struct drm_connector_state *conn_state =
5183 connector->base.state;
5184 struct intel_crtc_state *crtc_state;
5185 struct intel_crtc *crtc;
5186
5187 if (!intel_dp_has_connector(intel_dp, conn_state))
5188 continue;
5189
5190 crtc = to_intel_crtc(conn_state->crtc);
5191 if (!crtc)
5192 continue;
5193
5194 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5195 if (ret)
5196 break;
5197
5198 crtc_state = to_intel_crtc_state(crtc->base.state);
5199
5200 drm_WARN_ON(display->drm,
5201 !intel_crtc_has_dp_encoder(crtc_state));
5202
5203 if (!crtc_state->hw.active)
5204 continue;
5205
5206 wait_for_connector_hw_done(conn_state);
5207
5208 *pipe_mask |= BIT(crtc->pipe);
5209 }
5210 drm_connector_list_iter_end(&conn_iter);
5211
5212 return ret;
5213 }
5214
intel_dp_flush_connector_commits(struct intel_connector * connector)5215 void intel_dp_flush_connector_commits(struct intel_connector *connector)
5216 {
5217 wait_for_connector_hw_done(connector->base.state);
5218 }
5219
intel_dp_is_connected(struct intel_dp * intel_dp)5220 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5221 {
5222 struct intel_connector *connector = intel_dp->attached_connector;
5223
5224 return connector->base.status == connector_status_connected ||
5225 intel_dp->is_mst;
5226 }
5227
intel_dp_retrain_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)5228 static int intel_dp_retrain_link(struct intel_encoder *encoder,
5229 struct drm_modeset_acquire_ctx *ctx)
5230 {
5231 struct intel_display *display = to_intel_display(encoder);
5232 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5233 u8 pipe_mask;
5234 int ret;
5235
5236 if (!intel_dp_is_connected(intel_dp))
5237 return 0;
5238
5239 ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
5240 ctx);
5241 if (ret)
5242 return ret;
5243
5244 if (!intel_dp_needs_link_retrain(intel_dp))
5245 return 0;
5246
5247 ret = intel_dp_get_active_pipes(intel_dp, ctx, &pipe_mask);
5248 if (ret)
5249 return ret;
5250
5251 if (pipe_mask == 0)
5252 return 0;
5253
5254 if (!intel_dp_needs_link_retrain(intel_dp))
5255 return 0;
5256
5257 drm_dbg_kms(display->drm,
5258 "[ENCODER:%d:%s] retraining link (forced %s)\n",
5259 encoder->base.base.id, encoder->base.name,
5260 str_yes_no(intel_dp->link.force_retrain));
5261
5262 ret = intel_modeset_commit_pipes(display, pipe_mask, ctx);
5263 if (ret == -EDEADLK)
5264 return ret;
5265
5266 intel_dp->link.force_retrain = false;
5267
5268 if (ret)
5269 drm_dbg_kms(display->drm,
5270 "[ENCODER:%d:%s] link retraining failed: %pe\n",
5271 encoder->base.base.id, encoder->base.name,
5272 ERR_PTR(ret));
5273
5274 return ret;
5275 }
5276
intel_dp_link_check(struct intel_encoder * encoder)5277 void intel_dp_link_check(struct intel_encoder *encoder)
5278 {
5279 struct drm_modeset_acquire_ctx ctx;
5280 int ret;
5281
5282 intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
5283 ret = intel_dp_retrain_link(encoder, &ctx);
5284 }
5285
intel_dp_check_link_state(struct intel_dp * intel_dp)5286 void intel_dp_check_link_state(struct intel_dp *intel_dp)
5287 {
5288 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5289 struct intel_encoder *encoder = &dig_port->base;
5290
5291 if (!intel_dp_is_connected(intel_dp))
5292 return;
5293
5294 if (!intel_dp_needs_link_retrain(intel_dp))
5295 return;
5296
5297 intel_encoder_link_check_queue_work(encoder, 0);
5298 }
5299
intel_dp_check_device_service_irq(struct intel_dp * intel_dp)5300 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5301 {
5302 struct intel_display *display = to_intel_display(intel_dp);
5303 u8 val;
5304
5305 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5306 return;
5307
5308 if (drm_dp_dpcd_readb(&intel_dp->aux,
5309 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
5310 return;
5311
5312 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
5313
5314 if (val & DP_AUTOMATED_TEST_REQUEST)
5315 intel_dp_test_request(intel_dp);
5316
5317 if (val & DP_CP_IRQ)
5318 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
5319
5320 if (val & DP_SINK_SPECIFIC_IRQ)
5321 drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
5322 }
5323
intel_dp_check_link_service_irq(struct intel_dp * intel_dp)5324 static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5325 {
5326 struct intel_display *display = to_intel_display(intel_dp);
5327 bool reprobe_needed = false;
5328 u8 val;
5329
5330 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5331 return false;
5332
5333 if (drm_dp_dpcd_readb(&intel_dp->aux,
5334 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val)
5335 return false;
5336
5337 if ((val & DP_TUNNELING_IRQ) &&
5338 drm_dp_tunnel_handle_irq(display->dp_tunnel_mgr,
5339 &intel_dp->aux))
5340 reprobe_needed = true;
5341
5342 if (drm_dp_dpcd_writeb(&intel_dp->aux,
5343 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1)
5344 return reprobe_needed;
5345
5346 if (val & HDMI_LINK_STATUS_CHANGED)
5347 intel_dp_handle_hdmi_link_status_change(intel_dp);
5348
5349 return reprobe_needed;
5350 }
5351
5352 /*
5353 * According to DP spec
5354 * 5.1.2:
5355 * 1. Read DPCD
5356 * 2. Configure link according to Receiver Capabilities
5357 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5358 * 4. Check link status on receipt of hot-plug interrupt
5359 *
5360 * intel_dp_short_pulse - handles short pulse interrupts
5361 * when full detection is not required.
5362 * Returns %true if short pulse is handled and full detection
5363 * is NOT required and %false otherwise.
5364 */
5365 static bool
intel_dp_short_pulse(struct intel_dp * intel_dp)5366 intel_dp_short_pulse(struct intel_dp *intel_dp)
5367 {
5368 u8 old_sink_count = intel_dp->sink_count;
5369 bool reprobe_needed = false;
5370 bool ret;
5371
5372 intel_dp_test_reset(intel_dp);
5373
5374 /*
5375 * Now read the DPCD to see if it's actually running
5376 * If the current value of sink count doesn't match with
5377 * the value that was stored earlier or dpcd read failed
5378 * we need to do full detection
5379 */
5380 ret = intel_dp_get_dpcd(intel_dp);
5381
5382 if ((old_sink_count != intel_dp->sink_count) || !ret) {
5383 /* No need to proceed if we are going to do full detect */
5384 return false;
5385 }
5386
5387 intel_dp_check_device_service_irq(intel_dp);
5388 reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5389
5390 /* Handle CEC interrupts, if any */
5391 drm_dp_cec_irq(&intel_dp->aux);
5392
5393 intel_dp_check_link_state(intel_dp);
5394
5395 intel_psr_short_pulse(intel_dp);
5396
5397 if (intel_dp_test_short_pulse(intel_dp))
5398 reprobe_needed = true;
5399
5400 return !reprobe_needed;
5401 }
5402
5403 /* XXX this is probably wrong for multiple downstream ports */
5404 static enum drm_connector_status
intel_dp_detect_dpcd(struct intel_dp * intel_dp)5405 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5406 {
5407 struct intel_display *display = to_intel_display(intel_dp);
5408 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5409 u8 *dpcd = intel_dp->dpcd;
5410 u8 type;
5411
5412 if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
5413 return connector_status_connected;
5414
5415 intel_lspcon_resume(dig_port);
5416
5417 if (!intel_dp_get_dpcd(intel_dp))
5418 return connector_status_disconnected;
5419
5420 intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5421
5422 /* if there's no downstream port, we're done */
5423 if (!drm_dp_is_branch(dpcd))
5424 return connector_status_connected;
5425
5426 /* If we're HPD-aware, SINK_COUNT changes dynamically */
5427 if (intel_dp_has_sink_count(intel_dp) &&
5428 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5429 return intel_dp->sink_count ?
5430 connector_status_connected : connector_status_disconnected;
5431 }
5432
5433 if (intel_dp->mst_detect == DRM_DP_MST)
5434 return connector_status_connected;
5435
5436 /* If no HPD, poke DDC gently */
5437 if (drm_probe_ddc(&intel_dp->aux.ddc))
5438 return connector_status_connected;
5439
5440 /* Well we tried, say unknown for unreliable port types */
5441 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5442 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5443 if (type == DP_DS_PORT_TYPE_VGA ||
5444 type == DP_DS_PORT_TYPE_NON_EDID)
5445 return connector_status_unknown;
5446 } else {
5447 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5448 DP_DWN_STRM_PORT_TYPE_MASK;
5449 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5450 type == DP_DWN_STRM_PORT_TYPE_OTHER)
5451 return connector_status_unknown;
5452 }
5453
5454 /* Anything else is out of spec, warn and ignore */
5455 drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
5456 return connector_status_disconnected;
5457 }
5458
5459 static enum drm_connector_status
edp_detect(struct intel_dp * intel_dp)5460 edp_detect(struct intel_dp *intel_dp)
5461 {
5462 return connector_status_connected;
5463 }
5464
intel_digital_port_lock(struct intel_encoder * encoder)5465 void intel_digital_port_lock(struct intel_encoder *encoder)
5466 {
5467 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5468
5469 if (dig_port->lock)
5470 dig_port->lock(dig_port);
5471 }
5472
intel_digital_port_unlock(struct intel_encoder * encoder)5473 void intel_digital_port_unlock(struct intel_encoder *encoder)
5474 {
5475 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5476
5477 if (dig_port->unlock)
5478 dig_port->unlock(dig_port);
5479 }
5480
5481 /*
5482 * intel_digital_port_connected_locked - is the specified port connected?
5483 * @encoder: intel_encoder
5484 *
5485 * In cases where there's a connector physically connected but it can't be used
5486 * by our hardware we also return false, since the rest of the driver should
5487 * pretty much treat the port as disconnected. This is relevant for type-C
5488 * (starting on ICL) where there's ownership involved.
5489 *
5490 * The caller must hold the lock acquired by calling intel_digital_port_lock()
5491 * when calling this function.
5492 *
5493 * Return %true if port is connected, %false otherwise.
5494 */
intel_digital_port_connected_locked(struct intel_encoder * encoder)5495 bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5496 {
5497 struct intel_display *display = to_intel_display(encoder);
5498 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5499 bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5500 bool is_connected = false;
5501 intel_wakeref_t wakeref;
5502
5503 with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5504 unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);
5505
5506 do {
5507 is_connected = dig_port->connected(encoder);
5508 if (is_connected || is_glitch_free)
5509 break;
5510 usleep_range(10, 30);
5511 } while (time_before(jiffies, wait_expires));
5512 }
5513
5514 return is_connected;
5515 }
5516
intel_digital_port_connected(struct intel_encoder * encoder)5517 bool intel_digital_port_connected(struct intel_encoder *encoder)
5518 {
5519 bool ret;
5520
5521 intel_digital_port_lock(encoder);
5522 ret = intel_digital_port_connected_locked(encoder);
5523 intel_digital_port_unlock(encoder);
5524
5525 return ret;
5526 }
5527
5528 static const struct drm_edid *
intel_dp_get_edid(struct intel_dp * intel_dp)5529 intel_dp_get_edid(struct intel_dp *intel_dp)
5530 {
5531 struct intel_connector *connector = intel_dp->attached_connector;
5532 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5533
5534 /* Use panel fixed edid if we have one */
5535 if (fixed_edid) {
5536 /* invalid edid */
5537 if (IS_ERR(fixed_edid))
5538 return NULL;
5539
5540 return drm_edid_dup(fixed_edid);
5541 }
5542
5543 return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);
5544 }
5545
5546 static void
intel_dp_update_dfp(struct intel_dp * intel_dp,const struct drm_edid * drm_edid)5547 intel_dp_update_dfp(struct intel_dp *intel_dp,
5548 const struct drm_edid *drm_edid)
5549 {
5550 struct intel_display *display = to_intel_display(intel_dp);
5551 struct intel_connector *connector = intel_dp->attached_connector;
5552
5553 intel_dp->dfp.max_bpc =
5554 drm_dp_downstream_max_bpc(intel_dp->dpcd,
5555 intel_dp->downstream_ports, drm_edid);
5556
5557 intel_dp->dfp.max_dotclock =
5558 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
5559 intel_dp->downstream_ports);
5560
5561 intel_dp->dfp.min_tmds_clock =
5562 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
5563 intel_dp->downstream_ports,
5564 drm_edid);
5565 intel_dp->dfp.max_tmds_clock =
5566 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
5567 intel_dp->downstream_ports,
5568 drm_edid);
5569
5570 intel_dp->dfp.pcon_max_frl_bw =
5571 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,
5572 intel_dp->downstream_ports);
5573
5574 drm_dbg_kms(display->drm,
5575 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5576 connector->base.base.id, connector->base.name,
5577 intel_dp->dfp.max_bpc,
5578 intel_dp->dfp.max_dotclock,
5579 intel_dp->dfp.min_tmds_clock,
5580 intel_dp->dfp.max_tmds_clock,
5581 intel_dp->dfp.pcon_max_frl_bw);
5582
5583 intel_dp_get_pcon_dsc_cap(intel_dp);
5584 }
5585
5586 static bool
intel_dp_can_ycbcr420(struct intel_dp * intel_dp)5587 intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5588 {
5589 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420) &&
5590 (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5591 return true;
5592
5593 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_RGB) &&
5594 dfp_can_convert_from_rgb(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5595 return true;
5596
5597 if (source_can_output(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR444) &&
5598 dfp_can_convert_from_ycbcr444(intel_dp, INTEL_OUTPUT_FORMAT_YCBCR420))
5599 return true;
5600
5601 return false;
5602 }
5603
5604 static void
intel_dp_update_420(struct intel_dp * intel_dp)5605 intel_dp_update_420(struct intel_dp *intel_dp)
5606 {
5607 struct intel_display *display = to_intel_display(intel_dp);
5608 struct intel_connector *connector = intel_dp->attached_connector;
5609
5610 intel_dp->dfp.ycbcr420_passthrough =
5611 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
5612 intel_dp->downstream_ports);
5613 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5614 intel_dp->dfp.ycbcr_444_to_420 =
5615 intel_lspcon_active(dp_to_dig_port(intel_dp)) ||
5616 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
5617 intel_dp->downstream_ports);
5618 intel_dp->dfp.rgb_to_ycbcr =
5619 drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,
5620 intel_dp->downstream_ports,
5621 DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5622
5623 connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5624
5625 drm_dbg_kms(display->drm,
5626 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5627 connector->base.base.id, connector->base.name,
5628 str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5629 str_yes_no(connector->base.ycbcr_420_allowed),
5630 str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5631 }
5632
5633 static void
intel_dp_set_edid(struct intel_dp * intel_dp)5634 intel_dp_set_edid(struct intel_dp *intel_dp)
5635 {
5636 struct intel_display *display = to_intel_display(intel_dp);
5637 struct intel_connector *connector = intel_dp->attached_connector;
5638 const struct drm_edid *drm_edid;
5639 bool vrr_capable;
5640
5641 intel_dp_unset_edid(intel_dp);
5642 drm_edid = intel_dp_get_edid(intel_dp);
5643 connector->detect_edid = drm_edid;
5644
5645 /* Below we depend on display info having been updated */
5646 drm_edid_connector_update(&connector->base, drm_edid);
5647
5648 vrr_capable = intel_vrr_is_capable(connector);
5649 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5650 connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5651 drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
5652
5653 intel_dp_update_dfp(intel_dp, drm_edid);
5654 intel_dp_update_420(intel_dp);
5655
5656 drm_dp_cec_attach(&intel_dp->aux,
5657 connector->base.display_info.source_physical_address);
5658 }
5659
5660 static void
intel_dp_unset_edid(struct intel_dp * intel_dp)5661 intel_dp_unset_edid(struct intel_dp *intel_dp)
5662 {
5663 struct intel_connector *connector = intel_dp->attached_connector;
5664
5665 drm_dp_cec_unset_edid(&intel_dp->aux);
5666 drm_edid_free(connector->detect_edid);
5667 connector->detect_edid = NULL;
5668
5669 intel_dp->dfp.max_bpc = 0;
5670 intel_dp->dfp.max_dotclock = 0;
5671 intel_dp->dfp.min_tmds_clock = 0;
5672 intel_dp->dfp.max_tmds_clock = 0;
5673
5674 intel_dp->dfp.pcon_max_frl_bw = 0;
5675
5676 intel_dp->dfp.ycbcr_444_to_420 = false;
5677 connector->base.ycbcr_420_allowed = false;
5678
5679 drm_connector_set_vrr_capable_property(&connector->base,
5680 false);
5681 }
5682
5683 static void
intel_dp_detect_sdp_caps(struct intel_dp * intel_dp)5684 intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5685 {
5686 struct intel_display *display = to_intel_display(intel_dp);
5687
5688 intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
5689 drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);
5690 }
5691
5692 static int
intel_dp_detect(struct drm_connector * _connector,struct drm_modeset_acquire_ctx * ctx,bool force)5693 intel_dp_detect(struct drm_connector *_connector,
5694 struct drm_modeset_acquire_ctx *ctx,
5695 bool force)
5696 {
5697 struct intel_display *display = to_intel_display(_connector->dev);
5698 struct intel_connector *connector = to_intel_connector(_connector);
5699 struct intel_dp *intel_dp = intel_attached_dp(connector);
5700 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5701 struct intel_encoder *encoder = &dig_port->base;
5702 enum drm_connector_status status;
5703 int ret;
5704
5705 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5706 connector->base.base.id, connector->base.name);
5707 drm_WARN_ON(display->drm,
5708 !drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
5709
5710 if (!intel_display_device_enabled(display))
5711 return connector_status_disconnected;
5712
5713 if (!intel_display_driver_check_access(display))
5714 return connector->base.status;
5715
5716 intel_dp_flush_connector_commits(connector);
5717
5718 intel_pps_vdd_on(intel_dp);
5719
5720 /* Can't disconnect eDP */
5721 if (intel_dp_is_edp(intel_dp))
5722 status = edp_detect(intel_dp);
5723 else if (intel_digital_port_connected(encoder))
5724 status = intel_dp_detect_dpcd(intel_dp);
5725 else
5726 status = connector_status_disconnected;
5727
5728 if (status != connector_status_disconnected &&
5729 !intel_dp_mst_verify_dpcd_state(intel_dp))
5730 /*
5731 * This requires retrying detection for instance to re-enable
5732 * the MST mode that got reset via a long HPD pulse. The retry
5733 * will happen either via the hotplug handler's retry logic,
5734 * ensured by setting the connector here to SST/disconnected,
5735 * or via a userspace connector probing in response to the
5736 * hotplug uevent sent when removing the MST connectors.
5737 */
5738 status = connector_status_disconnected;
5739
5740 if (status == connector_status_disconnected) {
5741 intel_dp_test_reset(intel_dp);
5742 memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
5743 intel_dp->psr.sink_panel_replay_support = false;
5744 intel_dp->psr.sink_panel_replay_su_support = false;
5745
5746 intel_dp_mst_disconnect(intel_dp);
5747
5748 intel_dp_tunnel_disconnect(intel_dp);
5749
5750 goto out_unset_edid;
5751 }
5752
5753 intel_dp_init_source_oui(intel_dp);
5754
5755 ret = intel_dp_tunnel_detect(intel_dp, ctx);
5756 if (ret == -EDEADLK) {
5757 status = ret;
5758
5759 goto out_vdd_off;
5760 }
5761
5762 if (ret == 1)
5763 connector->base.epoch_counter++;
5764
5765 if (!intel_dp_is_edp(intel_dp))
5766 intel_psr_init_dpcd(intel_dp);
5767
5768 intel_dp_detect_dsc_caps(intel_dp, connector);
5769
5770 intel_dp_detect_sdp_caps(intel_dp);
5771
5772 if (intel_dp->reset_link_params) {
5773 intel_dp_reset_link_params(intel_dp);
5774 intel_dp->reset_link_params = false;
5775 }
5776
5777 intel_dp_mst_configure(intel_dp);
5778
5779 intel_dp_print_rates(intel_dp);
5780
5781 if (intel_dp->is_mst) {
5782 /*
5783 * If we are in MST mode then this connector
5784 * won't appear connected or have anything
5785 * with EDID on it
5786 */
5787 status = connector_status_disconnected;
5788 goto out_unset_edid;
5789 }
5790
5791 /*
5792 * Some external monitors do not signal loss of link synchronization
5793 * with an IRQ_HPD, so force a link status check.
5794 *
5795 * TODO: this probably became redundant, so remove it: the link state
5796 * is rechecked/recovered now after modesets, where the loss of
5797 * synchronization tends to occur.
5798 */
5799 if (!intel_dp_is_edp(intel_dp))
5800 intel_dp_check_link_state(intel_dp);
5801
5802 /*
5803 * Clearing NACK and defer counts to get their exact values
5804 * while reading EDID which are required by Compliance tests
5805 * 4.2.2.4 and 4.2.2.5
5806 */
5807 intel_dp->aux.i2c_nack_count = 0;
5808 intel_dp->aux.i2c_defer_count = 0;
5809
5810 intel_dp_set_edid(intel_dp);
5811 if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
5812 status = connector_status_connected;
5813
5814 intel_dp_check_device_service_irq(intel_dp);
5815
5816 out_unset_edid:
5817 if (status != connector_status_connected && !intel_dp->is_mst)
5818 intel_dp_unset_edid(intel_dp);
5819
5820 if (!intel_dp_is_edp(intel_dp))
5821 drm_dp_set_subconnector_property(&connector->base,
5822 status,
5823 intel_dp->dpcd,
5824 intel_dp->downstream_ports);
5825 out_vdd_off:
5826 intel_pps_vdd_off(intel_dp);
5827
5828 return status;
5829 }
5830
5831 static void
intel_dp_force(struct drm_connector * connector)5832 intel_dp_force(struct drm_connector *connector)
5833 {
5834 struct intel_display *display = to_intel_display(connector->dev);
5835 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5836
5837 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
5838 connector->base.id, connector->name);
5839
5840 if (!intel_display_driver_check_access(display))
5841 return;
5842
5843 intel_dp_unset_edid(intel_dp);
5844
5845 if (connector->status != connector_status_connected)
5846 return;
5847
5848 intel_dp_set_edid(intel_dp);
5849 }
5850
intel_dp_get_modes(struct drm_connector * _connector)5851 static int intel_dp_get_modes(struct drm_connector *_connector)
5852 {
5853 struct intel_display *display = to_intel_display(_connector->dev);
5854 struct intel_connector *connector = to_intel_connector(_connector);
5855 struct intel_dp *intel_dp = intel_attached_dp(connector);
5856 int num_modes;
5857
5858 /* drm_edid_connector_update() done in ->detect() or ->force() */
5859 num_modes = drm_edid_connector_add_modes(&connector->base);
5860
5861 /* Also add fixed mode, which may or may not be present in EDID */
5862 if (intel_dp_is_edp(intel_dp))
5863 num_modes += intel_panel_get_modes(connector);
5864
5865 if (num_modes)
5866 return num_modes;
5867
5868 if (!connector->detect_edid) {
5869 struct drm_display_mode *mode;
5870
5871 mode = drm_dp_downstream_mode(display->drm,
5872 intel_dp->dpcd,
5873 intel_dp->downstream_ports);
5874 if (mode) {
5875 drm_mode_probed_add(&connector->base, mode);
5876 num_modes++;
5877 }
5878 }
5879
5880 return num_modes;
5881 }
5882
5883 static int
intel_dp_connector_register(struct drm_connector * connector)5884 intel_dp_connector_register(struct drm_connector *connector)
5885 {
5886 struct intel_display *display = to_intel_display(connector->dev);
5887 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5888 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5889 int ret;
5890
5891 ret = intel_connector_register(connector);
5892 if (ret)
5893 return ret;
5894
5895 drm_dbg_kms(display->drm, "registering %s bus for %s\n",
5896 intel_dp->aux.name, connector->kdev->kobj.name);
5897
5898 intel_dp->aux.dev = connector->kdev;
5899 ret = drm_dp_aux_register(&intel_dp->aux);
5900 if (!ret)
5901 drm_dp_cec_register_connector(&intel_dp->aux, connector);
5902
5903 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))
5904 return ret;
5905
5906 /*
5907 * ToDo: Clean this up to handle lspcon init and resume more
5908 * efficiently and streamlined.
5909 */
5910 if (intel_lspcon_init(dig_port)) {
5911 if (intel_lspcon_detect_hdr_capability(dig_port))
5912 drm_connector_attach_hdr_output_metadata_property(connector);
5913 }
5914
5915 return ret;
5916 }
5917
5918 static void
intel_dp_connector_unregister(struct drm_connector * connector)5919 intel_dp_connector_unregister(struct drm_connector *connector)
5920 {
5921 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
5922
5923 drm_dp_cec_unregister_connector(&intel_dp->aux);
5924 drm_dp_aux_unregister(&intel_dp->aux);
5925 intel_connector_unregister(connector);
5926 }
5927
intel_dp_connector_sync_state(struct intel_connector * connector,const struct intel_crtc_state * crtc_state)5928 void intel_dp_connector_sync_state(struct intel_connector *connector,
5929 const struct intel_crtc_state *crtc_state)
5930 {
5931 struct intel_display *display = to_intel_display(connector);
5932
5933 if (crtc_state && crtc_state->dsc.compression_enable) {
5934 drm_WARN_ON(display->drm,
5935 !connector->dp.dsc_decompression_aux);
5936 connector->dp.dsc_decompression_enabled = true;
5937 } else {
5938 connector->dp.dsc_decompression_enabled = false;
5939 }
5940 }
5941
intel_dp_encoder_flush_work(struct drm_encoder * _encoder)5942 void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)
5943 {
5944 struct intel_encoder *encoder = to_intel_encoder(_encoder);
5945 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5946 struct intel_dp *intel_dp = &dig_port->dp;
5947
5948 intel_encoder_link_check_flush_work(encoder);
5949
5950 intel_dp_mst_encoder_cleanup(dig_port);
5951
5952 intel_dp_tunnel_destroy(intel_dp);
5953
5954 intel_pps_vdd_off_sync(intel_dp);
5955
5956 /*
5957 * Ensure power off delay is respected on module remove, so that we can
5958 * reduce delays at driver probe. See pps_init_timestamps().
5959 */
5960 intel_pps_wait_power_cycle(intel_dp);
5961
5962 intel_dp_aux_fini(intel_dp);
5963 }
5964
intel_dp_encoder_suspend(struct intel_encoder * encoder)5965 void intel_dp_encoder_suspend(struct intel_encoder *encoder)
5966 {
5967 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5968
5969 intel_pps_vdd_off_sync(intel_dp);
5970
5971 intel_dp_tunnel_suspend(intel_dp);
5972 }
5973
intel_dp_encoder_shutdown(struct intel_encoder * encoder)5974 void intel_dp_encoder_shutdown(struct intel_encoder *encoder)
5975 {
5976 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5977
5978 intel_pps_wait_power_cycle(intel_dp);
5979 }
5980
intel_modeset_tile_group(struct intel_atomic_state * state,int tile_group_id)5981 static int intel_modeset_tile_group(struct intel_atomic_state *state,
5982 int tile_group_id)
5983 {
5984 struct intel_display *display = to_intel_display(state);
5985 struct drm_connector_list_iter conn_iter;
5986 struct drm_connector *connector;
5987 int ret = 0;
5988
5989 drm_connector_list_iter_begin(display->drm, &conn_iter);
5990 drm_for_each_connector_iter(connector, &conn_iter) {
5991 struct drm_connector_state *conn_state;
5992 struct intel_crtc_state *crtc_state;
5993 struct intel_crtc *crtc;
5994
5995 if (!connector->has_tile ||
5996 connector->tile_group->id != tile_group_id)
5997 continue;
5998
5999 conn_state = drm_atomic_get_connector_state(&state->base,
6000 connector);
6001 if (IS_ERR(conn_state)) {
6002 ret = PTR_ERR(conn_state);
6003 break;
6004 }
6005
6006 crtc = to_intel_crtc(conn_state->crtc);
6007
6008 if (!crtc)
6009 continue;
6010
6011 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6012 crtc_state->uapi.mode_changed = true;
6013
6014 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6015 if (ret)
6016 break;
6017 }
6018 drm_connector_list_iter_end(&conn_iter);
6019
6020 return ret;
6021 }
6022
intel_modeset_affected_transcoders(struct intel_atomic_state * state,u8 transcoders)6023 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6024 {
6025 struct intel_display *display = to_intel_display(state);
6026 struct intel_crtc *crtc;
6027
6028 if (transcoders == 0)
6029 return 0;
6030
6031 for_each_intel_crtc(display->drm, crtc) {
6032 struct intel_crtc_state *crtc_state;
6033 int ret;
6034
6035 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6036 if (IS_ERR(crtc_state))
6037 return PTR_ERR(crtc_state);
6038
6039 if (!crtc_state->hw.enable)
6040 continue;
6041
6042 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6043 continue;
6044
6045 crtc_state->uapi.mode_changed = true;
6046
6047 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6048 if (ret)
6049 return ret;
6050
6051 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6052 if (ret)
6053 return ret;
6054
6055 transcoders &= ~BIT(crtc_state->cpu_transcoder);
6056 }
6057
6058 drm_WARN_ON(display->drm, transcoders != 0);
6059
6060 return 0;
6061 }
6062
intel_modeset_synced_crtcs(struct intel_atomic_state * state,struct drm_connector * connector)6063 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6064 struct drm_connector *connector)
6065 {
6066 const struct drm_connector_state *old_conn_state =
6067 drm_atomic_get_old_connector_state(&state->base, connector);
6068 const struct intel_crtc_state *old_crtc_state;
6069 struct intel_crtc *crtc;
6070 u8 transcoders;
6071
6072 crtc = to_intel_crtc(old_conn_state->crtc);
6073 if (!crtc)
6074 return 0;
6075
6076 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6077
6078 if (!old_crtc_state->hw.active)
6079 return 0;
6080
6081 transcoders = old_crtc_state->sync_mode_slaves_mask;
6082 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6083 transcoders |= BIT(old_crtc_state->master_transcoder);
6084
6085 return intel_modeset_affected_transcoders(state,
6086 transcoders);
6087 }
6088
intel_dp_connector_atomic_check(struct drm_connector * conn,struct drm_atomic_state * _state)6089 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
6090 struct drm_atomic_state *_state)
6091 {
6092 struct intel_display *display = to_intel_display(conn->dev);
6093 struct intel_atomic_state *state = to_intel_atomic_state(_state);
6094 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);
6095 struct intel_connector *intel_conn = to_intel_connector(conn);
6096 struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);
6097 int ret;
6098
6099 ret = intel_digital_connector_atomic_check(conn, &state->base);
6100 if (ret)
6101 return ret;
6102
6103 if (intel_dp_mst_source_support(intel_dp)) {
6104 ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst.mgr);
6105 if (ret)
6106 return ret;
6107 }
6108
6109 if (!intel_connector_needs_modeset(state, conn))
6110 return 0;
6111
6112 ret = intel_dp_tunnel_atomic_check_state(state,
6113 intel_dp,
6114 intel_conn);
6115 if (ret)
6116 return ret;
6117
6118 /*
6119 * We don't enable port sync on BDW due to missing w/as and
6120 * due to not having adjusted the modeset sequence appropriately.
6121 */
6122 if (DISPLAY_VER(display) < 9)
6123 return 0;
6124
6125 if (conn->has_tile) {
6126 ret = intel_modeset_tile_group(state, conn->tile_group->id);
6127 if (ret)
6128 return ret;
6129 }
6130
6131 return intel_modeset_synced_crtcs(state, conn);
6132 }
6133
intel_dp_oob_hotplug_event(struct drm_connector * connector,enum drm_connector_status hpd_state)6134 static void intel_dp_oob_hotplug_event(struct drm_connector *connector,
6135 enum drm_connector_status hpd_state)
6136 {
6137 struct intel_display *display = to_intel_display(connector->dev);
6138 struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));
6139 struct drm_i915_private *i915 = to_i915(connector->dev);
6140 bool hpd_high = hpd_state == connector_status_connected;
6141 unsigned int hpd_pin = encoder->hpd_pin;
6142 bool need_work = false;
6143
6144 spin_lock_irq(&i915->irq_lock);
6145 if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
6146 display->hotplug.event_bits |= BIT(hpd_pin);
6147
6148 __assign_bit(hpd_pin,
6149 &display->hotplug.oob_hotplug_last_state,
6150 hpd_high);
6151 need_work = true;
6152 }
6153 spin_unlock_irq(&i915->irq_lock);
6154
6155 if (need_work)
6156 intel_hpd_schedule_detection(i915);
6157 }
6158
6159 static const struct drm_connector_funcs intel_dp_connector_funcs = {
6160 .force = intel_dp_force,
6161 .fill_modes = drm_helper_probe_single_connector_modes,
6162 .atomic_get_property = intel_digital_connector_atomic_get_property,
6163 .atomic_set_property = intel_digital_connector_atomic_set_property,
6164 .late_register = intel_dp_connector_register,
6165 .early_unregister = intel_dp_connector_unregister,
6166 .destroy = intel_connector_destroy,
6167 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6168 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
6169 .oob_hotplug_event = intel_dp_oob_hotplug_event,
6170 };
6171
6172 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6173 .detect_ctx = intel_dp_detect,
6174 .get_modes = intel_dp_get_modes,
6175 .mode_valid = intel_dp_mode_valid,
6176 .atomic_check = intel_dp_connector_atomic_check,
6177 };
6178
6179 enum irqreturn
intel_dp_hpd_pulse(struct intel_digital_port * dig_port,bool long_hpd)6180 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6181 {
6182 struct intel_display *display = to_intel_display(dig_port);
6183 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
6184 struct intel_dp *intel_dp = &dig_port->dp;
6185 u8 dpcd[DP_RECEIVER_CAP_SIZE];
6186
6187 if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6188 (long_hpd ||
6189 intel_runtime_pm_suspended(&i915->runtime_pm) ||
6190 !intel_pps_have_panel_power_or_vdd(intel_dp))) {
6191 /*
6192 * vdd off can generate a long/short pulse on eDP which
6193 * would require vdd on to handle it, and thus we
6194 * would end up in an endless cycle of
6195 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6196 */
6197 drm_dbg_kms(display->drm,
6198 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6199 long_hpd ? "long" : "short",
6200 dig_port->base.base.base.id,
6201 dig_port->base.base.name);
6202 return IRQ_HANDLED;
6203 }
6204
6205 drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6206 dig_port->base.base.base.id,
6207 dig_port->base.base.name,
6208 long_hpd ? "long" : "short");
6209
6210 /*
6211 * TBT DP tunnels require the GFX driver to read out the DPRX caps in
6212 * response to long HPD pulses. The DP hotplug handler does that,
6213 * however the hotplug handler may be blocked by another
6214 * connector's/encoder's hotplug handler. Since the TBT CM may not
6215 * complete the DP tunnel BW request for the latter connector/encoder
6216 * waiting for this encoder's DPRX read, perform a dummy read here.
6217 */
6218 if (long_hpd)
6219 intel_dp_read_dprx_caps(intel_dp, dpcd);
6220
6221 if (long_hpd) {
6222 intel_dp->reset_link_params = true;
6223 intel_dp_invalidate_source_oui(intel_dp);
6224
6225 return IRQ_NONE;
6226 }
6227
6228 if (intel_dp->is_mst) {
6229 if (!intel_dp_check_mst_status(intel_dp))
6230 return IRQ_NONE;
6231 } else if (!intel_dp_short_pulse(intel_dp)) {
6232 return IRQ_NONE;
6233 }
6234
6235 return IRQ_HANDLED;
6236 }
6237
_intel_dp_is_port_edp(struct intel_display * display,const struct intel_bios_encoder_data * devdata,enum port port)6238 static bool _intel_dp_is_port_edp(struct intel_display *display,
6239 const struct intel_bios_encoder_data *devdata,
6240 enum port port)
6241 {
6242 /*
6243 * eDP not supported on g4x. so bail out early just
6244 * for a bit extra safety in case the VBT is bonkers.
6245 */
6246 if (DISPLAY_VER(display) < 5)
6247 return false;
6248
6249 if (DISPLAY_VER(display) < 9 && port == PORT_A)
6250 return true;
6251
6252 return devdata && intel_bios_encoder_supports_edp(devdata);
6253 }
6254
intel_dp_is_port_edp(struct intel_display * display,enum port port)6255 bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
6256 {
6257 const struct intel_bios_encoder_data *devdata =
6258 intel_bios_encoder_data_lookup(display, port);
6259
6260 return _intel_dp_is_port_edp(display, devdata, port);
6261 }
6262
6263 bool
intel_dp_has_gamut_metadata_dip(struct intel_encoder * encoder)6264 intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6265 {
6266 struct intel_display *display = to_intel_display(encoder);
6267 enum port port = encoder->port;
6268
6269 if (intel_bios_encoder_is_lspcon(encoder->devdata))
6270 return false;
6271
6272 if (DISPLAY_VER(display) >= 11)
6273 return true;
6274
6275 if (port == PORT_A)
6276 return false;
6277
6278 if (display->platform.haswell || display->platform.broadwell ||
6279 DISPLAY_VER(display) >= 9)
6280 return true;
6281
6282 return false;
6283 }
6284
6285 static void
intel_dp_add_properties(struct intel_dp * intel_dp,struct drm_connector * connector)6286 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
6287 {
6288 struct intel_display *display = to_intel_display(intel_dp);
6289 enum port port = dp_to_dig_port(intel_dp)->base.port;
6290
6291 if (!intel_dp_is_edp(intel_dp))
6292 drm_connector_attach_dp_subconnector_property(connector);
6293
6294 if (!display->platform.g4x && port != PORT_A)
6295 intel_attach_force_audio_property(connector);
6296
6297 intel_attach_broadcast_rgb_property(connector);
6298 if (HAS_GMCH(display))
6299 drm_connector_attach_max_bpc_property(connector, 6, 10);
6300 else if (DISPLAY_VER(display) >= 5)
6301 drm_connector_attach_max_bpc_property(connector, 6, 12);
6302
6303 /* Register HDMI colorspace for case of lspcon */
6304 if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {
6305 drm_connector_attach_content_type_property(connector);
6306 intel_attach_hdmi_colorspace_property(connector);
6307 } else {
6308 intel_attach_dp_colorspace_property(connector);
6309 }
6310
6311 if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
6312 drm_connector_attach_hdr_output_metadata_property(connector);
6313
6314 if (HAS_VRR(display))
6315 drm_connector_attach_vrr_capable_property(connector);
6316 }
6317
6318 static void
intel_edp_add_properties(struct intel_dp * intel_dp)6319 intel_edp_add_properties(struct intel_dp *intel_dp)
6320 {
6321 struct intel_display *display = to_intel_display(intel_dp);
6322 struct intel_connector *connector = intel_dp->attached_connector;
6323 const struct drm_display_mode *fixed_mode =
6324 intel_panel_preferred_fixed_mode(connector);
6325
6326 intel_attach_scaling_mode_property(&connector->base);
6327
6328 drm_connector_set_panel_orientation_with_quirk(&connector->base,
6329 display->vbt.orientation,
6330 fixed_mode->hdisplay,
6331 fixed_mode->vdisplay);
6332 }
6333
intel_edp_backlight_setup(struct intel_dp * intel_dp,struct intel_connector * connector)6334 static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6335 struct intel_connector *connector)
6336 {
6337 struct intel_display *display = to_intel_display(intel_dp);
6338 enum pipe pipe = INVALID_PIPE;
6339
6340 if (display->platform.valleyview || display->platform.cherryview)
6341 pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6342
6343 intel_backlight_setup(connector, pipe);
6344 }
6345
intel_edp_init_connector(struct intel_dp * intel_dp,struct intel_connector * connector)6346 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6347 struct intel_connector *connector)
6348 {
6349 struct intel_display *display = to_intel_display(intel_dp);
6350 struct drm_i915_private *dev_priv = to_i915(display->drm);
6351 struct drm_display_mode *fixed_mode;
6352 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6353 bool has_dpcd;
6354 const struct drm_edid *drm_edid;
6355
6356 if (!intel_dp_is_edp(intel_dp))
6357 return true;
6358
6359 /*
6360 * On IBX/CPT we may get here with LVDS already registered. Since the
6361 * driver uses the only internal power sequencer available for both
6362 * eDP and LVDS bail out early in this case to prevent interfering
6363 * with an already powered-on LVDS power sequencer.
6364 */
6365 if (intel_get_lvds_encoder(dev_priv)) {
6366 drm_WARN_ON(display->drm,
6367 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6368 drm_info(display->drm,
6369 "LVDS was detected, not registering eDP\n");
6370
6371 return false;
6372 }
6373
6374 intel_bios_init_panel_early(display, &connector->panel,
6375 encoder->devdata);
6376
6377 if (!intel_pps_init(intel_dp)) {
6378 drm_info(display->drm,
6379 "[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6380 encoder->base.base.id, encoder->base.name);
6381 /*
6382 * The BIOS may have still enabled VDD on the PPS even
6383 * though it's unusable. Make sure we turn it back off
6384 * and to release the power domain references/etc.
6385 */
6386 goto out_vdd_off;
6387 }
6388
6389 /*
6390 * Enable HPD sense for live status check.
6391 * intel_hpd_irq_setup() will turn it off again
6392 * if it's no longer needed later.
6393 *
6394 * The DPCD probe below will make sure VDD is on.
6395 */
6396 intel_hpd_enable_detection(encoder);
6397
6398 intel_alpm_init_dpcd(intel_dp);
6399
6400 /* Cache DPCD and EDID for edp. */
6401 has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
6402
6403 if (!has_dpcd) {
6404 /* if this fails, presume the device is a ghost */
6405 drm_info(display->drm,
6406 "[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6407 encoder->base.base.id, encoder->base.name);
6408 goto out_vdd_off;
6409 }
6410
6411 /*
6412 * VBT and straps are liars. Also check HPD as that seems
6413 * to be the most reliable piece of information available.
6414 *
6415 * ... expect on devices that forgot to hook HPD up for eDP
6416 * (eg. Acer Chromebook C710), so we'll check it only if multiple
6417 * ports are attempting to use the same AUX CH, according to VBT.
6418 */
6419 if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {
6420 /*
6421 * If this fails, presume the DPCD answer came
6422 * from some other port using the same AUX CH.
6423 *
6424 * FIXME maybe cleaner to check this before the
6425 * DPCD read? Would need sort out the VDD handling...
6426 */
6427 if (!intel_digital_port_connected(encoder)) {
6428 drm_info(display->drm,
6429 "[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6430 encoder->base.base.id, encoder->base.name);
6431 goto out_vdd_off;
6432 }
6433
6434 /*
6435 * Unfortunately even the HPD based detection fails on
6436 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6437 * back to checking for a VGA branch device. Only do this
6438 * on known affected platforms to minimize false positives.
6439 */
6440 if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&
6441 (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6442 DP_DWN_STRM_PORT_TYPE_ANALOG) {
6443 drm_info(display->drm,
6444 "[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6445 encoder->base.base.id, encoder->base.name);
6446 goto out_vdd_off;
6447 }
6448 }
6449
6450 mutex_lock(&display->drm->mode_config.mutex);
6451 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
6452 if (!drm_edid) {
6453 /* Fallback to EDID from ACPI OpRegion, if any */
6454 drm_edid = intel_opregion_get_edid(connector);
6455 if (drm_edid)
6456 drm_dbg_kms(display->drm,
6457 "[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6458 connector->base.base.id, connector->base.name);
6459 }
6460 if (drm_edid) {
6461 if (drm_edid_connector_update(&connector->base, drm_edid) ||
6462 !drm_edid_connector_add_modes(&connector->base)) {
6463 drm_edid_connector_update(&connector->base, NULL);
6464 drm_edid_free(drm_edid);
6465 drm_edid = ERR_PTR(-EINVAL);
6466 }
6467 } else {
6468 drm_edid = ERR_PTR(-ENOENT);
6469 }
6470
6471 intel_bios_init_panel_late(display, &connector->panel, encoder->devdata,
6472 IS_ERR(drm_edid) ? NULL : drm_edid);
6473
6474 intel_panel_add_edid_fixed_modes(connector, true);
6475
6476 /* MSO requires information from the EDID */
6477 intel_edp_mso_init(intel_dp);
6478
6479 /* multiply the mode clock and horizontal timings for MSO */
6480 list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)
6481 intel_edp_mso_mode_fixup(connector, fixed_mode);
6482
6483 /* fallback to VBT if available for eDP */
6484 if (!intel_panel_preferred_fixed_mode(connector))
6485 intel_panel_add_vbt_lfp_fixed_mode(connector);
6486
6487 mutex_unlock(&display->drm->mode_config.mutex);
6488
6489 if (!intel_panel_preferred_fixed_mode(connector)) {
6490 drm_info(display->drm,
6491 "[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6492 encoder->base.base.id, encoder->base.name);
6493 goto out_vdd_off;
6494 }
6495
6496 intel_panel_init(connector, drm_edid);
6497
6498 intel_edp_backlight_setup(intel_dp, connector);
6499
6500 intel_edp_add_properties(intel_dp);
6501
6502 intel_pps_init_late(intel_dp);
6503
6504 return true;
6505
6506 out_vdd_off:
6507 intel_pps_vdd_off_sync(intel_dp);
6508 intel_bios_fini_panel(&connector->panel);
6509
6510 return false;
6511 }
6512
6513 bool
intel_dp_init_connector(struct intel_digital_port * dig_port,struct intel_connector * connector)6514 intel_dp_init_connector(struct intel_digital_port *dig_port,
6515 struct intel_connector *connector)
6516 {
6517 struct intel_display *display = to_intel_display(dig_port);
6518 struct intel_dp *intel_dp = &dig_port->dp;
6519 struct intel_encoder *encoder = &dig_port->base;
6520 struct drm_device *dev = encoder->base.dev;
6521 enum port port = encoder->port;
6522 int type;
6523
6524 if (drm_WARN(dev, dig_port->max_lanes < 1,
6525 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6526 dig_port->max_lanes, encoder->base.base.id,
6527 encoder->base.name))
6528 return false;
6529
6530 intel_dp->reset_link_params = true;
6531
6532 /* Preserve the current hw state. */
6533 intel_dp->DP = intel_de_read(display, intel_dp->output_reg);
6534 intel_dp->attached_connector = connector;
6535
6536 if (_intel_dp_is_port_edp(display, encoder->devdata, port)) {
6537 /*
6538 * Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6539 * although in theory it could work on TypeC legacy ports.
6540 */
6541 drm_WARN_ON(dev, intel_encoder_is_tc(encoder) &&
6542 DISPLAY_VER(display) < 30);
6543 type = DRM_MODE_CONNECTOR_eDP;
6544 encoder->type = INTEL_OUTPUT_EDP;
6545
6546 /* eDP only on port B and/or C on vlv/chv */
6547 if (drm_WARN_ON(dev, (display->platform.valleyview ||
6548 display->platform.cherryview) &&
6549 port != PORT_B && port != PORT_C))
6550 return false;
6551 } else {
6552 type = DRM_MODE_CONNECTOR_DisplayPort;
6553 }
6554
6555 intel_dp_set_default_sink_rates(intel_dp);
6556 intel_dp_set_default_max_sink_lane_count(intel_dp);
6557
6558 if (display->platform.valleyview || display->platform.cherryview)
6559 vlv_pps_pipe_init(intel_dp);
6560
6561 intel_dp_aux_init(intel_dp);
6562 connector->dp.dsc_decompression_aux = &intel_dp->aux;
6563
6564 drm_dbg_kms(display->drm,
6565 "Adding %s connector on [ENCODER:%d:%s]\n",
6566 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6567 encoder->base.base.id, encoder->base.name);
6568
6569 drm_connector_init_with_ddc(dev, &connector->base, &intel_dp_connector_funcs,
6570 type, &intel_dp->aux.ddc);
6571 drm_connector_helper_add(&connector->base, &intel_dp_connector_helper_funcs);
6572
6573 if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
6574 connector->base.interlace_allowed = true;
6575
6576 if (type != DRM_MODE_CONNECTOR_eDP)
6577 connector->polled = DRM_CONNECTOR_POLL_HPD;
6578 connector->base.polled = connector->polled;
6579
6580 intel_connector_attach_encoder(connector, encoder);
6581
6582 if (HAS_DDI(display))
6583 connector->get_hw_state = intel_ddi_connector_get_hw_state;
6584 else
6585 connector->get_hw_state = intel_connector_get_hw_state;
6586 connector->sync_state = intel_dp_connector_sync_state;
6587
6588 if (!intel_edp_init_connector(intel_dp, connector)) {
6589 intel_dp_aux_fini(intel_dp);
6590 goto fail;
6591 }
6592
6593 intel_dp_set_source_rates(intel_dp);
6594 intel_dp_set_common_rates(intel_dp);
6595 intel_dp_reset_link_params(intel_dp);
6596
6597 /* init MST on ports that can support it */
6598 intel_dp_mst_encoder_init(dig_port, connector->base.base.id);
6599
6600 intel_dp_add_properties(intel_dp, &connector->base);
6601
6602 if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6603 int ret = intel_dp_hdcp_init(dig_port, connector);
6604 if (ret)
6605 drm_dbg_kms(display->drm,
6606 "HDCP init failed, skipping.\n");
6607 }
6608
6609 intel_dp->frl.is_trained = false;
6610 intel_dp->frl.trained_rate_gbps = 0;
6611
6612 intel_psr_init(intel_dp);
6613
6614 return true;
6615
6616 fail:
6617 intel_display_power_flush_work(display);
6618 drm_connector_cleanup(&connector->base);
6619
6620 return false;
6621 }
6622
intel_dp_mst_suspend(struct intel_display * display)6623 void intel_dp_mst_suspend(struct intel_display *display)
6624 {
6625 struct intel_encoder *encoder;
6626
6627 if (!HAS_DISPLAY(display))
6628 return;
6629
6630 for_each_intel_encoder(display->drm, encoder) {
6631 struct intel_dp *intel_dp;
6632
6633 if (encoder->type != INTEL_OUTPUT_DDI)
6634 continue;
6635
6636 intel_dp = enc_to_intel_dp(encoder);
6637
6638 if (!intel_dp_mst_source_support(intel_dp))
6639 continue;
6640
6641 if (intel_dp->is_mst)
6642 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst.mgr);
6643 }
6644 }
6645
intel_dp_mst_resume(struct intel_display * display)6646 void intel_dp_mst_resume(struct intel_display *display)
6647 {
6648 struct intel_encoder *encoder;
6649
6650 if (!HAS_DISPLAY(display))
6651 return;
6652
6653 for_each_intel_encoder(display->drm, encoder) {
6654 struct intel_dp *intel_dp;
6655 int ret;
6656
6657 if (encoder->type != INTEL_OUTPUT_DDI)
6658 continue;
6659
6660 intel_dp = enc_to_intel_dp(encoder);
6661
6662 if (!intel_dp_mst_source_support(intel_dp))
6663 continue;
6664
6665 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst.mgr, true);
6666 if (ret) {
6667 intel_dp->is_mst = false;
6668 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst.mgr, false);
6669 }
6670 }
6671 }
6672