1 /*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28 #include <drm/drm_scdc_helper.h>
29
30 #include "i915_drv.h"
31 #include "intel_audio.h"
32 #include "intel_combo_phy.h"
33 #include "intel_connector.h"
34 #include "intel_ddi.h"
35 #include "intel_display_types.h"
36 #include "intel_dp.h"
37 #include "intel_dp_mst.h"
38 #include "intel_dp_link_training.h"
39 #include "intel_dpio_phy.h"
40 #include "intel_dsi.h"
41 #include "intel_fifo_underrun.h"
42 #include "intel_gmbus.h"
43 #include "intel_hdcp.h"
44 #include "intel_hdmi.h"
45 #include "intel_hotplug.h"
46 #include "intel_lspcon.h"
47 #include "intel_panel.h"
48 #include "intel_psr.h"
49 #include "intel_sprite.h"
50 #include "intel_tc.h"
51 #include "intel_vdsc.h"
52
53 struct ddi_buf_trans {
54 u32 trans1; /* balance leg enable, de-emph level */
55 u32 trans2; /* vref sel, vswing */
56 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
57 };
58
59 static const u8 index_to_dp_signal_levels[] = {
60 [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
61 [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
62 [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
63 [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
64 [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
65 [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
66 [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
67 [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
68 [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
69 [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
70 };
71
72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
73 * them for both DP and FDI transports, allowing those ports to
74 * automatically adapt to HDMI connections as well
75 */
76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
77 { 0x00FFFFFF, 0x0006000E, 0x0 },
78 { 0x00D75FFF, 0x0005000A, 0x0 },
79 { 0x00C30FFF, 0x00040006, 0x0 },
80 { 0x80AAAFFF, 0x000B0000, 0x0 },
81 { 0x00FFFFFF, 0x0005000A, 0x0 },
82 { 0x00D75FFF, 0x000C0004, 0x0 },
83 { 0x80C30FFF, 0x000B0000, 0x0 },
84 { 0x00FFFFFF, 0x00040006, 0x0 },
85 { 0x80D75FFF, 0x000B0000, 0x0 },
86 };
87
88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
89 { 0x00FFFFFF, 0x0007000E, 0x0 },
90 { 0x00D75FFF, 0x000F000A, 0x0 },
91 { 0x00C30FFF, 0x00060006, 0x0 },
92 { 0x00AAAFFF, 0x001E0000, 0x0 },
93 { 0x00FFFFFF, 0x000F000A, 0x0 },
94 { 0x00D75FFF, 0x00160004, 0x0 },
95 { 0x00C30FFF, 0x001E0000, 0x0 },
96 { 0x00FFFFFF, 0x00060006, 0x0 },
97 { 0x00D75FFF, 0x001E0000, 0x0 },
98 };
99
100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
101 /* Idx NT mV d T mV d db */
102 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
103 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
104 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
105 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
106 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
107 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
108 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
109 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
110 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
111 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
112 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
113 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
114 };
115
116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
117 { 0x00FFFFFF, 0x00000012, 0x0 },
118 { 0x00EBAFFF, 0x00020011, 0x0 },
119 { 0x00C71FFF, 0x0006000F, 0x0 },
120 { 0x00AAAFFF, 0x000E000A, 0x0 },
121 { 0x00FFFFFF, 0x00020011, 0x0 },
122 { 0x00DB6FFF, 0x0005000F, 0x0 },
123 { 0x00BEEFFF, 0x000A000C, 0x0 },
124 { 0x00FFFFFF, 0x0005000F, 0x0 },
125 { 0x00DB6FFF, 0x000A000C, 0x0 },
126 };
127
128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
129 { 0x00FFFFFF, 0x0007000E, 0x0 },
130 { 0x00D75FFF, 0x000E000A, 0x0 },
131 { 0x00BEFFFF, 0x00140006, 0x0 },
132 { 0x80B2CFFF, 0x001B0002, 0x0 },
133 { 0x00FFFFFF, 0x000E000A, 0x0 },
134 { 0x00DB6FFF, 0x00160005, 0x0 },
135 { 0x80C71FFF, 0x001A0002, 0x0 },
136 { 0x00F7DFFF, 0x00180004, 0x0 },
137 { 0x80D75FFF, 0x001B0002, 0x0 },
138 };
139
140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
141 { 0x00FFFFFF, 0x0001000E, 0x0 },
142 { 0x00D75FFF, 0x0004000A, 0x0 },
143 { 0x00C30FFF, 0x00070006, 0x0 },
144 { 0x00AAAFFF, 0x000C0000, 0x0 },
145 { 0x00FFFFFF, 0x0004000A, 0x0 },
146 { 0x00D75FFF, 0x00090004, 0x0 },
147 { 0x00C30FFF, 0x000C0000, 0x0 },
148 { 0x00FFFFFF, 0x00070006, 0x0 },
149 { 0x00D75FFF, 0x000C0000, 0x0 },
150 };
151
152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
153 /* Idx NT mV d T mV df db */
154 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
155 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
156 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
157 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
158 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
159 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
160 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
161 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
162 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
163 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
164 };
165
166 /* Skylake H and S */
167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
168 { 0x00002016, 0x000000A0, 0x0 },
169 { 0x00005012, 0x0000009B, 0x0 },
170 { 0x00007011, 0x00000088, 0x0 },
171 { 0x80009010, 0x000000C0, 0x1 },
172 { 0x00002016, 0x0000009B, 0x0 },
173 { 0x00005012, 0x00000088, 0x0 },
174 { 0x80007011, 0x000000C0, 0x1 },
175 { 0x00002016, 0x000000DF, 0x0 },
176 { 0x80005012, 0x000000C0, 0x1 },
177 };
178
179 /* Skylake U */
180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
181 { 0x0000201B, 0x000000A2, 0x0 },
182 { 0x00005012, 0x00000088, 0x0 },
183 { 0x80007011, 0x000000CD, 0x1 },
184 { 0x80009010, 0x000000C0, 0x1 },
185 { 0x0000201B, 0x0000009D, 0x0 },
186 { 0x80005012, 0x000000C0, 0x1 },
187 { 0x80007011, 0x000000C0, 0x1 },
188 { 0x00002016, 0x00000088, 0x0 },
189 { 0x80005012, 0x000000C0, 0x1 },
190 };
191
192 /* Skylake Y */
193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
194 { 0x00000018, 0x000000A2, 0x0 },
195 { 0x00005012, 0x00000088, 0x0 },
196 { 0x80007011, 0x000000CD, 0x3 },
197 { 0x80009010, 0x000000C0, 0x3 },
198 { 0x00000018, 0x0000009D, 0x0 },
199 { 0x80005012, 0x000000C0, 0x3 },
200 { 0x80007011, 0x000000C0, 0x3 },
201 { 0x00000018, 0x00000088, 0x0 },
202 { 0x80005012, 0x000000C0, 0x3 },
203 };
204
205 /* Kabylake H and S */
206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
207 { 0x00002016, 0x000000A0, 0x0 },
208 { 0x00005012, 0x0000009B, 0x0 },
209 { 0x00007011, 0x00000088, 0x0 },
210 { 0x80009010, 0x000000C0, 0x1 },
211 { 0x00002016, 0x0000009B, 0x0 },
212 { 0x00005012, 0x00000088, 0x0 },
213 { 0x80007011, 0x000000C0, 0x1 },
214 { 0x00002016, 0x00000097, 0x0 },
215 { 0x80005012, 0x000000C0, 0x1 },
216 };
217
218 /* Kabylake U */
219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
220 { 0x0000201B, 0x000000A1, 0x0 },
221 { 0x00005012, 0x00000088, 0x0 },
222 { 0x80007011, 0x000000CD, 0x3 },
223 { 0x80009010, 0x000000C0, 0x3 },
224 { 0x0000201B, 0x0000009D, 0x0 },
225 { 0x80005012, 0x000000C0, 0x3 },
226 { 0x80007011, 0x000000C0, 0x3 },
227 { 0x00002016, 0x0000004F, 0x0 },
228 { 0x80005012, 0x000000C0, 0x3 },
229 };
230
231 /* Kabylake Y */
232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
233 { 0x00001017, 0x000000A1, 0x0 },
234 { 0x00005012, 0x00000088, 0x0 },
235 { 0x80007011, 0x000000CD, 0x3 },
236 { 0x8000800F, 0x000000C0, 0x3 },
237 { 0x00001017, 0x0000009D, 0x0 },
238 { 0x80005012, 0x000000C0, 0x3 },
239 { 0x80007011, 0x000000C0, 0x3 },
240 { 0x00001017, 0x0000004C, 0x0 },
241 { 0x80005012, 0x000000C0, 0x3 },
242 };
243
244 /*
245 * Skylake/Kabylake H and S
246 * eDP 1.4 low vswing translation parameters
247 */
248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
249 { 0x00000018, 0x000000A8, 0x0 },
250 { 0x00004013, 0x000000A9, 0x0 },
251 { 0x00007011, 0x000000A2, 0x0 },
252 { 0x00009010, 0x0000009C, 0x0 },
253 { 0x00000018, 0x000000A9, 0x0 },
254 { 0x00006013, 0x000000A2, 0x0 },
255 { 0x00007011, 0x000000A6, 0x0 },
256 { 0x00000018, 0x000000AB, 0x0 },
257 { 0x00007013, 0x0000009F, 0x0 },
258 { 0x00000018, 0x000000DF, 0x0 },
259 };
260
261 /*
262 * Skylake/Kabylake U
263 * eDP 1.4 low vswing translation parameters
264 */
265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
266 { 0x00000018, 0x000000A8, 0x0 },
267 { 0x00004013, 0x000000A9, 0x0 },
268 { 0x00007011, 0x000000A2, 0x0 },
269 { 0x00009010, 0x0000009C, 0x0 },
270 { 0x00000018, 0x000000A9, 0x0 },
271 { 0x00006013, 0x000000A2, 0x0 },
272 { 0x00007011, 0x000000A6, 0x0 },
273 { 0x00002016, 0x000000AB, 0x0 },
274 { 0x00005013, 0x0000009F, 0x0 },
275 { 0x00000018, 0x000000DF, 0x0 },
276 };
277
278 /*
279 * Skylake/Kabylake Y
280 * eDP 1.4 low vswing translation parameters
281 */
282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
283 { 0x00000018, 0x000000A8, 0x0 },
284 { 0x00004013, 0x000000AB, 0x0 },
285 { 0x00007011, 0x000000A4, 0x0 },
286 { 0x00009010, 0x000000DF, 0x0 },
287 { 0x00000018, 0x000000AA, 0x0 },
288 { 0x00006013, 0x000000A4, 0x0 },
289 { 0x00007011, 0x0000009D, 0x0 },
290 { 0x00000018, 0x000000A0, 0x0 },
291 { 0x00006012, 0x000000DF, 0x0 },
292 { 0x00000018, 0x0000008A, 0x0 },
293 };
294
295 /* Skylake/Kabylake U, H and S */
296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
297 { 0x00000018, 0x000000AC, 0x0 },
298 { 0x00005012, 0x0000009D, 0x0 },
299 { 0x00007011, 0x00000088, 0x0 },
300 { 0x00000018, 0x000000A1, 0x0 },
301 { 0x00000018, 0x00000098, 0x0 },
302 { 0x00004013, 0x00000088, 0x0 },
303 { 0x80006012, 0x000000CD, 0x1 },
304 { 0x00000018, 0x000000DF, 0x0 },
305 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
306 { 0x80003015, 0x000000C0, 0x1 },
307 { 0x80000018, 0x000000C0, 0x1 },
308 };
309
310 /* Skylake/Kabylake Y */
311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
312 { 0x00000018, 0x000000A1, 0x0 },
313 { 0x00005012, 0x000000DF, 0x0 },
314 { 0x80007011, 0x000000CB, 0x3 },
315 { 0x00000018, 0x000000A4, 0x0 },
316 { 0x00000018, 0x0000009D, 0x0 },
317 { 0x00004013, 0x00000080, 0x0 },
318 { 0x80006013, 0x000000C0, 0x3 },
319 { 0x00000018, 0x0000008A, 0x0 },
320 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
321 { 0x80003015, 0x000000C0, 0x3 },
322 { 0x80000018, 0x000000C0, 0x3 },
323 };
324
325 struct bxt_ddi_buf_trans {
326 u8 margin; /* swing value */
327 u8 scale; /* scale value */
328 u8 enable; /* scale enable */
329 u8 deemphasis;
330 };
331
332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
333 /* Idx NT mV diff db */
334 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
335 { 78, 0x9A, 0, 85, }, /* 1: 400 3.5 */
336 { 104, 0x9A, 0, 64, }, /* 2: 400 6 */
337 { 154, 0x9A, 0, 43, }, /* 3: 400 9.5 */
338 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
339 { 116, 0x9A, 0, 85, }, /* 5: 600 3.5 */
340 { 154, 0x9A, 0, 64, }, /* 6: 600 6 */
341 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
342 { 154, 0x9A, 0, 85, }, /* 8: 800 3.5 */
343 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
344 };
345
346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
347 /* Idx NT mV diff db */
348 { 26, 0, 0, 128, }, /* 0: 200 0 */
349 { 38, 0, 0, 112, }, /* 1: 200 1.5 */
350 { 48, 0, 0, 96, }, /* 2: 200 4 */
351 { 54, 0, 0, 69, }, /* 3: 200 6 */
352 { 32, 0, 0, 128, }, /* 4: 250 0 */
353 { 48, 0, 0, 104, }, /* 5: 250 1.5 */
354 { 54, 0, 0, 85, }, /* 6: 250 4 */
355 { 43, 0, 0, 128, }, /* 7: 300 0 */
356 { 54, 0, 0, 101, }, /* 8: 300 1.5 */
357 { 48, 0, 0, 128, }, /* 9: 300 0 */
358 };
359
360 /* BSpec has 2 recommended values - entries 0 and 8.
361 * Using the entry with higher vswing.
362 */
363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
364 /* Idx NT mV diff db */
365 { 52, 0x9A, 0, 128, }, /* 0: 400 0 */
366 { 52, 0x9A, 0, 85, }, /* 1: 400 3.5 */
367 { 52, 0x9A, 0, 64, }, /* 2: 400 6 */
368 { 42, 0x9A, 0, 43, }, /* 3: 400 9.5 */
369 { 77, 0x9A, 0, 128, }, /* 4: 600 0 */
370 { 77, 0x9A, 0, 85, }, /* 5: 600 3.5 */
371 { 77, 0x9A, 0, 64, }, /* 6: 600 6 */
372 { 102, 0x9A, 0, 128, }, /* 7: 800 0 */
373 { 102, 0x9A, 0, 85, }, /* 8: 800 3.5 */
374 { 154, 0x9A, 1, 128, }, /* 9: 1200 0 */
375 };
376
377 struct cnl_ddi_buf_trans {
378 u8 dw2_swing_sel;
379 u8 dw7_n_scalar;
380 u8 dw4_cursor_coeff;
381 u8 dw4_post_cursor_2;
382 u8 dw4_post_cursor_1;
383 };
384
385 /* Voltage Swing Programming for VccIO 0.85V for DP */
386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
387 /* NT mV Trans mV db */
388 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
389 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
390 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
391 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
392 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
393 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
394 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
395 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
396 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
397 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
398 };
399
400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
402 /* NT mV Trans mV db */
403 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
404 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
405 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
406 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 */
407 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
408 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
409 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
410 };
411
412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
414 /* NT mV Trans mV db */
415 { 0xA, 0x66, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
416 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
417 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
418 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
419 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
420 { 0xA, 0x66, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
421 { 0xB, 0x70, 0x3C, 0x00, 0x03 }, /* 460 600 2.3 */
422 { 0xC, 0x75, 0x3C, 0x00, 0x03 }, /* 537 700 2.3 */
423 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
424 };
425
426 /* Voltage Swing Programming for VccIO 0.95V for DP */
427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
428 /* NT mV Trans mV db */
429 { 0xA, 0x5D, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
430 { 0xA, 0x6A, 0x38, 0x00, 0x07 }, /* 350 500 3.1 */
431 { 0xB, 0x7A, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
432 { 0x6, 0x7C, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
433 { 0xA, 0x69, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
434 { 0xB, 0x7A, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
435 { 0x6, 0x7C, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
436 { 0xB, 0x7D, 0x3C, 0x00, 0x03 }, /* 650 725 0.9 */
437 { 0x6, 0x7C, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
438 { 0x6, 0x7B, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
439 };
440
441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
443 /* NT mV Trans mV db */
444 { 0xA, 0x5C, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
445 { 0xB, 0x69, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
446 { 0x5, 0x76, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
447 { 0xA, 0x5E, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
448 { 0xB, 0x69, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
449 { 0xB, 0x79, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
450 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
451 { 0x5, 0x76, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
452 { 0x6, 0x7D, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
453 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
454 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
455 };
456
457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
459 /* NT mV Trans mV db */
460 { 0xA, 0x61, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
461 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
462 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
463 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
464 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
465 { 0xA, 0x61, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
466 { 0xB, 0x68, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
467 { 0xC, 0x6E, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
468 { 0x4, 0x7F, 0x3A, 0x00, 0x05 }, /* 460 600 2.3 */
469 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
470 };
471
472 /* Voltage Swing Programming for VccIO 1.05V for DP */
473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
474 /* NT mV Trans mV db */
475 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
476 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
477 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
478 { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 400 1050 8.4 */
479 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
480 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
481 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 550 1050 5.6 */
482 { 0x5, 0x76, 0x3E, 0x00, 0x01 }, /* 850 900 0.5 */
483 { 0x6, 0x7F, 0x36, 0x00, 0x09 }, /* 750 1050 2.9 */
484 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
485 };
486
487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
489 /* NT mV Trans mV db */
490 { 0xA, 0x58, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
491 { 0xB, 0x64, 0x37, 0x00, 0x08 }, /* 400 600 3.5 */
492 { 0x5, 0x70, 0x31, 0x00, 0x0E }, /* 400 800 6.0 */
493 { 0xA, 0x5B, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
494 { 0xB, 0x64, 0x3F, 0x00, 0x00 }, /* 600 600 0.0 */
495 { 0x5, 0x73, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
496 { 0x6, 0x7C, 0x32, 0x00, 0x0D }, /* 600 1000 4.4 */
497 { 0x5, 0x70, 0x3F, 0x00, 0x00 }, /* 800 800 0.0 */
498 { 0x6, 0x7C, 0x39, 0x00, 0x06 }, /* 800 1000 1.9 */
499 { 0x6, 0x7F, 0x39, 0x00, 0x06 }, /* 850 1050 1.8 */
500 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1050 1050 0.0 */
501 };
502
503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
505 /* NT mV Trans mV db */
506 { 0xA, 0x5E, 0x3A, 0x00, 0x05 }, /* 384 500 2.3 */
507 { 0x0, 0x7F, 0x38, 0x00, 0x07 }, /* 153 200 2.3 */
508 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 192 250 2.3 */
509 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 230 300 2.3 */
510 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 269 350 2.3 */
511 { 0xA, 0x5E, 0x3C, 0x00, 0x03 }, /* 446 500 1.0 */
512 { 0xB, 0x64, 0x39, 0x00, 0x06 }, /* 460 600 2.3 */
513 { 0xE, 0x6A, 0x39, 0x00, 0x06 }, /* 537 700 2.3 */
514 { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
515 };
516
517 /* icl_combo_phy_ddi_translations */
518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
519 /* NT mV Trans mV db */
520 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
521 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
522 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
523 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
524 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
525 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
526 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
527 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
528 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
529 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
530 };
531
532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
533 /* NT mV Trans mV db */
534 { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
535 { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
536 { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
537 { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
538 { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
539 { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
540 { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
541 { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
542 { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
543 { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
544 };
545
546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
547 /* NT mV Trans mV db */
548 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
549 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
550 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
551 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
552 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
553 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
554 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
555 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
556 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
557 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
558 };
559
560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
561 /* NT mV Trans mV db */
562 { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
563 { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
564 { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
565 { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
566 { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
567 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
568 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
569 };
570
571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
572 /* NT mV Trans mV db */
573 { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
574 { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
575 { 0xC, 0x64, 0x34, 0x00, 0x0B }, /* 350 700 6.0 */
576 { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 350 900 8.2 */
577 { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
578 { 0xC, 0x64, 0x38, 0x00, 0x07 }, /* 500 700 2.9 */
579 { 0x6, 0x7F, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
580 { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
581 { 0x6, 0x7F, 0x38, 0x00, 0x07 }, /* 600 900 3.5 */
582 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
583 };
584
585 struct icl_mg_phy_ddi_buf_trans {
586 u32 cri_txdeemph_override_11_6;
587 u32 cri_txdeemph_override_5_0;
588 u32 cri_txdeemph_override_17_12;
589 };
590
591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
592 /* Voltage swing pre-emphasis */
593 { 0x18, 0x00, 0x00 }, /* 0 0 */
594 { 0x1D, 0x00, 0x05 }, /* 0 1 */
595 { 0x24, 0x00, 0x0C }, /* 0 2 */
596 { 0x2B, 0x00, 0x14 }, /* 0 3 */
597 { 0x21, 0x00, 0x00 }, /* 1 0 */
598 { 0x2B, 0x00, 0x08 }, /* 1 1 */
599 { 0x30, 0x00, 0x0F }, /* 1 2 */
600 { 0x31, 0x00, 0x03 }, /* 2 0 */
601 { 0x34, 0x00, 0x0B }, /* 2 1 */
602 { 0x3F, 0x00, 0x00 }, /* 3 0 */
603 };
604
605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
606 /* Voltage swing pre-emphasis */
607 { 0x18, 0x00, 0x00 }, /* 0 0 */
608 { 0x1D, 0x00, 0x05 }, /* 0 1 */
609 { 0x24, 0x00, 0x0C }, /* 0 2 */
610 { 0x2B, 0x00, 0x14 }, /* 0 3 */
611 { 0x26, 0x00, 0x00 }, /* 1 0 */
612 { 0x2C, 0x00, 0x07 }, /* 1 1 */
613 { 0x33, 0x00, 0x0C }, /* 1 2 */
614 { 0x2E, 0x00, 0x00 }, /* 2 0 */
615 { 0x36, 0x00, 0x09 }, /* 2 1 */
616 { 0x3F, 0x00, 0x00 }, /* 3 0 */
617 };
618
619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
620 /* HDMI Preset VS Pre-emph */
621 { 0x1A, 0x0, 0x0 }, /* 1 400mV 0dB */
622 { 0x20, 0x0, 0x0 }, /* 2 500mV 0dB */
623 { 0x29, 0x0, 0x0 }, /* 3 650mV 0dB */
624 { 0x32, 0x0, 0x0 }, /* 4 800mV 0dB */
625 { 0x3F, 0x0, 0x0 }, /* 5 1000mV 0dB */
626 { 0x3A, 0x0, 0x5 }, /* 6 Full -1.5 dB */
627 { 0x39, 0x0, 0x6 }, /* 7 Full -1.8 dB */
628 { 0x38, 0x0, 0x7 }, /* 8 Full -2 dB */
629 { 0x37, 0x0, 0x8 }, /* 9 Full -2.5 dB */
630 { 0x36, 0x0, 0x9 }, /* 10 Full -3 dB */
631 };
632
633 struct tgl_dkl_phy_ddi_buf_trans {
634 u32 dkl_vswing_control;
635 u32 dkl_preshoot_control;
636 u32 dkl_de_emphasis_control;
637 };
638
639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
640 /* VS pre-emp Non-trans mV Pre-emph dB */
641 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
642 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
643 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
644 { 0x0, 0x0, 0x18 }, /* 0 3 400mV 9.5 dB */
645 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
646 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
647 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
648 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
649 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
650 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
651 };
652
653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
654 /* VS pre-emp Non-trans mV Pre-emph dB */
655 { 0x7, 0x0, 0x00 }, /* 0 0 400mV 0 dB */
656 { 0x5, 0x0, 0x05 }, /* 0 1 400mV 3.5 dB */
657 { 0x2, 0x0, 0x0B }, /* 0 2 400mV 6 dB */
658 { 0x0, 0x0, 0x19 }, /* 0 3 400mV 9.5 dB */
659 { 0x5, 0x0, 0x00 }, /* 1 0 600mV 0 dB */
660 { 0x2, 0x0, 0x08 }, /* 1 1 600mV 3.5 dB */
661 { 0x0, 0x0, 0x14 }, /* 1 2 600mV 6 dB */
662 { 0x2, 0x0, 0x00 }, /* 2 0 800mV 0 dB */
663 { 0x0, 0x0, 0x0B }, /* 2 1 800mV 3.5 dB */
664 { 0x0, 0x0, 0x00 }, /* 3 0 1200mV 0 dB HDMI default */
665 };
666
667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
668 /* HDMI Preset VS Pre-emph */
669 { 0x7, 0x0, 0x0 }, /* 1 400mV 0dB */
670 { 0x6, 0x0, 0x0 }, /* 2 500mV 0dB */
671 { 0x4, 0x0, 0x0 }, /* 3 650mV 0dB */
672 { 0x2, 0x0, 0x0 }, /* 4 800mV 0dB */
673 { 0x0, 0x0, 0x0 }, /* 5 1000mV 0dB */
674 { 0x0, 0x0, 0x5 }, /* 6 Full -1.5 dB */
675 { 0x0, 0x0, 0x6 }, /* 7 Full -1.8 dB */
676 { 0x0, 0x0, 0x7 }, /* 8 Full -2 dB */
677 { 0x0, 0x0, 0x8 }, /* 9 Full -2.5 dB */
678 { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */
679 };
680
681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
682 /* NT mV Trans mV db */
683 { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
684 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
685 { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
686 { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
687 { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
688 { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
689 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
690 { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
691 { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
692 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
693 };
694
695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
696 /* NT mV Trans mV db */
697 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
698 { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
699 { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
700 { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
701 { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
702 { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
703 { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
704 { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
705 { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
706 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
707 };
708
709 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
710 /* NT mV Trans mV db */
711 { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
712 { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */
713 { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */
714 { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */
715 { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
716 { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
717 { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */
718 { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
719 { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */
720 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
721 };
722
723 /*
724 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
725 * that DisplayPort specification requires
726 */
727 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
728 /* VS pre-emp */
729 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 0 */
730 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 1 */
731 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 2 */
732 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 0 3 */
733 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 0 */
734 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 1 */
735 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 1 2 */
736 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 0 */
737 { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 2 1 */
738 };
739
is_hobl_buf_trans(const struct cnl_ddi_buf_trans * table)740 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
741 {
742 return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
743 }
744
745 static const struct ddi_buf_trans *
bdw_get_buf_trans_edp(struct intel_encoder * encoder,int * n_entries)746 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
747 {
748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
749
750 if (dev_priv->vbt.edp.low_vswing) {
751 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
752 return bdw_ddi_translations_edp;
753 } else {
754 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
755 return bdw_ddi_translations_dp;
756 }
757 }
758
759 static const struct ddi_buf_trans *
skl_get_buf_trans_dp(struct intel_encoder * encoder,int * n_entries)760 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
761 {
762 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
763
764 if (IS_SKL_ULX(dev_priv)) {
765 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
766 return skl_y_ddi_translations_dp;
767 } else if (IS_SKL_ULT(dev_priv)) {
768 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
769 return skl_u_ddi_translations_dp;
770 } else {
771 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
772 return skl_ddi_translations_dp;
773 }
774 }
775
776 static const struct ddi_buf_trans *
kbl_get_buf_trans_dp(struct intel_encoder * encoder,int * n_entries)777 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
778 {
779 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
780
781 if (IS_KBL_ULX(dev_priv) ||
782 IS_CFL_ULX(dev_priv) ||
783 IS_CML_ULX(dev_priv)) {
784 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
785 return kbl_y_ddi_translations_dp;
786 } else if (IS_KBL_ULT(dev_priv) ||
787 IS_CFL_ULT(dev_priv) ||
788 IS_CML_ULT(dev_priv)) {
789 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
790 return kbl_u_ddi_translations_dp;
791 } else {
792 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
793 return kbl_ddi_translations_dp;
794 }
795 }
796
797 static const struct ddi_buf_trans *
skl_get_buf_trans_edp(struct intel_encoder * encoder,int * n_entries)798 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
799 {
800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
801
802 if (dev_priv->vbt.edp.low_vswing) {
803 if (IS_SKL_ULX(dev_priv) ||
804 IS_KBL_ULX(dev_priv) ||
805 IS_CFL_ULX(dev_priv) ||
806 IS_CML_ULX(dev_priv)) {
807 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
808 return skl_y_ddi_translations_edp;
809 } else if (IS_SKL_ULT(dev_priv) ||
810 IS_KBL_ULT(dev_priv) ||
811 IS_CFL_ULT(dev_priv) ||
812 IS_CML_ULT(dev_priv)) {
813 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
814 return skl_u_ddi_translations_edp;
815 } else {
816 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
817 return skl_ddi_translations_edp;
818 }
819 }
820
821 if (IS_KABYLAKE(dev_priv) ||
822 IS_COFFEELAKE(dev_priv) ||
823 IS_COMETLAKE(dev_priv))
824 return kbl_get_buf_trans_dp(encoder, n_entries);
825 else
826 return skl_get_buf_trans_dp(encoder, n_entries);
827 }
828
829 static const struct ddi_buf_trans *
skl_get_buf_trans_hdmi(struct drm_i915_private * dev_priv,int * n_entries)830 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
831 {
832 if (IS_SKL_ULX(dev_priv) ||
833 IS_KBL_ULX(dev_priv) ||
834 IS_CFL_ULX(dev_priv) ||
835 IS_CML_ULX(dev_priv)) {
836 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
837 return skl_y_ddi_translations_hdmi;
838 } else {
839 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
840 return skl_ddi_translations_hdmi;
841 }
842 }
843
skl_buf_trans_num_entries(enum port port,int n_entries)844 static int skl_buf_trans_num_entries(enum port port, int n_entries)
845 {
846 /* Only DDIA and DDIE can select the 10th register with DP */
847 if (port == PORT_A || port == PORT_E)
848 return min(n_entries, 10);
849 else
850 return min(n_entries, 9);
851 }
852
853 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_dp(struct intel_encoder * encoder,int * n_entries)854 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
855 {
856 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
857
858 if (IS_KABYLAKE(dev_priv) ||
859 IS_COFFEELAKE(dev_priv) ||
860 IS_COMETLAKE(dev_priv)) {
861 const struct ddi_buf_trans *ddi_translations =
862 kbl_get_buf_trans_dp(encoder, n_entries);
863 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
864 return ddi_translations;
865 } else if (IS_SKYLAKE(dev_priv)) {
866 const struct ddi_buf_trans *ddi_translations =
867 skl_get_buf_trans_dp(encoder, n_entries);
868 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
869 return ddi_translations;
870 } else if (IS_BROADWELL(dev_priv)) {
871 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
872 return bdw_ddi_translations_dp;
873 } else if (IS_HASWELL(dev_priv)) {
874 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
875 return hsw_ddi_translations_dp;
876 }
877
878 *n_entries = 0;
879 return NULL;
880 }
881
882 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_edp(struct intel_encoder * encoder,int * n_entries)883 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
884 {
885 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
886
887 if (IS_GEN9_BC(dev_priv)) {
888 const struct ddi_buf_trans *ddi_translations =
889 skl_get_buf_trans_edp(encoder, n_entries);
890 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
891 return ddi_translations;
892 } else if (IS_BROADWELL(dev_priv)) {
893 return bdw_get_buf_trans_edp(encoder, n_entries);
894 } else if (IS_HASWELL(dev_priv)) {
895 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
896 return hsw_ddi_translations_dp;
897 }
898
899 *n_entries = 0;
900 return NULL;
901 }
902
903 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_fdi(struct drm_i915_private * dev_priv,int * n_entries)904 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
905 int *n_entries)
906 {
907 if (IS_BROADWELL(dev_priv)) {
908 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
909 return bdw_ddi_translations_fdi;
910 } else if (IS_HASWELL(dev_priv)) {
911 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
912 return hsw_ddi_translations_fdi;
913 }
914
915 *n_entries = 0;
916 return NULL;
917 }
918
919 static const struct ddi_buf_trans *
intel_ddi_get_buf_trans_hdmi(struct intel_encoder * encoder,int * n_entries)920 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
921 int *n_entries)
922 {
923 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
924
925 if (IS_GEN9_BC(dev_priv)) {
926 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
927 } else if (IS_BROADWELL(dev_priv)) {
928 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
929 return bdw_ddi_translations_hdmi;
930 } else if (IS_HASWELL(dev_priv)) {
931 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
932 return hsw_ddi_translations_hdmi;
933 }
934
935 *n_entries = 0;
936 return NULL;
937 }
938
939 static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_dp(struct intel_encoder * encoder,int * n_entries)940 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
941 {
942 *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
943 return bxt_ddi_translations_dp;
944 }
945
946 static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_edp(struct intel_encoder * encoder,int * n_entries)947 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
948 {
949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
950
951 if (dev_priv->vbt.edp.low_vswing) {
952 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
953 return bxt_ddi_translations_edp;
954 }
955
956 return bxt_get_buf_trans_dp(encoder, n_entries);
957 }
958
959 static const struct bxt_ddi_buf_trans *
bxt_get_buf_trans_hdmi(struct intel_encoder * encoder,int * n_entries)960 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
961 {
962 *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
963 return bxt_ddi_translations_hdmi;
964 }
965
966 static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_hdmi(struct intel_encoder * encoder,int * n_entries)967 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
968 {
969 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
970 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
971
972 if (voltage == VOLTAGE_INFO_0_85V) {
973 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
974 return cnl_ddi_translations_hdmi_0_85V;
975 } else if (voltage == VOLTAGE_INFO_0_95V) {
976 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
977 return cnl_ddi_translations_hdmi_0_95V;
978 } else if (voltage == VOLTAGE_INFO_1_05V) {
979 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
980 return cnl_ddi_translations_hdmi_1_05V;
981 } else {
982 *n_entries = 1; /* shut up gcc */
983 MISSING_CASE(voltage);
984 }
985 return NULL;
986 }
987
988 static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_dp(struct intel_encoder * encoder,int * n_entries)989 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
990 {
991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
992 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
993
994 if (voltage == VOLTAGE_INFO_0_85V) {
995 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
996 return cnl_ddi_translations_dp_0_85V;
997 } else if (voltage == VOLTAGE_INFO_0_95V) {
998 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
999 return cnl_ddi_translations_dp_0_95V;
1000 } else if (voltage == VOLTAGE_INFO_1_05V) {
1001 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1002 return cnl_ddi_translations_dp_1_05V;
1003 } else {
1004 *n_entries = 1; /* shut up gcc */
1005 MISSING_CASE(voltage);
1006 }
1007 return NULL;
1008 }
1009
1010 static const struct cnl_ddi_buf_trans *
cnl_get_buf_trans_edp(struct intel_encoder * encoder,int * n_entries)1011 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1012 {
1013 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1014 u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1015
1016 if (dev_priv->vbt.edp.low_vswing) {
1017 if (voltage == VOLTAGE_INFO_0_85V) {
1018 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1019 return cnl_ddi_translations_edp_0_85V;
1020 } else if (voltage == VOLTAGE_INFO_0_95V) {
1021 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1022 return cnl_ddi_translations_edp_0_95V;
1023 } else if (voltage == VOLTAGE_INFO_1_05V) {
1024 *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1025 return cnl_ddi_translations_edp_1_05V;
1026 } else {
1027 *n_entries = 1; /* shut up gcc */
1028 MISSING_CASE(voltage);
1029 }
1030 return NULL;
1031 } else {
1032 return cnl_get_buf_trans_dp(encoder, n_entries);
1033 }
1034 }
1035
1036 static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct intel_encoder * encoder,int type,int rate,int * n_entries)1037 icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1038 int *n_entries)
1039 {
1040 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1041
1042 if (type == INTEL_OUTPUT_HDMI) {
1043 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1044 return icl_combo_phy_ddi_translations_hdmi;
1045 } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
1046 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1047 return icl_combo_phy_ddi_translations_edp_hbr3;
1048 } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1049 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1050 return icl_combo_phy_ddi_translations_edp_hbr2;
1051 }
1052
1053 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1054 return icl_combo_phy_ddi_translations_dp_hbr2;
1055 }
1056
1057 static const struct icl_mg_phy_ddi_buf_trans *
icl_get_mg_buf_trans(struct intel_encoder * encoder,int type,int rate,int * n_entries)1058 icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
1059 int *n_entries)
1060 {
1061 if (type == INTEL_OUTPUT_HDMI) {
1062 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1063 return icl_mg_phy_ddi_translations_hdmi;
1064 } else if (rate > 270000) {
1065 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1066 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1067 }
1068
1069 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1070 return icl_mg_phy_ddi_translations_rbr_hbr;
1071 }
1072
1073 static const struct cnl_ddi_buf_trans *
ehl_get_combo_buf_trans(struct intel_encoder * encoder,int type,int rate,int * n_entries)1074 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1075 int *n_entries)
1076 {
1077 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1078
1079 switch (type) {
1080 case INTEL_OUTPUT_HDMI:
1081 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1082 return icl_combo_phy_ddi_translations_hdmi;
1083 case INTEL_OUTPUT_EDP:
1084 if (dev_priv->vbt.edp.low_vswing) {
1085 if (rate > 540000) {
1086 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1087 return icl_combo_phy_ddi_translations_edp_hbr3;
1088 } else {
1089 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1090 return icl_combo_phy_ddi_translations_edp_hbr2;
1091 }
1092 }
1093 /* fall through */
1094 default:
1095 /* All combo DP and eDP ports that do not support low_vswing */
1096 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1097 return ehl_combo_phy_ddi_translations_dp;
1098 }
1099 }
1100
1101 static const struct cnl_ddi_buf_trans *
tgl_get_combo_buf_trans(struct intel_encoder * encoder,int type,int rate,int * n_entries)1102 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1103 int *n_entries)
1104 {
1105 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1106
1107 switch (type) {
1108 case INTEL_OUTPUT_HDMI:
1109 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1110 return icl_combo_phy_ddi_translations_hdmi;
1111 case INTEL_OUTPUT_EDP:
1112 if (dev_priv->vbt.edp.hobl) {
1113 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1114
1115 if (!intel_dp->hobl_failed && rate <= 540000) {
1116 /* Same table applies to TGL, RKL and DG1 */
1117 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1118 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1119 }
1120 }
1121
1122 if (rate > 540000) {
1123 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1124 return icl_combo_phy_ddi_translations_edp_hbr3;
1125 } else if (dev_priv->vbt.edp.low_vswing) {
1126 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1127 return icl_combo_phy_ddi_translations_edp_hbr2;
1128 }
1129 /* fall through */
1130 default:
1131 /* All combo DP and eDP ports that do not support low_vswing */
1132 if (rate > 270000) {
1133 if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1134 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
1135 return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
1136 }
1137
1138 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1139 return tgl_combo_phy_ddi_translations_dp_hbr2;
1140 }
1141
1142 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1143 return tgl_combo_phy_ddi_translations_dp_hbr;
1144 }
1145 }
1146
1147 static const struct tgl_dkl_phy_ddi_buf_trans *
tgl_get_dkl_buf_trans(struct intel_encoder * encoder,int type,int rate,int * n_entries)1148 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
1149 int *n_entries)
1150 {
1151 if (type == INTEL_OUTPUT_HDMI) {
1152 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1153 return tgl_dkl_phy_hdmi_ddi_trans;
1154 } else if (rate > 270000) {
1155 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1156 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1157 }
1158
1159 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1160 return tgl_dkl_phy_dp_ddi_trans;
1161 }
1162
intel_ddi_hdmi_level(struct intel_encoder * encoder)1163 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
1164 {
1165 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1166 int n_entries, level, default_entry;
1167 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1168
1169 if (INTEL_GEN(dev_priv) >= 12) {
1170 if (intel_phy_is_combo(dev_priv, phy))
1171 tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1172 0, &n_entries);
1173 else
1174 tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1175 &n_entries);
1176 default_entry = n_entries - 1;
1177 } else if (INTEL_GEN(dev_priv) == 11) {
1178 if (intel_phy_is_combo(dev_priv, phy))
1179 icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1180 0, &n_entries);
1181 else
1182 icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1183 &n_entries);
1184 default_entry = n_entries - 1;
1185 } else if (IS_CANNONLAKE(dev_priv)) {
1186 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1187 default_entry = n_entries - 1;
1188 } else if (IS_GEN9_LP(dev_priv)) {
1189 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1190 default_entry = n_entries - 1;
1191 } else if (IS_GEN9_BC(dev_priv)) {
1192 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1193 default_entry = 8;
1194 } else if (IS_BROADWELL(dev_priv)) {
1195 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1196 default_entry = 7;
1197 } else if (IS_HASWELL(dev_priv)) {
1198 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1199 default_entry = 6;
1200 } else {
1201 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1202 return 0;
1203 }
1204
1205 if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1206 return 0;
1207
1208 level = intel_bios_hdmi_level_shift(encoder);
1209 if (level < 0)
1210 level = default_entry;
1211
1212 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1213 level = n_entries - 1;
1214
1215 return level;
1216 }
1217
1218 /*
1219 * Starting with Haswell, DDI port buffers must be programmed with correct
1220 * values in advance. This function programs the correct values for
1221 * DP/eDP/FDI use cases.
1222 */
intel_prepare_dp_ddi_buffers(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1223 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1224 const struct intel_crtc_state *crtc_state)
1225 {
1226 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1227 u32 iboost_bit = 0;
1228 int i, n_entries;
1229 enum port port = encoder->port;
1230 const struct ddi_buf_trans *ddi_translations;
1231
1232 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1233 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1234 &n_entries);
1235 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1236 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
1237 &n_entries);
1238 else
1239 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
1240 &n_entries);
1241
1242 /* If we're boosting the current, set bit 31 of trans1 */
1243 if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1244 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1245
1246 for (i = 0; i < n_entries; i++) {
1247 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1248 ddi_translations[i].trans1 | iboost_bit);
1249 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1250 ddi_translations[i].trans2);
1251 }
1252 }
1253
1254 /*
1255 * Starting with Haswell, DDI port buffers must be programmed with correct
1256 * values in advance. This function programs the correct values for
1257 * HDMI/DVI use cases.
1258 */
intel_prepare_hdmi_ddi_buffers(struct intel_encoder * encoder,int level)1259 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1260 int level)
1261 {
1262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1263 u32 iboost_bit = 0;
1264 int n_entries;
1265 enum port port = encoder->port;
1266 const struct ddi_buf_trans *ddi_translations;
1267
1268 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1269
1270 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1271 return;
1272 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1273 level = n_entries - 1;
1274
1275 /* If we're boosting the current, set bit 31 of trans1 */
1276 if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1277 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1278
1279 /* Entry 9 is for HDMI: */
1280 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1281 ddi_translations[level].trans1 | iboost_bit);
1282 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1283 ddi_translations[level].trans2);
1284 }
1285
intel_wait_ddi_buf_idle(struct drm_i915_private * dev_priv,enum port port)1286 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1287 enum port port)
1288 {
1289 if (IS_BROXTON(dev_priv)) {
1290 udelay(16);
1291 return;
1292 }
1293
1294 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1295 DDI_BUF_IS_IDLE), 8))
1296 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
1297 port_name(port));
1298 }
1299
intel_wait_ddi_buf_active(struct drm_i915_private * dev_priv,enum port port)1300 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
1301 enum port port)
1302 {
1303 /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
1304 if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
1305 usleep_range(518, 1000);
1306 return;
1307 }
1308
1309 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1310 DDI_BUF_IS_IDLE), 500))
1311 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
1312 port_name(port));
1313 }
1314
hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll * pll)1315 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1316 {
1317 switch (pll->info->id) {
1318 case DPLL_ID_WRPLL1:
1319 return PORT_CLK_SEL_WRPLL1;
1320 case DPLL_ID_WRPLL2:
1321 return PORT_CLK_SEL_WRPLL2;
1322 case DPLL_ID_SPLL:
1323 return PORT_CLK_SEL_SPLL;
1324 case DPLL_ID_LCPLL_810:
1325 return PORT_CLK_SEL_LCPLL_810;
1326 case DPLL_ID_LCPLL_1350:
1327 return PORT_CLK_SEL_LCPLL_1350;
1328 case DPLL_ID_LCPLL_2700:
1329 return PORT_CLK_SEL_LCPLL_2700;
1330 default:
1331 MISSING_CASE(pll->info->id);
1332 return PORT_CLK_SEL_NONE;
1333 }
1334 }
1335
icl_pll_to_ddi_clk_sel(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1336 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1337 const struct intel_crtc_state *crtc_state)
1338 {
1339 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1340 int clock = crtc_state->port_clock;
1341 const enum intel_dpll_id id = pll->info->id;
1342
1343 switch (id) {
1344 default:
1345 /*
1346 * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1347 * here, so do warn if this get passed in
1348 */
1349 MISSING_CASE(id);
1350 return DDI_CLK_SEL_NONE;
1351 case DPLL_ID_ICL_TBTPLL:
1352 switch (clock) {
1353 case 162000:
1354 return DDI_CLK_SEL_TBT_162;
1355 case 270000:
1356 return DDI_CLK_SEL_TBT_270;
1357 case 540000:
1358 return DDI_CLK_SEL_TBT_540;
1359 case 810000:
1360 return DDI_CLK_SEL_TBT_810;
1361 default:
1362 MISSING_CASE(clock);
1363 return DDI_CLK_SEL_NONE;
1364 }
1365 case DPLL_ID_ICL_MGPLL1:
1366 case DPLL_ID_ICL_MGPLL2:
1367 case DPLL_ID_ICL_MGPLL3:
1368 case DPLL_ID_ICL_MGPLL4:
1369 case DPLL_ID_TGL_MGPLL5:
1370 case DPLL_ID_TGL_MGPLL6:
1371 return DDI_CLK_SEL_MG;
1372 }
1373 }
1374
1375 /* Starting with Haswell, different DDI ports can work in FDI mode for
1376 * connection to the PCH-located connectors. For this, it is necessary to train
1377 * both the DDI port and PCH receiver for the desired DDI buffer settings.
1378 *
1379 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1380 * please note that when FDI mode is active on DDI E, it shares 2 lines with
1381 * DDI A (which is used for eDP)
1382 */
1383
hsw_fdi_link_train(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1384 void hsw_fdi_link_train(struct intel_encoder *encoder,
1385 const struct intel_crtc_state *crtc_state)
1386 {
1387 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1388 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1389 u32 temp, i, rx_ctl_val, ddi_pll_sel;
1390
1391 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1392
1393 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1394 * mode set "sequence for CRT port" document:
1395 * - TP1 to TP2 time with the default value
1396 * - FDI delay to 90h
1397 *
1398 * WaFDIAutoLinkSetTimingOverrride:hsw
1399 */
1400 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1401 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1402
1403 /* Enable the PCH Receiver FDI PLL */
1404 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1405 FDI_RX_PLL_ENABLE |
1406 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1407 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1408 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1409 udelay(220);
1410
1411 /* Switch from Rawclk to PCDclk */
1412 rx_ctl_val |= FDI_PCDCLK;
1413 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1414
1415 /* Configure Port Clock Select */
1416 ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1417 intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1418 drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1419
1420 /* Start the training iterating through available voltages and emphasis,
1421 * testing each value twice. */
1422 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1423 /* Configure DP_TP_CTL with auto-training */
1424 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1425 DP_TP_CTL_FDI_AUTOTRAIN |
1426 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1427 DP_TP_CTL_LINK_TRAIN_PAT1 |
1428 DP_TP_CTL_ENABLE);
1429
1430 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1431 * DDI E does not support port reversal, the functionality is
1432 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1433 * port reversal bit */
1434 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1435 DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1436 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1437
1438 udelay(600);
1439
1440 /* Program PCH FDI Receiver TU */
1441 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1442
1443 /* Enable PCH FDI Receiver with auto-training */
1444 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1445 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1446 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1447
1448 /* Wait for FDI receiver lane calibration */
1449 udelay(30);
1450
1451 /* Unset FDI_RX_MISC pwrdn lanes */
1452 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1453 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1454 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1455 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1456
1457 /* Wait for FDI auto training time */
1458 udelay(5);
1459
1460 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1461 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1462 drm_dbg_kms(&dev_priv->drm,
1463 "FDI link training done on step %d\n", i);
1464 break;
1465 }
1466
1467 /*
1468 * Leave things enabled even if we failed to train FDI.
1469 * Results in less fireworks from the state checker.
1470 */
1471 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1472 drm_err(&dev_priv->drm, "FDI link training failed!\n");
1473 break;
1474 }
1475
1476 rx_ctl_val &= ~FDI_RX_ENABLE;
1477 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1478 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1479
1480 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1481 temp &= ~DDI_BUF_CTL_ENABLE;
1482 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1483 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1484
1485 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1486 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1487 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1488 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1489 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1490 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1491
1492 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1493
1494 /* Reset FDI_RX_MISC pwrdn lanes */
1495 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1496 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1497 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1498 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1499 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1500 }
1501
1502 /* Enable normal pixel sending for FDI */
1503 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1504 DP_TP_CTL_FDI_AUTOTRAIN |
1505 DP_TP_CTL_LINK_TRAIN_NORMAL |
1506 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1507 DP_TP_CTL_ENABLE);
1508 }
1509
intel_ddi_init_dp_buf_reg(struct intel_encoder * encoder)1510 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1511 {
1512 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1513 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1514
1515 intel_dp->DP = dig_port->saved_port_bits |
1516 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1517 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1518 }
1519
icl_calc_tbt_pll_link(struct drm_i915_private * dev_priv,enum port port)1520 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1521 enum port port)
1522 {
1523 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1524
1525 switch (val) {
1526 case DDI_CLK_SEL_NONE:
1527 return 0;
1528 case DDI_CLK_SEL_TBT_162:
1529 return 162000;
1530 case DDI_CLK_SEL_TBT_270:
1531 return 270000;
1532 case DDI_CLK_SEL_TBT_540:
1533 return 540000;
1534 case DDI_CLK_SEL_TBT_810:
1535 return 810000;
1536 default:
1537 MISSING_CASE(val);
1538 return 0;
1539 }
1540 }
1541
ddi_dotclock_get(struct intel_crtc_state * pipe_config)1542 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1543 {
1544 int dotclock;
1545
1546 if (pipe_config->has_pch_encoder)
1547 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1548 &pipe_config->fdi_m_n);
1549 else if (intel_crtc_has_dp_encoder(pipe_config))
1550 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1551 &pipe_config->dp_m_n);
1552 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1553 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1554 else
1555 dotclock = pipe_config->port_clock;
1556
1557 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1558 !intel_crtc_has_dp_encoder(pipe_config))
1559 dotclock *= 2;
1560
1561 if (pipe_config->pixel_multiplier)
1562 dotclock /= pipe_config->pixel_multiplier;
1563
1564 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1565 }
1566
intel_ddi_clock_get(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)1567 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1568 struct intel_crtc_state *pipe_config)
1569 {
1570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1571 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1572
1573 if (intel_phy_is_tc(dev_priv, phy) &&
1574 intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1575 DPLL_ID_ICL_TBTPLL)
1576 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1577 encoder->port);
1578 else
1579 pipe_config->port_clock =
1580 intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1581
1582 ddi_dotclock_get(pipe_config);
1583 }
1584
intel_ddi_set_dp_msa(const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)1585 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1586 const struct drm_connector_state *conn_state)
1587 {
1588 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1589 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1590 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1591 u32 temp;
1592
1593 if (!intel_crtc_has_dp_encoder(crtc_state))
1594 return;
1595
1596 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1597
1598 temp = DP_MSA_MISC_SYNC_CLOCK;
1599
1600 switch (crtc_state->pipe_bpp) {
1601 case 18:
1602 temp |= DP_MSA_MISC_6_BPC;
1603 break;
1604 case 24:
1605 temp |= DP_MSA_MISC_8_BPC;
1606 break;
1607 case 30:
1608 temp |= DP_MSA_MISC_10_BPC;
1609 break;
1610 case 36:
1611 temp |= DP_MSA_MISC_12_BPC;
1612 break;
1613 default:
1614 MISSING_CASE(crtc_state->pipe_bpp);
1615 break;
1616 }
1617
1618 /* nonsense combination */
1619 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1620 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1621
1622 if (crtc_state->limited_color_range)
1623 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1624
1625 /*
1626 * As per DP 1.2 spec section 2.3.4.3 while sending
1627 * YCBCR 444 signals we should program MSA MISC1/0 fields with
1628 * colorspace information.
1629 */
1630 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1631 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1632
1633 /*
1634 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1635 * of Color Encoding Format and Content Color Gamut] while sending
1636 * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1637 * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1638 */
1639 if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1640 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1641
1642 intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1643 }
1644
bdw_trans_port_sync_master_select(enum transcoder master_transcoder)1645 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1646 {
1647 if (master_transcoder == TRANSCODER_EDP)
1648 return 0;
1649 else
1650 return master_transcoder + 1;
1651 }
1652
1653 /*
1654 * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1655 *
1656 * Only intended to be used by intel_ddi_enable_transcoder_func() and
1657 * intel_ddi_config_transcoder_func().
1658 */
1659 static u32
intel_ddi_transcoder_func_reg_val_get(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1660 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1661 const struct intel_crtc_state *crtc_state)
1662 {
1663 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1664 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665 enum pipe pipe = crtc->pipe;
1666 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1667 enum port port = encoder->port;
1668 u32 temp;
1669
1670 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1671 temp = TRANS_DDI_FUNC_ENABLE;
1672 if (INTEL_GEN(dev_priv) >= 12)
1673 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1674 else
1675 temp |= TRANS_DDI_SELECT_PORT(port);
1676
1677 switch (crtc_state->pipe_bpp) {
1678 case 18:
1679 temp |= TRANS_DDI_BPC_6;
1680 break;
1681 case 24:
1682 temp |= TRANS_DDI_BPC_8;
1683 break;
1684 case 30:
1685 temp |= TRANS_DDI_BPC_10;
1686 break;
1687 case 36:
1688 temp |= TRANS_DDI_BPC_12;
1689 break;
1690 default:
1691 BUG();
1692 }
1693
1694 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1695 temp |= TRANS_DDI_PVSYNC;
1696 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1697 temp |= TRANS_DDI_PHSYNC;
1698
1699 if (cpu_transcoder == TRANSCODER_EDP) {
1700 switch (pipe) {
1701 case PIPE_A:
1702 /* On Haswell, can only use the always-on power well for
1703 * eDP when not using the panel fitter, and when not
1704 * using motion blur mitigation (which we don't
1705 * support). */
1706 if (crtc_state->pch_pfit.force_thru)
1707 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1708 else
1709 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1710 break;
1711 case PIPE_B:
1712 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1713 break;
1714 case PIPE_C:
1715 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1716 break;
1717 default:
1718 BUG();
1719 break;
1720 }
1721 }
1722
1723 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1724 if (crtc_state->has_hdmi_sink)
1725 temp |= TRANS_DDI_MODE_SELECT_HDMI;
1726 else
1727 temp |= TRANS_DDI_MODE_SELECT_DVI;
1728
1729 if (crtc_state->hdmi_scrambling)
1730 temp |= TRANS_DDI_HDMI_SCRAMBLING;
1731 if (crtc_state->hdmi_high_tmds_clock_ratio)
1732 temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1733 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1734 temp |= TRANS_DDI_MODE_SELECT_FDI;
1735 temp |= (crtc_state->fdi_lanes - 1) << 1;
1736 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1737 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1738 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1739
1740 if (INTEL_GEN(dev_priv) >= 12) {
1741 enum transcoder master;
1742
1743 master = crtc_state->mst_master_transcoder;
1744 drm_WARN_ON(&dev_priv->drm,
1745 master == INVALID_TRANSCODER);
1746 temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1747 }
1748 } else {
1749 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1750 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1751 }
1752
1753 if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1754 crtc_state->master_transcoder != INVALID_TRANSCODER) {
1755 u8 master_select =
1756 bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1757
1758 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1759 TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1760 }
1761
1762 return temp;
1763 }
1764
intel_ddi_enable_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1765 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1766 const struct intel_crtc_state *crtc_state)
1767 {
1768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1770 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1771
1772 if (INTEL_GEN(dev_priv) >= 11) {
1773 enum transcoder master_transcoder = crtc_state->master_transcoder;
1774 u32 ctl2 = 0;
1775
1776 if (master_transcoder != INVALID_TRANSCODER) {
1777 u8 master_select =
1778 bdw_trans_port_sync_master_select(master_transcoder);
1779
1780 ctl2 |= PORT_SYNC_MODE_ENABLE |
1781 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1782 }
1783
1784 intel_de_write(dev_priv,
1785 TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1786 }
1787
1788 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
1789 intel_ddi_transcoder_func_reg_val_get(encoder,
1790 crtc_state));
1791 }
1792
1793 /*
1794 * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1795 * bit.
1796 */
1797 static void
intel_ddi_config_transcoder_func(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)1798 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
1799 const struct intel_crtc_state *crtc_state)
1800 {
1801 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1803 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1804 u32 ctl;
1805
1806 ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1807 ctl &= ~TRANS_DDI_FUNC_ENABLE;
1808 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1809 }
1810
intel_ddi_disable_transcoder_func(const struct intel_crtc_state * crtc_state)1811 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1812 {
1813 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1814 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1815 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1816 u32 ctl;
1817
1818 if (INTEL_GEN(dev_priv) >= 11)
1819 intel_de_write(dev_priv,
1820 TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
1821
1822 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1823
1824 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
1825
1826 ctl &= ~TRANS_DDI_FUNC_ENABLE;
1827
1828 if (IS_GEN_RANGE(dev_priv, 8, 10))
1829 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
1830 TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
1831
1832 if (INTEL_GEN(dev_priv) >= 12) {
1833 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1834 ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
1835 TRANS_DDI_MODE_SELECT_MASK);
1836 }
1837 } else {
1838 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1839 }
1840
1841 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1842
1843 if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1844 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1845 drm_dbg_kms(&dev_priv->drm,
1846 "Quirk Increase DDI disabled time\n");
1847 /* Quirk time at 100ms for reliable operation */
1848 msleep(100);
1849 }
1850 }
1851
intel_ddi_toggle_hdcp_signalling(struct intel_encoder * intel_encoder,enum transcoder cpu_transcoder,bool enable)1852 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1853 enum transcoder cpu_transcoder,
1854 bool enable)
1855 {
1856 struct drm_device *dev = intel_encoder->base.dev;
1857 struct drm_i915_private *dev_priv = to_i915(dev);
1858 intel_wakeref_t wakeref;
1859 int ret = 0;
1860 u32 tmp;
1861
1862 wakeref = intel_display_power_get_if_enabled(dev_priv,
1863 intel_encoder->power_domain);
1864 if (drm_WARN_ON(dev, !wakeref))
1865 return -ENXIO;
1866
1867 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1868 if (enable)
1869 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1870 else
1871 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1872 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
1873 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1874 return ret;
1875 }
1876
intel_ddi_connector_get_hw_state(struct intel_connector * intel_connector)1877 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1878 {
1879 struct drm_device *dev = intel_connector->base.dev;
1880 struct drm_i915_private *dev_priv = to_i915(dev);
1881 struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1882 int type = intel_connector->base.connector_type;
1883 enum port port = encoder->port;
1884 enum transcoder cpu_transcoder;
1885 intel_wakeref_t wakeref;
1886 enum pipe pipe = 0;
1887 u32 tmp;
1888 bool ret;
1889
1890 wakeref = intel_display_power_get_if_enabled(dev_priv,
1891 encoder->power_domain);
1892 if (!wakeref)
1893 return false;
1894
1895 if (!encoder->get_hw_state(encoder, &pipe)) {
1896 ret = false;
1897 goto out;
1898 }
1899
1900 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
1901 cpu_transcoder = TRANSCODER_EDP;
1902 else
1903 cpu_transcoder = (enum transcoder) pipe;
1904
1905 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1906
1907 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1908 case TRANS_DDI_MODE_SELECT_HDMI:
1909 case TRANS_DDI_MODE_SELECT_DVI:
1910 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1911 break;
1912
1913 case TRANS_DDI_MODE_SELECT_DP_SST:
1914 ret = type == DRM_MODE_CONNECTOR_eDP ||
1915 type == DRM_MODE_CONNECTOR_DisplayPort;
1916 break;
1917
1918 case TRANS_DDI_MODE_SELECT_DP_MST:
1919 /* if the transcoder is in MST state then
1920 * connector isn't connected */
1921 ret = false;
1922 break;
1923
1924 case TRANS_DDI_MODE_SELECT_FDI:
1925 ret = type == DRM_MODE_CONNECTOR_VGA;
1926 break;
1927
1928 default:
1929 ret = false;
1930 break;
1931 }
1932
1933 out:
1934 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1935
1936 return ret;
1937 }
1938
intel_ddi_get_encoder_pipes(struct intel_encoder * encoder,u8 * pipe_mask,bool * is_dp_mst)1939 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1940 u8 *pipe_mask, bool *is_dp_mst)
1941 {
1942 struct drm_device *dev = encoder->base.dev;
1943 struct drm_i915_private *dev_priv = to_i915(dev);
1944 enum port port = encoder->port;
1945 intel_wakeref_t wakeref;
1946 enum pipe p;
1947 u32 tmp;
1948 u8 mst_pipe_mask;
1949
1950 *pipe_mask = 0;
1951 *is_dp_mst = false;
1952
1953 wakeref = intel_display_power_get_if_enabled(dev_priv,
1954 encoder->power_domain);
1955 if (!wakeref)
1956 return;
1957
1958 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1959 if (!(tmp & DDI_BUF_CTL_ENABLE))
1960 goto out;
1961
1962 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
1963 tmp = intel_de_read(dev_priv,
1964 TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1965
1966 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1967 default:
1968 MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1969 fallthrough;
1970 case TRANS_DDI_EDP_INPUT_A_ON:
1971 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1972 *pipe_mask = BIT(PIPE_A);
1973 break;
1974 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1975 *pipe_mask = BIT(PIPE_B);
1976 break;
1977 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1978 *pipe_mask = BIT(PIPE_C);
1979 break;
1980 }
1981
1982 goto out;
1983 }
1984
1985 mst_pipe_mask = 0;
1986 for_each_pipe(dev_priv, p) {
1987 enum transcoder cpu_transcoder = (enum transcoder)p;
1988 unsigned int port_mask, ddi_select;
1989 intel_wakeref_t trans_wakeref;
1990
1991 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1992 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1993 if (!trans_wakeref)
1994 continue;
1995
1996 if (INTEL_GEN(dev_priv) >= 12) {
1997 port_mask = TGL_TRANS_DDI_PORT_MASK;
1998 ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
1999 } else {
2000 port_mask = TRANS_DDI_PORT_MASK;
2001 ddi_select = TRANS_DDI_SELECT_PORT(port);
2002 }
2003
2004 tmp = intel_de_read(dev_priv,
2005 TRANS_DDI_FUNC_CTL(cpu_transcoder));
2006 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2007 trans_wakeref);
2008
2009 if ((tmp & port_mask) != ddi_select)
2010 continue;
2011
2012 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2013 TRANS_DDI_MODE_SELECT_DP_MST)
2014 mst_pipe_mask |= BIT(p);
2015
2016 *pipe_mask |= BIT(p);
2017 }
2018
2019 if (!*pipe_mask)
2020 drm_dbg_kms(&dev_priv->drm,
2021 "No pipe for [ENCODER:%d:%s] found\n",
2022 encoder->base.base.id, encoder->base.name);
2023
2024 if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2025 drm_dbg_kms(&dev_priv->drm,
2026 "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2027 encoder->base.base.id, encoder->base.name,
2028 *pipe_mask);
2029 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2030 }
2031
2032 if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2033 drm_dbg_kms(&dev_priv->drm,
2034 "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2035 encoder->base.base.id, encoder->base.name,
2036 *pipe_mask, mst_pipe_mask);
2037 else
2038 *is_dp_mst = mst_pipe_mask;
2039
2040 out:
2041 if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2042 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
2043 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2044 BXT_PHY_LANE_POWERDOWN_ACK |
2045 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2046 drm_err(&dev_priv->drm,
2047 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
2048 encoder->base.base.id, encoder->base.name, tmp);
2049 }
2050
2051 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2052 }
2053
intel_ddi_get_hw_state(struct intel_encoder * encoder,enum pipe * pipe)2054 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2055 enum pipe *pipe)
2056 {
2057 u8 pipe_mask;
2058 bool is_mst;
2059
2060 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2061
2062 if (is_mst || !pipe_mask)
2063 return false;
2064
2065 *pipe = ffs(pipe_mask) - 1;
2066
2067 return true;
2068 }
2069
2070 static enum intel_display_power_domain
intel_ddi_main_link_aux_domain(struct intel_digital_port * dig_port)2071 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2072 {
2073 /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2074 * DC states enabled at the same time, while for driver initiated AUX
2075 * transfers we need the same AUX IOs to be powered but with DC states
2076 * disabled. Accordingly use the AUX power domain here which leaves DC
2077 * states enabled.
2078 * However, for non-A AUX ports the corresponding non-EDP transcoders
2079 * would have already enabled power well 2 and DC_OFF. This means we can
2080 * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2081 * specific AUX_IO reference without powering up any extra wells.
2082 * Note that PSR is enabled only on Port A even though this function
2083 * returns the correct domain for other ports too.
2084 */
2085 return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2086 intel_aux_power_domain(dig_port);
2087 }
2088
intel_ddi_get_power_domains(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state)2089 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2090 struct intel_crtc_state *crtc_state)
2091 {
2092 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2093 struct intel_digital_port *dig_port;
2094 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2095
2096 /*
2097 * TODO: Add support for MST encoders. Atm, the following should never
2098 * happen since fake-MST encoders don't set their get_power_domains()
2099 * hook.
2100 */
2101 if (drm_WARN_ON(&dev_priv->drm,
2102 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2103 return;
2104
2105 dig_port = enc_to_dig_port(encoder);
2106
2107 if (!intel_phy_is_tc(dev_priv, phy) ||
2108 dig_port->tc_mode != TC_PORT_TBT_ALT)
2109 intel_display_power_get(dev_priv,
2110 dig_port->ddi_io_power_domain);
2111
2112 /*
2113 * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2114 * ports.
2115 */
2116 if (intel_crtc_has_dp_encoder(crtc_state) ||
2117 intel_phy_is_tc(dev_priv, phy))
2118 intel_display_power_get(dev_priv,
2119 intel_ddi_main_link_aux_domain(dig_port));
2120
2121 /*
2122 * VDSC power is needed when DSC is enabled
2123 */
2124 if (crtc_state->dsc.compression_enable)
2125 intel_display_power_get(dev_priv,
2126 intel_dsc_power_domain(crtc_state));
2127 }
2128
intel_ddi_enable_pipe_clock(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2129 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
2130 const struct intel_crtc_state *crtc_state)
2131 {
2132 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2133 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2134 enum port port = encoder->port;
2135 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2136
2137 if (cpu_transcoder != TRANSCODER_EDP) {
2138 if (INTEL_GEN(dev_priv) >= 12)
2139 intel_de_write(dev_priv,
2140 TRANS_CLK_SEL(cpu_transcoder),
2141 TGL_TRANS_CLK_SEL_PORT(port));
2142 else
2143 intel_de_write(dev_priv,
2144 TRANS_CLK_SEL(cpu_transcoder),
2145 TRANS_CLK_SEL_PORT(port));
2146 }
2147 }
2148
intel_ddi_disable_pipe_clock(const struct intel_crtc_state * crtc_state)2149 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2150 {
2151 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2152 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2153
2154 if (cpu_transcoder != TRANSCODER_EDP) {
2155 if (INTEL_GEN(dev_priv) >= 12)
2156 intel_de_write(dev_priv,
2157 TRANS_CLK_SEL(cpu_transcoder),
2158 TGL_TRANS_CLK_SEL_DISABLED);
2159 else
2160 intel_de_write(dev_priv,
2161 TRANS_CLK_SEL(cpu_transcoder),
2162 TRANS_CLK_SEL_DISABLED);
2163 }
2164 }
2165
_skl_ddi_set_iboost(struct drm_i915_private * dev_priv,enum port port,u8 iboost)2166 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2167 enum port port, u8 iboost)
2168 {
2169 u32 tmp;
2170
2171 tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2172 tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2173 if (iboost)
2174 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2175 else
2176 tmp |= BALANCE_LEG_DISABLE(port);
2177 intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2178 }
2179
skl_ddi_set_iboost(struct intel_encoder * encoder,int level,enum intel_output_type type)2180 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2181 int level, enum intel_output_type type)
2182 {
2183 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2185 u8 iboost;
2186
2187 if (type == INTEL_OUTPUT_HDMI)
2188 iboost = intel_bios_hdmi_boost_level(encoder);
2189 else
2190 iboost = intel_bios_dp_boost_level(encoder);
2191
2192 if (iboost == 0) {
2193 const struct ddi_buf_trans *ddi_translations;
2194 int n_entries;
2195
2196 if (type == INTEL_OUTPUT_HDMI)
2197 ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
2198 else if (type == INTEL_OUTPUT_EDP)
2199 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
2200 &n_entries);
2201 else
2202 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
2203 &n_entries);
2204
2205 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2206 return;
2207 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2208 level = n_entries - 1;
2209
2210 iboost = ddi_translations[level].i_boost;
2211 }
2212
2213 /* Make sure that the requested I_boost is valid */
2214 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2215 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2216 return;
2217 }
2218
2219 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
2220
2221 if (encoder->port == PORT_A && dig_port->max_lanes == 4)
2222 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2223 }
2224
bxt_ddi_vswing_sequence(struct intel_encoder * encoder,int level,enum intel_output_type type)2225 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2226 int level, enum intel_output_type type)
2227 {
2228 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2229 const struct bxt_ddi_buf_trans *ddi_translations;
2230 enum port port = encoder->port;
2231 int n_entries;
2232
2233 if (type == INTEL_OUTPUT_HDMI)
2234 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
2235 else if (type == INTEL_OUTPUT_EDP)
2236 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
2237 else
2238 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
2239
2240 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2241 return;
2242 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2243 level = n_entries - 1;
2244
2245 bxt_ddi_phy_set_signal_level(dev_priv, port,
2246 ddi_translations[level].margin,
2247 ddi_translations[level].scale,
2248 ddi_translations[level].enable,
2249 ddi_translations[level].deemphasis);
2250 }
2251
intel_ddi_dp_voltage_max(struct intel_dp * intel_dp)2252 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
2253 {
2254 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2256 enum port port = encoder->port;
2257 enum phy phy = intel_port_to_phy(dev_priv, port);
2258 int n_entries;
2259
2260 if (INTEL_GEN(dev_priv) >= 12) {
2261 if (intel_phy_is_combo(dev_priv, phy))
2262 tgl_get_combo_buf_trans(encoder, encoder->type,
2263 intel_dp->link_rate, &n_entries);
2264 else
2265 tgl_get_dkl_buf_trans(encoder, encoder->type,
2266 intel_dp->link_rate, &n_entries);
2267 } else if (INTEL_GEN(dev_priv) == 11) {
2268 if (IS_ELKHARTLAKE(dev_priv))
2269 ehl_get_combo_buf_trans(encoder, encoder->type,
2270 intel_dp->link_rate, &n_entries);
2271 else if (intel_phy_is_combo(dev_priv, phy))
2272 icl_get_combo_buf_trans(encoder, encoder->type,
2273 intel_dp->link_rate, &n_entries);
2274 else
2275 icl_get_mg_buf_trans(encoder, encoder->type,
2276 intel_dp->link_rate, &n_entries);
2277 } else if (IS_CANNONLAKE(dev_priv)) {
2278 if (encoder->type == INTEL_OUTPUT_EDP)
2279 cnl_get_buf_trans_edp(encoder, &n_entries);
2280 else
2281 cnl_get_buf_trans_dp(encoder, &n_entries);
2282 } else if (IS_GEN9_LP(dev_priv)) {
2283 if (encoder->type == INTEL_OUTPUT_EDP)
2284 bxt_get_buf_trans_edp(encoder, &n_entries);
2285 else
2286 bxt_get_buf_trans_dp(encoder, &n_entries);
2287 } else {
2288 if (encoder->type == INTEL_OUTPUT_EDP)
2289 intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2290 else
2291 intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2292 }
2293
2294 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2295 n_entries = 1;
2296 if (drm_WARN_ON(&dev_priv->drm,
2297 n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2298 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2299
2300 return index_to_dp_signal_levels[n_entries - 1] &
2301 DP_TRAIN_VOLTAGE_SWING_MASK;
2302 }
2303
2304 /*
2305 * We assume that the full set of pre-emphasis values can be
2306 * used on all DDI platforms. Should that change we need to
2307 * rethink this code.
2308 */
intel_ddi_dp_preemph_max(struct intel_dp * intel_dp)2309 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
2310 {
2311 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2312 }
2313
cnl_ddi_vswing_program(struct intel_encoder * encoder,int level,enum intel_output_type type)2314 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2315 int level, enum intel_output_type type)
2316 {
2317 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2318 const struct cnl_ddi_buf_trans *ddi_translations;
2319 enum port port = encoder->port;
2320 int n_entries, ln;
2321 u32 val;
2322
2323 if (type == INTEL_OUTPUT_HDMI)
2324 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
2325 else if (type == INTEL_OUTPUT_EDP)
2326 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
2327 else
2328 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
2329
2330 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2331 return;
2332 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2333 level = n_entries - 1;
2334
2335 /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2336 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2337 val &= ~SCALING_MODE_SEL_MASK;
2338 val |= SCALING_MODE_SEL(2);
2339 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2340
2341 /* Program PORT_TX_DW2 */
2342 val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2343 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2344 RCOMP_SCALAR_MASK);
2345 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2346 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2347 /* Rcomp scalar is fixed as 0x98 for every table entry */
2348 val |= RCOMP_SCALAR(0x98);
2349 intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2350
2351 /* Program PORT_TX_DW4 */
2352 /* We cannot write to GRP. It would overrite individual loadgen */
2353 for (ln = 0; ln < 4; ln++) {
2354 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2355 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2356 CURSOR_COEFF_MASK);
2357 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2358 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2359 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2360 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2361 }
2362
2363 /* Program PORT_TX_DW5 */
2364 /* All DW5 values are fixed for every table entry */
2365 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2366 val &= ~RTERM_SELECT_MASK;
2367 val |= RTERM_SELECT(6);
2368 val |= TAP3_DISABLE;
2369 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2370
2371 /* Program PORT_TX_DW7 */
2372 val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2373 val &= ~N_SCALAR_MASK;
2374 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2375 intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2376 }
2377
cnl_ddi_vswing_sequence(struct intel_encoder * encoder,int level,enum intel_output_type type)2378 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2379 int level, enum intel_output_type type)
2380 {
2381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2382 enum port port = encoder->port;
2383 int width, rate, ln;
2384 u32 val;
2385
2386 if (type == INTEL_OUTPUT_HDMI) {
2387 width = 4;
2388 rate = 0; /* Rate is always < than 6GHz for HDMI */
2389 } else {
2390 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2391
2392 width = intel_dp->lane_count;
2393 rate = intel_dp->link_rate;
2394 }
2395
2396 /*
2397 * 1. If port type is eDP or DP,
2398 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2399 * else clear to 0b.
2400 */
2401 val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2402 if (type != INTEL_OUTPUT_HDMI)
2403 val |= COMMON_KEEPER_EN;
2404 else
2405 val &= ~COMMON_KEEPER_EN;
2406 intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2407
2408 /* 2. Program loadgen select */
2409 /*
2410 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2411 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2412 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2413 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2414 */
2415 for (ln = 0; ln <= 3; ln++) {
2416 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2417 val &= ~LOADGEN_SELECT;
2418
2419 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2420 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2421 val |= LOADGEN_SELECT;
2422 }
2423 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2424 }
2425
2426 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2427 val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2428 val |= SUS_CLOCK_CONFIG;
2429 intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2430
2431 /* 4. Clear training enable to change swing values */
2432 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2433 val &= ~TX_TRAINING_EN;
2434 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2435
2436 /* 5. Program swing and de-emphasis */
2437 cnl_ddi_vswing_program(encoder, level, type);
2438
2439 /* 6. Set training enable to trigger update */
2440 val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2441 val |= TX_TRAINING_EN;
2442 intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2443 }
2444
icl_ddi_combo_vswing_program(struct intel_encoder * encoder,u32 level,int type,int rate)2445 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
2446 u32 level, int type, int rate)
2447 {
2448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2449 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2450 const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2451 u32 n_entries, val;
2452 int ln;
2453
2454 if (INTEL_GEN(dev_priv) >= 12)
2455 ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
2456 &n_entries);
2457 else if (IS_ELKHARTLAKE(dev_priv))
2458 ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
2459 &n_entries);
2460 else
2461 ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
2462 &n_entries);
2463 if (!ddi_translations)
2464 return;
2465
2466 if (level >= n_entries) {
2467 drm_dbg_kms(&dev_priv->drm,
2468 "DDI translation not found for level %d. Using %d instead.",
2469 level, n_entries - 1);
2470 level = n_entries - 1;
2471 }
2472
2473 if (type == INTEL_OUTPUT_EDP) {
2474 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2475
2476 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
2477 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
2478 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
2479 intel_dp->hobl_active ? val : 0);
2480 }
2481
2482 /* Set PORT_TX_DW5 */
2483 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2484 val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2485 TAP2_DISABLE | TAP3_DISABLE);
2486 val |= SCALING_MODE_SEL(0x2);
2487 val |= RTERM_SELECT(0x6);
2488 val |= TAP3_DISABLE;
2489 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2490
2491 /* Program PORT_TX_DW2 */
2492 val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2493 val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2494 RCOMP_SCALAR_MASK);
2495 val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2496 val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2497 /* Program Rcomp scalar for every table entry */
2498 val |= RCOMP_SCALAR(0x98);
2499 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2500
2501 /* Program PORT_TX_DW4 */
2502 /* We cannot write to GRP. It would overwrite individual loadgen. */
2503 for (ln = 0; ln <= 3; ln++) {
2504 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2505 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2506 CURSOR_COEFF_MASK);
2507 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2508 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2509 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2510 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2511 }
2512
2513 /* Program PORT_TX_DW7 */
2514 val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2515 val &= ~N_SCALAR_MASK;
2516 val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2517 intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2518 }
2519
icl_combo_phy_ddi_vswing_sequence(struct intel_encoder * encoder,u32 level,enum intel_output_type type)2520 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2521 u32 level,
2522 enum intel_output_type type)
2523 {
2524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2525 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2526 int width = 0;
2527 int rate = 0;
2528 u32 val;
2529 int ln = 0;
2530
2531 if (type == INTEL_OUTPUT_HDMI) {
2532 width = 4;
2533 /* Rate is always < than 6GHz for HDMI */
2534 } else {
2535 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2536
2537 width = intel_dp->lane_count;
2538 rate = intel_dp->link_rate;
2539 }
2540
2541 /*
2542 * 1. If port type is eDP or DP,
2543 * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2544 * else clear to 0b.
2545 */
2546 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2547 if (type == INTEL_OUTPUT_HDMI)
2548 val &= ~COMMON_KEEPER_EN;
2549 else
2550 val |= COMMON_KEEPER_EN;
2551 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2552
2553 /* 2. Program loadgen select */
2554 /*
2555 * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2556 * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2557 * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2558 * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2559 */
2560 for (ln = 0; ln <= 3; ln++) {
2561 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2562 val &= ~LOADGEN_SELECT;
2563
2564 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2565 (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2566 val |= LOADGEN_SELECT;
2567 }
2568 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2569 }
2570
2571 /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2572 val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2573 val |= SUS_CLOCK_CONFIG;
2574 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2575
2576 /* 4. Clear training enable to change swing values */
2577 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2578 val &= ~TX_TRAINING_EN;
2579 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2580
2581 /* 5. Program swing and de-emphasis */
2582 icl_ddi_combo_vswing_program(encoder, level, type, rate);
2583
2584 /* 6. Set training enable to trigger update */
2585 val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2586 val |= TX_TRAINING_EN;
2587 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2588 }
2589
icl_mg_phy_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level,enum intel_output_type type)2590 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2591 int link_clock, u32 level,
2592 enum intel_output_type type)
2593 {
2594 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2595 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2596 const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2597 u32 n_entries, val;
2598 int ln, rate = 0;
2599
2600 if (type != INTEL_OUTPUT_HDMI) {
2601 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2602
2603 rate = intel_dp->link_rate;
2604 }
2605
2606 ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
2607 &n_entries);
2608 /* The table does not have values for level 3 and level 9. */
2609 if (level >= n_entries || level == 3 || level == 9) {
2610 drm_dbg_kms(&dev_priv->drm,
2611 "DDI translation not found for level %d. Using %d instead.",
2612 level, n_entries - 2);
2613 level = n_entries - 2;
2614 }
2615
2616 /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2617 for (ln = 0; ln < 2; ln++) {
2618 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2619 val &= ~CRI_USE_FS32;
2620 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2621
2622 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2623 val &= ~CRI_USE_FS32;
2624 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2625 }
2626
2627 /* Program MG_TX_SWINGCTRL with values from vswing table */
2628 for (ln = 0; ln < 2; ln++) {
2629 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2630 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2631 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2632 ddi_translations[level].cri_txdeemph_override_17_12);
2633 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2634
2635 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2636 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2637 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2638 ddi_translations[level].cri_txdeemph_override_17_12);
2639 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2640 }
2641
2642 /* Program MG_TX_DRVCTRL with values from vswing table */
2643 for (ln = 0; ln < 2; ln++) {
2644 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2645 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2646 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2647 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2648 ddi_translations[level].cri_txdeemph_override_5_0) |
2649 CRI_TXDEEMPH_OVERRIDE_11_6(
2650 ddi_translations[level].cri_txdeemph_override_11_6) |
2651 CRI_TXDEEMPH_OVERRIDE_EN;
2652 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2653
2654 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2655 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2656 CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2657 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2658 ddi_translations[level].cri_txdeemph_override_5_0) |
2659 CRI_TXDEEMPH_OVERRIDE_11_6(
2660 ddi_translations[level].cri_txdeemph_override_11_6) |
2661 CRI_TXDEEMPH_OVERRIDE_EN;
2662 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2663
2664 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2665 }
2666
2667 /*
2668 * Program MG_CLKHUB<LN, port being used> with value from frequency table
2669 * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2670 * values from table for which TX1 and TX2 enabled.
2671 */
2672 for (ln = 0; ln < 2; ln++) {
2673 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2674 if (link_clock < 300000)
2675 val |= CFG_LOW_RATE_LKREN_EN;
2676 else
2677 val &= ~CFG_LOW_RATE_LKREN_EN;
2678 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2679 }
2680
2681 /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2682 for (ln = 0; ln < 2; ln++) {
2683 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2684 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2685 if (link_clock <= 500000) {
2686 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2687 } else {
2688 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2689 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2690 }
2691 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2692
2693 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2694 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2695 if (link_clock <= 500000) {
2696 val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2697 } else {
2698 val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2699 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2700 }
2701 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2702 }
2703
2704 /* Program MG_TX_PISO_READLOAD with values from vswing table */
2705 for (ln = 0; ln < 2; ln++) {
2706 val = intel_de_read(dev_priv,
2707 MG_TX1_PISO_READLOAD(ln, tc_port));
2708 val |= CRI_CALCINIT;
2709 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2710 val);
2711
2712 val = intel_de_read(dev_priv,
2713 MG_TX2_PISO_READLOAD(ln, tc_port));
2714 val |= CRI_CALCINIT;
2715 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2716 val);
2717 }
2718 }
2719
icl_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level,enum intel_output_type type)2720 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2721 int link_clock,
2722 u32 level,
2723 enum intel_output_type type)
2724 {
2725 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2726 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2727
2728 if (intel_phy_is_combo(dev_priv, phy))
2729 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2730 else
2731 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
2732 type);
2733 }
2734
2735 static void
tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level,enum intel_output_type type)2736 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2737 u32 level, enum intel_output_type type)
2738 {
2739 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2740 enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2741 const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2742 u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2743 int rate = 0;
2744
2745 if (type != INTEL_OUTPUT_HDMI) {
2746 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2747
2748 rate = intel_dp->link_rate;
2749 }
2750
2751 ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
2752 &n_entries);
2753
2754 if (level >= n_entries)
2755 level = n_entries - 1;
2756
2757 dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2758 DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2759 DKL_TX_VSWING_CONTROL_MASK);
2760 dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2761 dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2762 dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2763
2764 for (ln = 0; ln < 2; ln++) {
2765 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2766 HIP_INDEX_VAL(tc_port, ln));
2767
2768 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2769
2770 /* All the registers are RMW */
2771 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2772 val &= ~dpcnt_mask;
2773 val |= dpcnt_val;
2774 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2775
2776 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2777 val &= ~dpcnt_mask;
2778 val |= dpcnt_val;
2779 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2780
2781 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2782 val &= ~DKL_TX_DP20BITMODE;
2783 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2784 }
2785 }
2786
tgl_ddi_vswing_sequence(struct intel_encoder * encoder,int link_clock,u32 level,enum intel_output_type type)2787 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2788 int link_clock,
2789 u32 level,
2790 enum intel_output_type type)
2791 {
2792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2793 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2794
2795 if (intel_phy_is_combo(dev_priv, phy))
2796 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2797 else
2798 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
2799 }
2800
translate_signal_level(struct intel_dp * intel_dp,int signal_levels)2801 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
2802 {
2803 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2804 int i;
2805
2806 for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2807 if (index_to_dp_signal_levels[i] == signal_levels)
2808 return i;
2809 }
2810
2811 drm_WARN(&i915->drm, 1,
2812 "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2813 signal_levels);
2814
2815 return 0;
2816 }
2817
intel_ddi_dp_level(struct intel_dp * intel_dp)2818 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2819 {
2820 u8 train_set = intel_dp->train_set[0];
2821 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2822 DP_TRAIN_PRE_EMPHASIS_MASK);
2823
2824 return translate_signal_level(intel_dp, signal_levels);
2825 }
2826
2827 static void
tgl_set_signal_levels(struct intel_dp * intel_dp)2828 tgl_set_signal_levels(struct intel_dp *intel_dp)
2829 {
2830 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2831 int level = intel_ddi_dp_level(intel_dp);
2832
2833 tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2834 level, encoder->type);
2835 }
2836
2837 static void
icl_set_signal_levels(struct intel_dp * intel_dp)2838 icl_set_signal_levels(struct intel_dp *intel_dp)
2839 {
2840 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2841 int level = intel_ddi_dp_level(intel_dp);
2842
2843 icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2844 level, encoder->type);
2845 }
2846
2847 static void
cnl_set_signal_levels(struct intel_dp * intel_dp)2848 cnl_set_signal_levels(struct intel_dp *intel_dp)
2849 {
2850 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2851 int level = intel_ddi_dp_level(intel_dp);
2852
2853 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2854 }
2855
2856 static void
bxt_set_signal_levels(struct intel_dp * intel_dp)2857 bxt_set_signal_levels(struct intel_dp *intel_dp)
2858 {
2859 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2860 int level = intel_ddi_dp_level(intel_dp);
2861
2862 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2863 }
2864
2865 static void
hsw_set_signal_levels(struct intel_dp * intel_dp)2866 hsw_set_signal_levels(struct intel_dp *intel_dp)
2867 {
2868 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2870 int level = intel_ddi_dp_level(intel_dp);
2871 enum port port = encoder->port;
2872 u32 signal_levels;
2873
2874 signal_levels = DDI_BUF_TRANS_SELECT(level);
2875
2876 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
2877 signal_levels);
2878
2879 intel_dp->DP &= ~DDI_BUF_EMP_MASK;
2880 intel_dp->DP |= signal_levels;
2881
2882 if (IS_GEN9_BC(dev_priv))
2883 skl_ddi_set_iboost(encoder, level, encoder->type);
2884
2885 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
2886 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
2887 }
2888
icl_dpclka_cfgcr0_clk_off(struct drm_i915_private * dev_priv,enum phy phy)2889 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2890 enum phy phy)
2891 {
2892 if (IS_ROCKETLAKE(dev_priv)) {
2893 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2894 } else if (intel_phy_is_combo(dev_priv, phy)) {
2895 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2896 } else if (intel_phy_is_tc(dev_priv, phy)) {
2897 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2898 (enum port)phy);
2899
2900 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2901 }
2902
2903 return 0;
2904 }
2905
icl_map_plls_to_ports(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)2906 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2907 const struct intel_crtc_state *crtc_state)
2908 {
2909 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2910 struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2911 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2912 u32 val;
2913
2914 mutex_lock(&dev_priv->dpll.lock);
2915
2916 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2917 drm_WARN_ON(&dev_priv->drm,
2918 (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2919
2920 if (intel_phy_is_combo(dev_priv, phy)) {
2921 u32 mask, sel;
2922
2923 if (IS_ROCKETLAKE(dev_priv)) {
2924 mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2925 sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2926 } else {
2927 mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2928 sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2929 }
2930
2931 /*
2932 * Even though this register references DDIs, note that we
2933 * want to pass the PHY rather than the port (DDI). For
2934 * ICL, port=phy in all cases so it doesn't matter, but for
2935 * EHL the bspec notes the following:
2936 *
2937 * "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2938 * Clock Select chooses the PLL for both DDIA and DDID and
2939 * drives port A in all cases."
2940 */
2941 val &= ~mask;
2942 val |= sel;
2943 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2944 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2945 }
2946
2947 val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2948 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2949
2950 mutex_unlock(&dev_priv->dpll.lock);
2951 }
2952
icl_unmap_plls_to_ports(struct intel_encoder * encoder)2953 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2954 {
2955 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2956 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2957 u32 val;
2958
2959 mutex_lock(&dev_priv->dpll.lock);
2960
2961 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2962 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2963 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2964
2965 mutex_unlock(&dev_priv->dpll.lock);
2966 }
2967
icl_sanitize_port_clk_off(struct drm_i915_private * dev_priv,u32 port_mask,bool ddi_clk_needed)2968 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2969 u32 port_mask, bool ddi_clk_needed)
2970 {
2971 enum port port;
2972 u32 val;
2973
2974 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2975 for_each_port_masked(port, port_mask) {
2976 enum phy phy = intel_port_to_phy(dev_priv, port);
2977 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2978 phy);
2979
2980 if (ddi_clk_needed == !ddi_clk_off)
2981 continue;
2982
2983 /*
2984 * Punt on the case now where clock is gated, but it would
2985 * be needed by the port. Something else is really broken then.
2986 */
2987 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2988 continue;
2989
2990 drm_notice(&dev_priv->drm,
2991 "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2992 phy_name(phy));
2993 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2994 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2995 }
2996 }
2997
icl_sanitize_encoder_pll_mapping(struct intel_encoder * encoder)2998 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2999 {
3000 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3001 u32 port_mask;
3002 bool ddi_clk_needed;
3003
3004 /*
3005 * In case of DP MST, we sanitize the primary encoder only, not the
3006 * virtual ones.
3007 */
3008 if (encoder->type == INTEL_OUTPUT_DP_MST)
3009 return;
3010
3011 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3012 u8 pipe_mask;
3013 bool is_mst;
3014
3015 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3016 /*
3017 * In the unlikely case that BIOS enables DP in MST mode, just
3018 * warn since our MST HW readout is incomplete.
3019 */
3020 if (drm_WARN_ON(&dev_priv->drm, is_mst))
3021 return;
3022 }
3023
3024 port_mask = BIT(encoder->port);
3025 ddi_clk_needed = encoder->base.crtc;
3026
3027 if (encoder->type == INTEL_OUTPUT_DSI) {
3028 struct intel_encoder *other_encoder;
3029
3030 port_mask = intel_dsi_encoder_ports(encoder);
3031 /*
3032 * Sanity check that we haven't incorrectly registered another
3033 * encoder using any of the ports of this DSI encoder.
3034 */
3035 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3036 if (other_encoder == encoder)
3037 continue;
3038
3039 if (drm_WARN_ON(&dev_priv->drm,
3040 port_mask & BIT(other_encoder->port)))
3041 return;
3042 }
3043 /*
3044 * For DSI we keep the ddi clocks gated
3045 * except during enable/disable sequence.
3046 */
3047 ddi_clk_needed = false;
3048 }
3049
3050 icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3051 }
3052
intel_ddi_clk_select(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3053 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3054 const struct intel_crtc_state *crtc_state)
3055 {
3056 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3057 enum port port = encoder->port;
3058 enum phy phy = intel_port_to_phy(dev_priv, port);
3059 u32 val;
3060 const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3061
3062 if (drm_WARN_ON(&dev_priv->drm, !pll))
3063 return;
3064
3065 mutex_lock(&dev_priv->dpll.lock);
3066
3067 if (INTEL_GEN(dev_priv) >= 11) {
3068 if (!intel_phy_is_combo(dev_priv, phy))
3069 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3070 icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3071 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3072 /*
3073 * MG does not exist but the programming is required
3074 * to ungate DDIC and DDID
3075 */
3076 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3077 DDI_CLK_SEL_MG);
3078 } else if (IS_CANNONLAKE(dev_priv)) {
3079 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3080 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3081 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3082 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3083 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3084
3085 /*
3086 * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3087 * This step and the step before must be done with separate
3088 * register writes.
3089 */
3090 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3091 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3092 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3093 } else if (IS_GEN9_BC(dev_priv)) {
3094 /* DDI -> PLL mapping */
3095 val = intel_de_read(dev_priv, DPLL_CTRL2);
3096
3097 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3098 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3099 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3100 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3101
3102 intel_de_write(dev_priv, DPLL_CTRL2, val);
3103
3104 } else if (INTEL_GEN(dev_priv) < 9) {
3105 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3106 hsw_pll_to_ddi_pll_sel(pll));
3107 }
3108
3109 mutex_unlock(&dev_priv->dpll.lock);
3110 }
3111
intel_ddi_clk_disable(struct intel_encoder * encoder)3112 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3113 {
3114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3115 enum port port = encoder->port;
3116 enum phy phy = intel_port_to_phy(dev_priv, port);
3117
3118 if (INTEL_GEN(dev_priv) >= 11) {
3119 if (!intel_phy_is_combo(dev_priv, phy) ||
3120 (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3121 intel_de_write(dev_priv, DDI_CLK_SEL(port),
3122 DDI_CLK_SEL_NONE);
3123 } else if (IS_CANNONLAKE(dev_priv)) {
3124 intel_de_write(dev_priv, DPCLKA_CFGCR0,
3125 intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3126 } else if (IS_GEN9_BC(dev_priv)) {
3127 intel_de_write(dev_priv, DPLL_CTRL2,
3128 intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
3129 } else if (INTEL_GEN(dev_priv) < 9) {
3130 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3131 PORT_CLK_SEL_NONE);
3132 }
3133 }
3134
3135 static void
icl_program_mg_dp_mode(struct intel_digital_port * dig_port,const struct intel_crtc_state * crtc_state)3136 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
3137 const struct intel_crtc_state *crtc_state)
3138 {
3139 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3140 enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3141 u32 ln0, ln1, pin_assignment;
3142 u8 width;
3143
3144 if (dig_port->tc_mode == TC_PORT_TBT_ALT)
3145 return;
3146
3147 if (INTEL_GEN(dev_priv) >= 12) {
3148 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3149 HIP_INDEX_VAL(tc_port, 0x0));
3150 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3151 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3152 HIP_INDEX_VAL(tc_port, 0x1));
3153 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3154 } else {
3155 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
3156 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
3157 }
3158
3159 ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3160 ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3161
3162 /* DPPATC */
3163 pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
3164 width = crtc_state->lane_count;
3165
3166 switch (pin_assignment) {
3167 case 0x0:
3168 drm_WARN_ON(&dev_priv->drm,
3169 dig_port->tc_mode != TC_PORT_LEGACY);
3170 if (width == 1) {
3171 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3172 } else {
3173 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3174 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3175 }
3176 break;
3177 case 0x1:
3178 if (width == 4) {
3179 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3180 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3181 }
3182 break;
3183 case 0x2:
3184 if (width == 2) {
3185 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3186 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3187 }
3188 break;
3189 case 0x3:
3190 case 0x5:
3191 if (width == 1) {
3192 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3193 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3194 } else {
3195 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3196 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3197 }
3198 break;
3199 case 0x4:
3200 case 0x6:
3201 if (width == 1) {
3202 ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3203 ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3204 } else {
3205 ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3206 ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3207 }
3208 break;
3209 default:
3210 MISSING_CASE(pin_assignment);
3211 }
3212
3213 if (INTEL_GEN(dev_priv) >= 12) {
3214 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3215 HIP_INDEX_VAL(tc_port, 0x0));
3216 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3217 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3218 HIP_INDEX_VAL(tc_port, 0x1));
3219 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3220 } else {
3221 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3222 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3223 }
3224 }
3225
intel_dp_sink_set_fec_ready(struct intel_dp * intel_dp,const struct intel_crtc_state * crtc_state)3226 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3227 const struct intel_crtc_state *crtc_state)
3228 {
3229 struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3230
3231 if (!crtc_state->fec_enable)
3232 return;
3233
3234 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3235 drm_dbg_kms(&i915->drm,
3236 "Failed to set FEC_READY in the sink\n");
3237 }
3238
intel_ddi_enable_fec(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3239 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3240 const struct intel_crtc_state *crtc_state)
3241 {
3242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3243 struct intel_dp *intel_dp;
3244 u32 val;
3245
3246 if (!crtc_state->fec_enable)
3247 return;
3248
3249 intel_dp = enc_to_intel_dp(encoder);
3250 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3251 val |= DP_TP_CTL_FEC_ENABLE;
3252 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3253
3254 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3255 DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3256 drm_err(&dev_priv->drm,
3257 "Timed out waiting for FEC Enable Status\n");
3258 }
3259
intel_ddi_disable_fec_state(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3260 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3261 const struct intel_crtc_state *crtc_state)
3262 {
3263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3264 struct intel_dp *intel_dp;
3265 u32 val;
3266
3267 if (!crtc_state->fec_enable)
3268 return;
3269
3270 intel_dp = enc_to_intel_dp(encoder);
3271 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3272 val &= ~DP_TP_CTL_FEC_ENABLE;
3273 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3274 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3275 }
3276
tgl_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3277 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3278 struct intel_encoder *encoder,
3279 const struct intel_crtc_state *crtc_state,
3280 const struct drm_connector_state *conn_state)
3281 {
3282 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3284 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3285 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3286 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3287 int level = intel_ddi_dp_level(intel_dp);
3288 enum transcoder transcoder = crtc_state->cpu_transcoder;
3289
3290 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3291 crtc_state->lane_count, is_mst);
3292
3293 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3294 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3295
3296 /*
3297 * 1. Enable Power Wells
3298 *
3299 * This was handled at the beginning of intel_atomic_commit_tail(),
3300 * before we called down into this function.
3301 */
3302
3303 /* 2. Enable Panel Power if PPS is required */
3304 intel_edp_panel_on(intel_dp);
3305
3306 /*
3307 * 3. For non-TBT Type-C ports, set FIA lane count
3308 * (DFLEXDPSP.DPX4TXLATC)
3309 *
3310 * This was done before tgl_ddi_pre_enable_dp by
3311 * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3312 */
3313
3314 /*
3315 * 4. Enable the port PLL.
3316 *
3317 * The PLL enabling itself was already done before this function by
3318 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
3319 * configure the PLL to port mapping here.
3320 */
3321 intel_ddi_clk_select(encoder, crtc_state);
3322
3323 /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3324 if (!intel_phy_is_tc(dev_priv, phy) ||
3325 dig_port->tc_mode != TC_PORT_TBT_ALT)
3326 intel_display_power_get(dev_priv,
3327 dig_port->ddi_io_power_domain);
3328
3329 /* 6. Program DP_MODE */
3330 icl_program_mg_dp_mode(dig_port, crtc_state);
3331
3332 /*
3333 * 7. The rest of the below are substeps under the bspec's "Enable and
3334 * Train Display Port" step. Note that steps that are specific to
3335 * MST will be handled by intel_mst_pre_enable_dp() before/after it
3336 * calls into this function. Also intel_mst_pre_enable_dp() only calls
3337 * us when active_mst_links==0, so any steps designated for "single
3338 * stream or multi-stream master transcoder" can just be performed
3339 * unconditionally here.
3340 */
3341
3342 /*
3343 * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3344 * Transcoder.
3345 */
3346 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3347
3348 /*
3349 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3350 * Transport Select
3351 */
3352 intel_ddi_config_transcoder_func(encoder, crtc_state);
3353
3354 /*
3355 * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3356 * selected
3357 *
3358 * This will be handled by the intel_dp_start_link_train() farther
3359 * down this function.
3360 */
3361
3362 /* 7.e Configure voltage swing and related IO settings */
3363 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3364 encoder->type);
3365
3366 /*
3367 * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3368 * the used lanes of the DDI.
3369 */
3370 if (intel_phy_is_combo(dev_priv, phy)) {
3371 bool lane_reversal =
3372 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3373
3374 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3375 crtc_state->lane_count,
3376 lane_reversal);
3377 }
3378
3379 /*
3380 * 7.g Configure and enable DDI_BUF_CTL
3381 * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3382 * after 500 us.
3383 *
3384 * We only configure what the register value will be here. Actual
3385 * enabling happens during link training farther down.
3386 */
3387 intel_ddi_init_dp_buf_reg(encoder);
3388
3389 if (!is_mst)
3390 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3391
3392 intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3393 /*
3394 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3395 * in the FEC_CONFIGURATION register to 1 before initiating link
3396 * training
3397 */
3398 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3399
3400 /*
3401 * 7.i Follow DisplayPort specification training sequence (see notes for
3402 * failure handling)
3403 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3404 * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3405 * (timeout after 800 us)
3406 */
3407 intel_dp_start_link_train(intel_dp);
3408
3409 /* 7.k Set DP_TP_CTL link training to Normal */
3410 if (!is_trans_port_sync_mode(crtc_state))
3411 intel_dp_stop_link_train(intel_dp);
3412
3413 /* 7.l Configure and enable FEC if needed */
3414 intel_ddi_enable_fec(encoder, crtc_state);
3415 intel_dsc_enable(encoder, crtc_state);
3416 }
3417
hsw_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3418 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3419 struct intel_encoder *encoder,
3420 const struct intel_crtc_state *crtc_state,
3421 const struct drm_connector_state *conn_state)
3422 {
3423 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3424 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3425 enum port port = encoder->port;
3426 enum phy phy = intel_port_to_phy(dev_priv, port);
3427 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3428 bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3429 int level = intel_ddi_dp_level(intel_dp);
3430
3431 if (INTEL_GEN(dev_priv) < 11)
3432 drm_WARN_ON(&dev_priv->drm,
3433 is_mst && (port == PORT_A || port == PORT_E));
3434 else
3435 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3436
3437 intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3438 crtc_state->lane_count, is_mst);
3439
3440 intel_edp_panel_on(intel_dp);
3441
3442 intel_ddi_clk_select(encoder, crtc_state);
3443
3444 if (!intel_phy_is_tc(dev_priv, phy) ||
3445 dig_port->tc_mode != TC_PORT_TBT_ALT)
3446 intel_display_power_get(dev_priv,
3447 dig_port->ddi_io_power_domain);
3448
3449 icl_program_mg_dp_mode(dig_port, crtc_state);
3450
3451 if (INTEL_GEN(dev_priv) >= 11)
3452 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3453 level, encoder->type);
3454 else if (IS_CANNONLAKE(dev_priv))
3455 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3456 else if (IS_GEN9_LP(dev_priv))
3457 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3458 else
3459 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3460
3461 if (intel_phy_is_combo(dev_priv, phy)) {
3462 bool lane_reversal =
3463 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3464
3465 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3466 crtc_state->lane_count,
3467 lane_reversal);
3468 }
3469
3470 intel_ddi_init_dp_buf_reg(encoder);
3471 if (!is_mst)
3472 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3473 intel_dp_configure_protocol_converter(intel_dp);
3474 intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3475 true);
3476 intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3477 intel_dp_start_link_train(intel_dp);
3478 if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3479 !is_trans_port_sync_mode(crtc_state))
3480 intel_dp_stop_link_train(intel_dp);
3481
3482 intel_ddi_enable_fec(encoder, crtc_state);
3483
3484 if (!is_mst)
3485 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3486
3487 intel_dsc_enable(encoder, crtc_state);
3488 }
3489
intel_ddi_pre_enable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3490 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3491 struct intel_encoder *encoder,
3492 const struct intel_crtc_state *crtc_state,
3493 const struct drm_connector_state *conn_state)
3494 {
3495 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3496
3497 if (INTEL_GEN(dev_priv) >= 12)
3498 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3499 else
3500 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3501
3502 /* MST will call a setting of MSA after an allocating of Virtual Channel
3503 * from MST encoder pre_enable callback.
3504 */
3505 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3506 intel_ddi_set_dp_msa(crtc_state, conn_state);
3507
3508 intel_dp_set_m_n(crtc_state, M1_N1);
3509 }
3510 }
3511
intel_ddi_pre_enable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3512 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3513 struct intel_encoder *encoder,
3514 const struct intel_crtc_state *crtc_state,
3515 const struct drm_connector_state *conn_state)
3516 {
3517 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3518 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3519 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3520 int level = intel_ddi_hdmi_level(encoder);
3521
3522 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3523 intel_ddi_clk_select(encoder, crtc_state);
3524
3525 intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3526
3527 icl_program_mg_dp_mode(dig_port, crtc_state);
3528
3529 if (INTEL_GEN(dev_priv) >= 12)
3530 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3531 level, INTEL_OUTPUT_HDMI);
3532 else if (INTEL_GEN(dev_priv) == 11)
3533 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3534 level, INTEL_OUTPUT_HDMI);
3535 else if (IS_CANNONLAKE(dev_priv))
3536 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3537 else if (IS_GEN9_LP(dev_priv))
3538 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3539 else
3540 intel_prepare_hdmi_ddi_buffers(encoder, level);
3541
3542 if (IS_GEN9_BC(dev_priv))
3543 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3544
3545 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3546
3547 dig_port->set_infoframes(encoder,
3548 crtc_state->has_infoframe,
3549 crtc_state, conn_state);
3550 }
3551
intel_ddi_pre_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3552 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3553 struct intel_encoder *encoder,
3554 const struct intel_crtc_state *crtc_state,
3555 const struct drm_connector_state *conn_state)
3556 {
3557 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3558 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3559 enum pipe pipe = crtc->pipe;
3560
3561 /*
3562 * When called from DP MST code:
3563 * - conn_state will be NULL
3564 * - encoder will be the main encoder (ie. mst->primary)
3565 * - the main connector associated with this port
3566 * won't be active or linked to a crtc
3567 * - crtc_state will be the state of the first stream to
3568 * be activated on this port, and it may not be the same
3569 * stream that will be deactivated last, but each stream
3570 * should have a state that is identical when it comes to
3571 * the DP link parameteres
3572 */
3573
3574 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3575
3576 if (INTEL_GEN(dev_priv) >= 11)
3577 icl_map_plls_to_ports(encoder, crtc_state);
3578
3579 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3580
3581 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3582 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3583 conn_state);
3584 } else {
3585 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3586
3587 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3588 conn_state);
3589
3590 /* FIXME precompute everything properly */
3591 /* FIXME how do we turn infoframes off again? */
3592 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3593 dig_port->set_infoframes(encoder,
3594 crtc_state->has_infoframe,
3595 crtc_state, conn_state);
3596 }
3597 }
3598
intel_disable_ddi_buf(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3599 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3600 const struct intel_crtc_state *crtc_state)
3601 {
3602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3603 enum port port = encoder->port;
3604 bool wait = false;
3605 u32 val;
3606
3607 val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3608 if (val & DDI_BUF_CTL_ENABLE) {
3609 val &= ~DDI_BUF_CTL_ENABLE;
3610 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3611 wait = true;
3612 }
3613
3614 if (intel_crtc_has_dp_encoder(crtc_state)) {
3615 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3616
3617 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3618 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3619 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3620 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3621 }
3622
3623 /* Disable FEC in DP Sink */
3624 intel_ddi_disable_fec_state(encoder, crtc_state);
3625
3626 if (wait)
3627 intel_wait_ddi_buf_idle(dev_priv, port);
3628 }
3629
intel_ddi_post_disable_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3630 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3631 struct intel_encoder *encoder,
3632 const struct intel_crtc_state *old_crtc_state,
3633 const struct drm_connector_state *old_conn_state)
3634 {
3635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3636 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3637 struct intel_dp *intel_dp = &dig_port->dp;
3638 bool is_mst = intel_crtc_has_type(old_crtc_state,
3639 INTEL_OUTPUT_DP_MST);
3640 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3641
3642 if (!is_mst)
3643 intel_dp_set_infoframes(encoder, false,
3644 old_crtc_state, old_conn_state);
3645
3646 /*
3647 * Power down sink before disabling the port, otherwise we end
3648 * up getting interrupts from the sink on detecting link loss.
3649 */
3650 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3651
3652 if (INTEL_GEN(dev_priv) >= 12) {
3653 if (is_mst) {
3654 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3655 u32 val;
3656
3657 val = intel_de_read(dev_priv,
3658 TRANS_DDI_FUNC_CTL(cpu_transcoder));
3659 val &= ~(TGL_TRANS_DDI_PORT_MASK |
3660 TRANS_DDI_MODE_SELECT_MASK);
3661 intel_de_write(dev_priv,
3662 TRANS_DDI_FUNC_CTL(cpu_transcoder),
3663 val);
3664 }
3665 } else {
3666 if (!is_mst)
3667 intel_ddi_disable_pipe_clock(old_crtc_state);
3668 }
3669
3670 intel_disable_ddi_buf(encoder, old_crtc_state);
3671
3672 /*
3673 * From TGL spec: "If single stream or multi-stream master transcoder:
3674 * Configure Transcoder Clock select to direct no clock to the
3675 * transcoder"
3676 */
3677 if (INTEL_GEN(dev_priv) >= 12)
3678 intel_ddi_disable_pipe_clock(old_crtc_state);
3679
3680 intel_edp_panel_vdd_on(intel_dp);
3681 intel_edp_panel_off(intel_dp);
3682
3683 if (!intel_phy_is_tc(dev_priv, phy) ||
3684 dig_port->tc_mode != TC_PORT_TBT_ALT)
3685 intel_display_power_put_unchecked(dev_priv,
3686 dig_port->ddi_io_power_domain);
3687
3688 intel_ddi_clk_disable(encoder);
3689 }
3690
intel_ddi_post_disable_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3691 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3692 struct intel_encoder *encoder,
3693 const struct intel_crtc_state *old_crtc_state,
3694 const struct drm_connector_state *old_conn_state)
3695 {
3696 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3697 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3698 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3699
3700 dig_port->set_infoframes(encoder, false,
3701 old_crtc_state, old_conn_state);
3702
3703 intel_ddi_disable_pipe_clock(old_crtc_state);
3704
3705 intel_disable_ddi_buf(encoder, old_crtc_state);
3706
3707 intel_display_power_put_unchecked(dev_priv,
3708 dig_port->ddi_io_power_domain);
3709
3710 intel_ddi_clk_disable(encoder);
3711
3712 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3713 }
3714
intel_ddi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3715 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3716 struct intel_encoder *encoder,
3717 const struct intel_crtc_state *old_crtc_state,
3718 const struct drm_connector_state *old_conn_state)
3719 {
3720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3721 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3722 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3723 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3724
3725 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3726 intel_crtc_vblank_off(old_crtc_state);
3727
3728 intel_disable_pipe(old_crtc_state);
3729
3730 intel_ddi_disable_transcoder_func(old_crtc_state);
3731
3732 intel_dsc_disable(old_crtc_state);
3733
3734 if (INTEL_GEN(dev_priv) >= 9)
3735 skl_scaler_disable(old_crtc_state);
3736 else
3737 ilk_pfit_disable(old_crtc_state);
3738 }
3739
3740 /*
3741 * When called from DP MST code:
3742 * - old_conn_state will be NULL
3743 * - encoder will be the main encoder (ie. mst->primary)
3744 * - the main connector associated with this port
3745 * won't be active or linked to a crtc
3746 * - old_crtc_state will be the state of the last stream to
3747 * be deactivated on this port, and it may not be the same
3748 * stream that was activated last, but each stream
3749 * should have a state that is identical when it comes to
3750 * the DP link parameteres
3751 */
3752
3753 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3754 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3755 old_conn_state);
3756 else
3757 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3758 old_conn_state);
3759
3760 if (INTEL_GEN(dev_priv) >= 11)
3761 icl_unmap_plls_to_ports(encoder);
3762
3763 if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3764 intel_display_power_put_unchecked(dev_priv,
3765 intel_ddi_main_link_aux_domain(dig_port));
3766
3767 if (is_tc_port)
3768 intel_tc_port_put_link(dig_port);
3769 }
3770
intel_ddi_fdi_post_disable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3771 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3772 struct intel_encoder *encoder,
3773 const struct intel_crtc_state *old_crtc_state,
3774 const struct drm_connector_state *old_conn_state)
3775 {
3776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3777 u32 val;
3778
3779 /*
3780 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3781 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3782 * step 13 is the correct place for it. Step 18 is where it was
3783 * originally before the BUN.
3784 */
3785 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3786 val &= ~FDI_RX_ENABLE;
3787 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3788
3789 intel_disable_ddi_buf(encoder, old_crtc_state);
3790 intel_ddi_clk_disable(encoder);
3791
3792 val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3793 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3794 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3795 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3796
3797 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3798 val &= ~FDI_PCDCLK;
3799 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3800
3801 val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3802 val &= ~FDI_RX_PLL_ENABLE;
3803 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3804 }
3805
trans_port_sync_stop_link_train(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)3806 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3807 struct intel_encoder *encoder,
3808 const struct intel_crtc_state *crtc_state)
3809 {
3810 const struct drm_connector_state *conn_state;
3811 struct drm_connector *conn;
3812 int i;
3813
3814 if (!crtc_state->sync_mode_slaves_mask)
3815 return;
3816
3817 for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3818 struct intel_encoder *slave_encoder =
3819 to_intel_encoder(conn_state->best_encoder);
3820 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3821 const struct intel_crtc_state *slave_crtc_state;
3822
3823 if (!slave_crtc)
3824 continue;
3825
3826 slave_crtc_state =
3827 intel_atomic_get_new_crtc_state(state, slave_crtc);
3828
3829 if (slave_crtc_state->master_transcoder !=
3830 crtc_state->cpu_transcoder)
3831 continue;
3832
3833 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
3834 }
3835
3836 usleep_range(200, 400);
3837
3838 intel_dp_stop_link_train(enc_to_intel_dp(encoder));
3839 }
3840
intel_enable_ddi_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3841 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3842 struct intel_encoder *encoder,
3843 const struct intel_crtc_state *crtc_state,
3844 const struct drm_connector_state *conn_state)
3845 {
3846 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3847 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3848 enum port port = encoder->port;
3849
3850 if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3851 intel_dp_stop_link_train(intel_dp);
3852
3853 intel_edp_backlight_on(crtc_state, conn_state);
3854 intel_psr_enable(intel_dp, crtc_state, conn_state);
3855 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3856 intel_edp_drrs_enable(intel_dp, crtc_state);
3857
3858 if (crtc_state->has_audio)
3859 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3860
3861 trans_port_sync_stop_link_train(state, encoder, crtc_state);
3862 }
3863
3864 static i915_reg_t
gen9_chicken_trans_reg_by_port(struct drm_i915_private * dev_priv,enum port port)3865 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3866 enum port port)
3867 {
3868 static const enum transcoder trans[] = {
3869 [PORT_A] = TRANSCODER_EDP,
3870 [PORT_B] = TRANSCODER_A,
3871 [PORT_C] = TRANSCODER_B,
3872 [PORT_D] = TRANSCODER_C,
3873 [PORT_E] = TRANSCODER_A,
3874 };
3875
3876 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3877
3878 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3879 port = PORT_A;
3880
3881 return CHICKEN_TRANS(trans[port]);
3882 }
3883
intel_enable_ddi_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3884 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3885 struct intel_encoder *encoder,
3886 const struct intel_crtc_state *crtc_state,
3887 const struct drm_connector_state *conn_state)
3888 {
3889 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3890 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3891 struct drm_connector *connector = conn_state->connector;
3892 enum port port = encoder->port;
3893
3894 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3895 crtc_state->hdmi_high_tmds_clock_ratio,
3896 crtc_state->hdmi_scrambling))
3897 drm_dbg_kms(&dev_priv->drm,
3898 "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3899 connector->base.id, connector->name);
3900
3901 /* Display WA #1143: skl,kbl,cfl */
3902 if (IS_GEN9_BC(dev_priv)) {
3903 /*
3904 * For some reason these chicken bits have been
3905 * stuffed into a transcoder register, event though
3906 * the bits affect a specific DDI port rather than
3907 * a specific transcoder.
3908 */
3909 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3910 u32 val;
3911
3912 val = intel_de_read(dev_priv, reg);
3913
3914 if (port == PORT_E)
3915 val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3916 DDIE_TRAINING_OVERRIDE_VALUE;
3917 else
3918 val |= DDI_TRAINING_OVERRIDE_ENABLE |
3919 DDI_TRAINING_OVERRIDE_VALUE;
3920
3921 intel_de_write(dev_priv, reg, val);
3922 intel_de_posting_read(dev_priv, reg);
3923
3924 udelay(1);
3925
3926 if (port == PORT_E)
3927 val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3928 DDIE_TRAINING_OVERRIDE_VALUE);
3929 else
3930 val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3931 DDI_TRAINING_OVERRIDE_VALUE);
3932
3933 intel_de_write(dev_priv, reg, val);
3934 }
3935
3936 /* In HDMI/DVI mode, the port width, and swing/emphasis values
3937 * are ignored so nothing special needs to be done besides
3938 * enabling the port.
3939 */
3940 intel_de_write(dev_priv, DDI_BUF_CTL(port),
3941 dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3942
3943 if (crtc_state->has_audio)
3944 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3945 }
3946
intel_enable_ddi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)3947 static void intel_enable_ddi(struct intel_atomic_state *state,
3948 struct intel_encoder *encoder,
3949 const struct intel_crtc_state *crtc_state,
3950 const struct drm_connector_state *conn_state)
3951 {
3952 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3953
3954 intel_ddi_enable_transcoder_func(encoder, crtc_state);
3955
3956 intel_enable_pipe(crtc_state);
3957
3958 intel_crtc_vblank_on(crtc_state);
3959
3960 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3961 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3962 else
3963 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3964
3965 /* Enable hdcp if it's desired */
3966 if (conn_state->content_protection ==
3967 DRM_MODE_CONTENT_PROTECTION_DESIRED)
3968 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3969 crtc_state->cpu_transcoder,
3970 (u8)conn_state->hdcp_content_type);
3971 }
3972
intel_disable_ddi_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3973 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3974 struct intel_encoder *encoder,
3975 const struct intel_crtc_state *old_crtc_state,
3976 const struct drm_connector_state *old_conn_state)
3977 {
3978 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3979
3980 intel_dp->link_trained = false;
3981
3982 if (old_crtc_state->has_audio)
3983 intel_audio_codec_disable(encoder,
3984 old_crtc_state, old_conn_state);
3985
3986 intel_edp_drrs_disable(intel_dp, old_crtc_state);
3987 intel_psr_disable(intel_dp, old_crtc_state);
3988 intel_edp_backlight_off(old_conn_state);
3989 /* Disable the decompression in DP Sink */
3990 intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3991 false);
3992 }
3993
intel_disable_ddi_hdmi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)3994 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
3995 struct intel_encoder *encoder,
3996 const struct intel_crtc_state *old_crtc_state,
3997 const struct drm_connector_state *old_conn_state)
3998 {
3999 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4000 struct drm_connector *connector = old_conn_state->connector;
4001
4002 if (old_crtc_state->has_audio)
4003 intel_audio_codec_disable(encoder,
4004 old_crtc_state, old_conn_state);
4005
4006 if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4007 false, false))
4008 drm_dbg_kms(&i915->drm,
4009 "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4010 connector->base.id, connector->name);
4011 }
4012
intel_disable_ddi(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)4013 static void intel_disable_ddi(struct intel_atomic_state *state,
4014 struct intel_encoder *encoder,
4015 const struct intel_crtc_state *old_crtc_state,
4016 const struct drm_connector_state *old_conn_state)
4017 {
4018 intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4019
4020 if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4021 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
4022 old_conn_state);
4023 else
4024 intel_disable_ddi_dp(state, encoder, old_crtc_state,
4025 old_conn_state);
4026 }
4027
intel_ddi_update_pipe_dp(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4028 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
4029 struct intel_encoder *encoder,
4030 const struct intel_crtc_state *crtc_state,
4031 const struct drm_connector_state *conn_state)
4032 {
4033 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4034
4035 intel_ddi_set_dp_msa(crtc_state, conn_state);
4036
4037 intel_psr_update(intel_dp, crtc_state, conn_state);
4038 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4039 intel_edp_drrs_update(intel_dp, crtc_state);
4040
4041 intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
4042 }
4043
intel_ddi_update_pipe(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4044 void intel_ddi_update_pipe(struct intel_atomic_state *state,
4045 struct intel_encoder *encoder,
4046 const struct intel_crtc_state *crtc_state,
4047 const struct drm_connector_state *conn_state)
4048 {
4049
4050 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
4051 !intel_encoder_is_mst(encoder))
4052 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
4053 conn_state);
4054
4055 intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
4056 }
4057
4058 static void
intel_ddi_update_prepare(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)4059 intel_ddi_update_prepare(struct intel_atomic_state *state,
4060 struct intel_encoder *encoder,
4061 struct intel_crtc *crtc)
4062 {
4063 struct intel_crtc_state *crtc_state =
4064 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4065 int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4066
4067 drm_WARN_ON(state->base.dev, crtc && crtc->active);
4068
4069 intel_tc_port_get_link(enc_to_dig_port(encoder),
4070 required_lanes);
4071 if (crtc_state && crtc_state->hw.active)
4072 intel_update_active_dpll(state, crtc, encoder);
4073 }
4074
4075 static void
intel_ddi_update_complete(struct intel_atomic_state * state,struct intel_encoder * encoder,struct intel_crtc * crtc)4076 intel_ddi_update_complete(struct intel_atomic_state *state,
4077 struct intel_encoder *encoder,
4078 struct intel_crtc *crtc)
4079 {
4080 intel_tc_port_put_link(enc_to_dig_port(encoder));
4081 }
4082
4083 static void
intel_ddi_pre_pll_enable(struct intel_atomic_state * state,struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)4084 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
4085 struct intel_encoder *encoder,
4086 const struct intel_crtc_state *crtc_state,
4087 const struct drm_connector_state *conn_state)
4088 {
4089 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4090 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4091 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4092 bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4093
4094 if (is_tc_port)
4095 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4096
4097 if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4098 intel_display_power_get(dev_priv,
4099 intel_ddi_main_link_aux_domain(dig_port));
4100
4101 if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4102 /*
4103 * Program the lane count for static/dynamic connections on
4104 * Type-C ports. Skip this step for TBT.
4105 */
4106 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4107 else if (IS_GEN9_LP(dev_priv))
4108 bxt_ddi_phy_set_lane_optim_mask(encoder,
4109 crtc_state->lane_lat_optim_mask);
4110 }
4111
intel_ddi_prepare_link_retrain(struct intel_dp * intel_dp)4112 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4113 {
4114 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4115 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4116 enum port port = dig_port->base.port;
4117 u32 dp_tp_ctl, ddi_buf_ctl;
4118 bool wait = false;
4119
4120 dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4121
4122 if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4123 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
4124 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4125 intel_de_write(dev_priv, DDI_BUF_CTL(port),
4126 ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4127 wait = true;
4128 }
4129
4130 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4131 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4132 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4133 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4134
4135 if (wait)
4136 intel_wait_ddi_buf_idle(dev_priv, port);
4137 }
4138
4139 dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
4140 if (intel_dp->link_mst)
4141 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4142 else {
4143 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4144 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4145 dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4146 }
4147 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4148 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4149
4150 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4151 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
4152 intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
4153
4154 intel_wait_ddi_buf_active(dev_priv, port);
4155 }
4156
intel_ddi_set_link_train(struct intel_dp * intel_dp,u8 dp_train_pat)4157 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
4158 u8 dp_train_pat)
4159 {
4160 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4161 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4162 u32 temp;
4163
4164 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4165
4166 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4167 switch (dp_train_pat & train_pat_mask) {
4168 case DP_TRAINING_PATTERN_DISABLE:
4169 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
4170 break;
4171 case DP_TRAINING_PATTERN_1:
4172 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
4173 break;
4174 case DP_TRAINING_PATTERN_2:
4175 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
4176 break;
4177 case DP_TRAINING_PATTERN_3:
4178 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
4179 break;
4180 case DP_TRAINING_PATTERN_4:
4181 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
4182 break;
4183 }
4184
4185 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
4186 }
4187
intel_ddi_set_idle_link_train(struct intel_dp * intel_dp)4188 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
4189 {
4190 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4191 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4192 enum port port = encoder->port;
4193 u32 val;
4194
4195 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4196 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4197 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4198 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4199
4200 /*
4201 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4202 * reason we need to set idle transmission mode is to work around a HW
4203 * issue where we enable the pipe while not in idle link-training mode.
4204 * In this case there is requirement to wait for a minimum number of
4205 * idle patterns to be sent.
4206 */
4207 if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4208 return;
4209
4210 if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4211 DP_TP_STATUS_IDLE_DONE, 1))
4212 drm_err(&dev_priv->drm,
4213 "Timed out waiting for DP idle patterns\n");
4214 }
4215
intel_ddi_is_audio_enabled(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)4216 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4217 enum transcoder cpu_transcoder)
4218 {
4219 if (cpu_transcoder == TRANSCODER_EDP)
4220 return false;
4221
4222 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4223 return false;
4224
4225 return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4226 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4227 }
4228
intel_ddi_compute_min_voltage_level(struct drm_i915_private * dev_priv,struct intel_crtc_state * crtc_state)4229 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4230 struct intel_crtc_state *crtc_state)
4231 {
4232 if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4233 crtc_state->min_voltage_level = 2;
4234 else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4235 crtc_state->min_voltage_level = 3;
4236 else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4237 crtc_state->min_voltage_level = 1;
4238 else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4239 crtc_state->min_voltage_level = 2;
4240 }
4241
bdw_transcoder_master_readout(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)4242 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4243 enum transcoder cpu_transcoder)
4244 {
4245 u32 master_select;
4246
4247 if (INTEL_GEN(dev_priv) >= 11) {
4248 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4249
4250 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4251 return INVALID_TRANSCODER;
4252
4253 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4254 } else {
4255 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4256
4257 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4258 return INVALID_TRANSCODER;
4259
4260 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4261 }
4262
4263 if (master_select == 0)
4264 return TRANSCODER_EDP;
4265 else
4266 return master_select - 1;
4267 }
4268
bdw_get_trans_port_sync_config(struct intel_crtc_state * crtc_state)4269 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4270 {
4271 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4272 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4273 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4274 enum transcoder cpu_transcoder;
4275
4276 crtc_state->master_transcoder =
4277 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4278
4279 for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4280 enum intel_display_power_domain power_domain;
4281 intel_wakeref_t trans_wakeref;
4282
4283 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4284 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4285 power_domain);
4286
4287 if (!trans_wakeref)
4288 continue;
4289
4290 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4291 crtc_state->cpu_transcoder)
4292 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4293
4294 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4295 }
4296
4297 drm_WARN_ON(&dev_priv->drm,
4298 crtc_state->master_transcoder != INVALID_TRANSCODER &&
4299 crtc_state->sync_mode_slaves_mask);
4300 }
4301
intel_ddi_get_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config)4302 void intel_ddi_get_config(struct intel_encoder *encoder,
4303 struct intel_crtc_state *pipe_config)
4304 {
4305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4306 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4307 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4308 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4309 u32 temp, flags = 0;
4310
4311 /* XXX: DSI transcoder paranoia */
4312 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4313 return;
4314
4315 intel_dsc_get_config(encoder, pipe_config);
4316
4317 temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4318 if (temp & TRANS_DDI_PHSYNC)
4319 flags |= DRM_MODE_FLAG_PHSYNC;
4320 else
4321 flags |= DRM_MODE_FLAG_NHSYNC;
4322 if (temp & TRANS_DDI_PVSYNC)
4323 flags |= DRM_MODE_FLAG_PVSYNC;
4324 else
4325 flags |= DRM_MODE_FLAG_NVSYNC;
4326
4327 pipe_config->hw.adjusted_mode.flags |= flags;
4328
4329 switch (temp & TRANS_DDI_BPC_MASK) {
4330 case TRANS_DDI_BPC_6:
4331 pipe_config->pipe_bpp = 18;
4332 break;
4333 case TRANS_DDI_BPC_8:
4334 pipe_config->pipe_bpp = 24;
4335 break;
4336 case TRANS_DDI_BPC_10:
4337 pipe_config->pipe_bpp = 30;
4338 break;
4339 case TRANS_DDI_BPC_12:
4340 pipe_config->pipe_bpp = 36;
4341 break;
4342 default:
4343 break;
4344 }
4345
4346 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4347 case TRANS_DDI_MODE_SELECT_HDMI:
4348 pipe_config->has_hdmi_sink = true;
4349
4350 pipe_config->infoframes.enable |=
4351 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4352
4353 if (pipe_config->infoframes.enable)
4354 pipe_config->has_infoframe = true;
4355
4356 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4357 pipe_config->hdmi_scrambling = true;
4358 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4359 pipe_config->hdmi_high_tmds_clock_ratio = true;
4360 fallthrough;
4361 case TRANS_DDI_MODE_SELECT_DVI:
4362 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4363 pipe_config->lane_count = 4;
4364 break;
4365 case TRANS_DDI_MODE_SELECT_FDI:
4366 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4367 break;
4368 case TRANS_DDI_MODE_SELECT_DP_SST:
4369 if (encoder->type == INTEL_OUTPUT_EDP)
4370 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4371 else
4372 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4373 pipe_config->lane_count =
4374 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4375 intel_dp_get_m_n(intel_crtc, pipe_config);
4376
4377 if (INTEL_GEN(dev_priv) >= 11) {
4378 i915_reg_t dp_tp_ctl;
4379
4380 if (IS_GEN(dev_priv, 11))
4381 dp_tp_ctl = DP_TP_CTL(encoder->port);
4382 else
4383 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4384
4385 pipe_config->fec_enable =
4386 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4387
4388 drm_dbg_kms(&dev_priv->drm,
4389 "[ENCODER:%d:%s] Fec status: %u\n",
4390 encoder->base.base.id, encoder->base.name,
4391 pipe_config->fec_enable);
4392 }
4393
4394 pipe_config->infoframes.enable |=
4395 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4396
4397 break;
4398 case TRANS_DDI_MODE_SELECT_DP_MST:
4399 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4400 pipe_config->lane_count =
4401 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4402
4403 if (INTEL_GEN(dev_priv) >= 12)
4404 pipe_config->mst_master_transcoder =
4405 REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4406
4407 intel_dp_get_m_n(intel_crtc, pipe_config);
4408
4409 pipe_config->infoframes.enable |=
4410 intel_hdmi_infoframes_enabled(encoder, pipe_config);
4411 break;
4412 default:
4413 break;
4414 }
4415
4416 if (INTEL_GEN(dev_priv) >= 12) {
4417 enum transcoder transcoder =
4418 intel_dp_mst_is_slave_trans(pipe_config) ?
4419 pipe_config->mst_master_transcoder :
4420 pipe_config->cpu_transcoder;
4421
4422 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
4423 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
4424 }
4425
4426 pipe_config->has_audio =
4427 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4428
4429 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4430 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4431 /*
4432 * This is a big fat ugly hack.
4433 *
4434 * Some machines in UEFI boot mode provide us a VBT that has 18
4435 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4436 * unknown we fail to light up. Yet the same BIOS boots up with
4437 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4438 * max, not what it tells us to use.
4439 *
4440 * Note: This will still be broken if the eDP panel is not lit
4441 * up by the BIOS, and thus we can't get the mode at module
4442 * load.
4443 */
4444 drm_dbg_kms(&dev_priv->drm,
4445 "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4446 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4447 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4448 }
4449
4450 intel_ddi_clock_get(encoder, pipe_config);
4451
4452 if (IS_GEN9_LP(dev_priv))
4453 pipe_config->lane_lat_optim_mask =
4454 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4455
4456 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4457
4458 intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4459
4460 intel_read_infoframe(encoder, pipe_config,
4461 HDMI_INFOFRAME_TYPE_AVI,
4462 &pipe_config->infoframes.avi);
4463 intel_read_infoframe(encoder, pipe_config,
4464 HDMI_INFOFRAME_TYPE_SPD,
4465 &pipe_config->infoframes.spd);
4466 intel_read_infoframe(encoder, pipe_config,
4467 HDMI_INFOFRAME_TYPE_VENDOR,
4468 &pipe_config->infoframes.hdmi);
4469 intel_read_infoframe(encoder, pipe_config,
4470 HDMI_INFOFRAME_TYPE_DRM,
4471 &pipe_config->infoframes.drm);
4472
4473 if (INTEL_GEN(dev_priv) >= 8)
4474 bdw_get_trans_port_sync_config(pipe_config);
4475
4476 intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4477 intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4478 }
4479
4480 static enum intel_output_type
intel_ddi_compute_output_type(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4481 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4482 struct intel_crtc_state *crtc_state,
4483 struct drm_connector_state *conn_state)
4484 {
4485 switch (conn_state->connector->connector_type) {
4486 case DRM_MODE_CONNECTOR_HDMIA:
4487 return INTEL_OUTPUT_HDMI;
4488 case DRM_MODE_CONNECTOR_eDP:
4489 return INTEL_OUTPUT_EDP;
4490 case DRM_MODE_CONNECTOR_DisplayPort:
4491 return INTEL_OUTPUT_DP;
4492 default:
4493 MISSING_CASE(conn_state->connector->connector_type);
4494 return INTEL_OUTPUT_UNUSED;
4495 }
4496 }
4497
intel_ddi_compute_config(struct intel_encoder * encoder,struct intel_crtc_state * pipe_config,struct drm_connector_state * conn_state)4498 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4499 struct intel_crtc_state *pipe_config,
4500 struct drm_connector_state *conn_state)
4501 {
4502 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4503 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4504 enum port port = encoder->port;
4505 int ret;
4506
4507 if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4508 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4509
4510 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4511 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4512 } else {
4513 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4514 }
4515
4516 if (ret)
4517 return ret;
4518
4519 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4520 pipe_config->cpu_transcoder == TRANSCODER_EDP)
4521 pipe_config->pch_pfit.force_thru =
4522 pipe_config->pch_pfit.enabled ||
4523 pipe_config->crc_enabled;
4524
4525 if (IS_GEN9_LP(dev_priv))
4526 pipe_config->lane_lat_optim_mask =
4527 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4528
4529 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4530
4531 return 0;
4532 }
4533
mode_equal(const struct drm_display_mode * mode1,const struct drm_display_mode * mode2)4534 static bool mode_equal(const struct drm_display_mode *mode1,
4535 const struct drm_display_mode *mode2)
4536 {
4537 return drm_mode_match(mode1, mode2,
4538 DRM_MODE_MATCH_TIMINGS |
4539 DRM_MODE_MATCH_FLAGS |
4540 DRM_MODE_MATCH_3D_FLAGS) &&
4541 mode1->clock == mode2->clock; /* we want an exact match */
4542 }
4543
m_n_equal(const struct intel_link_m_n * m_n_1,const struct intel_link_m_n * m_n_2)4544 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4545 const struct intel_link_m_n *m_n_2)
4546 {
4547 return m_n_1->tu == m_n_2->tu &&
4548 m_n_1->gmch_m == m_n_2->gmch_m &&
4549 m_n_1->gmch_n == m_n_2->gmch_n &&
4550 m_n_1->link_m == m_n_2->link_m &&
4551 m_n_1->link_n == m_n_2->link_n;
4552 }
4553
crtcs_port_sync_compatible(const struct intel_crtc_state * crtc_state1,const struct intel_crtc_state * crtc_state2)4554 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4555 const struct intel_crtc_state *crtc_state2)
4556 {
4557 return crtc_state1->hw.active && crtc_state2->hw.active &&
4558 crtc_state1->output_types == crtc_state2->output_types &&
4559 crtc_state1->output_format == crtc_state2->output_format &&
4560 crtc_state1->lane_count == crtc_state2->lane_count &&
4561 crtc_state1->port_clock == crtc_state2->port_clock &&
4562 mode_equal(&crtc_state1->hw.adjusted_mode,
4563 &crtc_state2->hw.adjusted_mode) &&
4564 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4565 }
4566
4567 static u8
intel_ddi_port_sync_transcoders(const struct intel_crtc_state * ref_crtc_state,int tile_group_id)4568 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4569 int tile_group_id)
4570 {
4571 struct drm_connector *connector;
4572 const struct drm_connector_state *conn_state;
4573 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4574 struct intel_atomic_state *state =
4575 to_intel_atomic_state(ref_crtc_state->uapi.state);
4576 u8 transcoders = 0;
4577 int i;
4578
4579 /*
4580 * We don't enable port sync on BDW due to missing w/as and
4581 * due to not having adjusted the modeset sequence appropriately.
4582 */
4583 if (INTEL_GEN(dev_priv) < 9)
4584 return 0;
4585
4586 if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4587 return 0;
4588
4589 for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4590 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4591 const struct intel_crtc_state *crtc_state;
4592
4593 if (!crtc)
4594 continue;
4595
4596 if (!connector->has_tile ||
4597 connector->tile_group->id !=
4598 tile_group_id)
4599 continue;
4600 crtc_state = intel_atomic_get_new_crtc_state(state,
4601 crtc);
4602 if (!crtcs_port_sync_compatible(ref_crtc_state,
4603 crtc_state))
4604 continue;
4605 transcoders |= BIT(crtc_state->cpu_transcoder);
4606 }
4607
4608 return transcoders;
4609 }
4610
intel_ddi_compute_config_late(struct intel_encoder * encoder,struct intel_crtc_state * crtc_state,struct drm_connector_state * conn_state)4611 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4612 struct intel_crtc_state *crtc_state,
4613 struct drm_connector_state *conn_state)
4614 {
4615 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4616 struct drm_connector *connector = conn_state->connector;
4617 u8 port_sync_transcoders = 0;
4618
4619 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4620 encoder->base.base.id, encoder->base.name,
4621 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4622
4623 if (connector->has_tile)
4624 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4625 connector->tile_group->id);
4626
4627 /*
4628 * EDP Transcoders cannot be ensalved
4629 * make them a master always when present
4630 */
4631 if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4632 crtc_state->master_transcoder = TRANSCODER_EDP;
4633 else
4634 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4635
4636 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4637 crtc_state->master_transcoder = INVALID_TRANSCODER;
4638 crtc_state->sync_mode_slaves_mask =
4639 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4640 }
4641
4642 return 0;
4643 }
4644
intel_ddi_encoder_destroy(struct drm_encoder * encoder)4645 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4646 {
4647 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4648
4649 intel_dp_encoder_flush_work(encoder);
4650
4651 drm_encoder_cleanup(encoder);
4652 kfree(dig_port);
4653 }
4654
4655 static const struct drm_encoder_funcs intel_ddi_funcs = {
4656 .reset = intel_dp_encoder_reset,
4657 .destroy = intel_ddi_encoder_destroy,
4658 };
4659
4660 static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port * dig_port)4661 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4662 {
4663 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4664 struct intel_connector *connector;
4665 enum port port = dig_port->base.port;
4666
4667 connector = intel_connector_alloc();
4668 if (!connector)
4669 return NULL;
4670
4671 dig_port->dp.output_reg = DDI_BUF_CTL(port);
4672 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4673 dig_port->dp.set_link_train = intel_ddi_set_link_train;
4674 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4675
4676 if (INTEL_GEN(dev_priv) >= 12)
4677 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4678 else if (INTEL_GEN(dev_priv) >= 11)
4679 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4680 else if (IS_CANNONLAKE(dev_priv))
4681 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
4682 else if (IS_GEN9_LP(dev_priv))
4683 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4684 else
4685 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4686
4687 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4688 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4689
4690 if (INTEL_GEN(dev_priv) < 12) {
4691 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4692 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4693 }
4694
4695 if (!intel_dp_init_connector(dig_port, connector)) {
4696 kfree(connector);
4697 return NULL;
4698 }
4699
4700 return connector;
4701 }
4702
modeset_pipe(struct drm_crtc * crtc,struct drm_modeset_acquire_ctx * ctx)4703 static int modeset_pipe(struct drm_crtc *crtc,
4704 struct drm_modeset_acquire_ctx *ctx)
4705 {
4706 struct drm_atomic_state *state;
4707 struct drm_crtc_state *crtc_state;
4708 int ret;
4709
4710 state = drm_atomic_state_alloc(crtc->dev);
4711 if (!state)
4712 return -ENOMEM;
4713
4714 state->acquire_ctx = ctx;
4715
4716 crtc_state = drm_atomic_get_crtc_state(state, crtc);
4717 if (IS_ERR(crtc_state)) {
4718 ret = PTR_ERR(crtc_state);
4719 goto out;
4720 }
4721
4722 crtc_state->connectors_changed = true;
4723
4724 ret = drm_atomic_commit(state);
4725 out:
4726 drm_atomic_state_put(state);
4727
4728 return ret;
4729 }
4730
intel_hdmi_reset_link(struct intel_encoder * encoder,struct drm_modeset_acquire_ctx * ctx)4731 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4732 struct drm_modeset_acquire_ctx *ctx)
4733 {
4734 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4735 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4736 struct intel_connector *connector = hdmi->attached_connector;
4737 struct i2c_adapter *adapter =
4738 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4739 struct drm_connector_state *conn_state;
4740 struct intel_crtc_state *crtc_state;
4741 struct intel_crtc *crtc;
4742 u8 config;
4743 int ret;
4744
4745 if (!connector || connector->base.status != connector_status_connected)
4746 return 0;
4747
4748 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4749 ctx);
4750 if (ret)
4751 return ret;
4752
4753 conn_state = connector->base.state;
4754
4755 crtc = to_intel_crtc(conn_state->crtc);
4756 if (!crtc)
4757 return 0;
4758
4759 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4760 if (ret)
4761 return ret;
4762
4763 crtc_state = to_intel_crtc_state(crtc->base.state);
4764
4765 drm_WARN_ON(&dev_priv->drm,
4766 !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4767
4768 if (!crtc_state->hw.active)
4769 return 0;
4770
4771 if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4772 !crtc_state->hdmi_scrambling)
4773 return 0;
4774
4775 if (conn_state->commit &&
4776 !try_wait_for_completion(&conn_state->commit->hw_done))
4777 return 0;
4778
4779 ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4780 if (ret < 0) {
4781 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4782 ret);
4783 return 0;
4784 }
4785
4786 if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4787 crtc_state->hdmi_high_tmds_clock_ratio &&
4788 !!(config & SCDC_SCRAMBLING_ENABLE) ==
4789 crtc_state->hdmi_scrambling)
4790 return 0;
4791
4792 /*
4793 * HDMI 2.0 says that one should not send scrambled data
4794 * prior to configuring the sink scrambling, and that
4795 * TMDS clock/data transmission should be suspended when
4796 * changing the TMDS clock rate in the sink. So let's
4797 * just do a full modeset here, even though some sinks
4798 * would be perfectly happy if were to just reconfigure
4799 * the SCDC settings on the fly.
4800 */
4801 return modeset_pipe(&crtc->base, ctx);
4802 }
4803
4804 static enum intel_hotplug_state
intel_ddi_hotplug(struct intel_encoder * encoder,struct intel_connector * connector)4805 intel_ddi_hotplug(struct intel_encoder *encoder,
4806 struct intel_connector *connector)
4807 {
4808 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4809 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4810 enum phy phy = intel_port_to_phy(i915, encoder->port);
4811 bool is_tc = intel_phy_is_tc(i915, phy);
4812 struct drm_modeset_acquire_ctx ctx;
4813 enum intel_hotplug_state state;
4814 int ret;
4815
4816 state = intel_encoder_hotplug(encoder, connector);
4817
4818 drm_modeset_acquire_init(&ctx, 0);
4819
4820 for (;;) {
4821 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4822 ret = intel_hdmi_reset_link(encoder, &ctx);
4823 else
4824 ret = intel_dp_retrain_link(encoder, &ctx);
4825
4826 if (ret == -EDEADLK) {
4827 drm_modeset_backoff(&ctx);
4828 continue;
4829 }
4830
4831 break;
4832 }
4833
4834 drm_modeset_drop_locks(&ctx);
4835 drm_modeset_acquire_fini(&ctx);
4836 drm_WARN(encoder->base.dev, ret,
4837 "Acquiring modeset locks failed with %i\n", ret);
4838
4839 /*
4840 * Unpowered type-c dongles can take some time to boot and be
4841 * responsible, so here giving some time to those dongles to power up
4842 * and then retrying the probe.
4843 *
4844 * On many platforms the HDMI live state signal is known to be
4845 * unreliable, so we can't use it to detect if a sink is connected or
4846 * not. Instead we detect if it's connected based on whether we can
4847 * read the EDID or not. That in turn has a problem during disconnect,
4848 * since the HPD interrupt may be raised before the DDC lines get
4849 * disconnected (due to how the required length of DDC vs. HPD
4850 * connector pins are specified) and so we'll still be able to get a
4851 * valid EDID. To solve this schedule another detection cycle if this
4852 * time around we didn't detect any change in the sink's connection
4853 * status.
4854 *
4855 * Type-c connectors which get their HPD signal deasserted then
4856 * reasserted, without unplugging/replugging the sink from the
4857 * connector, introduce a delay until the AUX channel communication
4858 * becomes functional. Retry the detection for 5 seconds on type-c
4859 * connectors to account for this delay.
4860 */
4861 if (state == INTEL_HOTPLUG_UNCHANGED &&
4862 connector->hotplug_retries < (is_tc ? 5 : 1) &&
4863 !dig_port->dp.is_mst)
4864 state = INTEL_HOTPLUG_RETRY;
4865
4866 return state;
4867 }
4868
lpt_digital_port_connected(struct intel_encoder * encoder)4869 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4870 {
4871 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4872 u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4873
4874 return intel_de_read(dev_priv, SDEISR) & bit;
4875 }
4876
hsw_digital_port_connected(struct intel_encoder * encoder)4877 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4878 {
4879 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4880 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4881
4882 return intel_de_read(dev_priv, DEISR) & bit;
4883 }
4884
bdw_digital_port_connected(struct intel_encoder * encoder)4885 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4886 {
4887 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4888 u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4889
4890 return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4891 }
4892
4893 static struct intel_connector *
intel_ddi_init_hdmi_connector(struct intel_digital_port * dig_port)4894 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4895 {
4896 struct intel_connector *connector;
4897 enum port port = dig_port->base.port;
4898
4899 connector = intel_connector_alloc();
4900 if (!connector)
4901 return NULL;
4902
4903 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4904 intel_hdmi_init_connector(dig_port, connector);
4905
4906 return connector;
4907 }
4908
intel_ddi_a_force_4_lanes(struct intel_digital_port * dig_port)4909 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4910 {
4911 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4912
4913 if (dig_port->base.port != PORT_A)
4914 return false;
4915
4916 if (dig_port->saved_port_bits & DDI_A_4_LANES)
4917 return false;
4918
4919 /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4920 * supported configuration
4921 */
4922 if (IS_GEN9_LP(dev_priv))
4923 return true;
4924
4925 /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4926 * one who does also have a full A/E split called
4927 * DDI_F what makes DDI_E useless. However for this
4928 * case let's trust VBT info.
4929 */
4930 if (IS_CANNONLAKE(dev_priv) &&
4931 !intel_bios_is_port_present(dev_priv, PORT_E))
4932 return true;
4933
4934 return false;
4935 }
4936
4937 static int
intel_ddi_max_lanes(struct intel_digital_port * dig_port)4938 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4939 {
4940 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4941 enum port port = dig_port->base.port;
4942 int max_lanes = 4;
4943
4944 if (INTEL_GEN(dev_priv) >= 11)
4945 return max_lanes;
4946
4947 if (port == PORT_A || port == PORT_E) {
4948 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4949 max_lanes = port == PORT_A ? 4 : 0;
4950 else
4951 /* Both A and E share 2 lanes */
4952 max_lanes = 2;
4953 }
4954
4955 /*
4956 * Some BIOS might fail to set this bit on port A if eDP
4957 * wasn't lit up at boot. Force this bit set when needed
4958 * so we use the proper lane count for our calculations.
4959 */
4960 if (intel_ddi_a_force_4_lanes(dig_port)) {
4961 drm_dbg_kms(&dev_priv->drm,
4962 "Forcing DDI_A_4_LANES for port A\n");
4963 dig_port->saved_port_bits |= DDI_A_4_LANES;
4964 max_lanes = 4;
4965 }
4966
4967 return max_lanes;
4968 }
4969
hti_uses_phy(struct drm_i915_private * i915,enum phy phy)4970 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4971 {
4972 return i915->hti_state & HDPORT_ENABLED &&
4973 (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
4974 i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
4975 }
4976
tgl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4977 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4978 enum port port)
4979 {
4980 if (port >= PORT_D)
4981 return HPD_PORT_TC1 + port - PORT_D;
4982 else
4983 return HPD_PORT_A + port - PORT_A;
4984 }
4985
rkl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4986 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4987 enum port port)
4988 {
4989 if (HAS_PCH_TGP(dev_priv))
4990 return tgl_hpd_pin(dev_priv, port);
4991
4992 if (port >= PORT_D)
4993 return HPD_PORT_C + port - PORT_D;
4994 else
4995 return HPD_PORT_A + port - PORT_A;
4996 }
4997
icl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)4998 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4999 enum port port)
5000 {
5001 if (port >= PORT_C)
5002 return HPD_PORT_TC1 + port - PORT_C;
5003 else
5004 return HPD_PORT_A + port - PORT_A;
5005 }
5006
ehl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)5007 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
5008 enum port port)
5009 {
5010 if (port == PORT_D)
5011 return HPD_PORT_A;
5012
5013 if (HAS_PCH_MCC(dev_priv))
5014 return icl_hpd_pin(dev_priv, port);
5015
5016 return HPD_PORT_A + port - PORT_A;
5017 }
5018
cnl_hpd_pin(struct drm_i915_private * dev_priv,enum port port)5019 static enum hpd_pin cnl_hpd_pin(struct drm_i915_private *dev_priv,
5020 enum port port)
5021 {
5022 if (port == PORT_F)
5023 return HPD_PORT_E;
5024
5025 return HPD_PORT_A + port - PORT_A;
5026 }
5027
intel_ddi_init(struct drm_i915_private * dev_priv,enum port port)5028 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
5029 {
5030 struct intel_digital_port *dig_port;
5031 struct intel_encoder *encoder;
5032 bool init_hdmi, init_dp, init_lspcon = false;
5033 enum phy phy = intel_port_to_phy(dev_priv, port);
5034
5035 /*
5036 * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
5037 * have taken over some of the PHYs and made them unavailable to the
5038 * driver. In that case we should skip initializing the corresponding
5039 * outputs.
5040 */
5041 if (hti_uses_phy(dev_priv, phy)) {
5042 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
5043 port_name(port), phy_name(phy));
5044 return;
5045 }
5046
5047 init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
5048 intel_bios_port_supports_hdmi(dev_priv, port);
5049 init_dp = intel_bios_port_supports_dp(dev_priv, port);
5050
5051 if (intel_bios_is_lspcon_present(dev_priv, port)) {
5052 /*
5053 * Lspcon device needs to be driven with DP connector
5054 * with special detection sequence. So make sure DP
5055 * is initialized before lspcon.
5056 */
5057 init_dp = true;
5058 init_lspcon = true;
5059 init_hdmi = false;
5060 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
5061 port_name(port));
5062 }
5063
5064 if (!init_dp && !init_hdmi) {
5065 drm_dbg_kms(&dev_priv->drm,
5066 "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5067 port_name(port));
5068 return;
5069 }
5070
5071 dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
5072 if (!dig_port)
5073 return;
5074
5075 encoder = &dig_port->base;
5076
5077 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5078 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
5079
5080 mutex_init(&dig_port->hdcp_mutex);
5081 dig_port->num_hdcp_streams = 0;
5082
5083 encoder->hotplug = intel_ddi_hotplug;
5084 encoder->compute_output_type = intel_ddi_compute_output_type;
5085 encoder->compute_config = intel_ddi_compute_config;
5086 encoder->compute_config_late = intel_ddi_compute_config_late;
5087 encoder->enable = intel_enable_ddi;
5088 encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5089 encoder->pre_enable = intel_ddi_pre_enable;
5090 encoder->disable = intel_disable_ddi;
5091 encoder->post_disable = intel_ddi_post_disable;
5092 encoder->update_pipe = intel_ddi_update_pipe;
5093 encoder->get_hw_state = intel_ddi_get_hw_state;
5094 encoder->get_config = intel_ddi_get_config;
5095 encoder->suspend = intel_dp_encoder_suspend;
5096 encoder->get_power_domains = intel_ddi_get_power_domains;
5097
5098 encoder->type = INTEL_OUTPUT_DDI;
5099 encoder->power_domain = intel_port_to_power_domain(port);
5100 encoder->port = port;
5101 encoder->cloneable = 0;
5102 encoder->pipe_mask = ~0;
5103
5104 if (IS_ROCKETLAKE(dev_priv))
5105 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
5106 else if (INTEL_GEN(dev_priv) >= 12)
5107 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
5108 else if (IS_ELKHARTLAKE(dev_priv))
5109 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
5110 else if (IS_GEN(dev_priv, 11))
5111 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
5112 else if (IS_GEN(dev_priv, 10))
5113 encoder->hpd_pin = cnl_hpd_pin(dev_priv, port);
5114 else
5115 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
5116
5117 if (INTEL_GEN(dev_priv) >= 11)
5118 dig_port->saved_port_bits =
5119 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5120 & DDI_BUF_PORT_REVERSAL;
5121 else
5122 dig_port->saved_port_bits =
5123 intel_de_read(dev_priv, DDI_BUF_CTL(port))
5124 & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
5125
5126 dig_port->dp.output_reg = INVALID_MMIO_REG;
5127 dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5128 dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
5129
5130 if (intel_phy_is_tc(dev_priv, phy)) {
5131 bool is_legacy =
5132 !intel_bios_port_supports_typec_usb(dev_priv, port) &&
5133 !intel_bios_port_supports_tbt(dev_priv, port);
5134
5135 intel_tc_port_init(dig_port, is_legacy);
5136
5137 encoder->update_prepare = intel_ddi_update_prepare;
5138 encoder->update_complete = intel_ddi_update_complete;
5139 }
5140
5141 drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5142 dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
5143 port - PORT_A;
5144
5145 if (init_dp) {
5146 if (!intel_ddi_init_dp_connector(dig_port))
5147 goto err;
5148
5149 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5150 }
5151
5152 /* In theory we don't need the encoder->type check, but leave it just in
5153 * case we have some really bad VBTs... */
5154 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5155 if (!intel_ddi_init_hdmi_connector(dig_port))
5156 goto err;
5157 }
5158
5159 if (init_lspcon) {
5160 if (lspcon_init(dig_port))
5161 /* TODO: handle hdmi info frame part */
5162 drm_dbg_kms(&dev_priv->drm,
5163 "LSPCON init success on port %c\n",
5164 port_name(port));
5165 else
5166 /*
5167 * LSPCON init faied, but DP init was success, so
5168 * lets try to drive as DP++ port.
5169 */
5170 drm_err(&dev_priv->drm,
5171 "LSPCON init failed on port %c\n",
5172 port_name(port));
5173 }
5174
5175 if (INTEL_GEN(dev_priv) >= 11) {
5176 if (intel_phy_is_tc(dev_priv, phy))
5177 dig_port->connected = intel_tc_port_connected;
5178 else
5179 dig_port->connected = lpt_digital_port_connected;
5180 } else if (INTEL_GEN(dev_priv) >= 8) {
5181 if (port == PORT_A || IS_GEN9_LP(dev_priv))
5182 dig_port->connected = bdw_digital_port_connected;
5183 else
5184 dig_port->connected = lpt_digital_port_connected;
5185 } else {
5186 if (port == PORT_A)
5187 dig_port->connected = hsw_digital_port_connected;
5188 else
5189 dig_port->connected = lpt_digital_port_connected;
5190 }
5191
5192 intel_infoframe_init(dig_port);
5193
5194 return;
5195
5196 err:
5197 drm_encoder_cleanup(&encoder->base);
5198 kfree(dig_port);
5199 }
5200