1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include "intel_cx0_phy.h"
7 #include "intel_ddi.h"
8 #include "intel_ddi_buf_trans.h"
9 #include "intel_de.h"
10 #include "intel_display_types.h"
11 #include "intel_display_utils.h"
12 #include "intel_dp.h"
13 #include "intel_lt_phy.h"
14
15 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
16 * them for both DP and FDI transports, allowing those ports to
17 * automatically adapt to HDMI connections as well
18 */
19 static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = {
20 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
21 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
22 { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
23 { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
24 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
25 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
26 { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
27 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
28 { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
29 };
30
31 static const struct intel_ddi_buf_trans hsw_trans_dp = {
32 .entries = _hsw_trans_dp,
33 .num_entries = ARRAY_SIZE(_hsw_trans_dp),
34 };
35
36 static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = {
37 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
38 { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } },
39 { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } },
40 { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } },
41 { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } },
42 { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } },
43 { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } },
44 { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } },
45 { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } },
46 };
47
48 static const struct intel_ddi_buf_trans hsw_trans_fdi = {
49 .entries = _hsw_trans_fdi,
50 .num_entries = ARRAY_SIZE(_hsw_trans_fdi),
51 };
52
53 static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = {
54 /* Idx NT mV d T mV d db */
55 { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } }, /* 0: 400 400 0 */
56 { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } }, /* 1: 400 500 2 */
57 { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } }, /* 2: 400 600 3.5 */
58 { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } }, /* 3: 600 600 0 */
59 { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } }, /* 4: 600 750 2 */
60 { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } }, /* 5: 600 900 3.5 */
61 { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } }, /* 6: 800 800 0 */
62 { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } }, /* 7: 800 1000 2 */
63 { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } }, /* 8: 850 850 0 */
64 { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } }, /* 9: 900 900 0 */
65 { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } }, /* 10: 950 950 0 */
66 { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } }, /* 11: 1000 1000 0 */
67 };
68
69 static const struct intel_ddi_buf_trans hsw_trans_hdmi = {
70 .entries = _hsw_trans_hdmi,
71 .num_entries = ARRAY_SIZE(_hsw_trans_hdmi),
72 .hdmi_default_entry = 6,
73 };
74
75 static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = {
76 { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } },
77 { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } },
78 { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } },
79 { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } },
80 { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } },
81 { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } },
82 { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } },
83 { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } },
84 { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } },
85 };
86
87 static const struct intel_ddi_buf_trans bdw_trans_edp = {
88 .entries = _bdw_trans_edp,
89 .num_entries = ARRAY_SIZE(_bdw_trans_edp),
90 };
91
92 static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = {
93 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
94 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
95 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
96 { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } },
97 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
98 { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } },
99 { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } },
100 { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } },
101 { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } },
102 };
103
104 static const struct intel_ddi_buf_trans bdw_trans_dp = {
105 .entries = _bdw_trans_dp,
106 .num_entries = ARRAY_SIZE(_bdw_trans_dp),
107 };
108
109 static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = {
110 { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } },
111 { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } },
112 { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } },
113 { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } },
114 { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } },
115 { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } },
116 { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } },
117 { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } },
118 { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } },
119 };
120
121 static const struct intel_ddi_buf_trans bdw_trans_fdi = {
122 .entries = _bdw_trans_fdi,
123 .num_entries = ARRAY_SIZE(_bdw_trans_fdi),
124 };
125
126 static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = {
127 /* Idx NT mV d T mV df db */
128 { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } }, /* 0: 400 400 0 */
129 { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } }, /* 1: 400 600 3.5 */
130 { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } }, /* 2: 400 800 6 */
131 { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } }, /* 3: 450 450 0 */
132 { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } }, /* 4: 600 600 0 */
133 { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } }, /* 5: 600 800 2.5 */
134 { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } }, /* 6: 600 1000 4.5 */
135 { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } }, /* 7: 800 800 0 */
136 { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } }, /* 8: 800 1000 2 */
137 { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } }, /* 9: 1000 1000 0 */
138 };
139
140 static const struct intel_ddi_buf_trans bdw_trans_hdmi = {
141 .entries = _bdw_trans_hdmi,
142 .num_entries = ARRAY_SIZE(_bdw_trans_hdmi),
143 .hdmi_default_entry = 7,
144 };
145
146 /* Skylake H and S */
147 static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = {
148 { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
149 { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
150 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
151 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
152 { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
153 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
154 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
155 { .hsw = { 0x00002016, 0x000000DF, 0x0 } },
156 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
157 };
158
159 static const struct intel_ddi_buf_trans skl_trans_dp = {
160 .entries = _skl_trans_dp,
161 .num_entries = ARRAY_SIZE(_skl_trans_dp),
162 };
163
164 /* Skylake U */
165 static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = {
166 { .hsw = { 0x0000201B, 0x000000A2, 0x0 } },
167 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
168 { .hsw = { 0x80007011, 0x000000CD, 0x1 } },
169 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
170 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
171 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
172 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
173 { .hsw = { 0x00002016, 0x00000088, 0x0 } },
174 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
175 };
176
177 static const struct intel_ddi_buf_trans skl_u_trans_dp = {
178 .entries = _skl_u_trans_dp,
179 .num_entries = ARRAY_SIZE(_skl_u_trans_dp),
180 };
181
182 /* Skylake Y */
183 static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = {
184 { .hsw = { 0x00000018, 0x000000A2, 0x0 } },
185 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
186 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
187 { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
188 { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
189 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
190 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
191 { .hsw = { 0x00000018, 0x00000088, 0x0 } },
192 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
193 };
194
195 static const struct intel_ddi_buf_trans skl_y_trans_dp = {
196 .entries = _skl_y_trans_dp,
197 .num_entries = ARRAY_SIZE(_skl_y_trans_dp),
198 };
199
200 /* Kabylake H and S */
201 static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = {
202 { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
203 { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
204 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
205 { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
206 { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
207 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
208 { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
209 { .hsw = { 0x00002016, 0x00000097, 0x0 } },
210 { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
211 };
212
213 static const struct intel_ddi_buf_trans kbl_trans_dp = {
214 .entries = _kbl_trans_dp,
215 .num_entries = ARRAY_SIZE(_kbl_trans_dp),
216 };
217
218 /* Kabylake U */
219 static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = {
220 { .hsw = { 0x0000201B, 0x000000A1, 0x0 } },
221 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
222 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
223 { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
224 { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
225 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
226 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
227 { .hsw = { 0x00002016, 0x0000004F, 0x0 } },
228 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
229 };
230
231 static const struct intel_ddi_buf_trans kbl_u_trans_dp = {
232 .entries = _kbl_u_trans_dp,
233 .num_entries = ARRAY_SIZE(_kbl_u_trans_dp),
234 };
235
236 /* Kabylake Y */
237 static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = {
238 { .hsw = { 0x00001017, 0x000000A1, 0x0 } },
239 { .hsw = { 0x00005012, 0x00000088, 0x0 } },
240 { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
241 { .hsw = { 0x8000800F, 0x000000C0, 0x3 } },
242 { .hsw = { 0x00001017, 0x0000009D, 0x0 } },
243 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
244 { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
245 { .hsw = { 0x00001017, 0x0000004C, 0x0 } },
246 { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
247 };
248
249 static const struct intel_ddi_buf_trans kbl_y_trans_dp = {
250 .entries = _kbl_y_trans_dp,
251 .num_entries = ARRAY_SIZE(_kbl_y_trans_dp),
252 };
253
254 /*
255 * Skylake/Kabylake H and S
256 * eDP 1.4 low vswing translation parameters
257 */
258 static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = {
259 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
260 { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
261 { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
262 { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
263 { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
264 { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
265 { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
266 { .hsw = { 0x00000018, 0x000000AB, 0x0 } },
267 { .hsw = { 0x00007013, 0x0000009F, 0x0 } },
268 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
269 };
270
271 static const struct intel_ddi_buf_trans skl_trans_edp = {
272 .entries = _skl_trans_edp,
273 .num_entries = ARRAY_SIZE(_skl_trans_edp),
274 };
275
276 /*
277 * Skylake/Kabylake U
278 * eDP 1.4 low vswing translation parameters
279 */
280 static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = {
281 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
282 { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
283 { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
284 { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
285 { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
286 { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
287 { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
288 { .hsw = { 0x00002016, 0x000000AB, 0x0 } },
289 { .hsw = { 0x00005013, 0x0000009F, 0x0 } },
290 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
291 };
292
293 static const struct intel_ddi_buf_trans skl_u_trans_edp = {
294 .entries = _skl_u_trans_edp,
295 .num_entries = ARRAY_SIZE(_skl_u_trans_edp),
296 };
297
298 /*
299 * Skylake/Kabylake Y
300 * eDP 1.4 low vswing translation parameters
301 */
302 static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = {
303 { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
304 { .hsw = { 0x00004013, 0x000000AB, 0x0 } },
305 { .hsw = { 0x00007011, 0x000000A4, 0x0 } },
306 { .hsw = { 0x00009010, 0x000000DF, 0x0 } },
307 { .hsw = { 0x00000018, 0x000000AA, 0x0 } },
308 { .hsw = { 0x00006013, 0x000000A4, 0x0 } },
309 { .hsw = { 0x00007011, 0x0000009D, 0x0 } },
310 { .hsw = { 0x00000018, 0x000000A0, 0x0 } },
311 { .hsw = { 0x00006012, 0x000000DF, 0x0 } },
312 { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
313 };
314
315 static const struct intel_ddi_buf_trans skl_y_trans_edp = {
316 .entries = _skl_y_trans_edp,
317 .num_entries = ARRAY_SIZE(_skl_y_trans_edp),
318 };
319
320 /* Skylake/Kabylake U, H and S */
321 static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = {
322 { .hsw = { 0x00000018, 0x000000AC, 0x0 } },
323 { .hsw = { 0x00005012, 0x0000009D, 0x0 } },
324 { .hsw = { 0x00007011, 0x00000088, 0x0 } },
325 { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
326 { .hsw = { 0x00000018, 0x00000098, 0x0 } },
327 { .hsw = { 0x00004013, 0x00000088, 0x0 } },
328 { .hsw = { 0x80006012, 0x000000CD, 0x1 } },
329 { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
330 { .hsw = { 0x80003015, 0x000000CD, 0x1 } }, /* Default */
331 { .hsw = { 0x80003015, 0x000000C0, 0x1 } },
332 { .hsw = { 0x80000018, 0x000000C0, 0x1 } },
333 };
334
335 static const struct intel_ddi_buf_trans skl_trans_hdmi = {
336 .entries = _skl_trans_hdmi,
337 .num_entries = ARRAY_SIZE(_skl_trans_hdmi),
338 .hdmi_default_entry = 8,
339 };
340
341 /* Skylake/Kabylake Y */
342 static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = {
343 { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
344 { .hsw = { 0x00005012, 0x000000DF, 0x0 } },
345 { .hsw = { 0x80007011, 0x000000CB, 0x3 } },
346 { .hsw = { 0x00000018, 0x000000A4, 0x0 } },
347 { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
348 { .hsw = { 0x00004013, 0x00000080, 0x0 } },
349 { .hsw = { 0x80006013, 0x000000C0, 0x3 } },
350 { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
351 { .hsw = { 0x80003015, 0x000000C0, 0x3 } }, /* Default */
352 { .hsw = { 0x80003015, 0x000000C0, 0x3 } },
353 { .hsw = { 0x80000018, 0x000000C0, 0x3 } },
354 };
355
356 static const struct intel_ddi_buf_trans skl_y_trans_hdmi = {
357 .entries = _skl_y_trans_hdmi,
358 .num_entries = ARRAY_SIZE(_skl_y_trans_hdmi),
359 .hdmi_default_entry = 8,
360 };
361
362 static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = {
363 /* Idx NT mV diff db */
364 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */
365 { .bxt = { 78, 0x9A, 0, 85, } }, /* 1: 400 3.5 */
366 { .bxt = { 104, 0x9A, 0, 64, } }, /* 2: 400 6 */
367 { .bxt = { 154, 0x9A, 0, 43, } }, /* 3: 400 9.5 */
368 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */
369 { .bxt = { 116, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
370 { .bxt = { 154, 0x9A, 0, 64, } }, /* 6: 600 6 */
371 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */
372 { .bxt = { 154, 0x9A, 0, 85, } }, /* 8: 800 3.5 */
373 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */
374 };
375
376 static const struct intel_ddi_buf_trans bxt_trans_dp = {
377 .entries = _bxt_trans_dp,
378 .num_entries = ARRAY_SIZE(_bxt_trans_dp),
379 };
380
381 static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = {
382 /* Idx NT mV diff db */
383 { .bxt = { 26, 0, 0, 128, } }, /* 0: 200 0 */
384 { .bxt = { 38, 0, 0, 112, } }, /* 1: 200 1.5 */
385 { .bxt = { 48, 0, 0, 96, } }, /* 2: 200 4 */
386 { .bxt = { 54, 0, 0, 69, } }, /* 3: 200 6 */
387 { .bxt = { 32, 0, 0, 128, } }, /* 4: 250 0 */
388 { .bxt = { 48, 0, 0, 104, } }, /* 5: 250 1.5 */
389 { .bxt = { 54, 0, 0, 85, } }, /* 6: 250 4 */
390 { .bxt = { 43, 0, 0, 128, } }, /* 7: 300 0 */
391 { .bxt = { 54, 0, 0, 101, } }, /* 8: 300 1.5 */
392 { .bxt = { 48, 0, 0, 128, } }, /* 9: 300 0 */
393 };
394
395 static const struct intel_ddi_buf_trans bxt_trans_edp = {
396 .entries = _bxt_trans_edp,
397 .num_entries = ARRAY_SIZE(_bxt_trans_edp),
398 };
399
400 /* BSpec has 2 recommended values - entries 0 and 8.
401 * Using the entry with higher vswing.
402 */
403 static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = {
404 /* Idx NT mV diff db */
405 { .bxt = { 52, 0x9A, 0, 128, } }, /* 0: 400 0 */
406 { .bxt = { 52, 0x9A, 0, 85, } }, /* 1: 400 3.5 */
407 { .bxt = { 52, 0x9A, 0, 64, } }, /* 2: 400 6 */
408 { .bxt = { 42, 0x9A, 0, 43, } }, /* 3: 400 9.5 */
409 { .bxt = { 77, 0x9A, 0, 128, } }, /* 4: 600 0 */
410 { .bxt = { 77, 0x9A, 0, 85, } }, /* 5: 600 3.5 */
411 { .bxt = { 77, 0x9A, 0, 64, } }, /* 6: 600 6 */
412 { .bxt = { 102, 0x9A, 0, 128, } }, /* 7: 800 0 */
413 { .bxt = { 102, 0x9A, 0, 85, } }, /* 8: 800 3.5 */
414 { .bxt = { 154, 0x9A, 1, 128, } }, /* 9: 1200 0 */
415 };
416
417 static const struct intel_ddi_buf_trans bxt_trans_hdmi = {
418 .entries = _bxt_trans_hdmi,
419 .num_entries = ARRAY_SIZE(_bxt_trans_hdmi),
420 .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
421 };
422
423 /* icl_combo_phy_trans */
424 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
425 /* NT mV Trans mV db */
426 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
427 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
428 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
429 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
430 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
431 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
432 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
433 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
434 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
435 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
436 };
437
438 static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = {
439 .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
440 .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
441 };
442
443 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = {
444 /* NT mV Trans mV db */
445 { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
446 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
447 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
448 { .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } }, /* 200 350 4.9 */
449 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
450 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
451 { .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
452 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
453 { .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
454 { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
455 };
456
457 static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = {
458 .entries = _icl_combo_phy_trans_edp_hbr2,
459 .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2),
460 };
461
462 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = {
463 /* NT mV Trans mV db */
464 { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } }, /* 450 450 0.0 */
465 { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } }, /* 450 650 3.2 */
466 { .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } }, /* 450 850 5.5 */
467 { .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } }, /* 650 650 0.0 ALS */
468 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 650 850 2.3 */
469 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 850 850 0.0 */
470 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 850 3.0 */
471 };
472
473 static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = {
474 .entries = _icl_combo_phy_trans_hdmi,
475 .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi),
476 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
477 };
478
479 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = {
480 /* NT mV Trans mV db */
481 { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
482 { .icl = { 0xA, 0x47, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
483 { .icl = { 0xC, 0x64, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
484 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 350 900 8.2 */
485 { .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
486 { .icl = { 0xC, 0x64, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
487 { .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
488 { .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
489 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
490 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
491 };
492
493 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = {
494 .entries = _ehl_combo_phy_trans_dp,
495 .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp),
496 };
497
498 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = {
499 /* NT mV Trans mV db */
500 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
501 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
502 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
503 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 200 350 4.9 */
504 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
505 { .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } }, /* 250 300 1.6 */
506 { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } }, /* 250 350 2.9 */
507 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
508 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
509 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
510 };
511
512 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = {
513 .entries = _ehl_combo_phy_trans_edp_hbr2,
514 .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2),
515 };
516
517 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = {
518 /* NT mV Trans mV db */
519 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
520 { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } }, /* 200 250 1.9 */
521 { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } }, /* 200 300 3.5 */
522 { .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } }, /* 200 350 4.9 */
523 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
524 { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
525 { .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } }, /* 250 350 2.9 */
526 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
527 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
528 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
529 };
530
531 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = {
532 .entries = _jsl_combo_phy_trans_edp_hbr,
533 .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr),
534 };
535
536 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = {
537 /* NT mV Trans mV db */
538 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 200 0.0 */
539 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 200 250 1.9 */
540 { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } }, /* 200 300 3.5 */
541 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 200 350 4.9 */
542 { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 250 0.0 */
543 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 250 300 1.6 */
544 { .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } }, /* 250 350 2.9 */
545 { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } }, /* 300 300 0.0 */
546 { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
547 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
548 };
549
550 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = {
551 .entries = _jsl_combo_phy_trans_edp_hbr2,
552 .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2),
553 };
554
555 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = {
556 /* NT mV Trans mV db */
557 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
558 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
559 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
560 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
561 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
562 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
563 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
564 { .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
565 { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } }, /* 600 900 3.5 */
566 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
567 };
568
569 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = {
570 .entries = _dg1_combo_phy_trans_dp_rbr_hbr,
571 .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr),
572 };
573
574 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = {
575 /* NT mV Trans mV db */
576 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
577 { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } }, /* 350 500 3.1 */
578 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
579 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
580 { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
581 { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
582 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
583 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
584 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
585 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
586 };
587
588 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = {
589 .entries = _dg1_combo_phy_trans_dp_hbr2_hbr3,
590 .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3),
591 };
592
593 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = {
594 /* Voltage swing pre-emphasis */
595 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */
596 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */
597 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */
598 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */
599 { .mg = { 0x21, 0x00, 0x00 } }, /* 1 0 */
600 { .mg = { 0x2B, 0x00, 0x08 } }, /* 1 1 */
601 { .mg = { 0x30, 0x00, 0x0F } }, /* 1 2 */
602 { .mg = { 0x31, 0x00, 0x03 } }, /* 2 0 */
603 { .mg = { 0x34, 0x00, 0x0B } }, /* 2 1 */
604 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */
605 };
606
607 static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = {
608 .entries = _icl_mg_phy_trans_rbr_hbr,
609 .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr),
610 };
611
612 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = {
613 /* Voltage swing pre-emphasis */
614 { .mg = { 0x18, 0x00, 0x00 } }, /* 0 0 */
615 { .mg = { 0x1D, 0x00, 0x05 } }, /* 0 1 */
616 { .mg = { 0x24, 0x00, 0x0C } }, /* 0 2 */
617 { .mg = { 0x2B, 0x00, 0x14 } }, /* 0 3 */
618 { .mg = { 0x26, 0x00, 0x00 } }, /* 1 0 */
619 { .mg = { 0x2C, 0x00, 0x07 } }, /* 1 1 */
620 { .mg = { 0x33, 0x00, 0x0C } }, /* 1 2 */
621 { .mg = { 0x2E, 0x00, 0x00 } }, /* 2 0 */
622 { .mg = { 0x36, 0x00, 0x09 } }, /* 2 1 */
623 { .mg = { 0x3F, 0x00, 0x00 } }, /* 3 0 */
624 };
625
626 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = {
627 .entries = _icl_mg_phy_trans_hbr2_hbr3,
628 .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3),
629 };
630
631 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = {
632 /* HDMI Preset VS Pre-emph */
633 { .mg = { 0x1A, 0x0, 0x0 } }, /* 1 400mV 0dB */
634 { .mg = { 0x20, 0x0, 0x0 } }, /* 2 500mV 0dB */
635 { .mg = { 0x29, 0x0, 0x0 } }, /* 3 650mV 0dB */
636 { .mg = { 0x32, 0x0, 0x0 } }, /* 4 800mV 0dB */
637 { .mg = { 0x3F, 0x0, 0x0 } }, /* 5 1000mV 0dB */
638 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
639 { .mg = { 0x39, 0x0, 0x6 } }, /* 7 Full -1.8 dB */
640 { .mg = { 0x38, 0x0, 0x7 } }, /* 8 Full -2 dB */
641 { .mg = { 0x37, 0x0, 0x8 } }, /* 9 Full -2.5 dB */
642 { .mg = { 0x36, 0x0, 0x9 } }, /* 10 Full -3 dB */
643 };
644
645 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = {
646 .entries = _icl_mg_phy_trans_hdmi,
647 .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi),
648 .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1,
649 };
650
651 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = {
652 /* VS pre-emp Non-trans mV Pre-emph dB */
653 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
654 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */
655 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
656 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */
657 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
658 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
659 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
660 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
661 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
662 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */
663 };
664
665 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = {
666 .entries = _tgl_dkl_phy_trans_dp_hbr,
667 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr),
668 };
669
670 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = {
671 /* VS pre-emp Non-trans mV Pre-emph dB */
672 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
673 { .dkl = { 0x5, 0x0, 0x05 } }, /* 0 1 400mV 3.5 dB */
674 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
675 { .dkl = { 0x0, 0x0, 0x19 } }, /* 0 3 400mV 9.5 dB */
676 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
677 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
678 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
679 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
680 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
681 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB HDMI default */
682 };
683
684 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = {
685 .entries = _tgl_dkl_phy_trans_dp_hbr2,
686 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2),
687 };
688
689 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = {
690 /* HDMI Preset VS Pre-emph */
691 { .dkl = { 0x7, 0x0, 0x0 } }, /* 1 400mV 0dB */
692 { .dkl = { 0x6, 0x0, 0x0 } }, /* 2 500mV 0dB */
693 { .dkl = { 0x4, 0x0, 0x0 } }, /* 3 650mV 0dB */
694 { .dkl = { 0x2, 0x0, 0x0 } }, /* 4 800mV 0dB */
695 { .dkl = { 0x0, 0x0, 0x0 } }, /* 5 1000mV 0dB */
696 { .dkl = { 0x0, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
697 { .dkl = { 0x0, 0x0, 0x6 } }, /* 7 Full -1.8 dB */
698 { .dkl = { 0x0, 0x0, 0x7 } }, /* 8 Full -2 dB */
699 { .dkl = { 0x0, 0x0, 0x8 } }, /* 9 Full -2.5 dB */
700 { .dkl = { 0x0, 0x0, 0xA } }, /* 10 Full -3 dB */
701 };
702
703 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = {
704 .entries = _tgl_dkl_phy_trans_hdmi,
705 .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi),
706 .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1,
707 };
708
709 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = {
710 /* NT mV Trans mV db */
711 { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
712 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
713 { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
714 { .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
715 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
716 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
717 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
718 { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
719 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
720 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
721 };
722
723 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = {
724 .entries = _tgl_combo_phy_trans_dp_hbr,
725 .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr),
726 };
727
728 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = {
729 /* NT mV Trans mV db */
730 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
731 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
732 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
733 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
734 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
735 { .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
736 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
737 { .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
738 { .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
739 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
740 };
741
742 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = {
743 .entries = _tgl_combo_phy_trans_dp_hbr2,
744 .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2),
745 };
746
747 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = {
748 /* NT mV Trans mV db */
749 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
750 { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } }, /* 350 500 3.1 */
751 { .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } }, /* 350 700 6.0 */
752 { .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } }, /* 350 900 8.2 */
753 { .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
754 { .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } }, /* 500 700 2.9 */
755 { .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
756 { .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
757 { .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } }, /* 600 900 3.5 */
758 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
759 };
760
761 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = {
762 .entries = _tgl_uy_combo_phy_trans_dp_hbr2,
763 .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2),
764 };
765
766 /*
767 * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
768 * that DisplayPort specification requires
769 */
770 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = {
771 /* VS pre-emp */
772 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 0 */
773 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 1 */
774 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 2 */
775 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 0 3 */
776 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 0 */
777 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 1 */
778 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 1 2 */
779 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 0 */
780 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 2 1 */
781 };
782
783 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = {
784 .entries = _tgl_combo_phy_trans_edp_hbr2_hobl,
785 .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl),
786 };
787
788 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = {
789 /* NT mV Trans mV db */
790 { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
791 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
792 { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } }, /* 350 700 6.0 */
793 { .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } }, /* 350 900 8.2 */
794 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
795 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
796 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
797 { .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } }, /* 650 700 0.6 */
798 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
799 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
800 };
801
802 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = {
803 .entries = _rkl_combo_phy_trans_dp_hbr,
804 .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr),
805 };
806
807 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = {
808 /* NT mV Trans mV db */
809 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
810 { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } }, /* 350 500 3.1 */
811 { .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } }, /* 350 700 6.0 */
812 { .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } }, /* 350 900 8.2 */
813 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
814 { .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } }, /* 500 700 2.9 */
815 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
816 { .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
817 { .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } }, /* 600 900 3.5 */
818 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
819 };
820
821 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = {
822 .entries = _rkl_combo_phy_trans_dp_hbr2_hbr3,
823 .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3),
824 };
825
826 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = {
827 /* NT mV Trans mV db */
828 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
829 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
830 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
831 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
832 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
833 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
834 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
835 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
836 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
837 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
838 };
839
840 static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = {
841 .entries = _adls_combo_phy_trans_dp_hbr2_hbr3,
842 .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3),
843 };
844
845 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = {
846 /* NT mV Trans mV db */
847 { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } }, /* 200 200 0.0 */
848 { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } }, /* 200 250 1.9 */
849 { .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } }, /* 200 300 3.5 */
850 { .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } }, /* 200 350 4.9 */
851 { .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } }, /* 250 250 0.0 */
852 { .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } }, /* 250 300 1.6 */
853 { .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } }, /* 250 350 2.9 */
854 { .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } }, /* 300 300 0.0 */
855 { .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } }, /* 300 350 1.3 */
856 { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } }, /* 350 350 0.0 */
857 };
858
859 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = {
860 .entries = _adls_combo_phy_trans_edp_hbr2,
861 .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2),
862 };
863
864 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = {
865 /* NT mV Trans mV db */
866 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
867 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
868 { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
869 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
870 { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
871 { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } }, /* 500 700 2.9 */
872 { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } }, /* 500 900 5.1 */
873 { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
874 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
875 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
876 };
877
878 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = {
879 .entries = _adls_combo_phy_trans_edp_hbr3,
880 .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3),
881 };
882
883 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = {
884 /* NT mV Trans mV db */
885 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
886 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
887 { .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } }, /* 350 700 6.0 */
888 { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } }, /* 350 900 8.2 */
889 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
890 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
891 { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500 900 5.1 */
892 { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } }, /* 650 700 0.6 */
893 { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600 900 3.5 */
894 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
895 };
896
897 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = {
898 .entries = _adlp_combo_phy_trans_dp_hbr,
899 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr),
900 };
901
902 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = {
903 /* NT mV Trans mV db */
904 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
905 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
906 { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } }, /* 350 700 6.0 */
907 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
908 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
909 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
910 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
911 { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
912 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
913 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
914 };
915
916 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_edp_hbr2[] = {
917 /* NT mV Trans mV db */
918 { .icl = { 0x4, 0x50, 0x38, 0x00, 0x07 } }, /* 200 200 0.0 */
919 { .icl = { 0x4, 0x58, 0x35, 0x00, 0x0A } }, /* 200 250 1.9 */
920 { .icl = { 0x4, 0x60, 0x34, 0x00, 0x0B } }, /* 200 300 3.5 */
921 { .icl = { 0x4, 0x6A, 0x32, 0x00, 0x0D } }, /* 200 350 4.9 */
922 { .icl = { 0x4, 0x5E, 0x38, 0x00, 0x07 } }, /* 250 250 0.0 */
923 { .icl = { 0x4, 0x61, 0x36, 0x00, 0x09 } }, /* 250 300 1.6 */
924 { .icl = { 0x4, 0x6B, 0x34, 0x00, 0x0B } }, /* 250 350 2.9 */
925 { .icl = { 0x4, 0x69, 0x39, 0x00, 0x06 } }, /* 300 300 0.0 */
926 { .icl = { 0x4, 0x73, 0x37, 0x00, 0x08 } }, /* 300 350 1.3 */
927 { .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } }, /* 350 350 0.0 */
928 };
929
930 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
931 /* NT mV Trans mV db */
932 { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350 350 0.0 */
933 { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350 500 3.1 */
934 { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } }, /* 350 700 6.0 */
935 { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350 900 8.2 */
936 { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500 500 0.0 */
937 { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500 700 2.9 */
938 { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } }, /* 500 900 5.1 */
939 { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } }, /* 650 700 0.6 */
940 { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } }, /* 600 900 3.5 */
941 { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900 900 0.0 */
942 };
943
944 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
945 .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
946 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
947 };
948
949 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
950 .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
951 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
952 };
953
954 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
955 .entries = _adlp_combo_phy_trans_edp_hbr2,
956 .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_edp_hbr2),
957 };
958
959 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = {
960 /* VS pre-emp Non-trans mV Pre-emph dB */
961 { .dkl = { 0x7, 0x0, 0x01 } }, /* 0 0 400mV 0 dB */
962 { .dkl = { 0x5, 0x0, 0x06 } }, /* 0 1 400mV 3.5 dB */
963 { .dkl = { 0x2, 0x0, 0x0B } }, /* 0 2 400mV 6 dB */
964 { .dkl = { 0x0, 0x0, 0x17 } }, /* 0 3 400mV 9.5 dB */
965 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
966 { .dkl = { 0x2, 0x0, 0x08 } }, /* 1 1 600mV 3.5 dB */
967 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
968 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
969 { .dkl = { 0x0, 0x0, 0x0B } }, /* 2 1 800mV 3.5 dB */
970 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */
971 };
972
973 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = {
974 .entries = _adlp_dkl_phy_trans_dp_hbr,
975 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr),
976 };
977
978 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = {
979 /* VS pre-emp Non-trans mV Pre-emph dB */
980 { .dkl = { 0x7, 0x0, 0x00 } }, /* 0 0 400mV 0 dB */
981 { .dkl = { 0x5, 0x0, 0x04 } }, /* 0 1 400mV 3.5 dB */
982 { .dkl = { 0x2, 0x0, 0x0A } }, /* 0 2 400mV 6 dB */
983 { .dkl = { 0x0, 0x0, 0x18 } }, /* 0 3 400mV 9.5 dB */
984 { .dkl = { 0x5, 0x0, 0x00 } }, /* 1 0 600mV 0 dB */
985 { .dkl = { 0x2, 0x0, 0x06 } }, /* 1 1 600mV 3.5 dB */
986 { .dkl = { 0x0, 0x0, 0x14 } }, /* 1 2 600mV 6 dB */
987 { .dkl = { 0x2, 0x0, 0x00 } }, /* 2 0 800mV 0 dB */
988 { .dkl = { 0x0, 0x0, 0x09 } }, /* 2 1 800mV 3.5 dB */
989 { .dkl = { 0x0, 0x0, 0x00 } }, /* 3 0 1200mV 0 dB */
990 };
991
992 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = {
993 .entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3,
994 .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3),
995 };
996
997 static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
998 { .snps = { 25, 0, 0 } }, /* VS 0, pre-emph 0 */
999 { .snps = { 32, 0, 6 } }, /* VS 0, pre-emph 1 */
1000 { .snps = { 35, 0, 10 } }, /* VS 0, pre-emph 2 */
1001 { .snps = { 43, 0, 17 } }, /* VS 0, pre-emph 3 */
1002 { .snps = { 35, 0, 0 } }, /* VS 1, pre-emph 0 */
1003 { .snps = { 45, 0, 8 } }, /* VS 1, pre-emph 1 */
1004 { .snps = { 48, 0, 14 } }, /* VS 1, pre-emph 2 */
1005 { .snps = { 47, 0, 0 } }, /* VS 2, pre-emph 0 */
1006 { .snps = { 55, 0, 7 } }, /* VS 2, pre-emph 1 */
1007 { .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */
1008 };
1009
1010 static const struct intel_ddi_buf_trans dg2_snps_trans = {
1011 .entries = _dg2_snps_trans,
1012 .num_entries = ARRAY_SIZE(_dg2_snps_trans),
1013 .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1,
1014 };
1015
1016 static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
1017 { .snps = { 62, 0, 0 } }, /* preset 0 */
1018 { .snps = { 55, 0, 7 } }, /* preset 1 */
1019 { .snps = { 50, 0, 12 } }, /* preset 2 */
1020 { .snps = { 44, 0, 18 } }, /* preset 3 */
1021 { .snps = { 35, 0, 21 } }, /* preset 4 */
1022 { .snps = { 59, 3, 0 } }, /* preset 5 */
1023 { .snps = { 53, 3, 6 } }, /* preset 6 */
1024 { .snps = { 48, 3, 11 } }, /* preset 7 */
1025 { .snps = { 42, 5, 15 } }, /* preset 8 */
1026 { .snps = { 37, 5, 20 } }, /* preset 9 */
1027 { .snps = { 56, 6, 0 } }, /* preset 10 */
1028 { .snps = { 48, 7, 7 } }, /* preset 11 */
1029 { .snps = { 45, 7, 10 } }, /* preset 12 */
1030 { .snps = { 39, 8, 15 } }, /* preset 13 */
1031 { .snps = { 48, 14, 0 } }, /* preset 14 */
1032 { .snps = { 45, 4, 4 } }, /* preset 15 */
1033 };
1034
1035 static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
1036 .entries = _dg2_snps_trans_uhbr,
1037 .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
1038 };
1039
1040 static const union intel_ddi_buf_trans_entry _mtl_c10_trans_dp14[] = {
1041 { .snps = { 26, 0, 0 } }, /* preset 0 */
1042 { .snps = { 33, 0, 6 } }, /* preset 1 */
1043 { .snps = { 38, 0, 11 } }, /* preset 2 */
1044 { .snps = { 43, 0, 19 } }, /* preset 3 */
1045 { .snps = { 39, 0, 0 } }, /* preset 4 */
1046 { .snps = { 45, 0, 7 } }, /* preset 5 */
1047 { .snps = { 46, 0, 13 } }, /* preset 6 */
1048 { .snps = { 46, 0, 0 } }, /* preset 7 */
1049 { .snps = { 55, 0, 7 } }, /* preset 8 */
1050 { .snps = { 62, 0, 0 } }, /* preset 9 */
1051 };
1052
1053 static const struct intel_ddi_buf_trans mtl_c10_trans_dp14 = {
1054 .entries = _mtl_c10_trans_dp14,
1055 .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14),
1056 .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
1057 };
1058
1059 /* DP1.4 */
1060 static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = {
1061 { .snps = { 20, 0, 0 } }, /* preset 0 */
1062 { .snps = { 24, 0, 4 } }, /* preset 1 */
1063 { .snps = { 30, 0, 9 } }, /* preset 2 */
1064 { .snps = { 34, 0, 14 } }, /* preset 3 */
1065 { .snps = { 29, 0, 0 } }, /* preset 4 */
1066 { .snps = { 34, 0, 5 } }, /* preset 5 */
1067 { .snps = { 38, 0, 10 } }, /* preset 6 */
1068 { .snps = { 36, 0, 0 } }, /* preset 7 */
1069 { .snps = { 40, 0, 6 } }, /* preset 8 */
1070 { .snps = { 48, 0, 0 } }, /* preset 9 */
1071 };
1072
1073 /* DP2.0 */
1074 static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
1075 { .snps = { 48, 0, 0 } }, /* preset 0 */
1076 { .snps = { 43, 0, 5 } }, /* preset 1 */
1077 { .snps = { 40, 0, 8 } }, /* preset 2 */
1078 { .snps = { 37, 0, 11 } }, /* preset 3 */
1079 { .snps = { 33, 0, 15 } }, /* preset 4 */
1080 { .snps = { 46, 2, 0 } }, /* preset 5 */
1081 { .snps = { 42, 2, 4 } }, /* preset 6 */
1082 { .snps = { 38, 2, 8 } }, /* preset 7 */
1083 { .snps = { 35, 2, 11 } }, /* preset 8 */
1084 { .snps = { 33, 2, 13 } }, /* preset 9 */
1085 { .snps = { 44, 4, 0 } }, /* preset 10 */
1086 { .snps = { 40, 4, 4 } }, /* preset 11 */
1087 { .snps = { 37, 4, 7 } }, /* preset 12 */
1088 { .snps = { 33, 4, 11 } }, /* preset 13 */
1089 { .snps = { 40, 8, 0 } }, /* preset 14 */
1090 { .snps = { 30, 2, 2 } }, /* preset 15 */
1091 };
1092
1093 /* HDMI2.0 */
1094 static const union intel_ddi_buf_trans_entry _mtl_c20_trans_hdmi[] = {
1095 { .snps = { 48, 0, 0 } }, /* preset 0 */
1096 { .snps = { 38, 4, 6 } }, /* preset 1 */
1097 { .snps = { 36, 4, 8 } }, /* preset 2 */
1098 { .snps = { 34, 4, 10 } }, /* preset 3 */
1099 { .snps = { 32, 4, 12 } }, /* preset 4 */
1100 };
1101
1102 static const struct intel_ddi_buf_trans mtl_c20_trans_hdmi = {
1103 .entries = _mtl_c20_trans_hdmi,
1104 .num_entries = ARRAY_SIZE(_mtl_c20_trans_hdmi),
1105 .hdmi_default_entry = 0,
1106 };
1107
1108 static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = {
1109 .entries = _mtl_c20_trans_dp14,
1110 .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14),
1111 .hdmi_default_entry = ARRAY_SIZE(_mtl_c20_trans_dp14) - 1,
1112 };
1113
1114 static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
1115 .entries = _mtl_c20_trans_uhbr,
1116 .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
1117 };
1118
1119 /* DP1.4 */
1120 static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_dp14[] = {
1121 { .lt = { 1, 0, 0, 21, 0 } },
1122 { .lt = { 1, 1, 0, 24, 3 } },
1123 { .lt = { 1, 2, 0, 28, 7 } },
1124 { .lt = { 0, 3, 0, 35, 13 } },
1125 { .lt = { 1, 1, 0, 27, 0 } },
1126 { .lt = { 1, 2, 0, 31, 4 } },
1127 { .lt = { 0, 3, 0, 39, 9 } },
1128 { .lt = { 1, 2, 0, 35, 0 } },
1129 { .lt = { 0, 3, 0, 41, 7 } },
1130 { .lt = { 0, 3, 0, 48, 0 } },
1131 };
1132
1133 /* DP2.1 */
1134 static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_uhbr[] = {
1135 { .lt = { 0, 0, 0, 48, 0 } },
1136 { .lt = { 0, 0, 0, 43, 5 } },
1137 { .lt = { 0, 0, 0, 40, 8 } },
1138 { .lt = { 0, 0, 0, 37, 11 } },
1139 { .lt = { 0, 0, 0, 33, 15 } },
1140 { .lt = { 0, 0, 2, 46, 0 } },
1141 { .lt = { 0, 0, 2, 42, 4 } },
1142 { .lt = { 0, 0, 2, 38, 8 } },
1143 { .lt = { 0, 0, 2, 35, 11 } },
1144 { .lt = { 0, 0, 2, 33, 13 } },
1145 { .lt = { 0, 0, 4, 44, 0 } },
1146 { .lt = { 0, 0, 4, 40, 4 } },
1147 { .lt = { 0, 0, 4, 37, 7 } },
1148 { .lt = { 0, 0, 4, 33, 11 } },
1149 { .lt = { 0, 0, 8, 40, 0 } },
1150 { .lt = { 1, 0, 2, 26, 2 } },
1151 };
1152
1153 /* eDp */
1154 static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
1155 { .lt = { 1, 0, 0, 12, 0 } },
1156 { .lt = { 1, 1, 0, 13, 1 } },
1157 { .lt = { 1, 2, 0, 15, 3 } },
1158 { .lt = { 1, 3, 0, 19, 7 } },
1159 { .lt = { 1, 1, 0, 14, 0 } },
1160 { .lt = { 1, 2, 0, 16, 2 } },
1161 { .lt = { 1, 3, 0, 21, 5 } },
1162 { .lt = { 1, 2, 0, 18, 0 } },
1163 { .lt = { 1, 3, 0, 22, 4 } },
1164 { .lt = { 1, 3, 0, 26, 0 } },
1165 };
1166
1167 static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
1168 .entries = _xe3plpd_lt_trans_dp14,
1169 .num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
1170 };
1171
1172 static const struct intel_ddi_buf_trans xe3plpd_lt_trans_uhbr = {
1173 .entries = _xe3plpd_lt_trans_uhbr,
1174 .num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_uhbr),
1175 };
1176
1177 static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
1178 .entries = _xe3plpd_lt_trans_edp,
1179 .num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
1180 };
1181
is_hobl_buf_trans(const struct intel_ddi_buf_trans * table)1182 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
1183 {
1184 return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
1185 }
1186
use_edp_hobl(struct intel_encoder * encoder)1187 static bool use_edp_hobl(struct intel_encoder *encoder)
1188 {
1189 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1190 struct intel_connector *connector = intel_dp->attached_connector;
1191
1192 return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;
1193 }
1194
use_edp_low_vswing(struct intel_encoder * encoder)1195 static bool use_edp_low_vswing(struct intel_encoder *encoder)
1196 {
1197 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1198 struct intel_connector *connector = intel_dp->attached_connector;
1199
1200 return connector->panel.vbt.edp.low_vswing;
1201 }
1202
1203 static const struct intel_ddi_buf_trans *
intel_get_buf_trans(const struct intel_ddi_buf_trans * trans,int * num_entries)1204 intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries)
1205 {
1206 *num_entries = trans->num_entries;
1207 return trans;
1208 }
1209
1210 static const struct intel_ddi_buf_trans *
hsw_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1211 hsw_get_buf_trans(struct intel_encoder *encoder,
1212 const struct intel_crtc_state *crtc_state,
1213 int *n_entries)
1214 {
1215 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1216 return intel_get_buf_trans(&hsw_trans_fdi, n_entries);
1217 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1218 return intel_get_buf_trans(&hsw_trans_hdmi, n_entries);
1219 else
1220 return intel_get_buf_trans(&hsw_trans_dp, n_entries);
1221 }
1222
1223 static const struct intel_ddi_buf_trans *
bdw_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1224 bdw_get_buf_trans(struct intel_encoder *encoder,
1225 const struct intel_crtc_state *crtc_state,
1226 int *n_entries)
1227 {
1228 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1229 return intel_get_buf_trans(&bdw_trans_fdi, n_entries);
1230 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1231 return intel_get_buf_trans(&bdw_trans_hdmi, n_entries);
1232 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1233 use_edp_low_vswing(encoder))
1234 return intel_get_buf_trans(&bdw_trans_edp, n_entries);
1235 else
1236 return intel_get_buf_trans(&bdw_trans_dp, n_entries);
1237 }
1238
skl_buf_trans_num_entries(enum port port,int n_entries)1239 static int skl_buf_trans_num_entries(enum port port, int n_entries)
1240 {
1241 /* Only DDIA and DDIE can select the 10th register with DP */
1242 if (port == PORT_A || port == PORT_E)
1243 return min(n_entries, 10);
1244 else
1245 return min(n_entries, 9);
1246 }
1247
1248 static const struct intel_ddi_buf_trans *
_skl_get_buf_trans_dp(struct intel_encoder * encoder,const struct intel_ddi_buf_trans * trans,int * n_entries)1249 _skl_get_buf_trans_dp(struct intel_encoder *encoder,
1250 const struct intel_ddi_buf_trans *trans,
1251 int *n_entries)
1252 {
1253 trans = intel_get_buf_trans(trans, n_entries);
1254 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
1255 return trans;
1256 }
1257
1258 static const struct intel_ddi_buf_trans *
skl_y_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1259 skl_y_get_buf_trans(struct intel_encoder *encoder,
1260 const struct intel_crtc_state *crtc_state,
1261 int *n_entries)
1262 {
1263 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1264 return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1265 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1266 use_edp_low_vswing(encoder))
1267 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1268 else
1269 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries);
1270 }
1271
1272 static const struct intel_ddi_buf_trans *
skl_u_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1273 skl_u_get_buf_trans(struct intel_encoder *encoder,
1274 const struct intel_crtc_state *crtc_state,
1275 int *n_entries)
1276 {
1277 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1278 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1279 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1280 use_edp_low_vswing(encoder))
1281 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1282 else
1283 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries);
1284 }
1285
1286 static const struct intel_ddi_buf_trans *
skl_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1287 skl_get_buf_trans(struct intel_encoder *encoder,
1288 const struct intel_crtc_state *crtc_state,
1289 int *n_entries)
1290 {
1291 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1292 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1293 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1294 use_edp_low_vswing(encoder))
1295 return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1296 else
1297 return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries);
1298 }
1299
1300 static const struct intel_ddi_buf_trans *
kbl_y_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1301 kbl_y_get_buf_trans(struct intel_encoder *encoder,
1302 const struct intel_crtc_state *crtc_state,
1303 int *n_entries)
1304 {
1305 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1306 return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1307 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1308 use_edp_low_vswing(encoder))
1309 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1310 else
1311 return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries);
1312 }
1313
1314 static const struct intel_ddi_buf_trans *
kbl_u_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1315 kbl_u_get_buf_trans(struct intel_encoder *encoder,
1316 const struct intel_crtc_state *crtc_state,
1317 int *n_entries)
1318 {
1319 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1320 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1321 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1322 use_edp_low_vswing(encoder))
1323 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1324 else
1325 return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries);
1326 }
1327
1328 static const struct intel_ddi_buf_trans *
kbl_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1329 kbl_get_buf_trans(struct intel_encoder *encoder,
1330 const struct intel_crtc_state *crtc_state,
1331 int *n_entries)
1332 {
1333 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1334 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1335 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1336 use_edp_low_vswing(encoder))
1337 return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1338 else
1339 return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries);
1340 }
1341
1342 static const struct intel_ddi_buf_trans *
bxt_get_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1343 bxt_get_buf_trans(struct intel_encoder *encoder,
1344 const struct intel_crtc_state *crtc_state,
1345 int *n_entries)
1346 {
1347 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1348 return intel_get_buf_trans(&bxt_trans_hdmi, n_entries);
1349 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1350 use_edp_low_vswing(encoder))
1351 return intel_get_buf_trans(&bxt_trans_edp, n_entries);
1352 else
1353 return intel_get_buf_trans(&bxt_trans_dp, n_entries);
1354 }
1355
1356 static const struct intel_ddi_buf_trans *
icl_get_combo_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1357 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1358 const struct intel_crtc_state *crtc_state,
1359 int *n_entries)
1360 {
1361 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1362 n_entries);
1363 }
1364
1365 static const struct intel_ddi_buf_trans *
icl_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1366 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1367 const struct intel_crtc_state *crtc_state,
1368 int *n_entries)
1369 {
1370 if (crtc_state->port_clock > 540000) {
1371 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1372 n_entries);
1373 } else if (use_edp_low_vswing(encoder)) {
1374 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1375 n_entries);
1376 }
1377
1378 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1379 }
1380
1381 static const struct intel_ddi_buf_trans *
icl_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1382 icl_get_combo_buf_trans(struct intel_encoder *encoder,
1383 const struct intel_crtc_state *crtc_state,
1384 int *n_entries)
1385 {
1386 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1387 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1388 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1389 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1390 else
1391 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1392 }
1393
1394 static const struct intel_ddi_buf_trans *
icl_get_mg_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1395 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1396 const struct intel_crtc_state *crtc_state,
1397 int *n_entries)
1398 {
1399 if (crtc_state->port_clock > 270000) {
1400 return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3,
1401 n_entries);
1402 } else {
1403 return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr,
1404 n_entries);
1405 }
1406 }
1407
1408 static const struct intel_ddi_buf_trans *
icl_get_mg_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1409 icl_get_mg_buf_trans(struct intel_encoder *encoder,
1410 const struct intel_crtc_state *crtc_state,
1411 int *n_entries)
1412 {
1413 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1414 return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries);
1415 else
1416 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1417 }
1418
1419 static const struct intel_ddi_buf_trans *
ehl_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1420 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1421 const struct intel_crtc_state *crtc_state,
1422 int *n_entries)
1423 {
1424 if (crtc_state->port_clock > 270000)
1425 return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries);
1426 else
1427 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries);
1428 }
1429
1430 static const struct intel_ddi_buf_trans *
ehl_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1431 ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1432 const struct intel_crtc_state *crtc_state,
1433 int *n_entries)
1434 {
1435 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1436 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1437 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1438 use_edp_low_vswing(encoder))
1439 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1440 else
1441 return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries);
1442 }
1443
1444 static const struct intel_ddi_buf_trans *
jsl_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1445 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1446 const struct intel_crtc_state *crtc_state,
1447 int *n_entries)
1448 {
1449 if (crtc_state->port_clock > 270000)
1450 return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries);
1451 else
1452 return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries);
1453 }
1454
1455 static const struct intel_ddi_buf_trans *
jsl_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1456 jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1457 const struct intel_crtc_state *crtc_state,
1458 int *n_entries)
1459 {
1460 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1461 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1462 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1463 use_edp_low_vswing(encoder))
1464 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1465 else
1466 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries);
1467 }
1468
1469 static const struct intel_ddi_buf_trans *
tgl_get_combo_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1470 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1471 const struct intel_crtc_state *crtc_state,
1472 int *n_entries)
1473 {
1474 struct intel_display *display = to_intel_display(encoder);
1475
1476 if (crtc_state->port_clock > 270000) {
1477 if (display->platform.tigerlake_uy) {
1478 return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
1479 n_entries);
1480 } else {
1481 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2,
1482 n_entries);
1483 }
1484 } else {
1485 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr,
1486 n_entries);
1487 }
1488 }
1489
1490 static const struct intel_ddi_buf_trans *
tgl_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1491 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1492 const struct intel_crtc_state *crtc_state,
1493 int *n_entries)
1494 {
1495 if (crtc_state->port_clock > 540000) {
1496 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1497 n_entries);
1498 } else if (use_edp_hobl(encoder)) {
1499 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1500 n_entries);
1501 } else if (use_edp_low_vswing(encoder)) {
1502 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1503 n_entries);
1504 }
1505
1506 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1507 }
1508
1509 static const struct intel_ddi_buf_trans *
tgl_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1510 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1511 const struct intel_crtc_state *crtc_state,
1512 int *n_entries)
1513 {
1514 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1515 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1516 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1517 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1518 else
1519 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1520 }
1521
1522 static const struct intel_ddi_buf_trans *
dg1_get_combo_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1523 dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1524 const struct intel_crtc_state *crtc_state,
1525 int *n_entries)
1526 {
1527 if (crtc_state->port_clock > 270000)
1528 return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3,
1529 n_entries);
1530 else
1531 return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr,
1532 n_entries);
1533 }
1534
1535 static const struct intel_ddi_buf_trans *
dg1_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1536 dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1537 const struct intel_crtc_state *crtc_state,
1538 int *n_entries)
1539 {
1540 if (crtc_state->port_clock > 540000)
1541 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1542 n_entries);
1543 else if (use_edp_hobl(encoder))
1544 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1545 n_entries);
1546 else if (use_edp_low_vswing(encoder))
1547 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1548 n_entries);
1549 else
1550 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1551 }
1552
1553 static const struct intel_ddi_buf_trans *
dg1_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1554 dg1_get_combo_buf_trans(struct intel_encoder *encoder,
1555 const struct intel_crtc_state *crtc_state,
1556 int *n_entries)
1557 {
1558 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1559 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1560 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1561 return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1562 else
1563 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1564 }
1565
1566 static const struct intel_ddi_buf_trans *
rkl_get_combo_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1567 rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1568 const struct intel_crtc_state *crtc_state,
1569 int *n_entries)
1570 {
1571 if (crtc_state->port_clock > 270000)
1572 return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1573 else
1574 return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries);
1575 }
1576
1577 static const struct intel_ddi_buf_trans *
rkl_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1578 rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1579 const struct intel_crtc_state *crtc_state,
1580 int *n_entries)
1581 {
1582 if (crtc_state->port_clock > 540000) {
1583 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1584 n_entries);
1585 } else if (use_edp_hobl(encoder)) {
1586 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1587 n_entries);
1588 } else if (use_edp_low_vswing(encoder)) {
1589 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1590 n_entries);
1591 }
1592
1593 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1594 }
1595
1596 static const struct intel_ddi_buf_trans *
rkl_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1597 rkl_get_combo_buf_trans(struct intel_encoder *encoder,
1598 const struct intel_crtc_state *crtc_state,
1599 int *n_entries)
1600 {
1601 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1602 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1603 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1604 return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1605 else
1606 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1607 }
1608
1609 static const struct intel_ddi_buf_trans *
adls_get_combo_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1610 adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1611 const struct intel_crtc_state *crtc_state,
1612 int *n_entries)
1613 {
1614 if (crtc_state->port_clock > 270000)
1615 return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1616 else
1617 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries);
1618 }
1619
1620 static const struct intel_ddi_buf_trans *
adls_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1621 adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1622 const struct intel_crtc_state *crtc_state,
1623 int *n_entries)
1624 {
1625 if (crtc_state->port_clock > 540000)
1626 return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries);
1627 else if (use_edp_hobl(encoder))
1628 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries);
1629 else if (use_edp_low_vswing(encoder))
1630 return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries);
1631 else
1632 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1633 }
1634
1635 static const struct intel_ddi_buf_trans *
adls_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1636 adls_get_combo_buf_trans(struct intel_encoder *encoder,
1637 const struct intel_crtc_state *crtc_state,
1638 int *n_entries)
1639 {
1640 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1641 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1642 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1643 return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1644 else
1645 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1646 }
1647
1648 static const struct intel_ddi_buf_trans *
adlp_get_combo_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1649 adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1650 const struct intel_crtc_state *crtc_state,
1651 int *n_entries)
1652 {
1653 if (crtc_state->port_clock > 270000)
1654 return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1655 else
1656 return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries);
1657 }
1658
1659 static const struct intel_ddi_buf_trans *
adlp_get_combo_buf_trans_edp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1660 adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1661 const struct intel_crtc_state *crtc_state,
1662 int *n_entries)
1663 {
1664 if (crtc_state->port_clock > 540000) {
1665 return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3,
1666 n_entries);
1667 } else if (use_edp_hobl(encoder)) {
1668 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1669 n_entries);
1670 } else if (use_edp_low_vswing(encoder)) {
1671 return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2,
1672 n_entries);
1673 }
1674
1675 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1676 }
1677
1678 static const struct intel_ddi_buf_trans *
adlp_get_combo_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1679 adlp_get_combo_buf_trans(struct intel_encoder *encoder,
1680 const struct intel_crtc_state *crtc_state,
1681 int *n_entries)
1682 {
1683 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1684 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1685 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1686 return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1687 else
1688 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1689 }
1690
1691 static const struct intel_ddi_buf_trans *
tgl_get_dkl_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1692 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1693 const struct intel_crtc_state *crtc_state,
1694 int *n_entries)
1695 {
1696 if (crtc_state->port_clock > 270000) {
1697 return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2,
1698 n_entries);
1699 } else {
1700 return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr,
1701 n_entries);
1702 }
1703 }
1704
1705 static const struct intel_ddi_buf_trans *
tgl_get_dkl_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1706 tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1707 const struct intel_crtc_state *crtc_state,
1708 int *n_entries)
1709 {
1710 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1711 return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1712 else
1713 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1714 }
1715
1716 static const struct intel_ddi_buf_trans *
adlp_get_dkl_buf_trans_dp(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1717 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1718 const struct intel_crtc_state *crtc_state,
1719 int *n_entries)
1720 {
1721 if (crtc_state->port_clock > 270000) {
1722 return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3,
1723 n_entries);
1724 } else {
1725 return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr,
1726 n_entries);
1727 }
1728 }
1729
1730 static const struct intel_ddi_buf_trans *
adlp_get_dkl_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1731 adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1732 const struct intel_crtc_state *crtc_state,
1733 int *n_entries)
1734 {
1735 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1736 return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1737 else
1738 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1739 }
1740
1741 static const struct intel_ddi_buf_trans *
dg2_get_snps_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1742 dg2_get_snps_buf_trans(struct intel_encoder *encoder,
1743 const struct intel_crtc_state *crtc_state,
1744 int *n_entries)
1745 {
1746 if (intel_crtc_has_dp_encoder(crtc_state) &&
1747 intel_dp_is_uhbr(crtc_state))
1748 return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
1749 else
1750 return intel_get_buf_trans(&dg2_snps_trans, n_entries);
1751 }
1752
1753 static const struct intel_ddi_buf_trans *
mtl_get_c10_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1754 mtl_get_c10_buf_trans(struct intel_encoder *encoder,
1755 const struct intel_crtc_state *crtc_state,
1756 int *n_entries)
1757 {
1758 return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries);
1759 }
1760
1761 static const struct intel_ddi_buf_trans *
mtl_get_c20_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1762 mtl_get_c20_buf_trans(struct intel_encoder *encoder,
1763 const struct intel_crtc_state *crtc_state,
1764 int *n_entries)
1765 {
1766 if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
1767 return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
1768 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1769 return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
1770 else
1771 return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries);
1772 }
1773
1774 static const struct intel_ddi_buf_trans *
xe3plpd_get_lt_buf_trans(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,int * n_entries)1775 xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
1776 const struct intel_crtc_state *crtc_state,
1777 int *n_entries)
1778 {
1779 if (intel_crtc_has_dp_encoder(crtc_state) && intel_dp_is_uhbr(crtc_state))
1780 return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
1781 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1782 return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
1783 else
1784 return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
1785 }
1786
intel_ddi_buf_trans_init(struct intel_encoder * encoder)1787 void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
1788 {
1789 struct intel_display *display = to_intel_display(encoder);
1790
1791 if (HAS_LT_PHY(display)) {
1792 encoder->get_buf_trans = xe3plpd_get_lt_buf_trans;
1793 } else if (DISPLAY_VER(display) >= 14) {
1794 if (intel_encoder_is_c10phy(encoder))
1795 encoder->get_buf_trans = mtl_get_c10_buf_trans;
1796 else
1797 encoder->get_buf_trans = mtl_get_c20_buf_trans;
1798 } else if (display->platform.dg2) {
1799 encoder->get_buf_trans = dg2_get_snps_buf_trans;
1800 } else if (display->platform.alderlake_p) {
1801 if (intel_encoder_is_combo(encoder))
1802 encoder->get_buf_trans = adlp_get_combo_buf_trans;
1803 else
1804 encoder->get_buf_trans = adlp_get_dkl_buf_trans;
1805 } else if (display->platform.alderlake_s) {
1806 encoder->get_buf_trans = adls_get_combo_buf_trans;
1807 } else if (display->platform.rocketlake) {
1808 encoder->get_buf_trans = rkl_get_combo_buf_trans;
1809 } else if (display->platform.dg1) {
1810 encoder->get_buf_trans = dg1_get_combo_buf_trans;
1811 } else if (DISPLAY_VER(display) >= 12) {
1812 if (intel_encoder_is_combo(encoder))
1813 encoder->get_buf_trans = tgl_get_combo_buf_trans;
1814 else
1815 encoder->get_buf_trans = tgl_get_dkl_buf_trans;
1816 } else if (DISPLAY_VER(display) == 11) {
1817 if (display->platform.jasperlake)
1818 encoder->get_buf_trans = jsl_get_combo_buf_trans;
1819 else if (display->platform.elkhartlake)
1820 encoder->get_buf_trans = ehl_get_combo_buf_trans;
1821 else if (intel_encoder_is_combo(encoder))
1822 encoder->get_buf_trans = icl_get_combo_buf_trans;
1823 else
1824 encoder->get_buf_trans = icl_get_mg_buf_trans;
1825 } else if (display->platform.geminilake || display->platform.broxton) {
1826 encoder->get_buf_trans = bxt_get_buf_trans;
1827 } else if (display->platform.cometlake_ulx ||
1828 display->platform.coffeelake_ulx ||
1829 display->platform.kabylake_ulx) {
1830 encoder->get_buf_trans = kbl_y_get_buf_trans;
1831 } else if (display->platform.cometlake_ult ||
1832 display->platform.coffeelake_ult ||
1833 display->platform.kabylake_ult) {
1834 encoder->get_buf_trans = kbl_u_get_buf_trans;
1835 } else if (display->platform.cometlake ||
1836 display->platform.coffeelake ||
1837 display->platform.kabylake) {
1838 encoder->get_buf_trans = kbl_get_buf_trans;
1839 } else if (display->platform.skylake_ulx) {
1840 encoder->get_buf_trans = skl_y_get_buf_trans;
1841 } else if (display->platform.skylake_ult) {
1842 encoder->get_buf_trans = skl_u_get_buf_trans;
1843 } else if (display->platform.skylake) {
1844 encoder->get_buf_trans = skl_get_buf_trans;
1845 } else if (display->platform.broadwell) {
1846 encoder->get_buf_trans = bdw_get_buf_trans;
1847 } else if (display->platform.haswell) {
1848 encoder->get_buf_trans = hsw_get_buf_trans;
1849 } else {
1850 struct pci_dev *pdev = to_pci_dev(display->drm->dev);
1851
1852 MISSING_CASE(pdev->device);
1853 }
1854 }
1855