1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_
4 #define _ICP_QAT_FW_INIT_ADMIN_H_
5 
6 #include "icp_qat_fw.h"
7 
8 #define RL_MAX_RP_IDS 16
9 
10 enum icp_qat_fw_init_admin_cmd_id {
11 	ICP_QAT_FW_INIT_AE = 0,
12 	ICP_QAT_FW_TRNG_ENABLE = 1,
13 	ICP_QAT_FW_TRNG_DISABLE = 2,
14 	ICP_QAT_FW_CONSTANTS_CFG = 3,
15 	ICP_QAT_FW_STATUS_GET = 4,
16 	ICP_QAT_FW_COUNTERS_GET = 5,
17 	ICP_QAT_FW_LOOPBACK = 6,
18 	ICP_QAT_FW_HEARTBEAT_SYNC = 7,
19 	ICP_QAT_FW_HEARTBEAT_GET = 8,
20 	ICP_QAT_FW_COMP_CAPABILITY_GET = 9,
21 	ICP_QAT_FW_CRYPTO_CAPABILITY_GET = 10,
22 	ICP_QAT_FW_DC_CHAIN_INIT = 11,
23 	ICP_QAT_FW_HEARTBEAT_TIMER_SET = 13,
24 	ICP_QAT_FW_RL_INIT = 15,
25 	ICP_QAT_FW_TIMER_GET = 19,
26 	ICP_QAT_FW_CNV_STATS_GET = 20,
27 	ICP_QAT_FW_PM_STATE_CONFIG = 128,
28 	ICP_QAT_FW_PM_INFO = 129,
29 	ICP_QAT_FW_RL_ADD = 134,
30 	ICP_QAT_FW_RL_UPDATE = 135,
31 	ICP_QAT_FW_RL_REMOVE = 136,
32 	ICP_QAT_FW_TL_START = 137,
33 	ICP_QAT_FW_TL_STOP = 138,
34 };
35 
36 enum icp_qat_fw_init_admin_resp_status {
37 	ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
38 	ICP_QAT_FW_INIT_RESP_STATUS_FAIL
39 };
40 
41 struct icp_qat_fw_init_admin_tl_rp_indexes {
42 	__u8 rp_num_index_0;
43 	__u8 rp_num_index_1;
44 	__u8 rp_num_index_2;
45 	__u8 rp_num_index_3;
46 };
47 
48 struct icp_qat_fw_init_admin_slice_cnt {
49 	__u8 cpr_cnt;
50 	__u8 xlt_cnt;
51 	__u8 dcpr_cnt;
52 	__u8 pke_cnt;
53 	__u8 wat_cnt;
54 	__u8 wcp_cnt;
55 	__u8 ucs_cnt;
56 	__u8 cph_cnt;
57 	__u8 ath_cnt;
58 };
59 
60 struct icp_qat_fw_init_admin_sla_config_params {
61 	__u32 pcie_in_cir;
62 	__u32 pcie_in_pir;
63 	__u32 pcie_out_cir;
64 	__u32 pcie_out_pir;
65 	__u32 slice_util_cir;
66 	__u32 slice_util_pir;
67 	__u32 ae_util_cir;
68 	__u32 ae_util_pir;
69 	__u16 rp_ids[RL_MAX_RP_IDS];
70 };
71 
72 struct icp_qat_fw_init_admin_req {
73 	__u16 init_cfg_sz;
74 	__u8 resrvd1;
75 	__u8 cmd_id;
76 	__u32 resrvd2;
77 	__u64 opaque_data;
78 	__u64 init_cfg_ptr;
79 
80 	union {
81 		struct {
82 			__u16 ibuf_size_in_kb;
83 			__u16 resrvd3;
84 		};
85 		struct {
86 			__u32 int_timer_ticks;
87 		};
88 		struct {
89 			__u32 heartbeat_ticks;
90 		};
91 		struct {
92 			__u16 node_id;
93 			__u8 node_type;
94 			__u8 svc_type;
95 			__u8 resrvd5[3];
96 			__u8 rp_count;
97 		};
98 		__u32 idle_filter;
99 		struct icp_qat_fw_init_admin_tl_rp_indexes rp_indexes;
100 	};
101 
102 	__u32 resrvd4;
103 } __packed;
104 
105 struct icp_qat_fw_init_admin_resp {
106 	__u8 flags;
107 	__u8 resrvd1;
108 	__u8 status;
109 	__u8 cmd_id;
110 	union {
111 		__u32 resrvd2;
112 		struct {
113 			__u16 version_minor_num;
114 			__u16 version_major_num;
115 		};
116 		__u32 extended_features;
117 		struct {
118 			__u16 error_count;
119 			__u16 latest_error;
120 		};
121 	};
122 	__u64 opaque_data;
123 	union {
124 		__u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4];
125 		struct {
126 			__u32 version_patch_num;
127 			__u8 context_id;
128 			__u8 ae_id;
129 			__u16 resrvd4;
130 			__u64 resrvd5;
131 		};
132 		struct {
133 			__u64 req_rec_count;
134 			__u64 resp_sent_count;
135 		};
136 		struct {
137 			__u16 compression_algos;
138 			__u16 checksum_algos;
139 			__u32 deflate_capabilities;
140 			__u32 resrvd6;
141 			__u32 lzs_capabilities;
142 		};
143 		struct {
144 			__u32 cipher_algos;
145 			__u32 hash_algos;
146 			__u16 keygen_algos;
147 			__u16 other;
148 			__u16 public_key_algos;
149 			__u16 prime_algos;
150 		};
151 		struct {
152 			__u64 timestamp;
153 			__u64 resrvd7;
154 		};
155 		struct {
156 			__u32 successful_count;
157 			__u32 unsuccessful_count;
158 			__u64 resrvd8;
159 		};
160 		struct icp_qat_fw_init_admin_slice_cnt slices;
161 		__u16 fw_capabilities;
162 	};
163 } __packed;
164 
165 #define ICP_QAT_FW_SYNC ICP_QAT_FW_HEARTBEAT_SYNC
166 #define ICP_QAT_FW_CAPABILITIES_GET ICP_QAT_FW_CRYPTO_CAPABILITY_GET
167 
168 #define ICP_QAT_NUMBER_OF_PM_EVENTS 8
169 
170 struct icp_qat_fw_init_admin_pm_info {
171 	__u16 max_pwrreq;
172 	__u16 min_pwrreq;
173 	__u16 resvrd1;
174 	__u8 pwr_state;
175 	__u8 resvrd2;
176 	__u32 fusectl0;
177 	struct_group(event_counters,
178 		__u32 sys_pm;
179 		__u32 host_msg;
180 		__u32 unknown;
181 		__u32 local_ssm;
182 		__u32 timer;
183 	);
184 	__u32 event_log[ICP_QAT_NUMBER_OF_PM_EVENTS];
185 	struct_group(pm,
186 		__u32 fw_init;
187 		__u32 pwrreq;
188 		__u32 status;
189 		__u32 main;
190 		__u32 thread;
191 	);
192 	struct_group(ssm,
193 		__u32 pm_enable;
194 		__u32 pm_active_status;
195 		__u32 pm_managed_status;
196 		__u32 pm_domain_status;
197 		__u32 active_constraint;
198 	);
199 	__u32 resvrd3[6];
200 };
201 
202 #endif
203