1
2 /*
3 * PowerPC CPU initialization for qemu.
4 *
5 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "qemu/osdep.h"
23 #include "disas/dis-asm.h"
24 #include "gdbstub/helpers.h"
25 #include "system/cpus.h"
26 #include "system/hw_accel.h"
27 #include "system/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qobject/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "qemu/cutils.h"
41 #include "disas/capstone.h"
42 #include "fpu/softfloat.h"
43 #include "exec/watchpoint.h"
44 #include "helper_regs.h"
45 #include "internal.h"
46 #include "spr_common.h"
47 #include "power8-pmu.h"
48 #ifndef CONFIG_USER_ONLY
49 #include "hw/boards.h"
50 #include "hw/intc/intc.h"
51 #include "kvm_ppc.h"
52 #endif
53
54 #include "cpu_init.h"
55 /* #define PPC_DEBUG_SPR */
56 /* #define USE_APPLE_GDB */
57
vscr_init(CPUPPCState * env,uint32_t val)58 static inline void vscr_init(CPUPPCState *env, uint32_t val)
59 {
60 /* Altivec always uses round-to-nearest */
61 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
62 ppc_store_vscr(env, val);
63 }
64
register_745_sprs(CPUPPCState * env)65 static void register_745_sprs(CPUPPCState *env)
66 {
67 /* SGPRs */
68 spr_register(env, SPR_SPRG4, "SPRG4",
69 SPR_NOACCESS, SPR_NOACCESS,
70 &spr_read_generic, &spr_write_generic,
71 0x00000000);
72 spr_register(env, SPR_SPRG5, "SPRG5",
73 SPR_NOACCESS, SPR_NOACCESS,
74 &spr_read_generic, &spr_write_generic,
75 0x00000000);
76 spr_register(env, SPR_SPRG6, "SPRG6",
77 SPR_NOACCESS, SPR_NOACCESS,
78 &spr_read_generic, &spr_write_generic,
79 0x00000000);
80 spr_register(env, SPR_SPRG7, "SPRG7",
81 SPR_NOACCESS, SPR_NOACCESS,
82 &spr_read_generic, &spr_write_generic,
83 0x00000000);
84
85 /* Hardware implementation registers */
86 spr_register(env, SPR_HID0, "HID0",
87 SPR_NOACCESS, SPR_NOACCESS,
88 &spr_read_generic, &spr_write_generic,
89 0x00000000);
90
91 spr_register(env, SPR_HID1, "HID1",
92 SPR_NOACCESS, SPR_NOACCESS,
93 &spr_read_generic, &spr_write_generic,
94 0x00000000);
95
96 spr_register(env, SPR_HID2, "HID2",
97 SPR_NOACCESS, SPR_NOACCESS,
98 &spr_read_generic, &spr_write_generic,
99 0x00000000);
100 }
101
register_755_sprs(CPUPPCState * env)102 static void register_755_sprs(CPUPPCState *env)
103 {
104 /* L2 cache control */
105 spr_register(env, SPR_L2CR, "L2CR",
106 SPR_NOACCESS, SPR_NOACCESS,
107 &spr_read_generic, spr_access_nop,
108 0x00000000);
109
110 spr_register(env, SPR_L2PMCR, "L2PMCR",
111 SPR_NOACCESS, SPR_NOACCESS,
112 &spr_read_generic, &spr_write_generic,
113 0x00000000);
114 }
115
116 /* SPR common to all 7xx PowerPC implementations */
register_7xx_sprs(CPUPPCState * env)117 static void register_7xx_sprs(CPUPPCState *env)
118 {
119 /* Breakpoints */
120 spr_register_kvm(env, SPR_DABR, "DABR",
121 SPR_NOACCESS, SPR_NOACCESS,
122 &spr_read_generic, &spr_write_generic,
123 KVM_REG_PPC_DABR, 0x00000000);
124
125 spr_register(env, SPR_IABR, "IABR",
126 SPR_NOACCESS, SPR_NOACCESS,
127 &spr_read_generic, &spr_write_generic,
128 0x00000000);
129 /* Cache management */
130 spr_register(env, SPR_ICTC, "ICTC",
131 SPR_NOACCESS, SPR_NOACCESS,
132 &spr_read_generic, &spr_write_generic,
133 0x00000000);
134 /* Performance monitors */
135 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
136 SPR_NOACCESS, SPR_NOACCESS,
137 &spr_read_generic, &spr_write_generic,
138 0x00000000);
139
140 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
141 SPR_NOACCESS, SPR_NOACCESS,
142 &spr_read_generic, &spr_write_generic,
143 0x00000000);
144
145 spr_register(env, SPR_7XX_PMC1, "PMC1",
146 SPR_NOACCESS, SPR_NOACCESS,
147 &spr_read_generic, &spr_write_generic,
148 0x00000000);
149
150 spr_register(env, SPR_7XX_PMC2, "PMC2",
151 SPR_NOACCESS, SPR_NOACCESS,
152 &spr_read_generic, &spr_write_generic,
153 0x00000000);
154
155 spr_register(env, SPR_7XX_PMC3, "PMC3",
156 SPR_NOACCESS, SPR_NOACCESS,
157 &spr_read_generic, &spr_write_generic,
158 0x00000000);
159
160 spr_register(env, SPR_7XX_PMC4, "PMC4",
161 SPR_NOACCESS, SPR_NOACCESS,
162 &spr_read_generic, &spr_write_generic,
163 0x00000000);
164
165 spr_register(env, SPR_7XX_SIAR, "SIAR",
166 SPR_NOACCESS, SPR_NOACCESS,
167 &spr_read_generic, SPR_NOACCESS,
168 0x00000000);
169
170 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
171 &spr_read_ureg, SPR_NOACCESS,
172 &spr_read_ureg, SPR_NOACCESS,
173 0x00000000);
174
175 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
176 &spr_read_ureg, SPR_NOACCESS,
177 &spr_read_ureg, SPR_NOACCESS,
178 0x00000000);
179
180 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
181 &spr_read_ureg, SPR_NOACCESS,
182 &spr_read_ureg, SPR_NOACCESS,
183 0x00000000);
184
185 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
186 &spr_read_ureg, SPR_NOACCESS,
187 &spr_read_ureg, SPR_NOACCESS,
188 0x00000000);
189
190 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
191 &spr_read_ureg, SPR_NOACCESS,
192 &spr_read_ureg, SPR_NOACCESS,
193 0x00000000);
194
195 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
196 &spr_read_ureg, SPR_NOACCESS,
197 &spr_read_ureg, SPR_NOACCESS,
198 0x00000000);
199
200 spr_register(env, SPR_7XX_USIAR, "USIAR",
201 &spr_read_ureg, SPR_NOACCESS,
202 &spr_read_ureg, SPR_NOACCESS,
203 0x00000000);
204 /* External access control */
205 spr_register(env, SPR_EAR, "EAR",
206 SPR_NOACCESS, SPR_NOACCESS,
207 &spr_read_generic, &spr_write_generic,
208 0x00000000);
209
210 /* Hardware implementation registers */
211 spr_register(env, SPR_HID0, "HID0",
212 SPR_NOACCESS, SPR_NOACCESS,
213 &spr_read_generic, &spr_write_generic,
214 0x00000000);
215
216 spr_register(env, SPR_HID1, "HID1",
217 SPR_NOACCESS, SPR_NOACCESS,
218 &spr_read_generic, &spr_write_generic,
219 0x00000000);
220 }
221
222 #ifdef TARGET_PPC64
register_amr_sprs(CPUPPCState * env)223 static void register_amr_sprs(CPUPPCState *env)
224 {
225 #ifndef CONFIG_USER_ONLY
226 /*
227 * Virtual Page Class Key protection
228 *
229 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
230 * userspace accessible, 29 is privileged. So we only need to set
231 * the kvm ONE_REG id on one of them, we use 29
232 */
233 spr_register(env, SPR_UAMR, "UAMR",
234 &spr_read_generic, &spr_write_amr,
235 &spr_read_generic, &spr_write_amr,
236 0);
237 spr_register_kvm_hv(env, SPR_AMR, "AMR",
238 SPR_NOACCESS, SPR_NOACCESS,
239 &spr_read_generic, &spr_write_amr,
240 &spr_read_generic, &spr_write_generic,
241 KVM_REG_PPC_AMR, 0);
242 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
243 SPR_NOACCESS, SPR_NOACCESS,
244 &spr_read_generic, &spr_write_uamor,
245 &spr_read_generic, &spr_write_generic,
246 KVM_REG_PPC_UAMOR, 0);
247 spr_register_hv(env, SPR_AMOR, "AMOR",
248 SPR_NOACCESS, SPR_NOACCESS,
249 SPR_NOACCESS, SPR_NOACCESS,
250 &spr_read_generic, &spr_core_lpar_write_generic,
251 0);
252 #endif /* !CONFIG_USER_ONLY */
253 }
254
register_iamr_sprs(CPUPPCState * env)255 static void register_iamr_sprs(CPUPPCState *env)
256 {
257 #ifndef CONFIG_USER_ONLY
258 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
259 SPR_NOACCESS, SPR_NOACCESS,
260 &spr_read_generic, &spr_write_iamr,
261 &spr_read_generic, &spr_write_generic,
262 KVM_REG_PPC_IAMR, 0);
263 #endif /* !CONFIG_USER_ONLY */
264 }
265 #endif /* TARGET_PPC64 */
266
267 /* SPR specific to PowerPC 604 implementation */
register_604_sprs(CPUPPCState * env)268 static void register_604_sprs(CPUPPCState *env)
269 {
270 /* Processor identification */
271 spr_register(env, SPR_PIR, "PIR",
272 SPR_NOACCESS, SPR_NOACCESS,
273 &spr_read_generic, &spr_write_pir,
274 0x00000000);
275 /* Breakpoints */
276 spr_register(env, SPR_IABR, "IABR",
277 SPR_NOACCESS, SPR_NOACCESS,
278 &spr_read_generic, &spr_write_generic,
279 0x00000000);
280
281 spr_register_kvm(env, SPR_DABR, "DABR",
282 SPR_NOACCESS, SPR_NOACCESS,
283 &spr_read_generic, &spr_write_generic,
284 KVM_REG_PPC_DABR, 0x00000000);
285 /* Performance counters */
286 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
287 SPR_NOACCESS, SPR_NOACCESS,
288 &spr_read_generic, &spr_write_generic,
289 0x00000000);
290
291 spr_register(env, SPR_7XX_PMC1, "PMC1",
292 SPR_NOACCESS, SPR_NOACCESS,
293 &spr_read_generic, &spr_write_generic,
294 0x00000000);
295
296 spr_register(env, SPR_7XX_PMC2, "PMC2",
297 SPR_NOACCESS, SPR_NOACCESS,
298 &spr_read_generic, &spr_write_generic,
299 0x00000000);
300
301 spr_register(env, SPR_7XX_SIAR, "SIAR",
302 SPR_NOACCESS, SPR_NOACCESS,
303 &spr_read_generic, SPR_NOACCESS,
304 0x00000000);
305
306 spr_register(env, SPR_SDA, "SDA",
307 SPR_NOACCESS, SPR_NOACCESS,
308 &spr_read_generic, SPR_NOACCESS,
309 0x00000000);
310 /* External access control */
311 spr_register(env, SPR_EAR, "EAR",
312 SPR_NOACCESS, SPR_NOACCESS,
313 &spr_read_generic, &spr_write_generic,
314 0x00000000);
315
316 /* Hardware implementation registers */
317 spr_register(env, SPR_HID0, "HID0",
318 SPR_NOACCESS, SPR_NOACCESS,
319 &spr_read_generic, &spr_write_generic,
320 0x00000000);
321 }
322
register_604e_sprs(CPUPPCState * env)323 static void register_604e_sprs(CPUPPCState *env)
324 {
325 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
326 SPR_NOACCESS, SPR_NOACCESS,
327 &spr_read_generic, &spr_write_generic,
328 0x00000000);
329
330 spr_register(env, SPR_7XX_PMC3, "PMC3",
331 SPR_NOACCESS, SPR_NOACCESS,
332 &spr_read_generic, &spr_write_generic,
333 0x00000000);
334
335 spr_register(env, SPR_7XX_PMC4, "PMC4",
336 SPR_NOACCESS, SPR_NOACCESS,
337 &spr_read_generic, &spr_write_generic,
338 0x00000000);
339 /* Hardware implementation registers */
340 spr_register(env, SPR_HID1, "HID1",
341 SPR_NOACCESS, SPR_NOACCESS,
342 &spr_read_generic, &spr_write_generic,
343 0x00000000);
344 }
345
346 /* SPR specific to PowerPC 603 implementation */
register_603_sprs(CPUPPCState * env)347 static void register_603_sprs(CPUPPCState *env)
348 {
349 /* External access control */
350 spr_register(env, SPR_EAR, "EAR",
351 SPR_NOACCESS, SPR_NOACCESS,
352 &spr_read_generic, &spr_write_generic,
353 0x00000000);
354 /* Breakpoints */
355 spr_register(env, SPR_IABR, "IABR",
356 SPR_NOACCESS, SPR_NOACCESS,
357 &spr_read_generic, &spr_write_generic,
358 0x00000000);
359
360 spr_register(env, SPR_HID0, "HID0",
361 SPR_NOACCESS, SPR_NOACCESS,
362 &spr_read_generic, &spr_write_generic,
363 0x00000000);
364
365 spr_register(env, SPR_HID1, "HID1",
366 SPR_NOACCESS, SPR_NOACCESS,
367 &spr_read_generic, &spr_write_generic,
368 0x00000000);
369 }
370
register_e300_sprs(CPUPPCState * env)371 static void register_e300_sprs(CPUPPCState *env)
372 {
373 /* hardware implementation registers */
374 spr_register(env, SPR_HID2, "HID2",
375 SPR_NOACCESS, SPR_NOACCESS,
376 &spr_read_generic, &spr_write_generic,
377 0x00000000);
378 /* Breakpoints */
379 spr_register(env, SPR_DABR, "DABR",
380 SPR_NOACCESS, SPR_NOACCESS,
381 &spr_read_generic, &spr_write_generic,
382 0x00000000);
383
384 spr_register(env, SPR_DABR2, "DABR2",
385 SPR_NOACCESS, SPR_NOACCESS,
386 &spr_read_generic, &spr_write_generic,
387 0x00000000);
388
389 spr_register(env, SPR_IABR2, "IABR2",
390 SPR_NOACCESS, SPR_NOACCESS,
391 &spr_read_generic, &spr_write_generic,
392 0x00000000);
393
394 spr_register(env, SPR_IBCR, "IBCR",
395 SPR_NOACCESS, SPR_NOACCESS,
396 &spr_read_generic, &spr_write_generic,
397 0x00000000);
398
399 spr_register(env, SPR_DBCR, "DBCR",
400 SPR_NOACCESS, SPR_NOACCESS,
401 &spr_read_generic, &spr_write_generic,
402 0x00000000);
403 }
404
405 /* SPR specific to PowerPC G2 implementation */
register_G2_sprs(CPUPPCState * env)406 static void register_G2_sprs(CPUPPCState *env)
407 {
408 /* Memory base address */
409 /* MBAR */
410 spr_register(env, SPR_MBAR, "MBAR",
411 SPR_NOACCESS, SPR_NOACCESS,
412 &spr_read_generic, &spr_write_generic,
413 0x00000000);
414 /* Exception processing */
415 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
416 SPR_NOACCESS, SPR_NOACCESS,
417 &spr_read_generic, &spr_write_generic,
418 0x00000000);
419 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
420 SPR_NOACCESS, SPR_NOACCESS,
421 &spr_read_generic, &spr_write_generic,
422 0x00000000);
423 /* Breakpoints */
424 spr_register(env, SPR_DABR, "DABR",
425 SPR_NOACCESS, SPR_NOACCESS,
426 &spr_read_generic, &spr_write_generic,
427 0x00000000);
428
429 spr_register(env, SPR_DABR2, "DABR2",
430 SPR_NOACCESS, SPR_NOACCESS,
431 &spr_read_generic, &spr_write_generic,
432 0x00000000);
433
434 spr_register(env, SPR_IABR, "IABR",
435 SPR_NOACCESS, SPR_NOACCESS,
436 &spr_read_generic, &spr_write_generic,
437 0x00000000);
438
439 spr_register(env, SPR_IABR2, "IABR2",
440 SPR_NOACCESS, SPR_NOACCESS,
441 &spr_read_generic, &spr_write_generic,
442 0x00000000);
443
444 spr_register(env, SPR_IBCR, "IBCR",
445 SPR_NOACCESS, SPR_NOACCESS,
446 &spr_read_generic, &spr_write_generic,
447 0x00000000);
448
449 spr_register(env, SPR_DBCR, "DBCR",
450 SPR_NOACCESS, SPR_NOACCESS,
451 &spr_read_generic, &spr_write_generic,
452 0x00000000);
453
454 /* External access control */
455 spr_register(env, SPR_EAR, "EAR",
456 SPR_NOACCESS, SPR_NOACCESS,
457 &spr_read_generic, &spr_write_generic,
458 0x00000000);
459 /* Hardware implementation register */
460 spr_register(env, SPR_HID0, "HID0",
461 SPR_NOACCESS, SPR_NOACCESS,
462 &spr_read_generic, &spr_write_generic,
463 0x00000000);
464
465 spr_register(env, SPR_HID1, "HID1",
466 SPR_NOACCESS, SPR_NOACCESS,
467 &spr_read_generic, &spr_write_generic,
468 0x00000000);
469
470 spr_register(env, SPR_HID2, "HID2",
471 SPR_NOACCESS, SPR_NOACCESS,
472 &spr_read_generic, &spr_write_generic,
473 0x00000000);
474
475 /* SGPRs */
476 spr_register(env, SPR_SPRG4, "SPRG4",
477 SPR_NOACCESS, SPR_NOACCESS,
478 &spr_read_generic, &spr_write_generic,
479 0x00000000);
480 spr_register(env, SPR_SPRG5, "SPRG5",
481 SPR_NOACCESS, SPR_NOACCESS,
482 &spr_read_generic, &spr_write_generic,
483 0x00000000);
484 spr_register(env, SPR_SPRG6, "SPRG6",
485 SPR_NOACCESS, SPR_NOACCESS,
486 &spr_read_generic, &spr_write_generic,
487 0x00000000);
488 spr_register(env, SPR_SPRG7, "SPRG7",
489 SPR_NOACCESS, SPR_NOACCESS,
490 &spr_read_generic, &spr_write_generic,
491 0x00000000);
492 }
493
register_74xx_sprs(CPUPPCState * env)494 static void register_74xx_sprs(CPUPPCState *env)
495 {
496 /* Breakpoints */
497 spr_register_kvm(env, SPR_DABR, "DABR",
498 SPR_NOACCESS, SPR_NOACCESS,
499 &spr_read_generic, &spr_write_generic,
500 KVM_REG_PPC_DABR, 0x00000000);
501
502 spr_register(env, SPR_IABR, "IABR",
503 SPR_NOACCESS, SPR_NOACCESS,
504 &spr_read_generic, &spr_write_generic,
505 0x00000000);
506 /* Cache management */
507 spr_register(env, SPR_ICTC, "ICTC",
508 SPR_NOACCESS, SPR_NOACCESS,
509 &spr_read_generic, &spr_write_generic,
510 0x00000000);
511 /* Performance monitors */
512 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
513 SPR_NOACCESS, SPR_NOACCESS,
514 &spr_read_generic, &spr_write_generic,
515 0x00000000);
516
517 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
518 SPR_NOACCESS, SPR_NOACCESS,
519 &spr_read_generic, &spr_write_generic,
520 0x00000000);
521
522 spr_register(env, SPR_7XX_PMC1, "PMC1",
523 SPR_NOACCESS, SPR_NOACCESS,
524 &spr_read_generic, &spr_write_generic,
525 0x00000000);
526
527 spr_register(env, SPR_7XX_PMC2, "PMC2",
528 SPR_NOACCESS, SPR_NOACCESS,
529 &spr_read_generic, &spr_write_generic,
530 0x00000000);
531
532 spr_register(env, SPR_7XX_PMC3, "PMC3",
533 SPR_NOACCESS, SPR_NOACCESS,
534 &spr_read_generic, &spr_write_generic,
535 0x00000000);
536
537 spr_register(env, SPR_7XX_PMC4, "PMC4",
538 SPR_NOACCESS, SPR_NOACCESS,
539 &spr_read_generic, &spr_write_generic,
540 0x00000000);
541
542 spr_register(env, SPR_7XX_SIAR, "SIAR",
543 SPR_NOACCESS, SPR_NOACCESS,
544 &spr_read_generic, SPR_NOACCESS,
545 0x00000000);
546
547 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
548 &spr_read_ureg, SPR_NOACCESS,
549 &spr_read_ureg, SPR_NOACCESS,
550 0x00000000);
551
552 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
553 &spr_read_ureg, SPR_NOACCESS,
554 &spr_read_ureg, SPR_NOACCESS,
555 0x00000000);
556
557 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
558 &spr_read_ureg, SPR_NOACCESS,
559 &spr_read_ureg, SPR_NOACCESS,
560 0x00000000);
561
562 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
563 &spr_read_ureg, SPR_NOACCESS,
564 &spr_read_ureg, SPR_NOACCESS,
565 0x00000000);
566
567 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
568 &spr_read_ureg, SPR_NOACCESS,
569 &spr_read_ureg, SPR_NOACCESS,
570 0x00000000);
571
572 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
573 &spr_read_ureg, SPR_NOACCESS,
574 &spr_read_ureg, SPR_NOACCESS,
575 0x00000000);
576
577 spr_register(env, SPR_7XX_USIAR, "USIAR",
578 &spr_read_ureg, SPR_NOACCESS,
579 &spr_read_ureg, SPR_NOACCESS,
580 0x00000000);
581 /* External access control */
582 spr_register(env, SPR_EAR, "EAR",
583 SPR_NOACCESS, SPR_NOACCESS,
584 &spr_read_generic, &spr_write_generic,
585 0x00000000);
586
587 /* Processor identification */
588 spr_register(env, SPR_PIR, "PIR",
589 SPR_NOACCESS, SPR_NOACCESS,
590 &spr_read_generic, &spr_write_pir,
591 0x00000000);
592
593 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
594 SPR_NOACCESS, SPR_NOACCESS,
595 &spr_read_generic, &spr_write_generic,
596 0x00000000);
597
598 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
599 &spr_read_ureg, SPR_NOACCESS,
600 &spr_read_ureg, SPR_NOACCESS,
601 0x00000000);
602
603 spr_register(env, SPR_BAMR, "BAMR",
604 SPR_NOACCESS, SPR_NOACCESS,
605 &spr_read_generic, &spr_write_generic,
606 0x00000000);
607
608 spr_register(env, SPR_MSSCR0, "MSSCR0",
609 SPR_NOACCESS, SPR_NOACCESS,
610 &spr_read_generic, &spr_write_generic,
611 0x00000000);
612 /* Hardware implementation registers */
613 spr_register(env, SPR_HID0, "HID0",
614 SPR_NOACCESS, SPR_NOACCESS,
615 &spr_read_generic, &spr_write_generic,
616 0x00000000);
617
618 spr_register(env, SPR_HID1, "HID1",
619 SPR_NOACCESS, SPR_NOACCESS,
620 &spr_read_generic, &spr_write_generic,
621 0x00000000);
622 /* Altivec */
623 spr_register(env, SPR_VRSAVE, "VRSAVE",
624 &spr_read_generic, &spr_write_generic,
625 &spr_read_generic, &spr_write_generic,
626 0x00000000);
627
628 spr_register(env, SPR_L2CR, "L2CR",
629 SPR_NOACCESS, SPR_NOACCESS,
630 &spr_read_generic, spr_access_nop,
631 0x00000000);
632 }
633
register_l3_ctrl(CPUPPCState * env)634 static void register_l3_ctrl(CPUPPCState *env)
635 {
636 /* L3CR */
637 spr_register(env, SPR_L3CR, "L3CR",
638 SPR_NOACCESS, SPR_NOACCESS,
639 &spr_read_generic, &spr_write_generic,
640 0x00000000);
641 /* L3ITCR0 */
642 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
643 SPR_NOACCESS, SPR_NOACCESS,
644 &spr_read_generic, &spr_write_generic,
645 0x00000000);
646 /* L3PM */
647 spr_register(env, SPR_L3PM, "L3PM",
648 SPR_NOACCESS, SPR_NOACCESS,
649 &spr_read_generic, &spr_write_generic,
650 0x00000000);
651 }
652
653 /* PowerPC BookE SPR */
register_BookE_sprs(CPUPPCState * env,uint64_t ivor_mask)654 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
655 {
656 const char *ivor_names[64] = {
657 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
658 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
659 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
660 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
661 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
662 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
663 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
664 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
665 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
666 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
667 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
668 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
669 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
670 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
671 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
672 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
673 };
674 #define SPR_BOOKE_IVORxx (-1)
675 int ivor_sprn[64] = {
676 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
677 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
678 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
679 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
684 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
685 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
686 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
692 };
693 int i;
694
695 /* Interrupt processing */
696 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
697 SPR_NOACCESS, SPR_NOACCESS,
698 &spr_read_generic, &spr_write_generic,
699 0x00000000);
700 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_generic,
703 0x00000000);
704 /* Debug */
705 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709
710 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_generic, &spr_write_generic,
713 0x00000000);
714
715 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719
720 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_generic, &spr_write_generic,
723 0x00000000);
724
725 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
726 SPR_NOACCESS, SPR_NOACCESS,
727 &spr_read_generic, &spr_write_40x_dbcr0,
728 0x00000000);
729
730 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_generic, &spr_write_generic,
733 0x00000000);
734
735 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
736 SPR_NOACCESS, SPR_NOACCESS,
737 &spr_read_generic, &spr_write_generic,
738 0x00000000);
739 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
740 SPR_NOACCESS, SPR_NOACCESS,
741 &spr_read_generic, &spr_write_generic,
742 0x00000000);
743 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_generic,
746 0x00000000);
747
748 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_generic, &spr_write_clear,
751 0x00000000);
752 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_generic, &spr_write_generic,
755 0x00000000);
756 spr_register(env, SPR_BOOKE_ESR, "ESR",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_generic, &spr_write_generic,
759 0x00000000);
760 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_generic, &spr_write_excp_prefix,
763 0x00000000);
764 /* Exception vectors */
765 for (i = 0; i < 64; i++) {
766 if (ivor_mask & (1ULL << i)) {
767 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
768 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
769 exit(1);
770 }
771 spr_register(env, ivor_sprn[i], ivor_names[i],
772 SPR_NOACCESS, SPR_NOACCESS,
773 &spr_read_generic, &spr_write_excp_vector,
774 0x00000000);
775 }
776 }
777 spr_register(env, SPR_BOOKE_PID, "PID",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_generic, &spr_write_booke_pid,
780 0x00000000);
781 spr_register(env, SPR_BOOKE_TCR, "TCR",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_generic, &spr_write_booke_tcr,
784 0x00000000);
785 spr_register(env, SPR_BOOKE_TSR, "TSR",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_generic, &spr_write_booke_tsr,
788 0x00000000);
789 /* Timer */
790 spr_register(env, SPR_DECR, "DECR",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_decr, &spr_write_decr,
793 0x00000000);
794 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
795 SPR_NOACCESS, SPR_NOACCESS,
796 SPR_NOACCESS, &spr_write_generic32,
797 0x00000000);
798 /* SPRGs */
799 spr_register(env, SPR_USPRG0, "USPRG0",
800 &spr_read_generic, &spr_write_generic,
801 &spr_read_generic, &spr_write_generic,
802 0x00000000);
803 spr_register(env, SPR_SPRG4, "SPRG4",
804 SPR_NOACCESS, SPR_NOACCESS,
805 &spr_read_generic, &spr_write_generic,
806 0x00000000);
807 spr_register(env, SPR_SPRG5, "SPRG5",
808 SPR_NOACCESS, SPR_NOACCESS,
809 &spr_read_generic, &spr_write_generic,
810 0x00000000);
811 spr_register(env, SPR_SPRG6, "SPRG6",
812 SPR_NOACCESS, SPR_NOACCESS,
813 &spr_read_generic, &spr_write_generic,
814 0x00000000);
815 spr_register(env, SPR_SPRG7, "SPRG7",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_generic, &spr_write_generic,
818 0x00000000);
819 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
820 SPR_NOACCESS, SPR_NOACCESS,
821 &spr_read_generic, &spr_write_generic,
822 0x00000000);
823 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
824 SPR_NOACCESS, SPR_NOACCESS,
825 &spr_read_generic, &spr_write_generic,
826 0x00000000);
827 }
828
829 #if !defined(CONFIG_USER_ONLY)
register_tlbncfg(uint32_t assoc,uint32_t minsize,uint32_t maxsize,uint32_t flags,uint32_t nentries)830 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
831 uint32_t maxsize, uint32_t flags,
832 uint32_t nentries)
833 {
834 return (assoc << TLBnCFG_ASSOC_SHIFT) |
835 (minsize << TLBnCFG_MINSIZE_SHIFT) |
836 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
837 flags | nentries;
838 }
839 #endif /* !CONFIG_USER_ONLY */
840
841 /* BookE 2.06 storage control registers */
register_BookE206_sprs(CPUPPCState * env,uint32_t mas_mask,uint32_t * tlbncfg,uint32_t mmucfg)842 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
843 uint32_t *tlbncfg, uint32_t mmucfg)
844 {
845 #if !defined(CONFIG_USER_ONLY)
846 const char *mas_names[8] = {
847 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
848 };
849 int mas_sprn[8] = {
850 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
851 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
852 };
853 int i;
854
855 /* TLB assist registers */
856 for (i = 0; i < 8; i++) {
857 if (mas_mask & (1 << i)) {
858 spr_register(env, mas_sprn[i], mas_names[i],
859 SPR_NOACCESS, SPR_NOACCESS,
860 &spr_read_generic,
861 (i == 2 && (env->insns_flags & PPC_64B))
862 ? &spr_write_generic : &spr_write_generic32,
863 0x00000000);
864 }
865 }
866 if (env->nb_pids > 1) {
867 spr_register(env, SPR_BOOKE_PID1, "PID1",
868 SPR_NOACCESS, SPR_NOACCESS,
869 &spr_read_generic, &spr_write_booke_pid,
870 0x00000000);
871 }
872 if (env->nb_pids > 2) {
873 spr_register(env, SPR_BOOKE_PID2, "PID2",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_generic, &spr_write_booke_pid,
876 0x00000000);
877 }
878
879 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, &spr_write_eplc,
882 0x00000000);
883 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, &spr_write_epsc,
886 0x00000000);
887
888 spr_register(env, SPR_MMUCFG, "MMUCFG",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_generic, SPR_NOACCESS,
891 mmucfg);
892 switch (env->nb_ways) {
893 case 4:
894 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_generic, SPR_NOACCESS,
897 tlbncfg[3]);
898 /* Fallthru */
899 case 3:
900 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_generic, SPR_NOACCESS,
903 tlbncfg[2]);
904 /* Fallthru */
905 case 2:
906 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_generic, SPR_NOACCESS,
909 tlbncfg[1]);
910 /* Fallthru */
911 case 1:
912 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
913 SPR_NOACCESS, SPR_NOACCESS,
914 &spr_read_generic, SPR_NOACCESS,
915 tlbncfg[0]);
916 /* Fallthru */
917 case 0:
918 default:
919 break;
920 }
921 #endif
922 }
923
register_atb_sprs(CPUPPCState * env)924 static void register_atb_sprs(CPUPPCState *env)
925 {
926 spr_register(env, SPR_ATBL, "ATBL",
927 &spr_read_atbl, SPR_NOACCESS,
928 &spr_read_atbl, SPR_NOACCESS,
929 0x00000000);
930 spr_register(env, SPR_ATBU, "ATBU",
931 &spr_read_atbu, SPR_NOACCESS,
932 &spr_read_atbu, SPR_NOACCESS,
933 0x00000000);
934 }
935
936 /* SPR specific to PowerPC 440 implementation */
register_440_sprs(CPUPPCState * env)937 static void register_440_sprs(CPUPPCState *env)
938 {
939 /* Cache control */
940 spr_register(env, SPR_440_DNV0, "DNV0",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_generic, &spr_write_generic,
943 0x00000000);
944
945 spr_register(env, SPR_440_DNV1, "DNV1",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, &spr_write_generic,
948 0x00000000);
949
950 spr_register(env, SPR_440_DNV2, "DNV2",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954
955 spr_register(env, SPR_440_DNV3, "DNV3",
956 SPR_NOACCESS, SPR_NOACCESS,
957 &spr_read_generic, &spr_write_generic,
958 0x00000000);
959
960 spr_register(env, SPR_440_DTV0, "DTV0",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_generic, &spr_write_generic,
963 0x00000000);
964
965 spr_register(env, SPR_440_DTV1, "DTV1",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969
970 spr_register(env, SPR_440_DTV2, "DTV2",
971 SPR_NOACCESS, SPR_NOACCESS,
972 &spr_read_generic, &spr_write_generic,
973 0x00000000);
974
975 spr_register(env, SPR_440_DTV3, "DTV3",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, &spr_write_generic,
978 0x00000000);
979
980 spr_register(env, SPR_440_DVLIM, "DVLIM",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984
985 spr_register(env, SPR_440_INV0, "INV0",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989
990 spr_register(env, SPR_440_INV1, "INV1",
991 SPR_NOACCESS, SPR_NOACCESS,
992 &spr_read_generic, &spr_write_generic,
993 0x00000000);
994
995 spr_register(env, SPR_440_INV2, "INV2",
996 SPR_NOACCESS, SPR_NOACCESS,
997 &spr_read_generic, &spr_write_generic,
998 0x00000000);
999
1000 spr_register(env, SPR_440_INV3, "INV3",
1001 SPR_NOACCESS, SPR_NOACCESS,
1002 &spr_read_generic, &spr_write_generic,
1003 0x00000000);
1004
1005 spr_register(env, SPR_440_ITV0, "ITV0",
1006 SPR_NOACCESS, SPR_NOACCESS,
1007 &spr_read_generic, &spr_write_generic,
1008 0x00000000);
1009
1010 spr_register(env, SPR_440_ITV1, "ITV1",
1011 SPR_NOACCESS, SPR_NOACCESS,
1012 &spr_read_generic, &spr_write_generic,
1013 0x00000000);
1014
1015 spr_register(env, SPR_440_ITV2, "ITV2",
1016 SPR_NOACCESS, SPR_NOACCESS,
1017 &spr_read_generic, &spr_write_generic,
1018 0x00000000);
1019
1020 spr_register(env, SPR_440_ITV3, "ITV3",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024
1025 spr_register(env, SPR_440_IVLIM, "IVLIM",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* Cache debug */
1030 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, SPR_NOACCESS,
1033 0x00000000);
1034
1035 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, SPR_NOACCESS,
1038 0x00000000);
1039
1040 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, SPR_NOACCESS,
1043 0x00000000);
1044
1045 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, SPR_NOACCESS,
1048 0x00000000);
1049
1050 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, SPR_NOACCESS,
1053 0x00000000);
1054
1055 spr_register(env, SPR_440_DBDR, "DBDR",
1056 SPR_NOACCESS, SPR_NOACCESS,
1057 &spr_read_generic, &spr_write_generic,
1058 0x00000000);
1059 /* Processor control */
1060 spr_register(env, SPR_4xx_CCR0, "CCR0",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, SPR_NOACCESS,
1067 0x00000000);
1068 /* Storage control */
1069 spr_register(env, SPR_440_MMUCR, "MMUCR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 0x00000000);
1073
1074 /* Processor identification */
1075 spr_register(env, SPR_BOOKE_PIR, "PIR",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_generic, &spr_write_pir,
1078 0x00000000);
1079
1080 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084
1085 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089
1090 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094
1095 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 }
1100
1101 /* SPR shared between PowerPC 40x implementations */
register_40x_sprs(CPUPPCState * env)1102 static void register_40x_sprs(CPUPPCState *env)
1103 {
1104 /* Cache */
1105 /* not emulated, as QEMU do not emulate caches */
1106 spr_register(env, SPR_40x_DCCR, "DCCR",
1107 SPR_NOACCESS, SPR_NOACCESS,
1108 &spr_read_generic, &spr_write_generic,
1109 0x00000000);
1110 /* not emulated, as QEMU do not emulate caches */
1111 spr_register(env, SPR_40x_ICCR, "ICCR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* not emulated, as QEMU do not emulate caches */
1116 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, SPR_NOACCESS,
1119 0x00000000);
1120 /* Exception */
1121 spr_register(env, SPR_40x_DEAR, "DEAR",
1122 SPR_NOACCESS, SPR_NOACCESS,
1123 &spr_read_generic, &spr_write_generic,
1124 0x00000000);
1125 spr_register(env, SPR_40x_ESR, "ESR",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 spr_register(env, SPR_40x_EVPR, "EVPR",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_generic, &spr_write_excp_prefix,
1132 0x00000000);
1133 spr_register(env, SPR_40x_SRR2, "SRR2",
1134 &spr_read_generic, &spr_write_generic,
1135 &spr_read_generic, &spr_write_generic,
1136 0x00000000);
1137 spr_register(env, SPR_40x_SRR3, "SRR3",
1138 &spr_read_generic, &spr_write_generic,
1139 &spr_read_generic, &spr_write_generic,
1140 0x00000000);
1141 /* Timers */
1142 spr_register(env, SPR_40x_PIT, "PIT",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_40x_pit, &spr_write_40x_pit,
1145 0x00000000);
1146 spr_register(env, SPR_40x_TCR, "TCR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_40x_tcr,
1149 0x00000000);
1150 spr_register(env, SPR_40x_TSR, "TSR",
1151 SPR_NOACCESS, SPR_NOACCESS,
1152 &spr_read_generic, &spr_write_40x_tsr,
1153 0x00000000);
1154 }
1155
1156 /* SPR specific to PowerPC 405 implementation */
register_405_sprs(CPUPPCState * env)1157 static void register_405_sprs(CPUPPCState *env)
1158 {
1159 /* MMU */
1160 spr_register(env, SPR_40x_PID, "PID",
1161 SPR_NOACCESS, SPR_NOACCESS,
1162 &spr_read_generic, &spr_write_40x_pid,
1163 0x00000000);
1164 spr_register(env, SPR_4xx_CCR0, "CCR0",
1165 SPR_NOACCESS, SPR_NOACCESS,
1166 &spr_read_generic, &spr_write_generic,
1167 0x00700000);
1168 /* Debug interface */
1169 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1170 SPR_NOACCESS, SPR_NOACCESS,
1171 &spr_read_generic, &spr_write_40x_dbcr0,
1172 0x00000000);
1173
1174 spr_register(env, SPR_405_DBCR1, "DBCR1",
1175 SPR_NOACCESS, SPR_NOACCESS,
1176 &spr_read_generic, &spr_write_generic,
1177 0x00000000);
1178
1179 spr_register(env, SPR_40x_DBSR, "DBSR",
1180 SPR_NOACCESS, SPR_NOACCESS,
1181 &spr_read_generic, &spr_write_clear,
1182 /* Last reset was system reset */
1183 0x00000300);
1184
1185 spr_register(env, SPR_40x_DAC1, "DAC1",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 spr_register(env, SPR_40x_DAC2, "DAC2",
1190 SPR_NOACCESS, SPR_NOACCESS,
1191 &spr_read_generic, &spr_write_generic,
1192 0x00000000);
1193
1194 spr_register(env, SPR_405_DVC1, "DVC1",
1195 SPR_NOACCESS, SPR_NOACCESS,
1196 &spr_read_generic, &spr_write_generic,
1197 0x00000000);
1198
1199 spr_register(env, SPR_405_DVC2, "DVC2",
1200 SPR_NOACCESS, SPR_NOACCESS,
1201 &spr_read_generic, &spr_write_generic,
1202 0x00000000);
1203
1204 spr_register(env, SPR_40x_IAC1, "IAC1",
1205 SPR_NOACCESS, SPR_NOACCESS,
1206 &spr_read_generic, &spr_write_generic,
1207 0x00000000);
1208 spr_register(env, SPR_40x_IAC2, "IAC2",
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic, &spr_write_generic,
1211 0x00000000);
1212
1213 spr_register(env, SPR_405_IAC3, "IAC3",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_generic,
1216 0x00000000);
1217
1218 spr_register(env, SPR_405_IAC4, "IAC4",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 /* Storage control */
1223 spr_register(env, SPR_405_SLER, "SLER",
1224 SPR_NOACCESS, SPR_NOACCESS,
1225 &spr_read_generic, &spr_write_40x_sler,
1226 0x00000000);
1227 spr_register(env, SPR_40x_ZPR, "ZPR",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231
1232 spr_register(env, SPR_405_SU0R, "SU0R",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* SPRG */
1237 spr_register(env, SPR_USPRG0, "USPRG0",
1238 &spr_read_ureg, SPR_NOACCESS,
1239 &spr_read_ureg, SPR_NOACCESS,
1240 0x00000000);
1241 spr_register(env, SPR_SPRG4, "SPRG4",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_generic,
1244 0x00000000);
1245 spr_register(env, SPR_SPRG5, "SPRG5",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 spr_read_generic, &spr_write_generic,
1248 0x00000000);
1249 spr_register(env, SPR_SPRG6, "SPRG6",
1250 SPR_NOACCESS, SPR_NOACCESS,
1251 spr_read_generic, &spr_write_generic,
1252 0x00000000);
1253 spr_register(env, SPR_SPRG7, "SPRG7",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 spr_read_generic, &spr_write_generic,
1256 0x00000000);
1257
1258 /* Bus access control */
1259 /* not emulated, as QEMU never does speculative access */
1260 spr_register(env, SPR_40x_SGR, "SGR",
1261 SPR_NOACCESS, SPR_NOACCESS,
1262 &spr_read_generic, &spr_write_generic,
1263 0xFFFFFFFF);
1264 /* not emulated, as QEMU do not emulate caches */
1265 spr_register(env, SPR_40x_DCWR, "DCWR",
1266 SPR_NOACCESS, SPR_NOACCESS,
1267 &spr_read_generic, &spr_write_generic,
1268 0x00000000);
1269 }
1270
1271
register_5xx_8xx_sprs(CPUPPCState * env)1272 static void register_5xx_8xx_sprs(CPUPPCState *env)
1273 {
1274 /* Exception processing */
1275 spr_register_kvm(env, SPR_DSISR, "DSISR",
1276 SPR_NOACCESS, SPR_NOACCESS,
1277 &spr_read_generic, &spr_write_generic,
1278 KVM_REG_PPC_DSISR, 0x00000000);
1279 spr_register_kvm(env, SPR_DAR, "DAR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 KVM_REG_PPC_DAR, 0x00000000);
1283 /* Timer */
1284 spr_register(env, SPR_DECR, "DECR",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_decr, &spr_write_decr,
1287 0x00000000);
1288
1289 spr_register(env, SPR_MPC_EIE, "EIE",
1290 SPR_NOACCESS, SPR_NOACCESS,
1291 &spr_read_generic, &spr_write_generic,
1292 0x00000000);
1293
1294 spr_register(env, SPR_MPC_EID, "EID",
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0x00000000);
1298
1299 spr_register(env, SPR_MPC_NRI, "NRI",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303
1304 spr_register(env, SPR_MPC_CMPA, "CMPA",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308
1309 spr_register(env, SPR_MPC_CMPB, "CMPB",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313
1314 spr_register(env, SPR_MPC_CMPC, "CMPC",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318
1319 spr_register(env, SPR_MPC_CMPD, "CMPD",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323
1324 spr_register(env, SPR_MPC_ECR, "ECR",
1325 SPR_NOACCESS, SPR_NOACCESS,
1326 &spr_read_generic, &spr_write_generic,
1327 0x00000000);
1328
1329 spr_register(env, SPR_MPC_DER, "DER",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333
1334 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338
1339 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343
1344 spr_register(env, SPR_MPC_CMPE, "CMPE",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348
1349 spr_register(env, SPR_MPC_CMPF, "CMPF",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353
1354 spr_register(env, SPR_MPC_CMPG, "CMPG",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358
1359 spr_register(env, SPR_MPC_CMPH, "CMPH",
1360 SPR_NOACCESS, SPR_NOACCESS,
1361 &spr_read_generic, &spr_write_generic,
1362 0x00000000);
1363
1364 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368
1369 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1370 SPR_NOACCESS, SPR_NOACCESS,
1371 &spr_read_generic, &spr_write_generic,
1372 0x00000000);
1373
1374 spr_register(env, SPR_MPC_BAR, "BAR",
1375 SPR_NOACCESS, SPR_NOACCESS,
1376 &spr_read_generic, &spr_write_generic,
1377 0x00000000);
1378
1379 spr_register(env, SPR_MPC_DPDR, "DPDR",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
1383
1384 spr_register(env, SPR_MPC_IMMR, "IMMR",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
1388 }
1389
register_5xx_sprs(CPUPPCState * env)1390 static void register_5xx_sprs(CPUPPCState *env)
1391 {
1392 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396
1397 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401
1402 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406
1407 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1408 SPR_NOACCESS, SPR_NOACCESS,
1409 &spr_read_generic, &spr_write_generic,
1410 0x00000000);
1411
1412 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1413 SPR_NOACCESS, SPR_NOACCESS,
1414 &spr_read_generic, &spr_write_generic,
1415 0x00000000);
1416
1417 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421
1422 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_generic,
1425 0x00000000);
1426
1427 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
1431
1432 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1433 SPR_NOACCESS, SPR_NOACCESS,
1434 &spr_read_generic, &spr_write_generic,
1435 0x00000000);
1436
1437 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1438 SPR_NOACCESS, SPR_NOACCESS,
1439 &spr_read_generic, &spr_write_generic,
1440 0x00000000);
1441
1442 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1443 SPR_NOACCESS, SPR_NOACCESS,
1444 &spr_read_generic, &spr_write_generic,
1445 0x00000000);
1446
1447 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1448 SPR_NOACCESS, SPR_NOACCESS,
1449 &spr_read_generic, &spr_write_generic,
1450 0x00000000);
1451
1452 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1453 SPR_NOACCESS, SPR_NOACCESS,
1454 &spr_read_generic, &spr_write_generic,
1455 0x00000000);
1456
1457 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_generic, &spr_write_generic,
1460 0x00000000);
1461
1462 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1463 SPR_NOACCESS, SPR_NOACCESS,
1464 &spr_read_generic, &spr_write_generic,
1465 0x00000000);
1466
1467 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 &spr_read_generic, &spr_write_generic,
1470 0x00000000);
1471
1472 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1473 SPR_NOACCESS, SPR_NOACCESS,
1474 &spr_read_generic, &spr_write_generic,
1475 0x00000000);
1476
1477 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_generic, &spr_write_generic,
1480 0x00000000);
1481
1482 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1483 SPR_NOACCESS, SPR_NOACCESS,
1484 &spr_read_generic, &spr_write_generic,
1485 0x00000000);
1486
1487 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1488 SPR_NOACCESS, SPR_NOACCESS,
1489 &spr_read_generic, &spr_write_generic,
1490 0x00000000);
1491
1492 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_generic, &spr_write_generic,
1495 0x00000000);
1496 }
1497
register_8xx_sprs(CPUPPCState * env)1498 static void register_8xx_sprs(CPUPPCState *env)
1499 {
1500
1501 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1502 SPR_NOACCESS, SPR_NOACCESS,
1503 &spr_read_generic, &spr_write_generic,
1504 0x00000000);
1505
1506 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_generic, &spr_write_generic,
1509 0x00000000);
1510
1511 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1512 SPR_NOACCESS, SPR_NOACCESS,
1513 &spr_read_generic, &spr_write_generic,
1514 0x00000000);
1515
1516 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1517 SPR_NOACCESS, SPR_NOACCESS,
1518 &spr_read_generic, &spr_write_generic,
1519 0x00000000);
1520
1521 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1522 SPR_NOACCESS, SPR_NOACCESS,
1523 &spr_read_generic, &spr_write_generic,
1524 0x00000000);
1525
1526 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1527 SPR_NOACCESS, SPR_NOACCESS,
1528 &spr_read_generic, &spr_write_generic,
1529 0x00000000);
1530
1531 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 &spr_read_generic, &spr_write_generic,
1534 0x00000000);
1535
1536 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1537 SPR_NOACCESS, SPR_NOACCESS,
1538 &spr_read_generic, &spr_write_generic,
1539 0x00000000);
1540
1541 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545
1546 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550
1551 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1552 SPR_NOACCESS, SPR_NOACCESS,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555
1556 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, &spr_write_generic,
1559 0x00000000);
1560
1561 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1562 SPR_NOACCESS, SPR_NOACCESS,
1563 &spr_read_generic, &spr_write_generic,
1564 0x00000000);
1565
1566 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_generic, &spr_write_generic,
1569 0x00000000);
1570
1571 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1572 SPR_NOACCESS, SPR_NOACCESS,
1573 &spr_read_generic, &spr_write_generic,
1574 0x00000000);
1575
1576 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1577 SPR_NOACCESS, SPR_NOACCESS,
1578 &spr_read_generic, &spr_write_generic,
1579 0x00000000);
1580
1581 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1582 SPR_NOACCESS, SPR_NOACCESS,
1583 &spr_read_generic, &spr_write_generic,
1584 0x00000000);
1585
1586 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1587 SPR_NOACCESS, SPR_NOACCESS,
1588 &spr_read_generic, &spr_write_generic,
1589 0x00000000);
1590
1591 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_generic,
1594 0x00000000);
1595
1596 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600
1601 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1602 SPR_NOACCESS, SPR_NOACCESS,
1603 &spr_read_generic, &spr_write_generic,
1604 0x00000000);
1605
1606 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1607 SPR_NOACCESS, SPR_NOACCESS,
1608 &spr_read_generic, &spr_write_generic,
1609 0x00000000);
1610
1611 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_generic,
1614 0x00000000);
1615
1616 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_generic,
1619 0x00000000);
1620
1621 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_generic,
1624 0x00000000);
1625 }
1626
1627 /*
1628 * AMR => SPR 29 (Power 2.04)
1629 * CTRL => SPR 136 (Power 2.04)
1630 * CTRL => SPR 152 (Power 2.04)
1631 * SCOMC => SPR 276 (64 bits ?)
1632 * SCOMD => SPR 277 (64 bits ?)
1633 * TBU40 => SPR 286 (Power 2.04 hypv)
1634 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1635 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1636 * HDSISR => SPR 306 (Power 2.04 hypv)
1637 * HDAR => SPR 307 (Power 2.04 hypv)
1638 * PURR => SPR 309 (Power 2.04 hypv)
1639 * HDEC => SPR 310 (Power 2.04 hypv)
1640 * HIOR => SPR 311 (hypv)
1641 * RMOR => SPR 312 (970)
1642 * HRMOR => SPR 313 (Power 2.04 hypv)
1643 * HSRR0 => SPR 314 (Power 2.04 hypv)
1644 * HSRR1 => SPR 315 (Power 2.04 hypv)
1645 * LPIDR => SPR 317 (970)
1646 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1)
1647 * EPR => SPR 702 (Power 2.04 emb)
1648 * perf => 768-783 (Power 2.04)
1649 * perf => 784-799 (Power 2.04)
1650 * PPR => SPR 896 (Power 2.04)
1651 * DABRX => 1015 (Power 2.04 hypv)
1652 * FPECR => SPR 1022 (?)
1653 * ... and more (thermal management, performance counters, ...)
1654 */
1655
1656 /*****************************************************************************/
1657 /* Exception vectors models */
init_excp_4xx(CPUPPCState * env)1658 static void init_excp_4xx(CPUPPCState *env)
1659 {
1660 #if !defined(CONFIG_USER_ONLY)
1661 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1662 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1663 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1664 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1665 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1666 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1667 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1668 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1669 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1670 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1671 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1672 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1673 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1674 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
1675 env->ivor_mask = 0x0000FFF0UL;
1676 env->ivpr_mask = 0xFFFF0000UL;
1677 /* Hardware reset vector */
1678 env->hreset_vector = 0xFFFFFFFCUL;
1679 #endif
1680 }
1681
init_excp_MPC5xx(CPUPPCState * env)1682 static void init_excp_MPC5xx(CPUPPCState *env)
1683 {
1684 #if !defined(CONFIG_USER_ONLY)
1685 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1686 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1687 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1688 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1689 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1690 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1691 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1692 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1693 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1694 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1695 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1696 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1697 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1698 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1699 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1700 env->ivor_mask = 0x0000FFF0UL;
1701 env->ivpr_mask = 0xFFFF0000UL;
1702 /* Hardware reset vector */
1703 env->hreset_vector = 0x00000100UL;
1704 #endif
1705 }
1706
init_excp_MPC8xx(CPUPPCState * env)1707 static void init_excp_MPC8xx(CPUPPCState *env)
1708 {
1709 #if !defined(CONFIG_USER_ONLY)
1710 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1711 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1712 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1713 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1714 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1715 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1716 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1717 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1718 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1719 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1720 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1721 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1722 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1723 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1724 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1725 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1726 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1727 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1728 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1729 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1730 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
1731 env->ivor_mask = 0x0000FFF0UL;
1732 env->ivpr_mask = 0xFFFF0000UL;
1733 /* Hardware reset vector */
1734 env->hreset_vector = 0x00000100UL;
1735 #endif
1736 }
1737
init_excp_G2(CPUPPCState * env)1738 static void init_excp_G2(CPUPPCState *env)
1739 {
1740 #if !defined(CONFIG_USER_ONLY)
1741 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1742 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1743 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1744 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1745 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1746 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1747 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1748 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1749 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1750 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
1751 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1752 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1753 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1754 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1755 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1756 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1757 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1758 /* Hardware reset vector */
1759 env->hreset_vector = 0x00000100UL;
1760 #endif
1761 }
1762
init_excp_e200(CPUPPCState * env,target_ulong ivpr_mask)1763 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
1764 {
1765 #if !defined(CONFIG_USER_ONLY)
1766 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1767 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1768 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1769 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1770 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1771 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1772 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1773 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1774 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1775 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1776 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1777 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1778 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1779 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1780 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1781 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1782 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1783 /*
1784 * These two are the same IVOR as POWERPC_EXCP_VPU and
1785 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1786 * powerpc_excp().
1787 */
1788 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1789 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
1790
1791 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
1792 env->ivor_mask = 0x0000FFF7UL;
1793 env->ivpr_mask = ivpr_mask;
1794 /* Hardware reset vector */
1795 env->hreset_vector = 0xFFFFFFFCUL;
1796 #endif
1797 }
1798
init_excp_BookE(CPUPPCState * env)1799 static void init_excp_BookE(CPUPPCState *env)
1800 {
1801 #if !defined(CONFIG_USER_ONLY)
1802 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1803 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1804 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1805 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1806 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1807 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1808 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1809 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1810 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1811 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1812 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1813 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1814 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1815 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1816 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1817 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
1818 env->ivor_mask = 0x0000FFF0UL;
1819 env->ivpr_mask = 0xFFFF0000UL;
1820 /* Hardware reset vector */
1821 env->hreset_vector = 0xFFFFFFFCUL;
1822 #endif
1823 }
1824
init_excp_603(CPUPPCState * env)1825 static void init_excp_603(CPUPPCState *env)
1826 {
1827 #if !defined(CONFIG_USER_ONLY)
1828 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1829 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1830 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1831 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1832 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1833 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1834 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1835 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1836 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1837 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1838 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1839 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1840 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1841 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1842 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1843 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1844 /* Hardware reset vector */
1845 env->hreset_vector = 0x00000100UL;
1846 #endif
1847 }
1848
init_excp_604(CPUPPCState * env)1849 static void init_excp_604(CPUPPCState *env)
1850 {
1851 #if !defined(CONFIG_USER_ONLY)
1852 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1853 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1854 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1855 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1856 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1857 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1858 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1859 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1860 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1861 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1862 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1863 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1864 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1865 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1866 /* Hardware reset vector */
1867 env->hreset_vector = 0x00000100UL;
1868 #endif
1869 }
1870
init_excp_7x0(CPUPPCState * env)1871 static void init_excp_7x0(CPUPPCState *env)
1872 {
1873 #if !defined(CONFIG_USER_ONLY)
1874 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1875 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1876 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1877 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1878 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1879 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1880 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1881 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1882 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1883 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1884 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1885 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1886 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1887 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1888 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1889 /* Hardware reset vector */
1890 env->hreset_vector = 0x00000100UL;
1891 #endif
1892 }
1893
init_excp_750cl(CPUPPCState * env)1894 static void init_excp_750cl(CPUPPCState *env)
1895 {
1896 #if !defined(CONFIG_USER_ONLY)
1897 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1898 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1899 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1900 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1901 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1902 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1903 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1904 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1905 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1906 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1907 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1908 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1909 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1910 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1911 /* Hardware reset vector */
1912 env->hreset_vector = 0x00000100UL;
1913 #endif
1914 }
1915
init_excp_750cx(CPUPPCState * env)1916 static void init_excp_750cx(CPUPPCState *env)
1917 {
1918 #if !defined(CONFIG_USER_ONLY)
1919 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1920 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1921 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1922 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1923 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1924 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1925 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1926 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1927 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1928 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1929 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1930 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1931 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1932 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1933 /* Hardware reset vector */
1934 env->hreset_vector = 0x00000100UL;
1935 #endif
1936 }
1937
1938 /* XXX: Check if this is correct */
init_excp_7x5(CPUPPCState * env)1939 static void init_excp_7x5(CPUPPCState *env)
1940 {
1941 #if !defined(CONFIG_USER_ONLY)
1942 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1943 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1944 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1945 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1946 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1947 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1948 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1949 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1950 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1951 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1952 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1953 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1954 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1955 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1956 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1957 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1958 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1959 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1960 /* Hardware reset vector */
1961 env->hreset_vector = 0x00000100UL;
1962 #endif
1963 }
1964
init_excp_7400(CPUPPCState * env)1965 static void init_excp_7400(CPUPPCState *env)
1966 {
1967 #if !defined(CONFIG_USER_ONLY)
1968 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1969 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1970 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1971 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1972 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1973 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1974 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1975 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1976 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1977 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1978 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1979 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1980 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1981 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1982 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1983 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1984 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1985 /* Hardware reset vector */
1986 env->hreset_vector = 0x00000100UL;
1987 #endif
1988 }
1989
init_excp_7450(CPUPPCState * env)1990 static void init_excp_7450(CPUPPCState *env)
1991 {
1992 #if !defined(CONFIG_USER_ONLY)
1993 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1994 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1995 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1996 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1997 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1998 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1999 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2000 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2001 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2002 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2003 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2004 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2005 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2006 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2007 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2008 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2009 /* Hardware reset vector */
2010 env->hreset_vector = 0x00000100UL;
2011 #endif
2012 }
2013
2014 #if defined(TARGET_PPC64)
init_excp_970(CPUPPCState * env)2015 static void init_excp_970(CPUPPCState *env)
2016 {
2017 #if !defined(CONFIG_USER_ONLY)
2018 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2019 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2020 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2021 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2022 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2023 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2024 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2025 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2026 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2027 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2028 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2029 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2030 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2031 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2032 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2033 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2034 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2035 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2036 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2037 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
2038 /* Hardware reset vector */
2039 env->hreset_vector = 0x0000000000000100ULL;
2040 #endif
2041 }
2042
init_excp_POWER7(CPUPPCState * env)2043 static void init_excp_POWER7(CPUPPCState *env)
2044 {
2045 #if !defined(CONFIG_USER_ONLY)
2046 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2047 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2048 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2049 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2050 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2051 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2052 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2053 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2054 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2055 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2056 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2057 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2058 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2059 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2060 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2061 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2062 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2063 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
2064 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2065 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2066 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
2067 /* Hardware reset vector */
2068 env->hreset_vector = 0x0000000000000100ULL;
2069 #endif
2070 }
2071
init_excp_POWER8(CPUPPCState * env)2072 static void init_excp_POWER8(CPUPPCState *env)
2073 {
2074 init_excp_POWER7(env);
2075
2076 #if !defined(CONFIG_USER_ONLY)
2077 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2078 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2079 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2080 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
2081
2082 /* Userland exceptions without vector value in PowerISA v3.1 */
2083 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2084 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
2085 #endif
2086 }
2087
init_excp_POWER9(CPUPPCState * env)2088 static void init_excp_POWER9(CPUPPCState *env)
2089 {
2090 init_excp_POWER8(env);
2091
2092 #if !defined(CONFIG_USER_ONLY)
2093 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
2094 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
2095 #endif
2096 }
2097
init_excp_POWER10(CPUPPCState * env)2098 static void init_excp_POWER10(CPUPPCState *env)
2099 {
2100 init_excp_POWER9(env);
2101 }
2102
2103 #endif
2104
check_pow_hid0(CPUPPCState * env)2105 static int check_pow_hid0(CPUPPCState *env)
2106 {
2107 if (env->spr[SPR_HID0] & 0x00E00000) {
2108 return 1;
2109 }
2110
2111 return 0;
2112 }
2113
check_pow_hid0_74xx(CPUPPCState * env)2114 static int check_pow_hid0_74xx(CPUPPCState *env)
2115 {
2116 if (env->spr[SPR_HID0] & 0x00600000) {
2117 return 1;
2118 }
2119
2120 return 0;
2121 }
2122
2123 #if defined(TARGET_PPC64)
check_attn_hid0(CPUPPCState * env)2124 static int check_attn_hid0(CPUPPCState *env)
2125 {
2126 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) {
2127 return 1;
2128 }
2129
2130 return 0;
2131 }
2132
check_attn_hid0_power9(CPUPPCState * env)2133 static int check_attn_hid0_power9(CPUPPCState *env)
2134 {
2135 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) {
2136 return 1;
2137 }
2138
2139 return 0;
2140 }
2141 #endif
2142
init_tlbs_emb(CPUPPCState * env)2143 static void init_tlbs_emb(CPUPPCState *env)
2144 {
2145 #ifndef CONFIG_USER_ONLY
2146 env->nb_tlb = 64;
2147 env->nb_ways = 1;
2148 env->tlb_type = TLB_EMB;
2149 #endif
2150 }
2151
init_proc_405(CPUPPCState * env)2152 static void init_proc_405(CPUPPCState *env)
2153 {
2154 register_40x_sprs(env);
2155 register_405_sprs(env);
2156 register_usprgh_sprs(env);
2157
2158 init_tlbs_emb(env);
2159 init_excp_4xx(env);
2160 env->dcache_line_size = 32;
2161 env->icache_line_size = 32;
2162 /* Allocate hardware IRQ controller */
2163 ppc40x_irq_init(env_archcpu(env));
2164
2165 SET_FIT_PERIOD(8, 12, 16, 20);
2166 SET_WDT_PERIOD(16, 20, 24, 28);
2167 }
2168
2169 POWERPC_FAMILY(405)(ObjectClass *oc, const void *data)
2170 {
2171 DeviceClass *dc = DEVICE_CLASS(oc);
2172 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2173
2174 dc->desc = "PowerPC 405";
2175 pcc->init_proc = init_proc_405;
2176 pcc->check_pow = check_pow_nocheck;
2177 pcc->check_attn = check_attn_none;
2178 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2179 PPC_DCR | PPC_WRTEE |
2180 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2181 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2182 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2183 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2184 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
2185 pcc->msr_mask = (1ull << MSR_WE) |
2186 (1ull << MSR_CE) |
2187 (1ull << MSR_EE) |
2188 (1ull << MSR_PR) |
2189 (1ull << MSR_FP) |
2190 (1ull << MSR_ME) |
2191 (1ull << MSR_DWE) |
2192 (1ull << MSR_DE) |
2193 (1ull << MSR_IR) |
2194 (1ull << MSR_DR);
2195 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2196 pcc->excp_model = POWERPC_EXCP_40x;
2197 pcc->bus_model = PPC_FLAGS_INPUT_405;
2198 pcc->bfd_mach = bfd_mach_ppc_403;
2199 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2200 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2201 }
2202
init_proc_440EP(CPUPPCState * env)2203 static void init_proc_440EP(CPUPPCState *env)
2204 {
2205 register_BookE_sprs(env, 0x000000000000FFFFULL);
2206 register_440_sprs(env);
2207 register_usprgh_sprs(env);
2208
2209 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2210 SPR_NOACCESS, SPR_NOACCESS,
2211 &spr_read_generic, &spr_write_generic,
2212 0x00000000);
2213 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2214 SPR_NOACCESS, SPR_NOACCESS,
2215 &spr_read_generic, &spr_write_generic,
2216 0x00000000);
2217 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2218 SPR_NOACCESS, SPR_NOACCESS,
2219 &spr_read_generic, &spr_write_generic,
2220 0x00000000);
2221
2222 spr_register(env, SPR_440_CCR1, "CCR1",
2223 SPR_NOACCESS, SPR_NOACCESS,
2224 &spr_read_generic, &spr_write_generic,
2225 0x00000000);
2226
2227 init_tlbs_emb(env);
2228 init_excp_BookE(env);
2229 env->dcache_line_size = 32;
2230 env->icache_line_size = 32;
2231 ppc40x_irq_init(env_archcpu(env));
2232
2233 SET_FIT_PERIOD(12, 16, 20, 24);
2234 SET_WDT_PERIOD(20, 24, 28, 32);
2235 }
2236
2237 POWERPC_FAMILY(440EP)(ObjectClass *oc, const void *data)
2238 {
2239 DeviceClass *dc = DEVICE_CLASS(oc);
2240 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2241
2242 dc->desc = "PowerPC 440 EP";
2243 pcc->init_proc = init_proc_440EP;
2244 pcc->check_pow = check_pow_nocheck;
2245 pcc->check_attn = check_attn_none;
2246 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2247 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2248 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2249 PPC_FLOAT_STFIWX |
2250 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2251 PPC_CACHE | PPC_CACHE_ICBI |
2252 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2253 PPC_MEM_TLBSYNC | PPC_MFTB |
2254 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2255 PPC_440_SPEC;
2256 pcc->msr_mask = (1ull << MSR_POW) |
2257 (1ull << MSR_CE) |
2258 (1ull << MSR_EE) |
2259 (1ull << MSR_PR) |
2260 (1ull << MSR_FP) |
2261 (1ull << MSR_ME) |
2262 (1ull << MSR_FE0) |
2263 (1ull << MSR_DWE) |
2264 (1ull << MSR_DE) |
2265 (1ull << MSR_FE1) |
2266 (1ull << MSR_IR) |
2267 (1ull << MSR_DR);
2268 pcc->mmu_model = POWERPC_MMU_BOOKE;
2269 pcc->excp_model = POWERPC_EXCP_BOOKE;
2270 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2271 pcc->bfd_mach = bfd_mach_ppc_403;
2272 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2273 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2274 }
2275
2276 POWERPC_FAMILY(460EX)(ObjectClass *oc, const void *data)
2277 {
2278 DeviceClass *dc = DEVICE_CLASS(oc);
2279 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2280
2281 dc->desc = "PowerPC 460 EX";
2282 pcc->init_proc = init_proc_440EP;
2283 pcc->check_pow = check_pow_nocheck;
2284 pcc->check_attn = check_attn_none;
2285 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2286 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2287 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2288 PPC_FLOAT_STFIWX |
2289 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2290 PPC_CACHE | PPC_CACHE_ICBI |
2291 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2292 PPC_MEM_TLBSYNC | PPC_MFTB |
2293 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2294 PPC_440_SPEC;
2295 pcc->msr_mask = (1ull << MSR_POW) |
2296 (1ull << MSR_CE) |
2297 (1ull << MSR_EE) |
2298 (1ull << MSR_PR) |
2299 (1ull << MSR_FP) |
2300 (1ull << MSR_ME) |
2301 (1ull << MSR_FE0) |
2302 (1ull << MSR_DWE) |
2303 (1ull << MSR_DE) |
2304 (1ull << MSR_FE1) |
2305 (1ull << MSR_IR) |
2306 (1ull << MSR_DR);
2307 pcc->mmu_model = POWERPC_MMU_BOOKE;
2308 pcc->excp_model = POWERPC_EXCP_BOOKE;
2309 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2310 pcc->bfd_mach = bfd_mach_ppc_403;
2311 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2312 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2313 }
2314
init_proc_440GP(CPUPPCState * env)2315 static void init_proc_440GP(CPUPPCState *env)
2316 {
2317 register_BookE_sprs(env, 0x000000000000FFFFULL);
2318 register_440_sprs(env);
2319 register_usprgh_sprs(env);
2320
2321 init_tlbs_emb(env);
2322 init_excp_BookE(env);
2323 env->dcache_line_size = 32;
2324 env->icache_line_size = 32;
2325 /* XXX: TODO: allocate internal IRQ controller */
2326
2327 SET_FIT_PERIOD(12, 16, 20, 24);
2328 SET_WDT_PERIOD(20, 24, 28, 32);
2329 }
2330
2331 POWERPC_FAMILY(440GP)(ObjectClass *oc, const void *data)
2332 {
2333 DeviceClass *dc = DEVICE_CLASS(oc);
2334 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2335
2336 dc->desc = "PowerPC 440 GP";
2337 pcc->init_proc = init_proc_440GP;
2338 pcc->check_pow = check_pow_nocheck;
2339 pcc->check_attn = check_attn_none;
2340 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2341 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2342 PPC_CACHE | PPC_CACHE_ICBI |
2343 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2344 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2345 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2346 PPC_440_SPEC;
2347 pcc->msr_mask = (1ull << MSR_POW) |
2348 (1ull << MSR_CE) |
2349 (1ull << MSR_EE) |
2350 (1ull << MSR_PR) |
2351 (1ull << MSR_FP) |
2352 (1ull << MSR_ME) |
2353 (1ull << MSR_FE0) |
2354 (1ull << MSR_DWE) |
2355 (1ull << MSR_DE) |
2356 (1ull << MSR_FE1) |
2357 (1ull << MSR_IR) |
2358 (1ull << MSR_DR);
2359 pcc->mmu_model = POWERPC_MMU_BOOKE;
2360 pcc->excp_model = POWERPC_EXCP_BOOKE;
2361 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2362 pcc->bfd_mach = bfd_mach_ppc_403;
2363 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2364 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2365 }
2366
init_proc_440x5(CPUPPCState * env)2367 static void init_proc_440x5(CPUPPCState *env)
2368 {
2369 register_BookE_sprs(env, 0x000000000000FFFFULL);
2370 register_440_sprs(env);
2371 register_usprgh_sprs(env);
2372
2373 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_generic,
2380 0x00000000);
2381 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385
2386 spr_register(env, SPR_440_CCR1, "CCR1",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390
2391 init_tlbs_emb(env);
2392 init_excp_BookE(env);
2393 env->dcache_line_size = 32;
2394 env->icache_line_size = 32;
2395 ppc40x_irq_init(env_archcpu(env));
2396
2397 SET_FIT_PERIOD(12, 16, 20, 24);
2398 SET_WDT_PERIOD(20, 24, 28, 32);
2399 }
2400
2401 POWERPC_FAMILY(440x5)(ObjectClass *oc, const void *data)
2402 {
2403 DeviceClass *dc = DEVICE_CLASS(oc);
2404 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2405
2406 dc->desc = "PowerPC 440x5";
2407 pcc->init_proc = init_proc_440x5;
2408 pcc->check_pow = check_pow_nocheck;
2409 pcc->check_attn = check_attn_none;
2410 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2411 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2412 PPC_CACHE | PPC_CACHE_ICBI |
2413 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2414 PPC_MEM_TLBSYNC | PPC_MFTB |
2415 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2416 PPC_440_SPEC;
2417 pcc->msr_mask = (1ull << MSR_POW) |
2418 (1ull << MSR_CE) |
2419 (1ull << MSR_EE) |
2420 (1ull << MSR_PR) |
2421 (1ull << MSR_FP) |
2422 (1ull << MSR_ME) |
2423 (1ull << MSR_FE0) |
2424 (1ull << MSR_DWE) |
2425 (1ull << MSR_DE) |
2426 (1ull << MSR_FE1) |
2427 (1ull << MSR_IR) |
2428 (1ull << MSR_DR);
2429 pcc->mmu_model = POWERPC_MMU_BOOKE;
2430 pcc->excp_model = POWERPC_EXCP_BOOKE;
2431 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2432 pcc->bfd_mach = bfd_mach_ppc_403;
2433 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2434 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2435 }
2436
2437 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, const void *data)
2438 {
2439 DeviceClass *dc = DEVICE_CLASS(oc);
2440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2441
2442 dc->desc = "PowerPC 440x5 with double precision FPU";
2443 pcc->init_proc = init_proc_440x5;
2444 pcc->check_pow = check_pow_nocheck;
2445 pcc->check_attn = check_attn_none;
2446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2447 PPC_FLOAT | PPC_FLOAT_FSQRT |
2448 PPC_FLOAT_STFIWX |
2449 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2450 PPC_CACHE | PPC_CACHE_ICBI |
2451 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2452 PPC_MEM_TLBSYNC | PPC_MFTB |
2453 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2454 PPC_440_SPEC;
2455 pcc->insns_flags2 = PPC2_FP_CVT_S64;
2456 pcc->msr_mask = (1ull << MSR_POW) |
2457 (1ull << MSR_CE) |
2458 (1ull << MSR_EE) |
2459 (1ull << MSR_PR) |
2460 (1ull << MSR_FP) |
2461 (1ull << MSR_ME) |
2462 (1ull << MSR_FE0) |
2463 (1ull << MSR_DWE) |
2464 (1ull << MSR_DE) |
2465 (1ull << MSR_FE1) |
2466 (1ull << MSR_IR) |
2467 (1ull << MSR_DR);
2468 pcc->mmu_model = POWERPC_MMU_BOOKE;
2469 pcc->excp_model = POWERPC_EXCP_BOOKE;
2470 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2471 pcc->bfd_mach = bfd_mach_ppc_403;
2472 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2473 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2474 }
2475
init_proc_MPC5xx(CPUPPCState * env)2476 static void init_proc_MPC5xx(CPUPPCState *env)
2477 {
2478 register_5xx_8xx_sprs(env);
2479 register_5xx_sprs(env);
2480 init_excp_MPC5xx(env);
2481 env->dcache_line_size = 32;
2482 env->icache_line_size = 32;
2483 /* XXX: TODO: allocate internal IRQ controller */
2484 }
2485
POWERPC_FAMILY(MPC5xx)2486 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, const void *data)
2487 {
2488 DeviceClass *dc = DEVICE_CLASS(oc);
2489 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2490
2491 dc->desc = "Freescale 5xx cores (aka RCPU)";
2492 pcc->init_proc = init_proc_MPC5xx;
2493 pcc->check_pow = check_pow_none;
2494 pcc->check_attn = check_attn_none;
2495 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2496 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2497 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2498 PPC_MFTB;
2499 pcc->msr_mask = (1ull << MSR_ILE) |
2500 (1ull << MSR_EE) |
2501 (1ull << MSR_PR) |
2502 (1ull << MSR_FP) |
2503 (1ull << MSR_ME) |
2504 (1ull << MSR_FE0) |
2505 (1ull << MSR_SE) |
2506 (1ull << MSR_DE) |
2507 (1ull << MSR_FE1) |
2508 (1ull << MSR_EP) |
2509 (1ull << MSR_RI) |
2510 (1ull << MSR_LE);
2511 pcc->mmu_model = POWERPC_MMU_REAL;
2512 pcc->excp_model = POWERPC_EXCP_6xx;
2513 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2514 pcc->bfd_mach = bfd_mach_ppc_505;
2515 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2516 POWERPC_FLAG_BUS_CLK;
2517 }
2518
init_proc_MPC8xx(CPUPPCState * env)2519 static void init_proc_MPC8xx(CPUPPCState *env)
2520 {
2521 register_5xx_8xx_sprs(env);
2522 register_8xx_sprs(env);
2523 init_excp_MPC8xx(env);
2524 env->dcache_line_size = 32;
2525 env->icache_line_size = 32;
2526 /* XXX: TODO: allocate internal IRQ controller */
2527 }
2528
POWERPC_FAMILY(MPC8xx)2529 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, const void *data)
2530 {
2531 DeviceClass *dc = DEVICE_CLASS(oc);
2532 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2533
2534 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
2535 pcc->init_proc = init_proc_MPC8xx;
2536 pcc->check_pow = check_pow_none;
2537 pcc->check_attn = check_attn_none;
2538 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2539 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2540 PPC_CACHE_ICBI | PPC_MFTB;
2541 pcc->msr_mask = (1ull << MSR_ILE) |
2542 (1ull << MSR_EE) |
2543 (1ull << MSR_PR) |
2544 (1ull << MSR_FP) |
2545 (1ull << MSR_ME) |
2546 (1ull << MSR_SE) |
2547 (1ull << MSR_DE) |
2548 (1ull << MSR_EP) |
2549 (1ull << MSR_IR) |
2550 (1ull << MSR_DR) |
2551 (1ull << MSR_RI) |
2552 (1ull << MSR_LE);
2553 pcc->mmu_model = POWERPC_MMU_MPC8xx;
2554 pcc->excp_model = POWERPC_EXCP_6xx;
2555 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2556 pcc->bfd_mach = bfd_mach_ppc_860;
2557 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2558 POWERPC_FLAG_BUS_CLK;
2559 }
2560
2561 /* Freescale 82xx cores (aka PowerQUICC-II) */
2562
init_proc_G2(CPUPPCState * env)2563 static void init_proc_G2(CPUPPCState *env)
2564 {
2565 register_non_embedded_sprs(env);
2566 register_sdr1_sprs(env);
2567 register_G2_sprs(env);
2568
2569 /* Memory management */
2570 register_low_BATs(env);
2571 register_high_BATs(env);
2572 register_6xx_7xx_soft_tlb(env, 64, 2);
2573 init_excp_G2(env);
2574 env->dcache_line_size = 32;
2575 env->icache_line_size = 32;
2576 /* Allocate hardware IRQ controller */
2577 ppc6xx_irq_init(env_archcpu(env));
2578 }
2579
POWERPC_FAMILY(G2)2580 POWERPC_FAMILY(G2)(ObjectClass *oc, const void *data)
2581 {
2582 DeviceClass *dc = DEVICE_CLASS(oc);
2583 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2584
2585 dc->desc = "PowerPC G2";
2586 pcc->init_proc = init_proc_G2;
2587 pcc->check_pow = check_pow_hid0;
2588 pcc->check_attn = check_attn_none;
2589 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2590 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2591 PPC_FLOAT_STFIWX |
2592 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2593 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2594 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2595 PPC_SEGMENT | PPC_EXTERN;
2596 pcc->msr_mask = (1ull << MSR_POW) |
2597 (1ull << MSR_TGPR) |
2598 (1ull << MSR_EE) |
2599 (1ull << MSR_PR) |
2600 (1ull << MSR_FP) |
2601 (1ull << MSR_ME) |
2602 (1ull << MSR_FE0) |
2603 (1ull << MSR_SE) |
2604 (1ull << MSR_DE) |
2605 (1ull << MSR_FE1) |
2606 (1ull << MSR_AL) |
2607 (1ull << MSR_EP) |
2608 (1ull << MSR_IR) |
2609 (1ull << MSR_DR) |
2610 (1ull << MSR_RI);
2611 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2612 pcc->excp_model = POWERPC_EXCP_6xx;
2613 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2614 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2615 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2616 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2617 }
2618
POWERPC_FAMILY(G2LE)2619 POWERPC_FAMILY(G2LE)(ObjectClass *oc, const void *data)
2620 {
2621 DeviceClass *dc = DEVICE_CLASS(oc);
2622 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2623
2624 dc->desc = "PowerPC G2LE";
2625 pcc->init_proc = init_proc_G2;
2626 pcc->check_pow = check_pow_hid0;
2627 pcc->check_attn = check_attn_none;
2628 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2629 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2630 PPC_FLOAT_STFIWX |
2631 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2632 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2633 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2634 PPC_SEGMENT | PPC_EXTERN;
2635 pcc->msr_mask = (1ull << MSR_POW) |
2636 (1ull << MSR_TGPR) |
2637 (1ull << MSR_ILE) |
2638 (1ull << MSR_EE) |
2639 (1ull << MSR_PR) |
2640 (1ull << MSR_FP) |
2641 (1ull << MSR_ME) |
2642 (1ull << MSR_FE0) |
2643 (1ull << MSR_SE) |
2644 (1ull << MSR_DE) |
2645 (1ull << MSR_FE1) |
2646 (1ull << MSR_AL) |
2647 (1ull << MSR_EP) |
2648 (1ull << MSR_IR) |
2649 (1ull << MSR_DR) |
2650 (1ull << MSR_RI) |
2651 (1ull << MSR_LE);
2652 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
2653 pcc->excp_model = POWERPC_EXCP_6xx;
2654 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2655 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2656 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2657 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
2658 }
2659
init_proc_e200(CPUPPCState * env)2660 static void init_proc_e200(CPUPPCState *env)
2661 {
2662 register_BookE_sprs(env, 0x000000070000FFFFULL);
2663
2664 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2665 &spr_read_spefscr, &spr_write_spefscr,
2666 &spr_read_spefscr, &spr_write_spefscr,
2667 0x00000000);
2668 /* Memory management */
2669 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
2670 register_usprgh_sprs(env);
2671
2672 spr_register(env, SPR_HID0, "HID0",
2673 SPR_NOACCESS, SPR_NOACCESS,
2674 &spr_read_generic, &spr_write_generic,
2675 0x00000000);
2676
2677 spr_register(env, SPR_HID1, "HID1",
2678 SPR_NOACCESS, SPR_NOACCESS,
2679 &spr_read_generic, &spr_write_generic,
2680 0x00000000);
2681
2682 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
2683 SPR_NOACCESS, SPR_NOACCESS,
2684 &spr_read_generic, &spr_write_generic,
2685 0x00000000);
2686
2687 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2688 SPR_NOACCESS, SPR_NOACCESS,
2689 &spr_read_generic, &spr_write_generic,
2690 0x00000000);
2691
2692 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2693 SPR_NOACCESS, SPR_NOACCESS,
2694 &spr_read_generic, &spr_write_generic,
2695 0x00000000);
2696
2697 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2698 SPR_NOACCESS, SPR_NOACCESS,
2699 &spr_read_generic, &spr_write_generic,
2700 0x00000000);
2701
2702 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2703 SPR_NOACCESS, SPR_NOACCESS,
2704 &spr_read_generic, &spr_write_generic,
2705 0x00000000);
2706
2707 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2708 &spr_read_generic, SPR_NOACCESS,
2709 &spr_read_generic, SPR_NOACCESS,
2710 0x00000000);
2711
2712 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2713 SPR_NOACCESS, SPR_NOACCESS,
2714 &spr_read_generic, &spr_write_generic,
2715 0x00000000);
2716
2717 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2718 SPR_NOACCESS, SPR_NOACCESS,
2719 &spr_read_generic, &spr_write_generic,
2720 0x00000000);
2721
2722 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2723 SPR_NOACCESS, SPR_NOACCESS,
2724 &spr_read_generic, &spr_write_generic,
2725 0x00000000);
2726
2727 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2728 SPR_NOACCESS, SPR_NOACCESS,
2729 &spr_read_generic, &spr_write_generic,
2730 0x00000000);
2731
2732 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2733 SPR_NOACCESS, SPR_NOACCESS,
2734 &spr_read_generic, &spr_write_generic,
2735 0x00000000);
2736
2737 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2738 SPR_NOACCESS, SPR_NOACCESS,
2739 &spr_read_generic, &spr_write_generic,
2740 0x00000000);
2741
2742 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2743 SPR_NOACCESS, SPR_NOACCESS,
2744 &spr_read_generic, &spr_write_generic,
2745 0x00000000); /* TOFIX */
2746
2747 init_tlbs_emb(env);
2748 init_excp_e200(env, 0xFFFF0000UL);
2749 env->dcache_line_size = 32;
2750 env->icache_line_size = 32;
2751 /* XXX: TODO: allocate internal IRQ controller */
2752 }
2753
POWERPC_FAMILY(e200)2754 POWERPC_FAMILY(e200)(ObjectClass *oc, const void *data)
2755 {
2756 DeviceClass *dc = DEVICE_CLASS(oc);
2757 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2758
2759 dc->desc = "e200 core";
2760 pcc->init_proc = init_proc_e200;
2761 pcc->check_pow = check_pow_hid0;
2762 pcc->check_attn = check_attn_none;
2763 /*
2764 * XXX: unimplemented instructions:
2765 * dcblc
2766 * dcbtlst
2767 * dcbtstls
2768 * icblc
2769 * icbtls
2770 * tlbivax
2771 * all SPE multiply-accumulate instructions
2772 */
2773 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2774 PPC_SPE | PPC_SPE_SINGLE |
2775 PPC_WRTEE | PPC_RFDI |
2776 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2777 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2778 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2779 PPC_BOOKE;
2780 pcc->msr_mask = (1ull << MSR_UCLE) |
2781 (1ull << MSR_SPE) |
2782 (1ull << MSR_POW) |
2783 (1ull << MSR_CE) |
2784 (1ull << MSR_EE) |
2785 (1ull << MSR_PR) |
2786 (1ull << MSR_FP) |
2787 (1ull << MSR_ME) |
2788 (1ull << MSR_FE0) |
2789 (1ull << MSR_DWE) |
2790 (1ull << MSR_DE) |
2791 (1ull << MSR_FE1) |
2792 (1ull << MSR_IR) |
2793 (1ull << MSR_DR);
2794 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2795 pcc->excp_model = POWERPC_EXCP_BOOKE;
2796 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2797 pcc->bfd_mach = bfd_mach_ppc_860;
2798 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2799 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2800 POWERPC_FLAG_BUS_CLK;
2801 }
2802
2803 enum fsl_e500_version {
2804 fsl_e500v1,
2805 fsl_e500v2,
2806 fsl_e500mc,
2807 fsl_e5500,
2808 fsl_e6500,
2809 };
2810
init_proc_e500(CPUPPCState * env,int version)2811 static void init_proc_e500(CPUPPCState *env, int version)
2812 {
2813 uint32_t tlbncfg[2];
2814 uint64_t ivor_mask;
2815 uint64_t ivpr_mask = 0xFFFF0000ULL;
2816 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2817 | 0x0020; /* 32 kb */
2818 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2819 | 0x0020; /* 32 kb */
2820 uint32_t mmucfg = 0;
2821 #if !defined(CONFIG_USER_ONLY)
2822 int i;
2823 #endif
2824
2825 /*
2826 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2827 * complain when accessing them.
2828 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
2829 */
2830 switch (version) {
2831 case fsl_e500v1:
2832 case fsl_e500v2:
2833 default:
2834 ivor_mask = 0x0000000F0000FFFFULL;
2835 break;
2836 case fsl_e500mc:
2837 case fsl_e5500:
2838 ivor_mask = 0x000003FE0000FFFFULL;
2839 break;
2840 case fsl_e6500:
2841 ivor_mask = 0x000003FF0000FFFFULL;
2842 break;
2843 }
2844 register_BookE_sprs(env, ivor_mask);
2845
2846 spr_register(env, SPR_USPRG3, "USPRG3",
2847 &spr_read_ureg, SPR_NOACCESS,
2848 &spr_read_ureg, SPR_NOACCESS,
2849 0x00000000);
2850
2851 /* Processor identification */
2852 spr_register(env, SPR_BOOKE_PIR, "PIR",
2853 SPR_NOACCESS, SPR_NOACCESS,
2854 &spr_read_generic, &spr_write_pir,
2855 0x00000000);
2856
2857 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
2858 &spr_read_spefscr, &spr_write_spefscr,
2859 &spr_read_spefscr, &spr_write_spefscr,
2860 0x00000000);
2861 #if !defined(CONFIG_USER_ONLY)
2862 /* Memory management */
2863 env->nb_pids = 3;
2864 env->nb_ways = 2;
2865 switch (version) {
2866 case fsl_e500v1:
2867 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2868 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2869 break;
2870 case fsl_e500v2:
2871 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2872 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
2873 break;
2874 case fsl_e500mc:
2875 case fsl_e5500:
2876 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2877 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
2878 break;
2879 case fsl_e6500:
2880 mmucfg = 0x6510B45;
2881 env->nb_pids = 1;
2882 tlbncfg[0] = 0x08052400;
2883 tlbncfg[1] = 0x40028040;
2884 break;
2885 default:
2886 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2887 env->spr[SPR_PVR]);
2888 }
2889 #endif
2890 /* Cache sizes */
2891 switch (version) {
2892 case fsl_e500v1:
2893 case fsl_e500v2:
2894 env->dcache_line_size = 32;
2895 env->icache_line_size = 32;
2896 break;
2897 case fsl_e500mc:
2898 case fsl_e5500:
2899 env->dcache_line_size = 64;
2900 env->icache_line_size = 64;
2901 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
2902 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
2903 break;
2904 case fsl_e6500:
2905 env->dcache_line_size = 32;
2906 env->icache_line_size = 32;
2907 l1cfg0 |= 0x0F83820;
2908 l1cfg1 |= 0x0B83820;
2909 break;
2910 default:
2911 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
2912 env->spr[SPR_PVR]);
2913 }
2914 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
2915 register_usprgh_sprs(env);
2916
2917 if (version != fsl_e500v1) {
2918 /* e500v1 has no support for alternate timebase */
2919 register_atb_sprs(env);
2920 }
2921
2922 spr_register(env, SPR_HID0, "HID0",
2923 SPR_NOACCESS, SPR_NOACCESS,
2924 &spr_read_generic, &spr_write_generic,
2925 0x00000000);
2926
2927 spr_register(env, SPR_HID1, "HID1",
2928 SPR_NOACCESS, SPR_NOACCESS,
2929 &spr_read_generic, &spr_write_generic,
2930 0x00000000);
2931
2932 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2933 SPR_NOACCESS, SPR_NOACCESS,
2934 &spr_read_generic, &spr_write_generic,
2935 0x00000000);
2936
2937 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2938 SPR_NOACCESS, SPR_NOACCESS,
2939 &spr_read_generic, &spr_write_generic,
2940 0x00000000);
2941
2942 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2943 SPR_NOACCESS, SPR_NOACCESS,
2944 &spr_read_generic, &spr_write_generic,
2945 0x00000000);
2946
2947 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2948 SPR_NOACCESS, SPR_NOACCESS,
2949 &spr_read_generic, &spr_write_generic,
2950 0x00000000);
2951
2952 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
2953 SPR_NOACCESS, SPR_NOACCESS,
2954 &spr_read_generic, &spr_write_generic,
2955 0x00000000);
2956
2957 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2958 SPR_NOACCESS, SPR_NOACCESS,
2959 &spr_read_generic, &spr_write_generic,
2960 0x00000000);
2961
2962 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
2963 &spr_read_generic, SPR_NOACCESS,
2964 &spr_read_generic, SPR_NOACCESS,
2965 l1cfg0);
2966 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2967 &spr_read_generic, SPR_NOACCESS,
2968 &spr_read_generic, SPR_NOACCESS,
2969 l1cfg1);
2970 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2971 SPR_NOACCESS, SPR_NOACCESS,
2972 &spr_read_generic, &spr_write_e500_l1csr0,
2973 0x00000000);
2974 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2975 SPR_NOACCESS, SPR_NOACCESS,
2976 &spr_read_generic, &spr_write_e500_l1csr1,
2977 0x00000000);
2978 if (version != fsl_e500v1 && version != fsl_e500v2) {
2979 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2980 SPR_NOACCESS, SPR_NOACCESS,
2981 &spr_read_generic, &spr_write_e500_l2csr0,
2982 0x00000000);
2983 }
2984 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2985 SPR_NOACCESS, SPR_NOACCESS,
2986 &spr_read_generic, &spr_write_generic,
2987 0x00000000);
2988 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2989 SPR_NOACCESS, SPR_NOACCESS,
2990 &spr_read_generic, &spr_write_generic,
2991 0x00000000);
2992 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2993 SPR_NOACCESS, SPR_NOACCESS,
2994 &spr_read_generic, &spr_write_booke206_mmucsr0,
2995 0x00000000);
2996 spr_register(env, SPR_BOOKE_EPR, "EPR",
2997 SPR_NOACCESS, SPR_NOACCESS,
2998 &spr_read_generic, SPR_NOACCESS,
2999 0x00000000);
3000 /* XXX better abstract into Emb.xxx features */
3001 if ((version == fsl_e5500) || (version == fsl_e6500)) {
3002 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
3003 SPR_NOACCESS, SPR_NOACCESS,
3004 &spr_read_generic, &spr_write_generic,
3005 0x00000000);
3006 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
3007 SPR_NOACCESS, SPR_NOACCESS,
3008 &spr_read_mas73, &spr_write_mas73,
3009 0x00000000);
3010 ivpr_mask = (target_ulong)~0xFFFFULL;
3011 }
3012
3013 if (version == fsl_e6500) {
3014 /* Thread identification */
3015 spr_register(env, SPR_TIR, "TIR",
3016 SPR_NOACCESS, SPR_NOACCESS,
3017 &spr_read_generic, SPR_NOACCESS,
3018 0x00000000);
3019 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
3020 SPR_NOACCESS, SPR_NOACCESS,
3021 &spr_read_generic, SPR_NOACCESS,
3022 0x00000004);
3023 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3024 SPR_NOACCESS, SPR_NOACCESS,
3025 &spr_read_generic, SPR_NOACCESS,
3026 0x7FFFFFFC);
3027 }
3028
3029 #if !defined(CONFIG_USER_ONLY)
3030 env->nb_tlb = 0;
3031 env->tlb_type = TLB_MAS;
3032 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3033 env->nb_tlb += booke206_tlb_size(env, i);
3034 }
3035 #endif
3036
3037 init_excp_e200(env, ivpr_mask);
3038 /* Allocate hardware IRQ controller */
3039 ppce500_irq_init(env_archcpu(env));
3040 }
3041
init_proc_e500v1(CPUPPCState * env)3042 static void init_proc_e500v1(CPUPPCState *env)
3043 {
3044 init_proc_e500(env, fsl_e500v1);
3045 }
3046
POWERPC_FAMILY(e500v1)3047 POWERPC_FAMILY(e500v1)(ObjectClass *oc, const void *data)
3048 {
3049 DeviceClass *dc = DEVICE_CLASS(oc);
3050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3051
3052 dc->desc = "e500v1 core";
3053 pcc->init_proc = init_proc_e500v1;
3054 pcc->check_pow = check_pow_hid0;
3055 pcc->check_attn = check_attn_none;
3056 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3057 PPC_SPE | PPC_SPE_SINGLE |
3058 PPC_WRTEE | PPC_RFDI |
3059 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3060 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3061 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3062 pcc->insns_flags2 = PPC2_BOOKE206;
3063 pcc->msr_mask = (1ull << MSR_UCLE) |
3064 (1ull << MSR_SPE) |
3065 (1ull << MSR_POW) |
3066 (1ull << MSR_CE) |
3067 (1ull << MSR_EE) |
3068 (1ull << MSR_PR) |
3069 (1ull << MSR_FP) |
3070 (1ull << MSR_ME) |
3071 (1ull << MSR_FE0) |
3072 (1ull << MSR_DWE) |
3073 (1ull << MSR_DE) |
3074 (1ull << MSR_FE1) |
3075 (1ull << MSR_IR) |
3076 (1ull << MSR_DR);
3077 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3078 pcc->excp_model = POWERPC_EXCP_BOOKE;
3079 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3080 pcc->bfd_mach = bfd_mach_ppc_860;
3081 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3082 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3083 POWERPC_FLAG_BUS_CLK;
3084 }
3085
init_proc_e500v2(CPUPPCState * env)3086 static void init_proc_e500v2(CPUPPCState *env)
3087 {
3088 init_proc_e500(env, fsl_e500v2);
3089 }
3090
POWERPC_FAMILY(e500v2)3091 POWERPC_FAMILY(e500v2)(ObjectClass *oc, const void *data)
3092 {
3093 DeviceClass *dc = DEVICE_CLASS(oc);
3094 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3095
3096 dc->desc = "e500v2 core";
3097 pcc->init_proc = init_proc_e500v2;
3098 pcc->check_pow = check_pow_hid0;
3099 pcc->check_attn = check_attn_none;
3100 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3101 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3102 PPC_WRTEE | PPC_RFDI |
3103 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3104 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3105 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3106 pcc->insns_flags2 = PPC2_BOOKE206;
3107 pcc->msr_mask = (1ull << MSR_UCLE) |
3108 (1ull << MSR_SPE) |
3109 (1ull << MSR_POW) |
3110 (1ull << MSR_CE) |
3111 (1ull << MSR_EE) |
3112 (1ull << MSR_PR) |
3113 (1ull << MSR_FP) |
3114 (1ull << MSR_ME) |
3115 (1ull << MSR_FE0) |
3116 (1ull << MSR_DWE) |
3117 (1ull << MSR_DE) |
3118 (1ull << MSR_FE1) |
3119 (1ull << MSR_IR) |
3120 (1ull << MSR_DR);
3121 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3122 pcc->excp_model = POWERPC_EXCP_BOOKE;
3123 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3124 pcc->bfd_mach = bfd_mach_ppc_860;
3125 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3126 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3127 POWERPC_FLAG_BUS_CLK;
3128 }
3129
init_proc_e500mc(CPUPPCState * env)3130 static void init_proc_e500mc(CPUPPCState *env)
3131 {
3132 init_proc_e500(env, fsl_e500mc);
3133 }
3134
POWERPC_FAMILY(e500mc)3135 POWERPC_FAMILY(e500mc)(ObjectClass *oc, const void *data)
3136 {
3137 DeviceClass *dc = DEVICE_CLASS(oc);
3138 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3139
3140 dc->desc = "e500mc core";
3141 pcc->init_proc = init_proc_e500mc;
3142 pcc->check_pow = check_pow_none;
3143 pcc->check_attn = check_attn_none;
3144 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3145 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3146 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3147 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3148 PPC_FLOAT | PPC_FLOAT_FRES |
3149 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3150 PPC_FLOAT_STFIWX | PPC_WAIT |
3151 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3152 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
3153 pcc->msr_mask = (1ull << MSR_GS) |
3154 (1ull << MSR_UCLE) |
3155 (1ull << MSR_CE) |
3156 (1ull << MSR_EE) |
3157 (1ull << MSR_PR) |
3158 (1ull << MSR_FP) |
3159 (1ull << MSR_ME) |
3160 (1ull << MSR_FE0) |
3161 (1ull << MSR_DE) |
3162 (1ull << MSR_FE1) |
3163 (1ull << MSR_IR) |
3164 (1ull << MSR_DR) |
3165 (1ull << MSR_PX) |
3166 (1ull << MSR_RI);
3167 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3168 pcc->excp_model = POWERPC_EXCP_BOOKE;
3169 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3170 /* FIXME: figure out the correct flag for e500mc */
3171 pcc->bfd_mach = bfd_mach_ppc_e500;
3172 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3173 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3174 }
3175
3176 #ifdef TARGET_PPC64
init_proc_e5500(CPUPPCState * env)3177 static void init_proc_e5500(CPUPPCState *env)
3178 {
3179 init_proc_e500(env, fsl_e5500);
3180 }
3181
POWERPC_FAMILY(e5500)3182 POWERPC_FAMILY(e5500)(ObjectClass *oc, const void *data)
3183 {
3184 DeviceClass *dc = DEVICE_CLASS(oc);
3185 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3186
3187 dc->desc = "e5500 core";
3188 pcc->init_proc = init_proc_e5500;
3189 pcc->check_pow = check_pow_none;
3190 pcc->check_attn = check_attn_none;
3191 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3192 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3193 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3194 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3195 PPC_FLOAT | PPC_FLOAT_FRES |
3196 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3197 PPC_FLOAT_STFIWX | PPC_WAIT |
3198 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3199 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
3200 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3201 PPC2_FP_CVT_S64;
3202 pcc->msr_mask = (1ull << MSR_CM) |
3203 (1ull << MSR_GS) |
3204 (1ull << MSR_UCLE) |
3205 (1ull << MSR_CE) |
3206 (1ull << MSR_EE) |
3207 (1ull << MSR_PR) |
3208 (1ull << MSR_FP) |
3209 (1ull << MSR_ME) |
3210 (1ull << MSR_FE0) |
3211 (1ull << MSR_DE) |
3212 (1ull << MSR_FE1) |
3213 (1ull << MSR_IR) |
3214 (1ull << MSR_DR) |
3215 (1ull << MSR_PX) |
3216 (1ull << MSR_RI);
3217 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3218 pcc->excp_model = POWERPC_EXCP_BOOKE;
3219 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3220 /* FIXME: figure out the correct flag for e5500 */
3221 pcc->bfd_mach = bfd_mach_ppc_e500;
3222 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3223 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3224 }
3225
init_proc_e6500(CPUPPCState * env)3226 static void init_proc_e6500(CPUPPCState *env)
3227 {
3228 init_proc_e500(env, fsl_e6500);
3229 }
3230
POWERPC_FAMILY(e6500)3231 POWERPC_FAMILY(e6500)(ObjectClass *oc, const void *data)
3232 {
3233 DeviceClass *dc = DEVICE_CLASS(oc);
3234 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3235
3236 dc->desc = "e6500 core";
3237 pcc->init_proc = init_proc_e6500;
3238 pcc->check_pow = check_pow_none;
3239 pcc->check_attn = check_attn_none;
3240 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3241 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3242 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3243 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3244 PPC_FLOAT | PPC_FLOAT_FRES |
3245 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3246 PPC_FLOAT_STFIWX | PPC_WAIT |
3247 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3248 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
3249 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
3250 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3251 pcc->msr_mask = (1ull << MSR_CM) |
3252 (1ull << MSR_GS) |
3253 (1ull << MSR_UCLE) |
3254 (1ull << MSR_CE) |
3255 (1ull << MSR_EE) |
3256 (1ull << MSR_PR) |
3257 (1ull << MSR_FP) |
3258 (1ull << MSR_ME) |
3259 (1ull << MSR_FE0) |
3260 (1ull << MSR_DE) |
3261 (1ull << MSR_FE1) |
3262 (1ull << MSR_IS) |
3263 (1ull << MSR_DS) |
3264 (1ull << MSR_PX) |
3265 (1ull << MSR_RI) |
3266 (1ull << MSR_VR);
3267 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3268 pcc->excp_model = POWERPC_EXCP_BOOKE;
3269 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3270 pcc->bfd_mach = bfd_mach_ppc_e500;
3271 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3272 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3273 }
3274
3275 #endif
3276
3277 /* Non-embedded PowerPC */
init_proc_603(CPUPPCState * env)3278 static void init_proc_603(CPUPPCState *env)
3279 {
3280 register_non_embedded_sprs(env);
3281 register_sdr1_sprs(env);
3282 register_603_sprs(env);
3283
3284 /* Memory management */
3285 register_low_BATs(env);
3286 register_6xx_7xx_soft_tlb(env, 64, 2);
3287 init_excp_603(env);
3288 env->dcache_line_size = 32;
3289 env->icache_line_size = 32;
3290 /* Allocate hardware IRQ controller */
3291 ppc6xx_irq_init(env_archcpu(env));
3292 }
3293
3294 POWERPC_FAMILY(603)(ObjectClass *oc, const void *data)
3295 {
3296 DeviceClass *dc = DEVICE_CLASS(oc);
3297 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3298
3299 dc->desc = "PowerPC 603";
3300 pcc->init_proc = init_proc_603;
3301 pcc->check_pow = check_pow_hid0;
3302 pcc->check_attn = check_attn_none;
3303 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3304 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3305 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3306 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3307 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3308 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3309 PPC_SEGMENT | PPC_EXTERN;
3310 pcc->msr_mask = (1ull << MSR_POW) |
3311 (1ull << MSR_TGPR) |
3312 (1ull << MSR_ILE) |
3313 (1ull << MSR_EE) |
3314 (1ull << MSR_PR) |
3315 (1ull << MSR_FP) |
3316 (1ull << MSR_ME) |
3317 (1ull << MSR_FE0) |
3318 (1ull << MSR_SE) |
3319 (1ull << MSR_DE) |
3320 (1ull << MSR_FE1) |
3321 (1ull << MSR_EP) |
3322 (1ull << MSR_IR) |
3323 (1ull << MSR_DR) |
3324 (1ull << MSR_RI) |
3325 (1ull << MSR_LE);
3326 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3327 pcc->excp_model = POWERPC_EXCP_6xx;
3328 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3329 pcc->bfd_mach = bfd_mach_ppc_603;
3330 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3331 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3332 }
3333
3334 POWERPC_FAMILY(603E)(ObjectClass *oc, const void *data)
3335 {
3336 DeviceClass *dc = DEVICE_CLASS(oc);
3337 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3338
3339 dc->desc = "PowerPC 603e";
3340 pcc->init_proc = init_proc_603;
3341 pcc->check_pow = check_pow_hid0;
3342 pcc->check_attn = check_attn_none;
3343 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3344 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3345 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3346 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3347 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3348 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3349 PPC_SEGMENT | PPC_EXTERN;
3350 pcc->msr_mask = (1ull << MSR_POW) |
3351 (1ull << MSR_TGPR) |
3352 (1ull << MSR_ILE) |
3353 (1ull << MSR_EE) |
3354 (1ull << MSR_PR) |
3355 (1ull << MSR_FP) |
3356 (1ull << MSR_ME) |
3357 (1ull << MSR_FE0) |
3358 (1ull << MSR_SE) |
3359 (1ull << MSR_DE) |
3360 (1ull << MSR_FE1) |
3361 (1ull << MSR_EP) |
3362 (1ull << MSR_IR) |
3363 (1ull << MSR_DR) |
3364 (1ull << MSR_RI) |
3365 (1ull << MSR_LE);
3366 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3367 pcc->excp_model = POWERPC_EXCP_6xx;
3368 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3369 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3370 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3371 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3372 }
3373
init_proc_e300(CPUPPCState * env)3374 static void init_proc_e300(CPUPPCState *env)
3375 {
3376 init_proc_603(env);
3377 register_e300_sprs(env);
3378 }
3379
POWERPC_FAMILY(e300)3380 POWERPC_FAMILY(e300)(ObjectClass *oc, const void *data)
3381 {
3382 DeviceClass *dc = DEVICE_CLASS(oc);
3383 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3384
3385 dc->desc = "e300 core";
3386 pcc->init_proc = init_proc_e300;
3387 pcc->check_pow = check_pow_hid0;
3388 pcc->check_attn = check_attn_none;
3389 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3390 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3391 PPC_FLOAT_STFIWX |
3392 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3393 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3394 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3395 PPC_SEGMENT | PPC_EXTERN;
3396 pcc->msr_mask = (1ull << MSR_POW) |
3397 (1ull << MSR_TGPR) |
3398 (1ull << MSR_ILE) |
3399 (1ull << MSR_EE) |
3400 (1ull << MSR_PR) |
3401 (1ull << MSR_FP) |
3402 (1ull << MSR_ME) |
3403 (1ull << MSR_FE0) |
3404 (1ull << MSR_SE) |
3405 (1ull << MSR_DE) |
3406 (1ull << MSR_FE1) |
3407 (1ull << MSR_AL) |
3408 (1ull << MSR_EP) |
3409 (1ull << MSR_IR) |
3410 (1ull << MSR_DR) |
3411 (1ull << MSR_RI) |
3412 (1ull << MSR_LE);
3413 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3414 pcc->excp_model = POWERPC_EXCP_6xx;
3415 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3416 pcc->bfd_mach = bfd_mach_ppc_603;
3417 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3418 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3419 }
3420
init_proc_604(CPUPPCState * env)3421 static void init_proc_604(CPUPPCState *env)
3422 {
3423 register_non_embedded_sprs(env);
3424 register_sdr1_sprs(env);
3425 register_604_sprs(env);
3426
3427 /* Memory management */
3428 register_low_BATs(env);
3429 init_excp_604(env);
3430 env->dcache_line_size = 32;
3431 env->icache_line_size = 32;
3432 /* Allocate hardware IRQ controller */
3433 ppc6xx_irq_init(env_archcpu(env));
3434 }
3435
3436 POWERPC_FAMILY(604)(ObjectClass *oc, const void *data)
3437 {
3438 DeviceClass *dc = DEVICE_CLASS(oc);
3439 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3440
3441 dc->desc = "PowerPC 604";
3442 pcc->init_proc = init_proc_604;
3443 pcc->check_pow = check_pow_nocheck;
3444 pcc->check_attn = check_attn_none;
3445 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3446 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3447 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3448 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3449 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3450 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3451 PPC_SEGMENT | PPC_EXTERN;
3452 pcc->msr_mask = (1ull << MSR_POW) |
3453 (1ull << MSR_ILE) |
3454 (1ull << MSR_EE) |
3455 (1ull << MSR_PR) |
3456 (1ull << MSR_FP) |
3457 (1ull << MSR_ME) |
3458 (1ull << MSR_FE0) |
3459 (1ull << MSR_SE) |
3460 (1ull << MSR_DE) |
3461 (1ull << MSR_FE1) |
3462 (1ull << MSR_EP) |
3463 (1ull << MSR_IR) |
3464 (1ull << MSR_DR) |
3465 (1ull << MSR_PMM) |
3466 (1ull << MSR_RI) |
3467 (1ull << MSR_LE);
3468 pcc->mmu_model = POWERPC_MMU_32B;
3469 pcc->excp_model = POWERPC_EXCP_6xx;
3470 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3471 pcc->bfd_mach = bfd_mach_ppc_604;
3472 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3473 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3474 }
3475
init_proc_604E(CPUPPCState * env)3476 static void init_proc_604E(CPUPPCState *env)
3477 {
3478 init_proc_604(env);
3479 register_604e_sprs(env);
3480 }
3481
3482 POWERPC_FAMILY(604E)(ObjectClass *oc, const void *data)
3483 {
3484 DeviceClass *dc = DEVICE_CLASS(oc);
3485 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3486
3487 dc->desc = "PowerPC 604E";
3488 pcc->init_proc = init_proc_604E;
3489 pcc->check_pow = check_pow_nocheck;
3490 pcc->check_attn = check_attn_none;
3491 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3492 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3493 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3494 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3495 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3496 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3497 PPC_SEGMENT | PPC_EXTERN;
3498 pcc->msr_mask = (1ull << MSR_POW) |
3499 (1ull << MSR_ILE) |
3500 (1ull << MSR_EE) |
3501 (1ull << MSR_PR) |
3502 (1ull << MSR_FP) |
3503 (1ull << MSR_ME) |
3504 (1ull << MSR_FE0) |
3505 (1ull << MSR_SE) |
3506 (1ull << MSR_DE) |
3507 (1ull << MSR_FE1) |
3508 (1ull << MSR_EP) |
3509 (1ull << MSR_IR) |
3510 (1ull << MSR_DR) |
3511 (1ull << MSR_PMM) |
3512 (1ull << MSR_RI) |
3513 (1ull << MSR_LE);
3514 pcc->mmu_model = POWERPC_MMU_32B;
3515 pcc->excp_model = POWERPC_EXCP_6xx;
3516 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3517 pcc->bfd_mach = bfd_mach_ppc_604;
3518 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3519 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3520 }
3521
init_proc_740(CPUPPCState * env)3522 static void init_proc_740(CPUPPCState *env)
3523 {
3524 register_non_embedded_sprs(env);
3525 register_sdr1_sprs(env);
3526 register_7xx_sprs(env);
3527 /* Thermal management */
3528 register_thrm_sprs(env);
3529
3530 /* Memory management */
3531 register_low_BATs(env);
3532 init_excp_7x0(env);
3533 env->dcache_line_size = 32;
3534 env->icache_line_size = 32;
3535 /* Allocate hardware IRQ controller */
3536 ppc6xx_irq_init(env_archcpu(env));
3537 }
3538
3539 POWERPC_FAMILY(740)(ObjectClass *oc, const void *data)
3540 {
3541 DeviceClass *dc = DEVICE_CLASS(oc);
3542 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3543
3544 dc->desc = "PowerPC 740";
3545 pcc->init_proc = init_proc_740;
3546 pcc->check_pow = check_pow_hid0;
3547 pcc->check_attn = check_attn_none;
3548 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3549 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3550 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3551 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3552 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3553 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3554 PPC_SEGMENT | PPC_EXTERN;
3555 pcc->msr_mask = (1ull << MSR_POW) |
3556 (1ull << MSR_ILE) |
3557 (1ull << MSR_EE) |
3558 (1ull << MSR_PR) |
3559 (1ull << MSR_FP) |
3560 (1ull << MSR_ME) |
3561 (1ull << MSR_FE0) |
3562 (1ull << MSR_SE) |
3563 (1ull << MSR_DE) |
3564 (1ull << MSR_FE1) |
3565 (1ull << MSR_EP) |
3566 (1ull << MSR_IR) |
3567 (1ull << MSR_DR) |
3568 (1ull << MSR_PMM) |
3569 (1ull << MSR_RI) |
3570 (1ull << MSR_LE);
3571 pcc->mmu_model = POWERPC_MMU_32B;
3572 pcc->excp_model = POWERPC_EXCP_7xx;
3573 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3574 pcc->bfd_mach = bfd_mach_ppc_750;
3575 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3576 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3577 }
3578
init_proc_750(CPUPPCState * env)3579 static void init_proc_750(CPUPPCState *env)
3580 {
3581 register_non_embedded_sprs(env);
3582 register_sdr1_sprs(env);
3583 register_7xx_sprs(env);
3584
3585 spr_register(env, SPR_L2CR, "L2CR",
3586 SPR_NOACCESS, SPR_NOACCESS,
3587 &spr_read_generic, spr_access_nop,
3588 0x00000000);
3589 /* Thermal management */
3590 register_thrm_sprs(env);
3591
3592 /* Memory management */
3593 register_low_BATs(env);
3594 /*
3595 * XXX: high BATs are also present but are known to be bugged on
3596 * die version 1.x
3597 */
3598 init_excp_7x0(env);
3599 env->dcache_line_size = 32;
3600 env->icache_line_size = 32;
3601 /* Allocate hardware IRQ controller */
3602 ppc6xx_irq_init(env_archcpu(env));
3603 }
3604
3605 POWERPC_FAMILY(750)(ObjectClass *oc, const void *data)
3606 {
3607 DeviceClass *dc = DEVICE_CLASS(oc);
3608 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3609
3610 dc->desc = "PowerPC 750";
3611 pcc->init_proc = init_proc_750;
3612 pcc->check_pow = check_pow_hid0;
3613 pcc->check_attn = check_attn_none;
3614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3615 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3616 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3617 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3618 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3619 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3620 PPC_SEGMENT | PPC_EXTERN;
3621 pcc->msr_mask = (1ull << MSR_POW) |
3622 (1ull << MSR_ILE) |
3623 (1ull << MSR_EE) |
3624 (1ull << MSR_PR) |
3625 (1ull << MSR_FP) |
3626 (1ull << MSR_ME) |
3627 (1ull << MSR_FE0) |
3628 (1ull << MSR_SE) |
3629 (1ull << MSR_DE) |
3630 (1ull << MSR_FE1) |
3631 (1ull << MSR_EP) |
3632 (1ull << MSR_IR) |
3633 (1ull << MSR_DR) |
3634 (1ull << MSR_PMM) |
3635 (1ull << MSR_RI) |
3636 (1ull << MSR_LE);
3637 pcc->mmu_model = POWERPC_MMU_32B;
3638 pcc->excp_model = POWERPC_EXCP_7xx;
3639 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3640 pcc->bfd_mach = bfd_mach_ppc_750;
3641 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3642 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3643 }
3644
init_proc_750cl(CPUPPCState * env)3645 static void init_proc_750cl(CPUPPCState *env)
3646 {
3647 register_non_embedded_sprs(env);
3648 register_sdr1_sprs(env);
3649 register_7xx_sprs(env);
3650
3651 spr_register(env, SPR_L2CR, "L2CR",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, spr_access_nop,
3654 0x00000000);
3655 /* Thermal management */
3656 /* Those registers are fake on 750CL */
3657 spr_register(env, SPR_THRM1, "THRM1",
3658 SPR_NOACCESS, SPR_NOACCESS,
3659 &spr_read_generic, &spr_write_generic,
3660 0x00000000);
3661 spr_register(env, SPR_THRM2, "THRM2",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 spr_register(env, SPR_THRM3, "THRM3",
3666 SPR_NOACCESS, SPR_NOACCESS,
3667 &spr_read_generic, &spr_write_generic,
3668 0x00000000);
3669
3670 spr_register(env, SPR_750_TDCL, "TDCL",
3671 SPR_NOACCESS, SPR_NOACCESS,
3672 &spr_read_generic, &spr_write_generic,
3673 0x00000000);
3674 spr_register(env, SPR_750_TDCH, "TDCH",
3675 SPR_NOACCESS, SPR_NOACCESS,
3676 &spr_read_generic, &spr_write_generic,
3677 0x00000000);
3678 /* DMA */
3679 spr_register(env, SPR_750_WPAR, "WPAR",
3680 SPR_NOACCESS, SPR_NOACCESS,
3681 &spr_read_generic, &spr_write_generic,
3682 0x00000000);
3683 spr_register(env, SPR_750_DMAL, "DMAL",
3684 SPR_NOACCESS, SPR_NOACCESS,
3685 &spr_read_generic, &spr_write_generic,
3686 0x00000000);
3687 spr_register(env, SPR_750_DMAU, "DMAU",
3688 SPR_NOACCESS, SPR_NOACCESS,
3689 &spr_read_generic, &spr_write_generic,
3690 0x00000000);
3691 /* Hardware implementation registers */
3692 spr_register(env, SPR_750CL_HID2, "HID2",
3693 SPR_NOACCESS, SPR_NOACCESS,
3694 &spr_read_generic, &spr_write_generic,
3695 0x00000000);
3696
3697 spr_register(env, SPR_750CL_HID4, "HID4",
3698 SPR_NOACCESS, SPR_NOACCESS,
3699 &spr_read_generic, &spr_write_generic,
3700 0x00000000);
3701 /* Quantization registers */
3702 spr_register(env, SPR_750_GQR0, "GQR0",
3703 SPR_NOACCESS, SPR_NOACCESS,
3704 &spr_read_generic, &spr_write_generic,
3705 0x00000000);
3706
3707 spr_register(env, SPR_750_GQR1, "GQR1",
3708 SPR_NOACCESS, SPR_NOACCESS,
3709 &spr_read_generic, &spr_write_generic,
3710 0x00000000);
3711
3712 spr_register(env, SPR_750_GQR2, "GQR2",
3713 SPR_NOACCESS, SPR_NOACCESS,
3714 &spr_read_generic, &spr_write_generic,
3715 0x00000000);
3716
3717 spr_register(env, SPR_750_GQR3, "GQR3",
3718 SPR_NOACCESS, SPR_NOACCESS,
3719 &spr_read_generic, &spr_write_generic,
3720 0x00000000);
3721
3722 spr_register(env, SPR_750_GQR4, "GQR4",
3723 SPR_NOACCESS, SPR_NOACCESS,
3724 &spr_read_generic, &spr_write_generic,
3725 0x00000000);
3726
3727 spr_register(env, SPR_750_GQR5, "GQR5",
3728 SPR_NOACCESS, SPR_NOACCESS,
3729 &spr_read_generic, &spr_write_generic,
3730 0x00000000);
3731
3732 spr_register(env, SPR_750_GQR6, "GQR6",
3733 SPR_NOACCESS, SPR_NOACCESS,
3734 &spr_read_generic, &spr_write_generic,
3735 0x00000000);
3736
3737 spr_register(env, SPR_750_GQR7, "GQR7",
3738 SPR_NOACCESS, SPR_NOACCESS,
3739 &spr_read_generic, &spr_write_generic,
3740 0x00000000);
3741 /* Memory management */
3742 register_low_BATs(env);
3743 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
3744 register_high_BATs(env);
3745 init_excp_750cl(env);
3746 env->dcache_line_size = 32;
3747 env->icache_line_size = 32;
3748 /* Allocate hardware IRQ controller */
3749 ppc6xx_irq_init(env_archcpu(env));
3750 }
3751
3752 POWERPC_FAMILY(750cl)(ObjectClass *oc, const void *data)
3753 {
3754 DeviceClass *dc = DEVICE_CLASS(oc);
3755 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3756
3757 dc->desc = "PowerPC 750 CL";
3758 pcc->init_proc = init_proc_750cl;
3759 pcc->check_pow = check_pow_hid0;
3760 pcc->check_attn = check_attn_none;
3761 /*
3762 * XXX: not implemented:
3763 * cache lock instructions:
3764 * dcbz_l
3765 * floating point paired instructions
3766 * psq_lux
3767 * psq_lx
3768 * psq_stux
3769 * psq_stx
3770 * ps_abs
3771 * ps_add
3772 * ps_cmpo0
3773 * ps_cmpo1
3774 * ps_cmpu0
3775 * ps_cmpu1
3776 * ps_div
3777 * ps_madd
3778 * ps_madds0
3779 * ps_madds1
3780 * ps_merge00
3781 * ps_merge01
3782 * ps_merge10
3783 * ps_merge11
3784 * ps_mr
3785 * ps_msub
3786 * ps_mul
3787 * ps_muls0
3788 * ps_muls1
3789 * ps_nabs
3790 * ps_neg
3791 * ps_nmadd
3792 * ps_nmsub
3793 * ps_res
3794 * ps_rsqrte
3795 * ps_sel
3796 * ps_sub
3797 * ps_sum0
3798 * ps_sum1
3799 */
3800 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3801 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3802 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3803 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3804 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3805 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3806 PPC_SEGMENT | PPC_EXTERN;
3807 pcc->msr_mask = (1ull << MSR_POW) |
3808 (1ull << MSR_ILE) |
3809 (1ull << MSR_EE) |
3810 (1ull << MSR_PR) |
3811 (1ull << MSR_FP) |
3812 (1ull << MSR_ME) |
3813 (1ull << MSR_FE0) |
3814 (1ull << MSR_SE) |
3815 (1ull << MSR_DE) |
3816 (1ull << MSR_FE1) |
3817 (1ull << MSR_EP) |
3818 (1ull << MSR_IR) |
3819 (1ull << MSR_DR) |
3820 (1ull << MSR_PMM) |
3821 (1ull << MSR_RI) |
3822 (1ull << MSR_LE);
3823 pcc->mmu_model = POWERPC_MMU_32B;
3824 pcc->excp_model = POWERPC_EXCP_7xx;
3825 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3826 pcc->bfd_mach = bfd_mach_ppc_750;
3827 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3828 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3829 }
3830
init_proc_750cx(CPUPPCState * env)3831 static void init_proc_750cx(CPUPPCState *env)
3832 {
3833 register_non_embedded_sprs(env);
3834 register_sdr1_sprs(env);
3835 register_7xx_sprs(env);
3836
3837 spr_register(env, SPR_L2CR, "L2CR",
3838 SPR_NOACCESS, SPR_NOACCESS,
3839 &spr_read_generic, spr_access_nop,
3840 0x00000000);
3841 /* Thermal management */
3842 register_thrm_sprs(env);
3843
3844 spr_register(env, SPR_SDA, "SDA",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848
3849 /* Memory management */
3850 register_low_BATs(env);
3851 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
3852 register_high_BATs(env);
3853 init_excp_750cx(env);
3854 env->dcache_line_size = 32;
3855 env->icache_line_size = 32;
3856 /* Allocate hardware IRQ controller */
3857 ppc6xx_irq_init(env_archcpu(env));
3858 }
3859
3860 POWERPC_FAMILY(750cx)(ObjectClass *oc, const void *data)
3861 {
3862 DeviceClass *dc = DEVICE_CLASS(oc);
3863 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3864
3865 dc->desc = "PowerPC 750CX";
3866 pcc->init_proc = init_proc_750cx;
3867 pcc->check_pow = check_pow_hid0;
3868 pcc->check_attn = check_attn_none;
3869 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3870 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3871 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3872 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3873 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3874 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3875 PPC_SEGMENT | PPC_EXTERN;
3876 pcc->msr_mask = (1ull << MSR_POW) |
3877 (1ull << MSR_ILE) |
3878 (1ull << MSR_EE) |
3879 (1ull << MSR_PR) |
3880 (1ull << MSR_FP) |
3881 (1ull << MSR_ME) |
3882 (1ull << MSR_FE0) |
3883 (1ull << MSR_SE) |
3884 (1ull << MSR_DE) |
3885 (1ull << MSR_FE1) |
3886 (1ull << MSR_EP) |
3887 (1ull << MSR_IR) |
3888 (1ull << MSR_DR) |
3889 (1ull << MSR_PMM) |
3890 (1ull << MSR_RI) |
3891 (1ull << MSR_LE);
3892 pcc->mmu_model = POWERPC_MMU_32B;
3893 pcc->excp_model = POWERPC_EXCP_7xx;
3894 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3895 pcc->bfd_mach = bfd_mach_ppc_750;
3896 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3897 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3898 }
3899
init_proc_750fx(CPUPPCState * env)3900 static void init_proc_750fx(CPUPPCState *env)
3901 {
3902 register_non_embedded_sprs(env);
3903 register_sdr1_sprs(env);
3904 register_7xx_sprs(env);
3905
3906 spr_register(env, SPR_L2CR, "L2CR",
3907 SPR_NOACCESS, SPR_NOACCESS,
3908 &spr_read_generic, spr_access_nop,
3909 0x00000000);
3910 /* Thermal management */
3911 register_thrm_sprs(env);
3912
3913 spr_register(env, SPR_750_THRM4, "THRM4",
3914 SPR_NOACCESS, SPR_NOACCESS,
3915 &spr_read_generic, &spr_write_generic,
3916 0x00000000);
3917 /* Hardware implementation registers */
3918 spr_register(env, SPR_750FX_HID2, "HID2",
3919 SPR_NOACCESS, SPR_NOACCESS,
3920 &spr_read_generic, &spr_write_generic,
3921 0x00000000);
3922 /* Memory management */
3923 register_low_BATs(env);
3924 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3925 register_high_BATs(env);
3926 init_excp_7x0(env);
3927 env->dcache_line_size = 32;
3928 env->icache_line_size = 32;
3929 /* Allocate hardware IRQ controller */
3930 ppc6xx_irq_init(env_archcpu(env));
3931 }
3932
3933 POWERPC_FAMILY(750fx)(ObjectClass *oc, const void *data)
3934 {
3935 DeviceClass *dc = DEVICE_CLASS(oc);
3936 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3937
3938 dc->desc = "PowerPC 750FX";
3939 pcc->init_proc = init_proc_750fx;
3940 pcc->check_pow = check_pow_hid0;
3941 pcc->check_attn = check_attn_none;
3942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3943 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3944 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3945 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3946 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3947 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3948 PPC_SEGMENT | PPC_EXTERN;
3949 pcc->msr_mask = (1ull << MSR_POW) |
3950 (1ull << MSR_ILE) |
3951 (1ull << MSR_EE) |
3952 (1ull << MSR_PR) |
3953 (1ull << MSR_FP) |
3954 (1ull << MSR_ME) |
3955 (1ull << MSR_FE0) |
3956 (1ull << MSR_SE) |
3957 (1ull << MSR_DE) |
3958 (1ull << MSR_FE1) |
3959 (1ull << MSR_EP) |
3960 (1ull << MSR_IR) |
3961 (1ull << MSR_DR) |
3962 (1ull << MSR_PMM) |
3963 (1ull << MSR_RI) |
3964 (1ull << MSR_LE);
3965 pcc->mmu_model = POWERPC_MMU_32B;
3966 pcc->excp_model = POWERPC_EXCP_7xx;
3967 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3968 pcc->bfd_mach = bfd_mach_ppc_750;
3969 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3970 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
3971 }
3972
init_proc_750gx(CPUPPCState * env)3973 static void init_proc_750gx(CPUPPCState *env)
3974 {
3975 register_non_embedded_sprs(env);
3976 register_sdr1_sprs(env);
3977 register_7xx_sprs(env);
3978
3979 spr_register(env, SPR_L2CR, "L2CR",
3980 SPR_NOACCESS, SPR_NOACCESS,
3981 &spr_read_generic, spr_access_nop,
3982 0x00000000);
3983 /* Thermal management */
3984 register_thrm_sprs(env);
3985
3986 spr_register(env, SPR_750_THRM4, "THRM4",
3987 SPR_NOACCESS, SPR_NOACCESS,
3988 &spr_read_generic, &spr_write_generic,
3989 0x00000000);
3990 /* Hardware implementation registers */
3991 spr_register(env, SPR_750FX_HID2, "HID2",
3992 SPR_NOACCESS, SPR_NOACCESS,
3993 &spr_read_generic, &spr_write_generic,
3994 0x00000000);
3995 /* Memory management */
3996 register_low_BATs(env);
3997 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
3998 register_high_BATs(env);
3999 init_excp_7x0(env);
4000 env->dcache_line_size = 32;
4001 env->icache_line_size = 32;
4002 /* Allocate hardware IRQ controller */
4003 ppc6xx_irq_init(env_archcpu(env));
4004 }
4005
4006 POWERPC_FAMILY(750gx)(ObjectClass *oc, const void *data)
4007 {
4008 DeviceClass *dc = DEVICE_CLASS(oc);
4009 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4010
4011 dc->desc = "PowerPC 750GX";
4012 pcc->init_proc = init_proc_750gx;
4013 pcc->check_pow = check_pow_hid0;
4014 pcc->check_attn = check_attn_none;
4015 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4016 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4017 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4018 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4019 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4020 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4021 PPC_SEGMENT | PPC_EXTERN;
4022 pcc->msr_mask = (1ull << MSR_POW) |
4023 (1ull << MSR_ILE) |
4024 (1ull << MSR_EE) |
4025 (1ull << MSR_PR) |
4026 (1ull << MSR_FP) |
4027 (1ull << MSR_ME) |
4028 (1ull << MSR_FE0) |
4029 (1ull << MSR_SE) |
4030 (1ull << MSR_DE) |
4031 (1ull << MSR_FE1) |
4032 (1ull << MSR_EP) |
4033 (1ull << MSR_IR) |
4034 (1ull << MSR_DR) |
4035 (1ull << MSR_PMM) |
4036 (1ull << MSR_RI) |
4037 (1ull << MSR_LE);
4038 pcc->mmu_model = POWERPC_MMU_32B;
4039 pcc->excp_model = POWERPC_EXCP_7xx;
4040 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4041 pcc->bfd_mach = bfd_mach_ppc_750;
4042 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4043 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4044 }
4045
init_proc_745(CPUPPCState * env)4046 static void init_proc_745(CPUPPCState *env)
4047 {
4048 register_non_embedded_sprs(env);
4049 register_sdr1_sprs(env);
4050 register_7xx_sprs(env);
4051 register_745_sprs(env);
4052 /* Thermal management */
4053 register_thrm_sprs(env);
4054
4055 /* Memory management */
4056 register_low_BATs(env);
4057 register_high_BATs(env);
4058 register_6xx_7xx_soft_tlb(env, 64, 2);
4059 init_excp_7x5(env);
4060 env->dcache_line_size = 32;
4061 env->icache_line_size = 32;
4062 /* Allocate hardware IRQ controller */
4063 ppc6xx_irq_init(env_archcpu(env));
4064 }
4065
4066 POWERPC_FAMILY(745)(ObjectClass *oc, const void *data)
4067 {
4068 DeviceClass *dc = DEVICE_CLASS(oc);
4069 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4070
4071 dc->desc = "PowerPC 745";
4072 pcc->init_proc = init_proc_745;
4073 pcc->check_pow = check_pow_hid0;
4074 pcc->check_attn = check_attn_none;
4075 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4077 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4078 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4079 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4080 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4081 PPC_SEGMENT | PPC_EXTERN;
4082 pcc->msr_mask = (1ull << MSR_POW) |
4083 (1ull << MSR_ILE) |
4084 (1ull << MSR_EE) |
4085 (1ull << MSR_PR) |
4086 (1ull << MSR_FP) |
4087 (1ull << MSR_ME) |
4088 (1ull << MSR_FE0) |
4089 (1ull << MSR_SE) |
4090 (1ull << MSR_DE) |
4091 (1ull << MSR_FE1) |
4092 (1ull << MSR_EP) |
4093 (1ull << MSR_IR) |
4094 (1ull << MSR_DR) |
4095 (1ull << MSR_PMM) |
4096 (1ull << MSR_RI) |
4097 (1ull << MSR_LE);
4098 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4099 pcc->excp_model = POWERPC_EXCP_7xx;
4100 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4101 pcc->bfd_mach = bfd_mach_ppc_750;
4102 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4103 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4104 }
4105
init_proc_755(CPUPPCState * env)4106 static void init_proc_755(CPUPPCState *env)
4107 {
4108 init_proc_745(env);
4109 register_755_sprs(env);
4110 }
4111
4112 POWERPC_FAMILY(755)(ObjectClass *oc, const void *data)
4113 {
4114 DeviceClass *dc = DEVICE_CLASS(oc);
4115 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4116
4117 dc->desc = "PowerPC 755";
4118 pcc->init_proc = init_proc_755;
4119 pcc->check_pow = check_pow_hid0;
4120 pcc->check_attn = check_attn_none;
4121 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4122 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4123 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4124 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4125 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4126 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4127 PPC_SEGMENT | PPC_EXTERN;
4128 pcc->msr_mask = (1ull << MSR_POW) |
4129 (1ull << MSR_ILE) |
4130 (1ull << MSR_EE) |
4131 (1ull << MSR_PR) |
4132 (1ull << MSR_FP) |
4133 (1ull << MSR_ME) |
4134 (1ull << MSR_FE0) |
4135 (1ull << MSR_SE) |
4136 (1ull << MSR_DE) |
4137 (1ull << MSR_FE1) |
4138 (1ull << MSR_EP) |
4139 (1ull << MSR_IR) |
4140 (1ull << MSR_DR) |
4141 (1ull << MSR_PMM) |
4142 (1ull << MSR_RI) |
4143 (1ull << MSR_LE);
4144 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4145 pcc->excp_model = POWERPC_EXCP_7xx;
4146 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4147 pcc->bfd_mach = bfd_mach_ppc_750;
4148 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4149 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4150 }
4151
init_proc_7400(CPUPPCState * env)4152 static void init_proc_7400(CPUPPCState *env)
4153 {
4154 register_non_embedded_sprs(env);
4155 register_sdr1_sprs(env);
4156 register_74xx_sprs(env);
4157 vscr_init(env, 0x00010000);
4158
4159 spr_register(env, SPR_UBAMR, "UBAMR",
4160 &spr_read_ureg, SPR_NOACCESS,
4161 &spr_read_ureg, SPR_NOACCESS,
4162 0x00000000);
4163
4164 spr_register(env, SPR_MSSCR1, "MSSCR1",
4165 SPR_NOACCESS, SPR_NOACCESS,
4166 &spr_read_generic, &spr_write_generic,
4167 0x00000000);
4168 /* Thermal management */
4169 register_thrm_sprs(env);
4170 /* Memory management */
4171 register_low_BATs(env);
4172 init_excp_7400(env);
4173 env->dcache_line_size = 32;
4174 env->icache_line_size = 32;
4175 /* Allocate hardware IRQ controller */
4176 ppc6xx_irq_init(env_archcpu(env));
4177 }
4178
4179 POWERPC_FAMILY(7400)(ObjectClass *oc, const void *data)
4180 {
4181 DeviceClass *dc = DEVICE_CLASS(oc);
4182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4183
4184 dc->desc = "PowerPC 7400 (aka G4)";
4185 pcc->init_proc = init_proc_7400;
4186 pcc->check_pow = check_pow_hid0;
4187 pcc->check_attn = check_attn_none;
4188 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4189 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4190 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4191 PPC_FLOAT_STFIWX |
4192 PPC_CACHE | PPC_CACHE_ICBI |
4193 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4194 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4195 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4196 PPC_MEM_TLBIA |
4197 PPC_SEGMENT | PPC_EXTERN |
4198 PPC_ALTIVEC;
4199 pcc->msr_mask = (1ull << MSR_VR) |
4200 (1ull << MSR_POW) |
4201 (1ull << MSR_ILE) |
4202 (1ull << MSR_EE) |
4203 (1ull << MSR_PR) |
4204 (1ull << MSR_FP) |
4205 (1ull << MSR_ME) |
4206 (1ull << MSR_FE0) |
4207 (1ull << MSR_SE) |
4208 (1ull << MSR_DE) |
4209 (1ull << MSR_FE1) |
4210 (1ull << MSR_EP) |
4211 (1ull << MSR_IR) |
4212 (1ull << MSR_DR) |
4213 (1ull << MSR_PMM) |
4214 (1ull << MSR_RI) |
4215 (1ull << MSR_LE);
4216 pcc->mmu_model = POWERPC_MMU_32B;
4217 pcc->excp_model = POWERPC_EXCP_74xx;
4218 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4219 pcc->bfd_mach = bfd_mach_ppc_7400;
4220 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4221 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4222 POWERPC_FLAG_BUS_CLK;
4223 }
4224
init_proc_7410(CPUPPCState * env)4225 static void init_proc_7410(CPUPPCState *env)
4226 {
4227 register_non_embedded_sprs(env);
4228 register_sdr1_sprs(env);
4229 register_74xx_sprs(env);
4230 vscr_init(env, 0x00010000);
4231
4232 spr_register(env, SPR_UBAMR, "UBAMR",
4233 &spr_read_ureg, SPR_NOACCESS,
4234 &spr_read_ureg, SPR_NOACCESS,
4235 0x00000000);
4236 /* Thermal management */
4237 register_thrm_sprs(env);
4238 /* L2PMCR */
4239
4240 spr_register(env, SPR_L2PMCR, "L2PMCR",
4241 SPR_NOACCESS, SPR_NOACCESS,
4242 &spr_read_generic, &spr_write_generic,
4243 0x00000000);
4244 /* LDSTDB */
4245
4246 spr_register(env, SPR_LDSTDB, "LDSTDB",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* Memory management */
4251 register_low_BATs(env);
4252 init_excp_7400(env);
4253 env->dcache_line_size = 32;
4254 env->icache_line_size = 32;
4255 /* Allocate hardware IRQ controller */
4256 ppc6xx_irq_init(env_archcpu(env));
4257 }
4258
4259 POWERPC_FAMILY(7410)(ObjectClass *oc, const void *data)
4260 {
4261 DeviceClass *dc = DEVICE_CLASS(oc);
4262 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4263
4264 dc->desc = "PowerPC 7410 (aka G4)";
4265 pcc->init_proc = init_proc_7410;
4266 pcc->check_pow = check_pow_hid0;
4267 pcc->check_attn = check_attn_none;
4268 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4269 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4270 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4271 PPC_FLOAT_STFIWX |
4272 PPC_CACHE | PPC_CACHE_ICBI |
4273 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4274 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4275 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4276 PPC_MEM_TLBIA |
4277 PPC_SEGMENT | PPC_EXTERN |
4278 PPC_ALTIVEC;
4279 pcc->msr_mask = (1ull << MSR_VR) |
4280 (1ull << MSR_POW) |
4281 (1ull << MSR_ILE) |
4282 (1ull << MSR_EE) |
4283 (1ull << MSR_PR) |
4284 (1ull << MSR_FP) |
4285 (1ull << MSR_ME) |
4286 (1ull << MSR_FE0) |
4287 (1ull << MSR_SE) |
4288 (1ull << MSR_DE) |
4289 (1ull << MSR_FE1) |
4290 (1ull << MSR_EP) |
4291 (1ull << MSR_IR) |
4292 (1ull << MSR_DR) |
4293 (1ull << MSR_PMM) |
4294 (1ull << MSR_RI) |
4295 (1ull << MSR_LE);
4296 pcc->mmu_model = POWERPC_MMU_32B;
4297 pcc->excp_model = POWERPC_EXCP_74xx;
4298 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4299 pcc->bfd_mach = bfd_mach_ppc_7400;
4300 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4301 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4302 POWERPC_FLAG_BUS_CLK;
4303 }
4304
init_proc_7440(CPUPPCState * env)4305 static void init_proc_7440(CPUPPCState *env)
4306 {
4307 register_non_embedded_sprs(env);
4308 register_sdr1_sprs(env);
4309 register_74xx_sprs(env);
4310 vscr_init(env, 0x00010000);
4311
4312 spr_register(env, SPR_UBAMR, "UBAMR",
4313 &spr_read_ureg, SPR_NOACCESS,
4314 &spr_read_ureg, SPR_NOACCESS,
4315 0x00000000);
4316 /* LDSTCR */
4317 spr_register(env, SPR_LDSTCR, "LDSTCR",
4318 SPR_NOACCESS, SPR_NOACCESS,
4319 &spr_read_generic, &spr_write_generic,
4320 0x00000000);
4321 /* ICTRL */
4322 spr_register(env, SPR_ICTRL, "ICTRL",
4323 SPR_NOACCESS, SPR_NOACCESS,
4324 &spr_read_generic, &spr_write_generic,
4325 0x00000000);
4326 /* MSSSR0 */
4327 spr_register(env, SPR_MSSSR0, "MSSSR0",
4328 SPR_NOACCESS, SPR_NOACCESS,
4329 &spr_read_generic, &spr_write_generic,
4330 0x00000000);
4331 /* PMC */
4332 spr_register(env, SPR_7XX_PMC5, "PMC5",
4333 SPR_NOACCESS, SPR_NOACCESS,
4334 &spr_read_generic, &spr_write_generic,
4335 0x00000000);
4336
4337 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4338 &spr_read_ureg, SPR_NOACCESS,
4339 &spr_read_ureg, SPR_NOACCESS,
4340 0x00000000);
4341
4342 spr_register(env, SPR_7XX_PMC6, "PMC6",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0x00000000);
4346
4347 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4348 &spr_read_ureg, SPR_NOACCESS,
4349 &spr_read_ureg, SPR_NOACCESS,
4350 0x00000000);
4351 /* Memory management */
4352 register_low_BATs(env);
4353 init_excp_7450(env);
4354 env->dcache_line_size = 32;
4355 env->icache_line_size = 32;
4356 /* Allocate hardware IRQ controller */
4357 ppc6xx_irq_init(env_archcpu(env));
4358 }
4359
4360 POWERPC_FAMILY(7440)(ObjectClass *oc, const void *data)
4361 {
4362 DeviceClass *dc = DEVICE_CLASS(oc);
4363 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4364
4365 dc->desc = "PowerPC 7440 (aka G4)";
4366 pcc->init_proc = init_proc_7440;
4367 pcc->check_pow = check_pow_hid0_74xx;
4368 pcc->check_attn = check_attn_none;
4369 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4370 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4371 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4372 PPC_FLOAT_STFIWX |
4373 PPC_CACHE | PPC_CACHE_ICBI |
4374 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4375 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4376 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4377 PPC_MEM_TLBIA |
4378 PPC_SEGMENT | PPC_EXTERN |
4379 PPC_ALTIVEC;
4380 pcc->msr_mask = (1ull << MSR_VR) |
4381 (1ull << MSR_POW) |
4382 (1ull << MSR_ILE) |
4383 (1ull << MSR_EE) |
4384 (1ull << MSR_PR) |
4385 (1ull << MSR_FP) |
4386 (1ull << MSR_ME) |
4387 (1ull << MSR_FE0) |
4388 (1ull << MSR_SE) |
4389 (1ull << MSR_DE) |
4390 (1ull << MSR_FE1) |
4391 (1ull << MSR_EP) |
4392 (1ull << MSR_IR) |
4393 (1ull << MSR_DR) |
4394 (1ull << MSR_PMM) |
4395 (1ull << MSR_RI) |
4396 (1ull << MSR_LE);
4397 pcc->mmu_model = POWERPC_MMU_32B;
4398 pcc->excp_model = POWERPC_EXCP_74xx;
4399 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4400 pcc->bfd_mach = bfd_mach_ppc_7400;
4401 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4402 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4403 POWERPC_FLAG_BUS_CLK;
4404 }
4405
init_proc_7450(CPUPPCState * env)4406 static void init_proc_7450(CPUPPCState *env)
4407 {
4408 register_non_embedded_sprs(env);
4409 register_sdr1_sprs(env);
4410 register_74xx_sprs(env);
4411 vscr_init(env, 0x00010000);
4412 /* Level 3 cache control */
4413 register_l3_ctrl(env);
4414 /* L3ITCR1 */
4415 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4416 SPR_NOACCESS, SPR_NOACCESS,
4417 &spr_read_generic, &spr_write_generic,
4418 0x00000000);
4419 /* L3ITCR2 */
4420 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, &spr_write_generic,
4423 0x00000000);
4424 /* L3ITCR3 */
4425 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4426 SPR_NOACCESS, SPR_NOACCESS,
4427 &spr_read_generic, &spr_write_generic,
4428 0x00000000);
4429 /* L3OHCR */
4430 spr_register(env, SPR_L3OHCR, "L3OHCR",
4431 SPR_NOACCESS, SPR_NOACCESS,
4432 &spr_read_generic, &spr_write_generic,
4433 0x00000000);
4434
4435 spr_register(env, SPR_UBAMR, "UBAMR",
4436 &spr_read_ureg, SPR_NOACCESS,
4437 &spr_read_ureg, SPR_NOACCESS,
4438 0x00000000);
4439 /* LDSTCR */
4440 spr_register(env, SPR_LDSTCR, "LDSTCR",
4441 SPR_NOACCESS, SPR_NOACCESS,
4442 &spr_read_generic, &spr_write_generic,
4443 0x00000000);
4444 /* ICTRL */
4445 spr_register(env, SPR_ICTRL, "ICTRL",
4446 SPR_NOACCESS, SPR_NOACCESS,
4447 &spr_read_generic, &spr_write_generic,
4448 0x00000000);
4449 /* MSSSR0 */
4450 spr_register(env, SPR_MSSSR0, "MSSSR0",
4451 SPR_NOACCESS, SPR_NOACCESS,
4452 &spr_read_generic, &spr_write_generic,
4453 0x00000000);
4454 /* PMC */
4455 spr_register(env, SPR_7XX_PMC5, "PMC5",
4456 SPR_NOACCESS, SPR_NOACCESS,
4457 &spr_read_generic, &spr_write_generic,
4458 0x00000000);
4459
4460 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4461 &spr_read_ureg, SPR_NOACCESS,
4462 &spr_read_ureg, SPR_NOACCESS,
4463 0x00000000);
4464
4465 spr_register(env, SPR_7XX_PMC6, "PMC6",
4466 SPR_NOACCESS, SPR_NOACCESS,
4467 &spr_read_generic, &spr_write_generic,
4468 0x00000000);
4469
4470 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4471 &spr_read_ureg, SPR_NOACCESS,
4472 &spr_read_ureg, SPR_NOACCESS,
4473 0x00000000);
4474 /* Memory management */
4475 register_low_BATs(env);
4476 init_excp_7450(env);
4477 env->dcache_line_size = 32;
4478 env->icache_line_size = 32;
4479 /* Allocate hardware IRQ controller */
4480 ppc6xx_irq_init(env_archcpu(env));
4481 }
4482
4483 POWERPC_FAMILY(7450)(ObjectClass *oc, const void *data)
4484 {
4485 DeviceClass *dc = DEVICE_CLASS(oc);
4486 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4487
4488 dc->desc = "PowerPC 7450 (aka G4)";
4489 pcc->init_proc = init_proc_7450;
4490 pcc->check_pow = check_pow_hid0_74xx;
4491 pcc->check_attn = check_attn_none;
4492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4493 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4495 PPC_FLOAT_STFIWX |
4496 PPC_CACHE | PPC_CACHE_ICBI |
4497 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4498 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4499 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4500 PPC_MEM_TLBIA |
4501 PPC_SEGMENT | PPC_EXTERN |
4502 PPC_ALTIVEC;
4503 pcc->msr_mask = (1ull << MSR_VR) |
4504 (1ull << MSR_POW) |
4505 (1ull << MSR_ILE) |
4506 (1ull << MSR_EE) |
4507 (1ull << MSR_PR) |
4508 (1ull << MSR_FP) |
4509 (1ull << MSR_ME) |
4510 (1ull << MSR_FE0) |
4511 (1ull << MSR_SE) |
4512 (1ull << MSR_DE) |
4513 (1ull << MSR_FE1) |
4514 (1ull << MSR_EP) |
4515 (1ull << MSR_IR) |
4516 (1ull << MSR_DR) |
4517 (1ull << MSR_PMM) |
4518 (1ull << MSR_RI) |
4519 (1ull << MSR_LE);
4520 pcc->mmu_model = POWERPC_MMU_32B;
4521 pcc->excp_model = POWERPC_EXCP_74xx;
4522 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4523 pcc->bfd_mach = bfd_mach_ppc_7400;
4524 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4525 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4526 POWERPC_FLAG_BUS_CLK;
4527 }
4528
init_proc_7445(CPUPPCState * env)4529 static void init_proc_7445(CPUPPCState *env)
4530 {
4531 register_non_embedded_sprs(env);
4532 register_sdr1_sprs(env);
4533 register_74xx_sprs(env);
4534 vscr_init(env, 0x00010000);
4535 /* LDSTCR */
4536 spr_register(env, SPR_LDSTCR, "LDSTCR",
4537 SPR_NOACCESS, SPR_NOACCESS,
4538 &spr_read_generic, &spr_write_generic,
4539 0x00000000);
4540 /* ICTRL */
4541 spr_register(env, SPR_ICTRL, "ICTRL",
4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_generic,
4544 0x00000000);
4545 /* MSSSR0 */
4546 spr_register(env, SPR_MSSSR0, "MSSSR0",
4547 SPR_NOACCESS, SPR_NOACCESS,
4548 &spr_read_generic, &spr_write_generic,
4549 0x00000000);
4550 /* PMC */
4551 spr_register(env, SPR_7XX_PMC5, "PMC5",
4552 SPR_NOACCESS, SPR_NOACCESS,
4553 &spr_read_generic, &spr_write_generic,
4554 0x00000000);
4555
4556 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4557 &spr_read_ureg, SPR_NOACCESS,
4558 &spr_read_ureg, SPR_NOACCESS,
4559 0x00000000);
4560
4561 spr_register(env, SPR_7XX_PMC6, "PMC6",
4562 SPR_NOACCESS, SPR_NOACCESS,
4563 &spr_read_generic, &spr_write_generic,
4564 0x00000000);
4565
4566 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4567 &spr_read_ureg, SPR_NOACCESS,
4568 &spr_read_ureg, SPR_NOACCESS,
4569 0x00000000);
4570 /* SPRGs */
4571 spr_register(env, SPR_SPRG4, "SPRG4",
4572 SPR_NOACCESS, SPR_NOACCESS,
4573 &spr_read_generic, &spr_write_generic,
4574 0x00000000);
4575 spr_register(env, SPR_USPRG4, "USPRG4",
4576 &spr_read_ureg, SPR_NOACCESS,
4577 &spr_read_ureg, SPR_NOACCESS,
4578 0x00000000);
4579 spr_register(env, SPR_SPRG5, "SPRG5",
4580 SPR_NOACCESS, SPR_NOACCESS,
4581 &spr_read_generic, &spr_write_generic,
4582 0x00000000);
4583 spr_register(env, SPR_USPRG5, "USPRG5",
4584 &spr_read_ureg, SPR_NOACCESS,
4585 &spr_read_ureg, SPR_NOACCESS,
4586 0x00000000);
4587 spr_register(env, SPR_SPRG6, "SPRG6",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 spr_register(env, SPR_USPRG6, "USPRG6",
4592 &spr_read_ureg, SPR_NOACCESS,
4593 &spr_read_ureg, SPR_NOACCESS,
4594 0x00000000);
4595 spr_register(env, SPR_SPRG7, "SPRG7",
4596 SPR_NOACCESS, SPR_NOACCESS,
4597 &spr_read_generic, &spr_write_generic,
4598 0x00000000);
4599 spr_register(env, SPR_USPRG7, "USPRG7",
4600 &spr_read_ureg, SPR_NOACCESS,
4601 &spr_read_ureg, SPR_NOACCESS,
4602 0x00000000);
4603 /* Memory management */
4604 register_low_BATs(env);
4605 register_high_BATs(env);
4606 init_excp_7450(env);
4607 env->dcache_line_size = 32;
4608 env->icache_line_size = 32;
4609 /* Allocate hardware IRQ controller */
4610 ppc6xx_irq_init(env_archcpu(env));
4611 }
4612
4613 POWERPC_FAMILY(7445)(ObjectClass *oc, const void *data)
4614 {
4615 DeviceClass *dc = DEVICE_CLASS(oc);
4616 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4617
4618 dc->desc = "PowerPC 7445 (aka G4)";
4619 pcc->init_proc = init_proc_7445;
4620 pcc->check_pow = check_pow_hid0_74xx;
4621 pcc->check_attn = check_attn_none;
4622 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4623 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4624 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4625 PPC_FLOAT_STFIWX |
4626 PPC_CACHE | PPC_CACHE_ICBI |
4627 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4628 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4629 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4630 PPC_MEM_TLBIA |
4631 PPC_SEGMENT | PPC_EXTERN |
4632 PPC_ALTIVEC;
4633 pcc->msr_mask = (1ull << MSR_VR) |
4634 (1ull << MSR_POW) |
4635 (1ull << MSR_ILE) |
4636 (1ull << MSR_EE) |
4637 (1ull << MSR_PR) |
4638 (1ull << MSR_FP) |
4639 (1ull << MSR_ME) |
4640 (1ull << MSR_FE0) |
4641 (1ull << MSR_SE) |
4642 (1ull << MSR_DE) |
4643 (1ull << MSR_FE1) |
4644 (1ull << MSR_EP) |
4645 (1ull << MSR_IR) |
4646 (1ull << MSR_DR) |
4647 (1ull << MSR_PMM) |
4648 (1ull << MSR_RI) |
4649 (1ull << MSR_LE);
4650 pcc->mmu_model = POWERPC_MMU_32B;
4651 pcc->excp_model = POWERPC_EXCP_74xx;
4652 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4653 pcc->bfd_mach = bfd_mach_ppc_7400;
4654 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4655 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4656 POWERPC_FLAG_BUS_CLK;
4657 }
4658
init_proc_7455(CPUPPCState * env)4659 static void init_proc_7455(CPUPPCState *env)
4660 {
4661 register_non_embedded_sprs(env);
4662 register_sdr1_sprs(env);
4663 register_74xx_sprs(env);
4664 vscr_init(env, 0x00010000);
4665 /* Level 3 cache control */
4666 register_l3_ctrl(env);
4667 /* LDSTCR */
4668 spr_register(env, SPR_LDSTCR, "LDSTCR",
4669 SPR_NOACCESS, SPR_NOACCESS,
4670 &spr_read_generic, &spr_write_generic,
4671 0x00000000);
4672 /* ICTRL */
4673 spr_register(env, SPR_ICTRL, "ICTRL",
4674 SPR_NOACCESS, SPR_NOACCESS,
4675 &spr_read_generic, &spr_write_generic,
4676 0x00000000);
4677 /* MSSSR0 */
4678 spr_register(env, SPR_MSSSR0, "MSSSR0",
4679 SPR_NOACCESS, SPR_NOACCESS,
4680 &spr_read_generic, &spr_write_generic,
4681 0x00000000);
4682 /* PMC */
4683 spr_register(env, SPR_7XX_PMC5, "PMC5",
4684 SPR_NOACCESS, SPR_NOACCESS,
4685 &spr_read_generic, &spr_write_generic,
4686 0x00000000);
4687
4688 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4689 &spr_read_ureg, SPR_NOACCESS,
4690 &spr_read_ureg, SPR_NOACCESS,
4691 0x00000000);
4692
4693 spr_register(env, SPR_7XX_PMC6, "PMC6",
4694 SPR_NOACCESS, SPR_NOACCESS,
4695 &spr_read_generic, &spr_write_generic,
4696 0x00000000);
4697
4698 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4699 &spr_read_ureg, SPR_NOACCESS,
4700 &spr_read_ureg, SPR_NOACCESS,
4701 0x00000000);
4702 /* SPRGs */
4703 spr_register(env, SPR_SPRG4, "SPRG4",
4704 SPR_NOACCESS, SPR_NOACCESS,
4705 &spr_read_generic, &spr_write_generic,
4706 0x00000000);
4707 spr_register(env, SPR_USPRG4, "USPRG4",
4708 &spr_read_ureg, SPR_NOACCESS,
4709 &spr_read_ureg, SPR_NOACCESS,
4710 0x00000000);
4711 spr_register(env, SPR_SPRG5, "SPRG5",
4712 SPR_NOACCESS, SPR_NOACCESS,
4713 &spr_read_generic, &spr_write_generic,
4714 0x00000000);
4715 spr_register(env, SPR_USPRG5, "USPRG5",
4716 &spr_read_ureg, SPR_NOACCESS,
4717 &spr_read_ureg, SPR_NOACCESS,
4718 0x00000000);
4719 spr_register(env, SPR_SPRG6, "SPRG6",
4720 SPR_NOACCESS, SPR_NOACCESS,
4721 &spr_read_generic, &spr_write_generic,
4722 0x00000000);
4723 spr_register(env, SPR_USPRG6, "USPRG6",
4724 &spr_read_ureg, SPR_NOACCESS,
4725 &spr_read_ureg, SPR_NOACCESS,
4726 0x00000000);
4727 spr_register(env, SPR_SPRG7, "SPRG7",
4728 SPR_NOACCESS, SPR_NOACCESS,
4729 &spr_read_generic, &spr_write_generic,
4730 0x00000000);
4731 spr_register(env, SPR_USPRG7, "USPRG7",
4732 &spr_read_ureg, SPR_NOACCESS,
4733 &spr_read_ureg, SPR_NOACCESS,
4734 0x00000000);
4735 /* Memory management */
4736 register_low_BATs(env);
4737 register_high_BATs(env);
4738 init_excp_7450(env);
4739 env->dcache_line_size = 32;
4740 env->icache_line_size = 32;
4741 /* Allocate hardware IRQ controller */
4742 ppc6xx_irq_init(env_archcpu(env));
4743 }
4744
4745 POWERPC_FAMILY(7455)(ObjectClass *oc, const void *data)
4746 {
4747 DeviceClass *dc = DEVICE_CLASS(oc);
4748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4749
4750 dc->desc = "PowerPC 7455 (aka G4)";
4751 pcc->init_proc = init_proc_7455;
4752 pcc->check_pow = check_pow_hid0_74xx;
4753 pcc->check_attn = check_attn_none;
4754 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4755 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4756 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4757 PPC_FLOAT_STFIWX |
4758 PPC_CACHE | PPC_CACHE_ICBI |
4759 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4760 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4761 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4762 PPC_MEM_TLBIA |
4763 PPC_SEGMENT | PPC_EXTERN |
4764 PPC_ALTIVEC;
4765 pcc->msr_mask = (1ull << MSR_VR) |
4766 (1ull << MSR_POW) |
4767 (1ull << MSR_ILE) |
4768 (1ull << MSR_EE) |
4769 (1ull << MSR_PR) |
4770 (1ull << MSR_FP) |
4771 (1ull << MSR_ME) |
4772 (1ull << MSR_FE0) |
4773 (1ull << MSR_SE) |
4774 (1ull << MSR_DE) |
4775 (1ull << MSR_FE1) |
4776 (1ull << MSR_EP) |
4777 (1ull << MSR_IR) |
4778 (1ull << MSR_DR) |
4779 (1ull << MSR_PMM) |
4780 (1ull << MSR_RI) |
4781 (1ull << MSR_LE);
4782 pcc->mmu_model = POWERPC_MMU_32B;
4783 pcc->excp_model = POWERPC_EXCP_74xx;
4784 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4785 pcc->bfd_mach = bfd_mach_ppc_7400;
4786 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4787 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4788 POWERPC_FLAG_BUS_CLK;
4789 }
4790
init_proc_7457(CPUPPCState * env)4791 static void init_proc_7457(CPUPPCState *env)
4792 {
4793 register_non_embedded_sprs(env);
4794 register_sdr1_sprs(env);
4795 register_74xx_sprs(env);
4796 vscr_init(env, 0x00010000);
4797 /* Level 3 cache control */
4798 register_l3_ctrl(env);
4799 /* L3ITCR1 */
4800 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, &spr_write_generic,
4803 0x00000000);
4804 /* L3ITCR2 */
4805 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4806 SPR_NOACCESS, SPR_NOACCESS,
4807 &spr_read_generic, &spr_write_generic,
4808 0x00000000);
4809 /* L3ITCR3 */
4810 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4811 SPR_NOACCESS, SPR_NOACCESS,
4812 &spr_read_generic, &spr_write_generic,
4813 0x00000000);
4814 /* L3OHCR */
4815 spr_register(env, SPR_L3OHCR, "L3OHCR",
4816 SPR_NOACCESS, SPR_NOACCESS,
4817 &spr_read_generic, &spr_write_generic,
4818 0x00000000);
4819 /* LDSTCR */
4820 spr_register(env, SPR_LDSTCR, "LDSTCR",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, &spr_write_generic,
4823 0x00000000);
4824 /* ICTRL */
4825 spr_register(env, SPR_ICTRL, "ICTRL",
4826 SPR_NOACCESS, SPR_NOACCESS,
4827 &spr_read_generic, &spr_write_generic,
4828 0x00000000);
4829 /* MSSSR0 */
4830 spr_register(env, SPR_MSSSR0, "MSSSR0",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_generic, &spr_write_generic,
4833 0x00000000);
4834 /* PMC */
4835 spr_register(env, SPR_7XX_PMC5, "PMC5",
4836 SPR_NOACCESS, SPR_NOACCESS,
4837 &spr_read_generic, &spr_write_generic,
4838 0x00000000);
4839
4840 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4841 &spr_read_ureg, SPR_NOACCESS,
4842 &spr_read_ureg, SPR_NOACCESS,
4843 0x00000000);
4844
4845 spr_register(env, SPR_7XX_PMC6, "PMC6",
4846 SPR_NOACCESS, SPR_NOACCESS,
4847 &spr_read_generic, &spr_write_generic,
4848 0x00000000);
4849
4850 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4851 &spr_read_ureg, SPR_NOACCESS,
4852 &spr_read_ureg, SPR_NOACCESS,
4853 0x00000000);
4854 /* SPRGs */
4855 spr_register(env, SPR_SPRG4, "SPRG4",
4856 SPR_NOACCESS, SPR_NOACCESS,
4857 &spr_read_generic, &spr_write_generic,
4858 0x00000000);
4859 spr_register(env, SPR_USPRG4, "USPRG4",
4860 &spr_read_ureg, SPR_NOACCESS,
4861 &spr_read_ureg, SPR_NOACCESS,
4862 0x00000000);
4863 spr_register(env, SPR_SPRG5, "SPRG5",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, &spr_write_generic,
4866 0x00000000);
4867 spr_register(env, SPR_USPRG5, "USPRG5",
4868 &spr_read_ureg, SPR_NOACCESS,
4869 &spr_read_ureg, SPR_NOACCESS,
4870 0x00000000);
4871 spr_register(env, SPR_SPRG6, "SPRG6",
4872 SPR_NOACCESS, SPR_NOACCESS,
4873 &spr_read_generic, &spr_write_generic,
4874 0x00000000);
4875 spr_register(env, SPR_USPRG6, "USPRG6",
4876 &spr_read_ureg, SPR_NOACCESS,
4877 &spr_read_ureg, SPR_NOACCESS,
4878 0x00000000);
4879 spr_register(env, SPR_SPRG7, "SPRG7",
4880 SPR_NOACCESS, SPR_NOACCESS,
4881 &spr_read_generic, &spr_write_generic,
4882 0x00000000);
4883 spr_register(env, SPR_USPRG7, "USPRG7",
4884 &spr_read_ureg, SPR_NOACCESS,
4885 &spr_read_ureg, SPR_NOACCESS,
4886 0x00000000);
4887 /* Memory management */
4888 register_low_BATs(env);
4889 register_high_BATs(env);
4890 init_excp_7450(env);
4891 env->dcache_line_size = 32;
4892 env->icache_line_size = 32;
4893 /* Allocate hardware IRQ controller */
4894 ppc6xx_irq_init(env_archcpu(env));
4895 }
4896
4897 POWERPC_FAMILY(7457)(ObjectClass *oc, const void *data)
4898 {
4899 DeviceClass *dc = DEVICE_CLASS(oc);
4900 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4901
4902 dc->desc = "PowerPC 7457 (aka G4)";
4903 pcc->init_proc = init_proc_7457;
4904 pcc->check_pow = check_pow_hid0_74xx;
4905 pcc->check_attn = check_attn_none;
4906 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4907 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4908 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4909 PPC_FLOAT_STFIWX |
4910 PPC_CACHE | PPC_CACHE_ICBI |
4911 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4912 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4913 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4914 PPC_MEM_TLBIA |
4915 PPC_SEGMENT | PPC_EXTERN |
4916 PPC_ALTIVEC;
4917 pcc->msr_mask = (1ull << MSR_VR) |
4918 (1ull << MSR_POW) |
4919 (1ull << MSR_ILE) |
4920 (1ull << MSR_EE) |
4921 (1ull << MSR_PR) |
4922 (1ull << MSR_FP) |
4923 (1ull << MSR_ME) |
4924 (1ull << MSR_FE0) |
4925 (1ull << MSR_SE) |
4926 (1ull << MSR_DE) |
4927 (1ull << MSR_FE1) |
4928 (1ull << MSR_EP) |
4929 (1ull << MSR_IR) |
4930 (1ull << MSR_DR) |
4931 (1ull << MSR_PMM) |
4932 (1ull << MSR_RI) |
4933 (1ull << MSR_LE);
4934 pcc->mmu_model = POWERPC_MMU_32B;
4935 pcc->excp_model = POWERPC_EXCP_74xx;
4936 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4937 pcc->bfd_mach = bfd_mach_ppc_7400;
4938 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4939 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4940 POWERPC_FLAG_BUS_CLK;
4941 }
4942
init_proc_e600(CPUPPCState * env)4943 static void init_proc_e600(CPUPPCState *env)
4944 {
4945 register_non_embedded_sprs(env);
4946 register_sdr1_sprs(env);
4947 register_74xx_sprs(env);
4948 vscr_init(env, 0x00010000);
4949
4950 spr_register(env, SPR_UBAMR, "UBAMR",
4951 &spr_read_ureg, SPR_NOACCESS,
4952 &spr_read_ureg, SPR_NOACCESS,
4953 0x00000000);
4954
4955 spr_register(env, SPR_LDSTCR, "LDSTCR",
4956 SPR_NOACCESS, SPR_NOACCESS,
4957 &spr_read_generic, &spr_write_generic,
4958 0x00000000);
4959
4960 spr_register(env, SPR_ICTRL, "ICTRL",
4961 SPR_NOACCESS, SPR_NOACCESS,
4962 &spr_read_generic, &spr_write_generic,
4963 0x00000000);
4964
4965 spr_register(env, SPR_MSSSR0, "MSSSR0",
4966 SPR_NOACCESS, SPR_NOACCESS,
4967 &spr_read_generic, &spr_write_generic,
4968 0x00000000);
4969
4970 spr_register(env, SPR_7XX_PMC5, "PMC5",
4971 SPR_NOACCESS, SPR_NOACCESS,
4972 &spr_read_generic, &spr_write_generic,
4973 0x00000000);
4974
4975 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4976 &spr_read_ureg, SPR_NOACCESS,
4977 &spr_read_ureg, SPR_NOACCESS,
4978 0x00000000);
4979
4980 spr_register(env, SPR_7XX_PMC6, "PMC6",
4981 SPR_NOACCESS, SPR_NOACCESS,
4982 &spr_read_generic, &spr_write_generic,
4983 0x00000000);
4984
4985 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4986 &spr_read_ureg, SPR_NOACCESS,
4987 &spr_read_ureg, SPR_NOACCESS,
4988 0x00000000);
4989 /* SPRGs */
4990 spr_register(env, SPR_SPRG4, "SPRG4",
4991 SPR_NOACCESS, SPR_NOACCESS,
4992 &spr_read_generic, &spr_write_generic,
4993 0x00000000);
4994 spr_register(env, SPR_USPRG4, "USPRG4",
4995 &spr_read_ureg, SPR_NOACCESS,
4996 &spr_read_ureg, SPR_NOACCESS,
4997 0x00000000);
4998 spr_register(env, SPR_SPRG5, "SPRG5",
4999 SPR_NOACCESS, SPR_NOACCESS,
5000 &spr_read_generic, &spr_write_generic,
5001 0x00000000);
5002 spr_register(env, SPR_USPRG5, "USPRG5",
5003 &spr_read_ureg, SPR_NOACCESS,
5004 &spr_read_ureg, SPR_NOACCESS,
5005 0x00000000);
5006 spr_register(env, SPR_SPRG6, "SPRG6",
5007 SPR_NOACCESS, SPR_NOACCESS,
5008 &spr_read_generic, &spr_write_generic,
5009 0x00000000);
5010 spr_register(env, SPR_USPRG6, "USPRG6",
5011 &spr_read_ureg, SPR_NOACCESS,
5012 &spr_read_ureg, SPR_NOACCESS,
5013 0x00000000);
5014 spr_register(env, SPR_SPRG7, "SPRG7",
5015 SPR_NOACCESS, SPR_NOACCESS,
5016 &spr_read_generic, &spr_write_generic,
5017 0x00000000);
5018 spr_register(env, SPR_USPRG7, "USPRG7",
5019 &spr_read_ureg, SPR_NOACCESS,
5020 &spr_read_ureg, SPR_NOACCESS,
5021 0x00000000);
5022 /* Memory management */
5023 register_low_BATs(env);
5024 register_high_BATs(env);
5025 init_excp_7450(env);
5026 env->dcache_line_size = 32;
5027 env->icache_line_size = 32;
5028 /* Allocate hardware IRQ controller */
5029 ppc6xx_irq_init(env_archcpu(env));
5030 }
5031
POWERPC_FAMILY(e600)5032 POWERPC_FAMILY(e600)(ObjectClass *oc, const void *data)
5033 {
5034 DeviceClass *dc = DEVICE_CLASS(oc);
5035 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5036
5037 dc->desc = "PowerPC e600";
5038 pcc->init_proc = init_proc_e600;
5039 pcc->check_pow = check_pow_hid0_74xx;
5040 pcc->check_attn = check_attn_none;
5041 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5042 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5043 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5044 PPC_FLOAT_STFIWX |
5045 PPC_CACHE | PPC_CACHE_ICBI |
5046 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5047 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5048 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5049 PPC_MEM_TLBIA |
5050 PPC_SEGMENT | PPC_EXTERN |
5051 PPC_ALTIVEC;
5052 pcc->insns_flags2 = PPC_NONE;
5053 pcc->msr_mask = (1ull << MSR_VR) |
5054 (1ull << MSR_POW) |
5055 (1ull << MSR_ILE) |
5056 (1ull << MSR_EE) |
5057 (1ull << MSR_PR) |
5058 (1ull << MSR_FP) |
5059 (1ull << MSR_ME) |
5060 (1ull << MSR_FE0) |
5061 (1ull << MSR_SE) |
5062 (1ull << MSR_DE) |
5063 (1ull << MSR_FE1) |
5064 (1ull << MSR_EP) |
5065 (1ull << MSR_IR) |
5066 (1ull << MSR_DR) |
5067 (1ull << MSR_PMM) |
5068 (1ull << MSR_RI) |
5069 (1ull << MSR_LE);
5070 pcc->mmu_model = POWERPC_MMU_32B;
5071 pcc->excp_model = POWERPC_EXCP_74xx;
5072 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5073 pcc->bfd_mach = bfd_mach_ppc_7400;
5074 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5075 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5076 POWERPC_FLAG_BUS_CLK;
5077 }
5078
5079 #if defined(TARGET_PPC64)
5080 #if defined(CONFIG_USER_ONLY)
5081 #define POWERPC970_HID5_INIT 0x00000080
5082 #else
5083 #define POWERPC970_HID5_INIT 0x00000000
5084 #endif
5085
check_pow_970(CPUPPCState * env)5086 static int check_pow_970(CPUPPCState *env)
5087 {
5088 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
5089 return 1;
5090 }
5091
5092 return 0;
5093 }
5094
register_970_hid_sprs(CPUPPCState * env)5095 static void register_970_hid_sprs(CPUPPCState *env)
5096 {
5097 /* Hardware implementation registers */
5098 spr_register(env, SPR_HID0, "HID0",
5099 SPR_NOACCESS, SPR_NOACCESS,
5100 &spr_read_generic, &spr_write_clear,
5101 0x60000000);
5102 spr_register(env, SPR_HID1, "HID1",
5103 SPR_NOACCESS, SPR_NOACCESS,
5104 &spr_read_generic, &spr_write_generic,
5105 0x00000000);
5106 spr_register(env, SPR_970_HID5, "HID5",
5107 SPR_NOACCESS, SPR_NOACCESS,
5108 &spr_read_generic, &spr_write_generic,
5109 POWERPC970_HID5_INIT);
5110 }
5111
register_970_hior_sprs(CPUPPCState * env)5112 static void register_970_hior_sprs(CPUPPCState *env)
5113 {
5114 spr_register(env, SPR_HIOR, "HIOR",
5115 SPR_NOACCESS, SPR_NOACCESS,
5116 &spr_read_hior, &spr_write_hior,
5117 0x00000000);
5118 }
5119
register_book3s_ctrl_sprs(CPUPPCState * env)5120 static void register_book3s_ctrl_sprs(CPUPPCState *env)
5121 {
5122 spr_register(env, SPR_CTRL, "CTRL",
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 SPR_NOACCESS, &spr_write_CTRL,
5125 0x00000000);
5126 spr_register(env, SPR_UCTRL, "UCTRL",
5127 &spr_read_ureg, SPR_NOACCESS,
5128 &spr_read_ureg, SPR_NOACCESS,
5129 0x00000000);
5130 }
5131
register_book3s_altivec_sprs(CPUPPCState * env)5132 static void register_book3s_altivec_sprs(CPUPPCState *env)
5133 {
5134 if (!(env->insns_flags & PPC_ALTIVEC)) {
5135 return;
5136 }
5137
5138 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5139 &spr_read_generic, &spr_write_generic32,
5140 &spr_read_generic, &spr_write_generic32,
5141 KVM_REG_PPC_VRSAVE, 0x00000000);
5142
5143 }
5144
register_book3s_dbg_sprs(CPUPPCState * env)5145 static void register_book3s_dbg_sprs(CPUPPCState *env)
5146 {
5147 /*
5148 * TODO: different specs define different scopes for these,
5149 * will have to address this:
5150 * 970: super/write and super/read
5151 * powerisa 2.03..2.04: hypv/write and super/read.
5152 * powerisa 2.05 and newer: hypv/write and hypv/read.
5153 */
5154 spr_register_kvm(env, SPR_DABR, "DABR",
5155 SPR_NOACCESS, SPR_NOACCESS,
5156 &spr_read_generic, &spr_write_generic,
5157 KVM_REG_PPC_DABR, 0x00000000);
5158 spr_register_kvm(env, SPR_DABRX, "DABRX",
5159 SPR_NOACCESS, SPR_NOACCESS,
5160 &spr_read_generic, &spr_write_generic,
5161 KVM_REG_PPC_DABRX, 0x00000000);
5162 }
5163
register_book3s_207_dbg_sprs(CPUPPCState * env)5164 static void register_book3s_207_dbg_sprs(CPUPPCState *env)
5165 {
5166 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
5167 SPR_NOACCESS, SPR_NOACCESS,
5168 SPR_NOACCESS, SPR_NOACCESS,
5169 &spr_read_generic, &spr_write_dawr0,
5170 KVM_REG_PPC_DAWR, 0x00000000);
5171 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
5172 SPR_NOACCESS, SPR_NOACCESS,
5173 SPR_NOACCESS, SPR_NOACCESS,
5174 &spr_read_generic, &spr_write_dawrx0,
5175 KVM_REG_PPC_DAWRX, 0x00000000);
5176 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5177 SPR_NOACCESS, SPR_NOACCESS,
5178 SPR_NOACCESS, SPR_NOACCESS,
5179 &spr_read_generic, &spr_write_ciabr,
5180 KVM_REG_PPC_CIABR, 0x00000000);
5181 }
5182
register_book3s_310_dbg_sprs(CPUPPCState * env)5183 static void register_book3s_310_dbg_sprs(CPUPPCState *env)
5184 {
5185 spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1",
5186 SPR_NOACCESS, SPR_NOACCESS,
5187 SPR_NOACCESS, SPR_NOACCESS,
5188 &spr_read_generic, &spr_write_dawr1,
5189 KVM_REG_PPC_DAWR1, 0x00000000);
5190 spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1",
5191 SPR_NOACCESS, SPR_NOACCESS,
5192 SPR_NOACCESS, SPR_NOACCESS,
5193 &spr_read_generic, &spr_write_dawrx1,
5194 KVM_REG_PPC_DAWRX1, 0x00000000);
5195 }
5196
register_970_dbg_sprs(CPUPPCState * env)5197 static void register_970_dbg_sprs(CPUPPCState *env)
5198 {
5199 /* Breakpoints */
5200 spr_register(env, SPR_IABR, "IABR",
5201 SPR_NOACCESS, SPR_NOACCESS,
5202 &spr_read_generic, &spr_write_generic,
5203 0x00000000);
5204 }
5205
register_book3s_pmu_sup_sprs(CPUPPCState * env)5206 static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
5207 {
5208 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5209 SPR_NOACCESS, SPR_NOACCESS,
5210 &spr_read_generic, &spr_write_MMCR0,
5211 KVM_REG_PPC_MMCR0, 0x80000000);
5212 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5213 SPR_NOACCESS, SPR_NOACCESS,
5214 &spr_read_generic, &spr_write_MMCR1,
5215 KVM_REG_PPC_MMCR1, 0x00000000);
5216 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5217 SPR_NOACCESS, SPR_NOACCESS,
5218 &spr_read_generic, &spr_write_MMCRA,
5219 KVM_REG_PPC_MMCRA, 0x00000000);
5220 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5221 SPR_NOACCESS, SPR_NOACCESS,
5222 &spr_read_PMC, &spr_write_PMC,
5223 KVM_REG_PPC_PMC1, 0x00000000);
5224 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5225 SPR_NOACCESS, SPR_NOACCESS,
5226 &spr_read_PMC, &spr_write_PMC,
5227 KVM_REG_PPC_PMC2, 0x00000000);
5228 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5229 SPR_NOACCESS, SPR_NOACCESS,
5230 &spr_read_PMC, &spr_write_PMC,
5231 KVM_REG_PPC_PMC3, 0x00000000);
5232 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5233 SPR_NOACCESS, SPR_NOACCESS,
5234 &spr_read_PMC, &spr_write_PMC,
5235 KVM_REG_PPC_PMC4, 0x00000000);
5236 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5237 SPR_NOACCESS, SPR_NOACCESS,
5238 &spr_read_PMC, &spr_write_PMC,
5239 KVM_REG_PPC_PMC5, 0x00000000);
5240 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_PMC, &spr_write_PMC,
5243 KVM_REG_PPC_PMC6, 0x00000000);
5244 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5245 SPR_NOACCESS, SPR_NOACCESS,
5246 &spr_read_generic, &spr_write_generic,
5247 KVM_REG_PPC_SIAR, 0x00000000);
5248 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5249 SPR_NOACCESS, SPR_NOACCESS,
5250 &spr_read_generic, &spr_write_generic,
5251 KVM_REG_PPC_SDAR, 0x00000000);
5252 }
5253
register_book3s_pmu_user_sprs(CPUPPCState * env)5254 static void register_book3s_pmu_user_sprs(CPUPPCState *env)
5255 {
5256 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
5257 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
5258 &spr_read_ureg, &spr_write_ureg,
5259 0x80000000);
5260 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5261 &spr_read_ureg, SPR_NOACCESS,
5262 &spr_read_ureg, &spr_write_ureg,
5263 0x00000000);
5264 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5265 &spr_read_ureg, SPR_NOACCESS,
5266 &spr_read_ureg, &spr_write_ureg,
5267 0x00000000);
5268 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
5269 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5270 &spr_read_ureg, &spr_write_ureg,
5271 0x00000000);
5272 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
5273 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5274 &spr_read_ureg, &spr_write_ureg,
5275 0x00000000);
5276 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
5277 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5278 &spr_read_ureg, &spr_write_ureg,
5279 0x00000000);
5280 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
5281 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
5282 &spr_read_ureg, &spr_write_ureg,
5283 0x00000000);
5284 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
5285 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5286 &spr_read_ureg, &spr_write_ureg,
5287 0x00000000);
5288 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
5289 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
5290 &spr_read_ureg, &spr_write_ureg,
5291 0x00000000);
5292 spr_register(env, SPR_POWER_USIAR, "USIAR",
5293 &spr_read_ureg, SPR_NOACCESS,
5294 &spr_read_ureg, &spr_write_ureg,
5295 0x00000000);
5296 spr_register(env, SPR_POWER_USDAR, "USDAR",
5297 &spr_read_ureg, SPR_NOACCESS,
5298 &spr_read_ureg, &spr_write_ureg,
5299 0x00000000);
5300 }
5301
register_970_pmu_sup_sprs(CPUPPCState * env)5302 static void register_970_pmu_sup_sprs(CPUPPCState *env)
5303 {
5304 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5305 SPR_NOACCESS, SPR_NOACCESS,
5306 &spr_read_generic, &spr_write_generic,
5307 KVM_REG_PPC_PMC7, 0x00000000);
5308 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5309 SPR_NOACCESS, SPR_NOACCESS,
5310 &spr_read_generic, &spr_write_generic,
5311 KVM_REG_PPC_PMC8, 0x00000000);
5312 }
5313
register_970_pmu_user_sprs(CPUPPCState * env)5314 static void register_970_pmu_user_sprs(CPUPPCState *env)
5315 {
5316 spr_register(env, SPR_970_UPMC7, "UPMC7",
5317 &spr_read_ureg, SPR_NOACCESS,
5318 &spr_read_ureg, &spr_write_ureg,
5319 0x00000000);
5320 spr_register(env, SPR_970_UPMC8, "UPMC8",
5321 &spr_read_ureg, SPR_NOACCESS,
5322 &spr_read_ureg, &spr_write_ureg,
5323 0x00000000);
5324 }
5325
register_power8_pmu_sup_sprs(CPUPPCState * env)5326 static void register_power8_pmu_sup_sprs(CPUPPCState *env)
5327 {
5328 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5329 SPR_NOACCESS, SPR_NOACCESS,
5330 &spr_read_generic, &spr_write_generic,
5331 KVM_REG_PPC_MMCR2, 0x00000000);
5332 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5333 SPR_NOACCESS, SPR_NOACCESS,
5334 &spr_read_generic, &spr_write_generic,
5335 KVM_REG_PPC_MMCRS, 0x00000000);
5336 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5337 SPR_NOACCESS, SPR_NOACCESS,
5338 &spr_read_generic, &spr_write_generic,
5339 KVM_REG_PPC_SIER, 0x00000000);
5340 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5341 SPR_NOACCESS, SPR_NOACCESS,
5342 &spr_read_generic, &spr_write_generic,
5343 KVM_REG_PPC_SPMC1, 0x00000000);
5344 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5345 SPR_NOACCESS, SPR_NOACCESS,
5346 &spr_read_generic, &spr_write_generic,
5347 KVM_REG_PPC_SPMC2, 0x00000000);
5348 spr_register_kvm(env, SPR_TACR, "TACR",
5349 SPR_NOACCESS, SPR_NOACCESS,
5350 &spr_read_generic, &spr_write_generic,
5351 KVM_REG_PPC_TACR, 0x00000000);
5352 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5353 SPR_NOACCESS, SPR_NOACCESS,
5354 &spr_read_generic, &spr_write_generic,
5355 KVM_REG_PPC_TCSCR, 0x00000000);
5356 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 &spr_read_generic, &spr_write_generic,
5359 KVM_REG_PPC_CSIGR, 0x00000000);
5360 }
5361
register_power8_pmu_user_sprs(CPUPPCState * env)5362 static void register_power8_pmu_user_sprs(CPUPPCState *env)
5363 {
5364 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
5365 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
5366 &spr_read_ureg, &spr_write_ureg,
5367 0x00000000);
5368 spr_register(env, SPR_POWER_USIER, "USIER",
5369 &spr_read_generic, SPR_NOACCESS,
5370 &spr_read_generic, &spr_write_generic,
5371 0x00000000);
5372 }
5373
register_power10_pmu_sup_sprs(CPUPPCState * env)5374 static void register_power10_pmu_sup_sprs(CPUPPCState *env)
5375 {
5376 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3",
5377 SPR_NOACCESS, SPR_NOACCESS,
5378 &spr_read_generic, &spr_write_generic,
5379 KVM_REG_PPC_MMCR3, 0x00000000);
5380 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2",
5381 SPR_NOACCESS, SPR_NOACCESS,
5382 &spr_read_generic, &spr_write_generic,
5383 KVM_REG_PPC_SIER2, 0x00000000);
5384 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3",
5385 SPR_NOACCESS, SPR_NOACCESS,
5386 &spr_read_generic, &spr_write_generic,
5387 KVM_REG_PPC_SIER3, 0x00000000);
5388 }
5389
register_power10_pmu_user_sprs(CPUPPCState * env)5390 static void register_power10_pmu_user_sprs(CPUPPCState *env)
5391 {
5392 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3",
5393 &spr_read_generic, &spr_write_generic,
5394 &spr_read_generic, &spr_write_generic,
5395 0x00000000);
5396 spr_register(env, SPR_POWER_USIER2, "USIER2",
5397 &spr_read_generic, SPR_NOACCESS,
5398 &spr_read_generic, &spr_write_generic,
5399 0x00000000);
5400 spr_register(env, SPR_POWER_USIER3, "USIER3",
5401 &spr_read_generic, SPR_NOACCESS,
5402 &spr_read_generic, &spr_write_generic,
5403 0x00000000);
5404 }
5405
register_power5p_ear_sprs(CPUPPCState * env)5406 static void register_power5p_ear_sprs(CPUPPCState *env)
5407 {
5408 /* External access control */
5409 spr_register(env, SPR_EAR, "EAR",
5410 SPR_NOACCESS, SPR_NOACCESS,
5411 &spr_read_generic, &spr_write_generic,
5412 0x00000000);
5413 }
5414
register_power5p_tb_sprs(CPUPPCState * env)5415 static void register_power5p_tb_sprs(CPUPPCState *env)
5416 {
5417 /* TBU40 (High 40 bits of the Timebase register */
5418 spr_register_hv(env, SPR_TBU40, "TBU40",
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 SPR_NOACCESS, SPR_NOACCESS,
5421 SPR_NOACCESS, &spr_write_tbu40,
5422 0x00000000);
5423 }
5424
register_970_lpar_sprs(CPUPPCState * env)5425 static void register_970_lpar_sprs(CPUPPCState *env)
5426 {
5427 #if !defined(CONFIG_USER_ONLY)
5428 /*
5429 * PPC970: HID4 covers things later controlled by the LPCR and
5430 * RMOR in later CPUs, but with a different encoding. We only
5431 * support the 970 in "Apple mode" which has all hypervisor
5432 * facilities disabled by strapping, so we can basically just
5433 * ignore it
5434 */
5435 spr_register(env, SPR_970_HID4, "HID4",
5436 SPR_NOACCESS, SPR_NOACCESS,
5437 &spr_read_generic, &spr_write_generic,
5438 0x00000000);
5439 #endif
5440 }
5441
register_power5p_lpar_sprs(CPUPPCState * env)5442 static void register_power5p_lpar_sprs(CPUPPCState *env)
5443 {
5444 #if !defined(CONFIG_USER_ONLY)
5445 /* Logical partitioning */
5446 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5447 SPR_NOACCESS, SPR_NOACCESS,
5448 SPR_NOACCESS, SPR_NOACCESS,
5449 &spr_read_generic, &spr_write_lpcr,
5450 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
5451 spr_register_hv(env, SPR_HDEC, "HDEC",
5452 SPR_NOACCESS, SPR_NOACCESS,
5453 SPR_NOACCESS, SPR_NOACCESS,
5454 &spr_read_hdecr, &spr_write_hdecr, 0);
5455 #endif
5456 }
5457
register_book3s_ids_sprs(CPUPPCState * env)5458 static void register_book3s_ids_sprs(CPUPPCState *env)
5459 {
5460 /* FIXME: Will need to deal with thread vs core only SPRs */
5461
5462 /* Processor identification */
5463 spr_register_hv(env, SPR_PIR, "PIR",
5464 SPR_NOACCESS, SPR_NOACCESS,
5465 &spr_read_generic, SPR_NOACCESS,
5466 &spr_read_generic, NULL,
5467 0x00000000);
5468 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5469 SPR_NOACCESS, SPR_NOACCESS,
5470 SPR_NOACCESS, SPR_NOACCESS,
5471 &spr_read_generic, &spr_write_lpidr,
5472 0x00000000);
5473 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5474 SPR_NOACCESS, SPR_NOACCESS,
5475 SPR_NOACCESS, SPR_NOACCESS,
5476 &spr_read_generic, &spr_write_generic,
5477 0x00000000);
5478 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5479 SPR_NOACCESS, SPR_NOACCESS,
5480 SPR_NOACCESS, SPR_NOACCESS,
5481 &spr_read_generic, &spr_core_write_generic32,
5482 0x00000000);
5483 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5484 SPR_NOACCESS, SPR_NOACCESS,
5485 SPR_NOACCESS, SPR_NOACCESS,
5486 &spr_read_generic, &spr_write_generic,
5487 0x00000000);
5488 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5489 SPR_NOACCESS, SPR_NOACCESS,
5490 SPR_NOACCESS, SPR_NOACCESS,
5491 &spr_read_generic, &spr_write_generic,
5492 0x00000000);
5493 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5494 SPR_NOACCESS, SPR_NOACCESS,
5495 SPR_NOACCESS, SPR_NOACCESS,
5496 &spr_read_generic, &spr_write_generic,
5497 0x00000000);
5498 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5499 SPR_NOACCESS, SPR_NOACCESS,
5500 SPR_NOACCESS, SPR_NOACCESS,
5501 &spr_read_generic, &spr_write_generic,
5502 0x00000000);
5503 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5504 SPR_NOACCESS, SPR_NOACCESS,
5505 SPR_NOACCESS, SPR_NOACCESS,
5506 &spr_read_generic, &spr_write_generic,
5507 0x00000000);
5508 spr_register_hv(env, SPR_HDAR, "HDAR",
5509 SPR_NOACCESS, SPR_NOACCESS,
5510 SPR_NOACCESS, SPR_NOACCESS,
5511 &spr_read_generic, &spr_write_generic,
5512 0x00000000);
5513 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5514 SPR_NOACCESS, SPR_NOACCESS,
5515 SPR_NOACCESS, SPR_NOACCESS,
5516 &spr_read_generic, &spr_write_generic32,
5517 0x00000000);
5518 spr_register_hv(env, SPR_HRMOR, "HRMOR",
5519 SPR_NOACCESS, SPR_NOACCESS,
5520 SPR_NOACCESS, SPR_NOACCESS,
5521 &spr_read_generic, &spr_core_write_generic,
5522 0x00000000);
5523 }
5524
register_rmor_sprs(CPUPPCState * env)5525 static void register_rmor_sprs(CPUPPCState *env)
5526 {
5527 spr_register_hv(env, SPR_RMOR, "RMOR",
5528 SPR_NOACCESS, SPR_NOACCESS,
5529 SPR_NOACCESS, SPR_NOACCESS,
5530 &spr_read_generic, &spr_write_generic,
5531 0x00000000);
5532 }
5533
register_power8_ids_sprs(CPUPPCState * env)5534 static void register_power8_ids_sprs(CPUPPCState *env)
5535 {
5536 /* Thread identification */
5537 spr_register(env, SPR_TIR, "TIR",
5538 SPR_NOACCESS, SPR_NOACCESS,
5539 &spr_read_generic, SPR_NOACCESS,
5540 0x00000000);
5541 }
5542
register_book3s_purr_sprs(CPUPPCState * env)5543 static void register_book3s_purr_sprs(CPUPPCState *env)
5544 {
5545 #if !defined(CONFIG_USER_ONLY)
5546 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5547 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5548 &spr_read_purr, SPR_NOACCESS,
5549 &spr_read_purr, SPR_NOACCESS,
5550 &spr_read_purr, &spr_write_purr,
5551 KVM_REG_PPC_PURR, 0x00000000);
5552 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5553 &spr_read_purr, SPR_NOACCESS,
5554 &spr_read_purr, SPR_NOACCESS,
5555 &spr_read_purr, &spr_write_purr,
5556 KVM_REG_PPC_SPURR, 0x00000000);
5557 #endif
5558 }
5559
register_power6_dbg_sprs(CPUPPCState * env)5560 static void register_power6_dbg_sprs(CPUPPCState *env)
5561 {
5562 #if !defined(CONFIG_USER_ONLY)
5563 spr_register(env, SPR_CFAR, "CFAR",
5564 SPR_NOACCESS, SPR_NOACCESS,
5565 &spr_read_cfar, &spr_write_cfar,
5566 0x00000000);
5567 #endif
5568 }
5569
register_power5p_common_sprs(CPUPPCState * env)5570 static void register_power5p_common_sprs(CPUPPCState *env)
5571 {
5572 spr_register_kvm(env, SPR_PPR, "PPR",
5573 &spr_read_generic, &spr_write_generic,
5574 &spr_read_generic, &spr_write_generic,
5575 KVM_REG_PPC_PPR, 0x00000000);
5576 }
5577
register_power6_common_sprs(CPUPPCState * env)5578 static void register_power6_common_sprs(CPUPPCState *env)
5579 {
5580 #if !defined(CONFIG_USER_ONLY)
5581 spr_register_kvm(env, SPR_DSCR, "DSCR",
5582 SPR_NOACCESS, SPR_NOACCESS,
5583 &spr_read_generic, &spr_write_generic,
5584 KVM_REG_PPC_DSCR, 0x00000000);
5585 #endif
5586 /*
5587 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
5588 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5589 */
5590 spr_register_hv(env, SPR_PCR, "PCR",
5591 SPR_NOACCESS, SPR_NOACCESS,
5592 SPR_NOACCESS, SPR_NOACCESS,
5593 &spr_read_generic, &spr_write_pcr,
5594 0x00000000);
5595 }
5596
register_HEIR32_spr(CPUPPCState * env)5597 static void register_HEIR32_spr(CPUPPCState *env)
5598 {
5599 spr_register_hv(env, SPR_HEIR, "HEIR",
5600 SPR_NOACCESS, SPR_NOACCESS,
5601 SPR_NOACCESS, SPR_NOACCESS,
5602 &spr_read_generic, &spr_write_generic32,
5603 0x00000000);
5604 }
5605
register_HEIR64_spr(CPUPPCState * env)5606 static void register_HEIR64_spr(CPUPPCState *env)
5607 {
5608 spr_register_hv(env, SPR_HEIR, "HEIR",
5609 SPR_NOACCESS, SPR_NOACCESS,
5610 SPR_NOACCESS, SPR_NOACCESS,
5611 &spr_read_generic, &spr_write_generic,
5612 0x00000000);
5613 }
5614
register_power7_common_sprs(CPUPPCState * env)5615 static void register_power7_common_sprs(CPUPPCState *env)
5616 {
5617 spr_register(env, SPR_PPR32, "PPR32",
5618 &spr_read_ppr32, &spr_write_ppr32,
5619 &spr_read_ppr32, &spr_write_ppr32,
5620 0x00000000);
5621 }
5622
register_power8_tce_address_control_sprs(CPUPPCState * env)5623 static void register_power8_tce_address_control_sprs(CPUPPCState *env)
5624 {
5625 spr_register_kvm(env, SPR_TAR, "TAR",
5626 &spr_read_tar, &spr_write_tar,
5627 &spr_read_generic, &spr_write_generic,
5628 KVM_REG_PPC_TAR, 0x00000000);
5629 }
5630
register_power8_tm_sprs(CPUPPCState * env)5631 static void register_power8_tm_sprs(CPUPPCState *env)
5632 {
5633 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5634 &spr_read_tm, &spr_write_tm,
5635 &spr_read_tm, &spr_write_tm,
5636 KVM_REG_PPC_TFHAR, 0x00000000);
5637 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5638 &spr_read_tm, &spr_write_tm,
5639 &spr_read_tm, &spr_write_tm,
5640 KVM_REG_PPC_TFIAR, 0x00000000);
5641 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5642 &spr_read_tm, &spr_write_tm,
5643 &spr_read_tm, &spr_write_tm,
5644 KVM_REG_PPC_TEXASR, 0x00000000);
5645 spr_register(env, SPR_TEXASRU, "TEXASRU",
5646 &spr_read_tm_upper32, &spr_write_tm_upper32,
5647 &spr_read_tm_upper32, &spr_write_tm_upper32,
5648 0x00000000);
5649 }
5650
register_power8_ebb_sprs(CPUPPCState * env)5651 static void register_power8_ebb_sprs(CPUPPCState *env)
5652 {
5653 spr_register(env, SPR_BESCRS, "BESCRS",
5654 &spr_read_ebb, &spr_write_ebb,
5655 &spr_read_generic, &spr_write_generic,
5656 0x00000000);
5657 spr_register(env, SPR_BESCRSU, "BESCRSU",
5658 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5659 &spr_read_prev_upper32, &spr_write_prev_upper32,
5660 0x00000000);
5661 spr_register(env, SPR_BESCRR, "BESCRR",
5662 &spr_read_ebb, &spr_write_ebb,
5663 &spr_read_generic, &spr_write_generic,
5664 0x00000000);
5665 spr_register(env, SPR_BESCRRU, "BESCRRU",
5666 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5667 &spr_read_prev_upper32, &spr_write_prev_upper32,
5668 0x00000000);
5669 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5670 &spr_read_ebb, &spr_write_ebb,
5671 &spr_read_generic, &spr_write_generic,
5672 KVM_REG_PPC_EBBHR, 0x00000000);
5673 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5674 &spr_read_ebb, &spr_write_ebb,
5675 &spr_read_generic, &spr_write_generic,
5676 KVM_REG_PPC_EBBRR, 0x00000000);
5677 spr_register_kvm(env, SPR_BESCR, "BESCR",
5678 &spr_read_ebb, &spr_write_ebb,
5679 &spr_read_generic, &spr_write_generic,
5680 KVM_REG_PPC_BESCR, 0x00000000);
5681 }
5682
5683 /* Virtual Time Base */
register_vtb_sprs(CPUPPCState * env)5684 static void register_vtb_sprs(CPUPPCState *env)
5685 {
5686 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_vtb, SPR_NOACCESS,
5689 &spr_read_vtb, &spr_write_vtb,
5690 KVM_REG_PPC_VTB, 0x00000000);
5691 }
5692
register_power8_fscr_sprs(CPUPPCState * env)5693 static void register_power8_fscr_sprs(CPUPPCState *env)
5694 {
5695 #if defined(CONFIG_USER_ONLY)
5696 target_ulong initval = 1ULL << FSCR_TAR;
5697 #else
5698 target_ulong initval = 0;
5699 #endif
5700 spr_register_kvm(env, SPR_FSCR, "FSCR",
5701 SPR_NOACCESS, SPR_NOACCESS,
5702 &spr_read_generic, &spr_write_generic,
5703 KVM_REG_PPC_FSCR, initval);
5704 }
5705
register_power8_pspb_sprs(CPUPPCState * env)5706 static void register_power8_pspb_sprs(CPUPPCState *env)
5707 {
5708 spr_register_kvm(env, SPR_PSPB, "PSPB",
5709 SPR_NOACCESS, SPR_NOACCESS,
5710 &spr_read_generic, &spr_write_generic32,
5711 KVM_REG_PPC_PSPB, 0);
5712 }
5713
register_power8_dpdes_sprs(CPUPPCState * env)5714 static void register_power8_dpdes_sprs(CPUPPCState *env)
5715 {
5716 #if !defined(CONFIG_USER_ONLY)
5717 /* Directed Privileged Door-bell Exception State, used for IPI */
5718 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5719 SPR_NOACCESS, SPR_NOACCESS,
5720 &spr_read_dpdes, SPR_NOACCESS,
5721 &spr_read_dpdes, &spr_write_dpdes,
5722 KVM_REG_PPC_DPDES, 0x00000000);
5723 #endif
5724 }
5725
register_power8_ic_sprs(CPUPPCState * env)5726 static void register_power8_ic_sprs(CPUPPCState *env)
5727 {
5728 #if !defined(CONFIG_USER_ONLY)
5729 spr_register_hv(env, SPR_IC, "IC",
5730 SPR_NOACCESS, SPR_NOACCESS,
5731 &spr_read_generic, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0);
5734 #endif
5735 }
5736
5737 /* SPRs specific to IBM POWER CPUs */
register_power_common_book4_sprs(CPUPPCState * env)5738 static void register_power_common_book4_sprs(CPUPPCState *env)
5739 {
5740 #if !defined(CONFIG_USER_ONLY)
5741 spr_register_hv(env, SPR_HID0, "HID0",
5742 SPR_NOACCESS, SPR_NOACCESS,
5743 SPR_NOACCESS, SPR_NOACCESS,
5744 &spr_read_generic, &spr_core_write_generic,
5745 0x00000000);
5746 spr_register_hv(env, SPR_TSCR, "TSCR",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 SPR_NOACCESS, SPR_NOACCESS,
5749 &spr_read_generic, &spr_core_write_generic32,
5750 0x00000000);
5751 spr_register_hv(env, SPR_HMER, "HMER",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 SPR_NOACCESS, SPR_NOACCESS,
5754 &spr_read_generic, &spr_write_hmer,
5755 0x00000000);
5756 spr_register_hv(env, SPR_HMEER, "HMEER",
5757 SPR_NOACCESS, SPR_NOACCESS,
5758 SPR_NOACCESS, SPR_NOACCESS,
5759 &spr_read_generic, &spr_core_write_generic,
5760 0x00000000);
5761 spr_register_hv(env, SPR_TFMR, "TFMR",
5762 SPR_NOACCESS, SPR_NOACCESS,
5763 SPR_NOACCESS, SPR_NOACCESS,
5764 &spr_read_tfmr, &spr_write_tfmr,
5765 0x00000000);
5766 spr_register_hv(env, SPR_TRIG1, "TRIG1",
5767 SPR_NOACCESS, SPR_NOACCESS,
5768 &spr_access_nop, &spr_write_generic,
5769 &spr_access_nop, &spr_write_generic,
5770 0x00000000);
5771 spr_register_hv(env, SPR_TRIG2, "TRIG2",
5772 SPR_NOACCESS, SPR_NOACCESS,
5773 &spr_access_nop, &spr_write_generic,
5774 &spr_access_nop, &spr_write_generic,
5775 0x00000000);
5776 spr_register_hv(env, SPR_LDBAR, "LDBAR",
5777 SPR_NOACCESS, SPR_NOACCESS,
5778 SPR_NOACCESS, SPR_NOACCESS,
5779 &spr_read_generic, &spr_core_lpar_write_generic,
5780 0x00000000);
5781 spr_register_hv(env, SPR_POWER_TTR, "TTR",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 SPR_NOACCESS, SPR_NOACCESS,
5784 &spr_read_generic, &spr_core_write_generic,
5785 0x00000000);
5786 #endif
5787 }
5788
register_power9_book4_sprs(CPUPPCState * env)5789 static void register_power9_book4_sprs(CPUPPCState *env)
5790 {
5791 /* Add a number of P9 book4 registers */
5792 register_power_common_book4_sprs(env);
5793 #if !defined(CONFIG_USER_ONLY)
5794 spr_register_kvm(env, SPR_WORT, "WORT",
5795 SPR_NOACCESS, SPR_NOACCESS,
5796 &spr_read_generic, &spr_write_generic,
5797 KVM_REG_PPC_WORT, 0);
5798 spr_register_hv(env, SPR_RWMR, "RWMR",
5799 SPR_NOACCESS, SPR_NOACCESS,
5800 &spr_read_generic, &spr_write_generic,
5801 &spr_read_generic, &spr_write_generic,
5802 0x00000000);
5803
5804 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */
5805 spr_register_hv(env, SPR_POWER_SPRC, "SPRC",
5806 SPR_NOACCESS, SPR_NOACCESS,
5807 SPR_NOACCESS, SPR_NOACCESS,
5808 &spr_read_generic, &spr_write_sprc,
5809 0x00000000);
5810 spr_register_hv(env, SPR_POWER_SPRD, "SPRD",
5811 SPR_NOACCESS, SPR_NOACCESS,
5812 SPR_NOACCESS, SPR_NOACCESS,
5813 &spr_read_sprd, &spr_write_sprd,
5814 0x00000000);
5815 #endif
5816 }
5817
register_power8_book4_sprs(CPUPPCState * env)5818 static void register_power8_book4_sprs(CPUPPCState *env)
5819 {
5820 /* Add a number of P8 book4 registers */
5821 register_power_common_book4_sprs(env);
5822 #if !defined(CONFIG_USER_ONLY)
5823 spr_register_kvm(env, SPR_ACOP, "ACOP",
5824 SPR_NOACCESS, SPR_NOACCESS,
5825 &spr_read_generic, &spr_write_generic,
5826 KVM_REG_PPC_ACOP, 0);
5827 /* PID is only in BookE in ISA v2.07 */
5828 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5829 SPR_NOACCESS, SPR_NOACCESS,
5830 &spr_read_generic, &spr_write_pidr,
5831 KVM_REG_PPC_PID, 0);
5832 spr_register_kvm(env, SPR_WORT, "WORT",
5833 SPR_NOACCESS, SPR_NOACCESS,
5834 &spr_read_generic, &spr_write_generic,
5835 KVM_REG_PPC_WORT, 0);
5836 #endif
5837 }
5838
register_power7_book4_sprs(CPUPPCState * env)5839 static void register_power7_book4_sprs(CPUPPCState *env)
5840 {
5841 /* Add a number of P7 book4 registers */
5842 #if !defined(CONFIG_USER_ONLY)
5843 register_power_common_book4_sprs(env);
5844 spr_register_kvm(env, SPR_ACOP, "ACOP",
5845 SPR_NOACCESS, SPR_NOACCESS,
5846 &spr_read_generic, &spr_write_generic,
5847 KVM_REG_PPC_ACOP, 0);
5848 /* PID is only in BookE in ISA v2.06 */
5849 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5850 SPR_NOACCESS, SPR_NOACCESS,
5851 &spr_read_generic, &spr_write_generic32,
5852 KVM_REG_PPC_PID, 0);
5853 #endif
5854 }
5855
register_power8_rpr_sprs(CPUPPCState * env)5856 static void register_power8_rpr_sprs(CPUPPCState *env)
5857 {
5858 #if !defined(CONFIG_USER_ONLY)
5859 spr_register_hv(env, SPR_RPR, "RPR",
5860 SPR_NOACCESS, SPR_NOACCESS,
5861 SPR_NOACCESS, SPR_NOACCESS,
5862 &spr_read_generic, &spr_core_write_generic,
5863 0x00000103070F1F3F);
5864 #endif
5865 }
5866
register_power9_mmu_sprs(CPUPPCState * env)5867 static void register_power9_mmu_sprs(CPUPPCState *env)
5868 {
5869 #if !defined(CONFIG_USER_ONLY)
5870 /* Partition Table Control */
5871 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5872 SPR_NOACCESS, SPR_NOACCESS,
5873 SPR_NOACCESS, SPR_NOACCESS,
5874 &spr_read_generic, &spr_write_ptcr,
5875 KVM_REG_PPC_PTCR, 0x00000000);
5876 /* Address Segment Descriptor Register */
5877 spr_register_hv(env, SPR_ASDR, "ASDR",
5878 SPR_NOACCESS, SPR_NOACCESS,
5879 SPR_NOACCESS, SPR_NOACCESS,
5880 &spr_read_generic, &spr_write_generic,
5881 0x0000000000000000);
5882 /* PID is part of the BookS ISA from v3.0 */
5883 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR",
5884 SPR_NOACCESS, SPR_NOACCESS,
5885 &spr_read_generic, &spr_write_pidr,
5886 KVM_REG_PPC_PID, 0);
5887 #endif
5888 }
5889
register_power10_hash_sprs(CPUPPCState * env)5890 static void register_power10_hash_sprs(CPUPPCState *env)
5891 {
5892 /*
5893 * it's the OS responsibility to generate a random value for the registers
5894 * in each process' context. So, initialize it with 0 here.
5895 */
5896 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5897 #if defined(CONFIG_USER_ONLY)
5898 /* in linux-user, setup the hash register with a random value */
5899 GRand *rand = g_rand_new();
5900 hashkeyr_initial_value =
5901 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5902 hashpkeyr_initial_value =
5903 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5904 g_rand_free(rand);
5905 #endif
5906 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR",
5907 SPR_NOACCESS, SPR_NOACCESS,
5908 &spr_read_generic, &spr_write_generic,
5909 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value);
5910 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5911 SPR_NOACCESS, SPR_NOACCESS,
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_generic,
5914 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value);
5915 }
5916
register_power10_dexcr_sprs(CPUPPCState * env)5917 static void register_power10_dexcr_sprs(CPUPPCState *env)
5918 {
5919 spr_register_kvm(env, SPR_DEXCR, "DEXCR",
5920 SPR_NOACCESS, SPR_NOACCESS,
5921 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR,
5922 0);
5923
5924 spr_register(env, SPR_UDEXCR, "UDEXCR",
5925 &spr_read_dexcr_ureg, SPR_NOACCESS,
5926 &spr_read_dexcr_ureg, SPR_NOACCESS,
5927 0);
5928
5929 spr_register_hv(env, SPR_HDEXCR, "HDEXCR",
5930 SPR_NOACCESS, SPR_NOACCESS,
5931 SPR_NOACCESS, SPR_NOACCESS,
5932 &spr_read_generic, &spr_write_generic,
5933 0);
5934
5935 spr_register(env, SPR_UHDEXCR, "UHDEXCR",
5936 &spr_read_dexcr_ureg, SPR_NOACCESS,
5937 &spr_read_dexcr_ureg, SPR_NOACCESS,
5938 0);
5939 }
5940
5941 /*
5942 * Initialize PMU counter overflow timers for Power8 and
5943 * newer Power chips when using TCG.
5944 */
init_tcg_pmu_power8(CPUPPCState * env)5945 static void init_tcg_pmu_power8(CPUPPCState *env)
5946 {
5947 /* Init PMU overflow timers */
5948 if (tcg_enabled()) {
5949 cpu_ppc_pmu_init(env);
5950 }
5951 }
5952
init_proc_book3s_common(CPUPPCState * env)5953 static void init_proc_book3s_common(CPUPPCState *env)
5954 {
5955 register_non_embedded_sprs(env);
5956 register_book3s_altivec_sprs(env);
5957 register_book3s_pmu_sup_sprs(env);
5958 register_book3s_pmu_user_sprs(env);
5959 register_book3s_ctrl_sprs(env);
5960 /*
5961 * Can't find information on what this should be on reset. This
5962 * value is the one used by 74xx processors.
5963 */
5964 vscr_init(env, 0x00010000);
5965
5966 spr_register(env, SPR_USPRG3, "USPRG3",
5967 &spr_read_ureg, SPR_NOACCESS,
5968 &spr_read_ureg, SPR_NOACCESS,
5969 0x00000000);
5970 }
5971
init_proc_970(CPUPPCState * env)5972 static void init_proc_970(CPUPPCState *env)
5973 {
5974 /* Common Registers */
5975 init_proc_book3s_common(env);
5976 register_sdr1_sprs(env);
5977 register_book3s_dbg_sprs(env);
5978
5979 /* 970 Specific Registers */
5980 register_970_hid_sprs(env);
5981 register_970_hior_sprs(env);
5982 register_low_BATs(env);
5983 register_970_pmu_sup_sprs(env);
5984 register_970_pmu_user_sprs(env);
5985 register_970_lpar_sprs(env);
5986 register_970_dbg_sprs(env);
5987
5988 /* env variables */
5989 env->dcache_line_size = 128;
5990 env->icache_line_size = 128;
5991
5992 /* Allocate hardware IRQ controller */
5993 init_excp_970(env);
5994 ppc970_irq_init(env_archcpu(env));
5995 }
5996
5997 POWERPC_FAMILY(970)(ObjectClass *oc, const void *data)
5998 {
5999 DeviceClass *dc = DEVICE_CLASS(oc);
6000 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6001
6002 dc->desc = "PowerPC 970";
6003 pcc->init_proc = init_proc_970;
6004 pcc->check_pow = check_pow_970;
6005 pcc->check_attn = check_attn_hid0;
6006 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6007 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6008 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6009 PPC_FLOAT_STFIWX |
6010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6011 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6013 PPC_64B | PPC_ALTIVEC |
6014 PPC_SEGMENT_64B | PPC_SLBI;
6015 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
6016 pcc->msr_mask = (1ull << MSR_SF) |
6017 (1ull << MSR_VR) |
6018 (1ull << MSR_POW) |
6019 (1ull << MSR_EE) |
6020 (1ull << MSR_PR) |
6021 (1ull << MSR_FP) |
6022 (1ull << MSR_ME) |
6023 (1ull << MSR_FE0) |
6024 (1ull << MSR_SE) |
6025 (1ull << MSR_DE) |
6026 (1ull << MSR_FE1) |
6027 (1ull << MSR_IR) |
6028 (1ull << MSR_DR) |
6029 (1ull << MSR_PMM) |
6030 (1ull << MSR_RI);
6031 pcc->mmu_model = POWERPC_MMU_64B;
6032 #if !defined(CONFIG_USER_ONLY)
6033 pcc->hash64_opts = &ppc_hash64_opts_basic;
6034 #endif
6035 pcc->excp_model = POWERPC_EXCP_970;
6036 pcc->bus_model = PPC_FLAGS_INPUT_970;
6037 pcc->bfd_mach = bfd_mach_ppc64;
6038 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6039 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6040 POWERPC_FLAG_BUS_CLK;
6041 pcc->l1_dcache_size = 0x8000;
6042 pcc->l1_icache_size = 0x10000;
6043 }
6044
init_proc_power5plus(CPUPPCState * env)6045 static void init_proc_power5plus(CPUPPCState *env)
6046 {
6047 /* Common Registers */
6048 init_proc_book3s_common(env);
6049 register_sdr1_sprs(env);
6050 register_book3s_dbg_sprs(env);
6051
6052 /* POWER5+ Specific Registers */
6053 register_970_hid_sprs(env);
6054 register_970_hior_sprs(env);
6055 register_low_BATs(env);
6056 register_970_pmu_sup_sprs(env);
6057 register_970_pmu_user_sprs(env);
6058 register_power5p_common_sprs(env);
6059 register_power5p_lpar_sprs(env);
6060 register_power5p_ear_sprs(env);
6061 register_power5p_tb_sprs(env);
6062
6063 /* env variables */
6064 env->dcache_line_size = 128;
6065 env->icache_line_size = 128;
6066
6067 /* Allocate hardware IRQ controller */
6068 init_excp_970(env);
6069 ppc970_irq_init(env_archcpu(env));
6070 }
6071
POWERPC_FAMILY(POWER5P)6072 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, const void *data)
6073 {
6074 DeviceClass *dc = DEVICE_CLASS(oc);
6075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6076
6077 dc->fw_name = "PowerPC,POWER5";
6078 dc->desc = "POWER5+";
6079 pcc->init_proc = init_proc_power5plus;
6080 pcc->check_pow = check_pow_970;
6081 pcc->check_attn = check_attn_hid0;
6082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6084 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6085 PPC_FLOAT_STFIWX |
6086 PPC_FLOAT_EXT |
6087 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6088 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6089 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6090 PPC_64B |
6091 PPC_POPCNTB |
6092 PPC_SEGMENT_64B | PPC_SLBI;
6093 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
6094 pcc->msr_mask = (1ull << MSR_SF) |
6095 (1ull << MSR_VR) |
6096 (1ull << MSR_POW) |
6097 (1ull << MSR_EE) |
6098 (1ull << MSR_PR) |
6099 (1ull << MSR_FP) |
6100 (1ull << MSR_ME) |
6101 (1ull << MSR_FE0) |
6102 (1ull << MSR_SE) |
6103 (1ull << MSR_DE) |
6104 (1ull << MSR_FE1) |
6105 (1ull << MSR_IR) |
6106 (1ull << MSR_DR) |
6107 (1ull << MSR_PMM) |
6108 (1ull << MSR_RI);
6109 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
6110 LPCR_RMI | LPCR_HDICE;
6111 pcc->mmu_model = POWERPC_MMU_2_03;
6112 #if !defined(CONFIG_USER_ONLY)
6113 pcc->hash64_opts = &ppc_hash64_opts_basic;
6114 pcc->lrg_decr_bits = 32;
6115 #endif
6116 pcc->excp_model = POWERPC_EXCP_970;
6117 pcc->bus_model = PPC_FLAGS_INPUT_970;
6118 pcc->bfd_mach = bfd_mach_ppc64;
6119 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6120 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6121 POWERPC_FLAG_BUS_CLK;
6122 pcc->l1_dcache_size = 0x8000;
6123 pcc->l1_icache_size = 0x10000;
6124 }
6125
init_proc_POWER7(CPUPPCState * env)6126 static void init_proc_POWER7(CPUPPCState *env)
6127 {
6128 /* Common Registers */
6129 init_proc_book3s_common(env);
6130 register_sdr1_sprs(env);
6131 register_book3s_dbg_sprs(env);
6132
6133 /* POWER7 Specific Registers */
6134 register_book3s_ids_sprs(env);
6135 register_rmor_sprs(env);
6136 register_amr_sprs(env);
6137 register_book3s_purr_sprs(env);
6138 register_power5p_common_sprs(env);
6139 register_power5p_lpar_sprs(env);
6140 register_power5p_ear_sprs(env);
6141 register_power5p_tb_sprs(env);
6142 register_power6_common_sprs(env);
6143 register_HEIR32_spr(env);
6144 register_power6_dbg_sprs(env);
6145 register_power7_common_sprs(env);
6146 register_power7_book4_sprs(env);
6147
6148 /* env variables */
6149 env->dcache_line_size = 128;
6150 env->icache_line_size = 128;
6151
6152 /* Allocate hardware IRQ controller */
6153 init_excp_POWER7(env);
6154 ppcPOWER7_irq_init(env_archcpu(env));
6155 }
6156
ppc_pvr_match_power7(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6157 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6158 {
6159 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6160 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6161
6162 if (!best) {
6163 if (base == CPU_POWERPC_POWER7_BASE) {
6164 return true;
6165 }
6166 if (base == CPU_POWERPC_POWER7P_BASE) {
6167 return true;
6168 }
6169 }
6170
6171 if (base != pcc_base) {
6172 return false;
6173 }
6174
6175 return true;
6176 }
6177
POWERPC_FAMILY(POWER7)6178 POWERPC_FAMILY(POWER7)(ObjectClass *oc, const void *data)
6179 {
6180 DeviceClass *dc = DEVICE_CLASS(oc);
6181 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6182
6183 dc->fw_name = "PowerPC,POWER7";
6184 dc->desc = "POWER7";
6185 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS;
6186 pcc->pvr_match = ppc_pvr_match_power7;
6187 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6188 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6189 pcc->init_proc = init_proc_POWER7;
6190 pcc->check_pow = check_pow_nocheck;
6191 pcc->check_attn = check_attn_hid0;
6192 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6193 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6194 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6195 PPC_FLOAT_FRSQRTES |
6196 PPC_FLOAT_STFIWX |
6197 PPC_FLOAT_EXT |
6198 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6199 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6200 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6201 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6202 PPC_SEGMENT_64B | PPC_SLBI |
6203 PPC_POPCNTB | PPC_POPCNTWD |
6204 PPC_CILDST;
6205 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
6206 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6207 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6208 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
6209 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
6210 pcc->msr_mask = (1ull << MSR_SF) |
6211 (1ull << MSR_VR) |
6212 (1ull << MSR_VSX) |
6213 (1ull << MSR_EE) |
6214 (1ull << MSR_PR) |
6215 (1ull << MSR_FP) |
6216 (1ull << MSR_ME) |
6217 (1ull << MSR_FE0) |
6218 (1ull << MSR_SE) |
6219 (1ull << MSR_DE) |
6220 (1ull << MSR_FE1) |
6221 (1ull << MSR_IR) |
6222 (1ull << MSR_DR) |
6223 (1ull << MSR_PMM) |
6224 (1ull << MSR_RI) |
6225 (1ull << MSR_LE);
6226 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6227 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6228 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6229 LPCR_MER | LPCR_TC |
6230 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6231 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
6232 pcc->mmu_model = POWERPC_MMU_2_06;
6233 #if !defined(CONFIG_USER_ONLY)
6234 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6235 pcc->lrg_decr_bits = 32;
6236 #endif
6237 pcc->excp_model = POWERPC_EXCP_POWER7;
6238 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6239 pcc->bfd_mach = bfd_mach_ppc64;
6240 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6241 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6242 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6243 POWERPC_FLAG_VSX;
6244 pcc->l1_dcache_size = 0x8000;
6245 pcc->l1_icache_size = 0x8000;
6246 }
6247
bhrb_init_state(CPUPPCState * env,target_long num_entries_log2)6248 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2)
6249 {
6250 if (env->flags & POWERPC_FLAG_BHRB) {
6251 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) {
6252 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2;
6253 }
6254 env->bhrb_num_entries = 1 << num_entries_log2;
6255 env->bhrb_base = (intptr_t)&env->bhrb[0];
6256 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1;
6257 }
6258 }
6259
bhrb_reset_state(CPUPPCState * env)6260 static void bhrb_reset_state(CPUPPCState *env)
6261 {
6262 if (env->flags & POWERPC_FLAG_BHRB) {
6263 env->bhrb_offset = 0;
6264 env->bhrb_filter = 0;
6265 memset(env->bhrb, 0, sizeof(env->bhrb));
6266 }
6267 }
6268
6269 #define POWER8_BHRB_ENTRIES_LOG2 5
init_proc_POWER8(CPUPPCState * env)6270 static void init_proc_POWER8(CPUPPCState *env)
6271 {
6272 /* Common Registers */
6273 init_proc_book3s_common(env);
6274 register_sdr1_sprs(env);
6275 register_book3s_207_dbg_sprs(env);
6276
6277 /* Common TCG PMU */
6278 init_tcg_pmu_power8(env);
6279
6280 /* POWER8 Specific Registers */
6281 register_book3s_ids_sprs(env);
6282 register_rmor_sprs(env);
6283 register_amr_sprs(env);
6284 register_iamr_sprs(env);
6285 register_book3s_purr_sprs(env);
6286 register_power5p_common_sprs(env);
6287 register_power5p_lpar_sprs(env);
6288 register_power5p_ear_sprs(env);
6289 register_power5p_tb_sprs(env);
6290 register_power6_common_sprs(env);
6291 register_HEIR32_spr(env);
6292 register_power6_dbg_sprs(env);
6293 register_power7_common_sprs(env);
6294 register_power8_tce_address_control_sprs(env);
6295 register_power8_ids_sprs(env);
6296 register_power8_ebb_sprs(env);
6297 register_power8_fscr_sprs(env);
6298 register_power8_pmu_sup_sprs(env);
6299 register_power8_pmu_user_sprs(env);
6300 register_power8_tm_sprs(env);
6301 register_power8_pspb_sprs(env);
6302 register_power8_dpdes_sprs(env);
6303 register_vtb_sprs(env);
6304 register_power8_ic_sprs(env);
6305 register_power8_book4_sprs(env);
6306 register_power8_rpr_sprs(env);
6307
6308 /* env variables */
6309 env->dcache_line_size = 128;
6310 env->icache_line_size = 128;
6311
6312 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2);
6313
6314 /* Allocate hardware IRQ controller */
6315 init_excp_POWER8(env);
6316 ppcPOWER7_irq_init(env_archcpu(env));
6317 }
6318
ppc_pvr_match_power8(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6319 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6320 {
6321 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6322 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6323
6324 if (!best) {
6325 if (base == CPU_POWERPC_POWER8_BASE) {
6326 return true;
6327 }
6328 if (base == CPU_POWERPC_POWER8E_BASE) {
6329 return true;
6330 }
6331 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6332 return true;
6333 }
6334 }
6335 if (base != pcc_base) {
6336 return false;
6337 }
6338
6339 return true;
6340 }
6341
POWERPC_FAMILY(POWER8)6342 POWERPC_FAMILY(POWER8)(ObjectClass *oc, const void *data)
6343 {
6344 DeviceClass *dc = DEVICE_CLASS(oc);
6345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6346
6347 dc->fw_name = "PowerPC,POWER8";
6348 dc->desc = "POWER8";
6349 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07;
6350 pcc->pvr_match = ppc_pvr_match_power8;
6351 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6352 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6353 pcc->init_proc = init_proc_POWER8;
6354 pcc->check_pow = check_pow_nocheck;
6355 pcc->check_attn = check_attn_hid0;
6356 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6357 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6358 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6359 PPC_FLOAT_FRSQRTES |
6360 PPC_FLOAT_STFIWX |
6361 PPC_FLOAT_EXT |
6362 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6363 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6364 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6365 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6366 PPC_SEGMENT_64B | PPC_SLBI |
6367 PPC_POPCNTB | PPC_POPCNTWD |
6368 PPC_CILDST;
6369 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6370 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6371 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6372 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6373 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6374 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
6375 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6376 PPC2_BCDA_ISA206;
6377 pcc->msr_mask = (1ull << MSR_SF) |
6378 (1ull << MSR_HV) |
6379 (1ull << MSR_TM) |
6380 (1ull << MSR_VR) |
6381 (1ull << MSR_VSX) |
6382 (1ull << MSR_EE) |
6383 (1ull << MSR_PR) |
6384 (1ull << MSR_FP) |
6385 (1ull << MSR_ME) |
6386 (1ull << MSR_FE0) |
6387 (1ull << MSR_SE) |
6388 (1ull << MSR_DE) |
6389 (1ull << MSR_FE1) |
6390 (1ull << MSR_IR) |
6391 (1ull << MSR_DR) |
6392 (1ull << MSR_PMM) |
6393 (1ull << MSR_RI) |
6394 (1ull << MSR_TS0) |
6395 (1ull << MSR_TS1) |
6396 (1ull << MSR_LE);
6397 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6398 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6399 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6400 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6401 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6402 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6403 LPCR_P8_PECE3 | LPCR_P8_PECE4;
6404 pcc->mmu_model = POWERPC_MMU_2_07;
6405 #if !defined(CONFIG_USER_ONLY)
6406 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6407 pcc->lrg_decr_bits = 32;
6408 pcc->n_host_threads = 8;
6409 #endif
6410 pcc->excp_model = POWERPC_EXCP_POWER8;
6411 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6412 pcc->bfd_mach = bfd_mach_ppc64;
6413 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6414 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6415 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6416 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6417 pcc->l1_dcache_size = 0x8000;
6418 pcc->l1_icache_size = 0x8000;
6419 }
6420
6421 #ifndef CONFIG_USER_ONLY
6422 /*
6423 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6424 * Encoded as array of int_32s in the form:
6425 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6426 * x -> AP encoding
6427 * y -> radix mode supported page size (encoded as a shift)
6428 */
6429 static struct ppc_radix_page_info POWER9_radix_page_info = {
6430 .count = 4,
6431 .entries = {
6432 0x0000000c, /* 4K - enc: 0x0 */
6433 0xa0000010, /* 64K - enc: 0x5 */
6434 0x20000015, /* 2M - enc: 0x1 */
6435 0x4000001e /* 1G - enc: 0x2 */
6436 }
6437 };
6438 #endif /* CONFIG_USER_ONLY */
6439
6440 #define POWER9_BHRB_ENTRIES_LOG2 5
register_power9_common_sprs(CPUPPCState * env)6441 static void register_power9_common_sprs(CPUPPCState *env)
6442 {
6443 /* Common Registers */
6444 init_proc_book3s_common(env);
6445 register_book3s_207_dbg_sprs(env);
6446
6447 /* Common TCG PMU */
6448 init_tcg_pmu_power8(env);
6449
6450 /* POWER8 Specific Registers */
6451 register_book3s_ids_sprs(env);
6452 register_amr_sprs(env);
6453 register_iamr_sprs(env);
6454 register_book3s_purr_sprs(env);
6455 register_power5p_common_sprs(env);
6456 register_power5p_lpar_sprs(env);
6457 register_power5p_ear_sprs(env);
6458 register_power5p_tb_sprs(env);
6459 register_power6_common_sprs(env);
6460 register_power6_dbg_sprs(env);
6461 register_power7_common_sprs(env);
6462 register_power8_tce_address_control_sprs(env);
6463 register_power8_ids_sprs(env);
6464 register_power8_ebb_sprs(env);
6465 register_power8_fscr_sprs(env);
6466 register_power8_pmu_sup_sprs(env);
6467 register_power8_pmu_user_sprs(env);
6468 register_power8_tm_sprs(env);
6469 register_power8_pspb_sprs(env);
6470 register_power8_dpdes_sprs(env);
6471 register_vtb_sprs(env);
6472 register_power8_ic_sprs(env);
6473 register_power9_book4_sprs(env);
6474 register_power8_rpr_sprs(env);
6475 register_power9_mmu_sprs(env);
6476
6477 /* FIXME: Filter fields properly based on privilege level */
6478 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6479 spr_read_generic, spr_write_generic,
6480 KVM_REG_PPC_PSSCR, 0);
6481
6482 spr_register_hv(env, SPR_PMSR, "PMSR",
6483 SPR_NOACCESS, SPR_NOACCESS,
6484 SPR_NOACCESS, SPR_NOACCESS,
6485 &spr_read_pmsr, SPR_NOACCESS,
6486 0);
6487 spr_register_hv(env, SPR_PMCR, "PMCR",
6488 SPR_NOACCESS, SPR_NOACCESS,
6489 SPR_NOACCESS, SPR_NOACCESS,
6490 &spr_read_generic, &spr_write_pmcr,
6491 PPC_BIT(63)); /* Version 1 (POWER9/10) */
6492
6493 }
6494
init_proc_POWER9(CPUPPCState * env)6495 static void init_proc_POWER9(CPUPPCState *env)
6496 {
6497 register_power9_common_sprs(env);
6498 register_HEIR32_spr(env);
6499 /* POWER9 Specific registers */
6500 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6501 spr_read_generic, spr_write_generic,
6502 KVM_REG_PPC_TIDR, 0);
6503 /* env variables */
6504 env->dcache_line_size = 128;
6505 env->icache_line_size = 128;
6506
6507 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2);
6508
6509 /* Allocate hardware IRQ controller */
6510 init_excp_POWER9(env);
6511 ppcPOWER9_irq_init(env_archcpu(env));
6512 }
6513
ppc_pvr_match_power9(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6514 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6515 {
6516 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6517 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6518
6519 if (!best) {
6520 if (base == CPU_POWERPC_POWER9_BASE) {
6521 return true;
6522 }
6523 }
6524
6525 if (base != pcc_base) {
6526 return false;
6527 }
6528
6529 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) {
6530 /* Major DD version does not match */
6531 return false;
6532 }
6533
6534 if ((pvr & 0x0f00) == 0x200) {
6535 if ((pvr & 0xf) < 2) {
6536 /* DD2.0, DD2.1 match power9_v2.0 */
6537 if ((pcc->pvr & 0xf) == 0) {
6538 return true;
6539 }
6540 } else {
6541 /* DD2.2, DD2.3 match power9_v2.2 */
6542 if ((pcc->pvr & 0xf) == 2) {
6543 return true;
6544 }
6545 }
6546 }
6547
6548 return false;
6549 }
6550
POWERPC_FAMILY(POWER9)6551 POWERPC_FAMILY(POWER9)(ObjectClass *oc, const void *data)
6552 {
6553 DeviceClass *dc = DEVICE_CLASS(oc);
6554 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6555
6556 dc->fw_name = "PowerPC,POWER9";
6557 dc->desc = "POWER9";
6558 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00;
6559 pcc->pvr_match = ppc_pvr_match_power9;
6560 pcc->pcr_mask = PPC_PCR_MASK_POWER9;
6561 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9;
6562 pcc->init_proc = init_proc_POWER9;
6563 pcc->check_pow = check_pow_nocheck;
6564 pcc->check_attn = check_attn_hid0_power9;
6565 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9;
6566 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9;
6567 pcc->msr_mask = PPC_MSR_MASK_POWER9;
6568 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9;
6569 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6570 pcc->mmu_model = POWERPC_MMU_3_00;
6571 #if !defined(CONFIG_USER_ONLY)
6572 /* segment page size remain the same */
6573 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6574 pcc->radix_page_info = &POWER9_radix_page_info;
6575 pcc->lrg_decr_bits = 56;
6576 pcc->n_host_threads = 4;
6577 #endif
6578 pcc->excp_model = POWERPC_EXCP_POWER9;
6579 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6580 pcc->bfd_mach = bfd_mach_ppc64;
6581 pcc->flags = POWERPC_FLAGS_POWER9;
6582 pcc->l1_dcache_size = 0x8000;
6583 pcc->l1_icache_size = 0x8000;
6584 }
6585
6586 #ifndef CONFIG_USER_ONLY
6587 /*
6588 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6589 * Encoded as array of int_32s in the form:
6590 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6591 * x -> AP encoding
6592 * y -> radix mode supported page size (encoded as a shift)
6593 */
6594 static struct ppc_radix_page_info POWER10_radix_page_info = {
6595 .count = 4,
6596 .entries = {
6597 0x0000000c, /* 4K - enc: 0x0 */
6598 0xa0000010, /* 64K - enc: 0x5 */
6599 0x20000015, /* 2M - enc: 0x1 */
6600 0x4000001e /* 1G - enc: 0x2 */
6601 }
6602 };
6603 #endif /* !CONFIG_USER_ONLY */
6604
6605 #define POWER10_BHRB_ENTRIES_LOG2 5
init_proc_POWER10(CPUPPCState * env)6606 static void init_proc_POWER10(CPUPPCState *env)
6607 {
6608 register_power9_common_sprs(env);
6609 register_HEIR64_spr(env);
6610 register_book3s_310_dbg_sprs(env);
6611 register_power10_hash_sprs(env);
6612 register_power10_dexcr_sprs(env);
6613 register_power10_pmu_sup_sprs(env);
6614 register_power10_pmu_user_sprs(env);
6615 /* env variables */
6616 env->dcache_line_size = 128;
6617 env->icache_line_size = 128;
6618
6619 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2);
6620
6621 /* Allocate hardware IRQ controller */
6622 init_excp_POWER10(env);
6623 ppcPOWER9_irq_init(env_archcpu(env));
6624 }
6625
ppc_pvr_match_power10(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6626 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6627 {
6628 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6629 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6630
6631 if (!best) {
6632 if (base == CPU_POWERPC_POWER10_BASE) {
6633 return true;
6634 }
6635 }
6636
6637 if (base != pcc_base) {
6638 return false;
6639 }
6640
6641 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6642 /* Major DD version matches power10_v2.0 */
6643 return true;
6644 }
6645
6646 return false;
6647 }
6648
POWERPC_FAMILY(POWER10)6649 POWERPC_FAMILY(POWER10)(ObjectClass *oc, const void *data)
6650 {
6651 DeviceClass *dc = DEVICE_CLASS(oc);
6652 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6653
6654 dc->fw_name = "PowerPC,POWER10";
6655 dc->desc = "POWER10";
6656 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10;
6657 pcc->pvr_match = ppc_pvr_match_power10;
6658 pcc->pcr_mask = PPC_PCR_MASK_POWER10;
6659 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10;
6660 pcc->init_proc = init_proc_POWER10;
6661 pcc->check_pow = check_pow_nocheck;
6662 pcc->check_attn = check_attn_hid0_power9;
6663 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10;
6664 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10;
6665 pcc->msr_mask = PPC_MSR_MASK_POWER10;
6666 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10;
6667
6668 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6669 pcc->mmu_model = POWERPC_MMU_3_00;
6670 #if !defined(CONFIG_USER_ONLY)
6671 /* segment page size remain the same */
6672 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6673 pcc->radix_page_info = &POWER10_radix_page_info;
6674 pcc->lrg_decr_bits = 56;
6675 #endif
6676 pcc->excp_model = POWERPC_EXCP_POWER10;
6677 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6678 pcc->bfd_mach = bfd_mach_ppc64;
6679 pcc->flags = POWERPC_FLAGS_POWER10;
6680 pcc->l1_dcache_size = 0x8000;
6681 pcc->l1_icache_size = 0x8000;
6682 }
6683
init_proc_POWER11(CPUPPCState * env)6684 static void init_proc_POWER11(CPUPPCState *env)
6685 {
6686 init_proc_POWER10(env);
6687 }
6688
ppc_pvr_match_power11(PowerPCCPUClass * pcc,uint32_t pvr,bool best)6689 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
6690 {
6691 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6692 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6693
6694 if (!best && (base == CPU_POWERPC_POWER11_BASE)) {
6695 return true;
6696 }
6697
6698 if (base != pcc_base) {
6699 return false;
6700 }
6701
6702 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6703 return true;
6704 }
6705
6706 return false;
6707 }
6708
POWERPC_FAMILY(POWER11)6709 POWERPC_FAMILY(POWER11)(ObjectClass *oc, const void *data)
6710 {
6711 DeviceClass *dc = DEVICE_CLASS(oc);
6712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6713
6714 dc->fw_name = "PowerPC,POWER11";
6715 dc->desc = "POWER11";
6716 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11;
6717 pcc->pvr_match = ppc_pvr_match_power11;
6718 pcc->pcr_mask = PPC_PCR_MASK_POWER11;
6719 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11;
6720 pcc->init_proc = init_proc_POWER11;
6721 pcc->check_pow = check_pow_nocheck;
6722 pcc->check_attn = check_attn_hid0_power9;
6723 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11;
6724 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11;
6725 pcc->msr_mask = PPC_MSR_MASK_POWER11;
6726 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11;
6727
6728 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
6729 pcc->mmu_model = POWERPC_MMU_3_00;
6730 #if !defined(CONFIG_USER_ONLY)
6731 /* segment page size remain the same */
6732 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6733 pcc->radix_page_info = &POWER10_radix_page_info;
6734 pcc->lrg_decr_bits = 56;
6735 #endif
6736 pcc->excp_model = POWERPC_EXCP_POWER11;
6737 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6738 pcc->bfd_mach = bfd_mach_ppc64;
6739 pcc->flags = POWERPC_FLAGS_POWER11;
6740 pcc->l1_dcache_size = 0x8000;
6741 pcc->l1_icache_size = 0x8000;
6742 }
6743
6744 #if !defined(CONFIG_USER_ONLY)
cpu_ppc_set_vhyp(PowerPCCPU * cpu,PPCVirtualHypervisor * vhyp)6745 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
6746 {
6747 CPUPPCState *env = &cpu->env;
6748
6749 cpu->vhyp = vhyp;
6750 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp);
6751
6752 /*
6753 * With a virtual hypervisor mode we never allow the CPU to go
6754 * hypervisor mode itself
6755 */
6756 env->msr_mask &= ~MSR_HVB;
6757 }
6758
cpu_ppc_set_1lpar(PowerPCCPU * cpu)6759 void cpu_ppc_set_1lpar(PowerPCCPU *cpu)
6760 {
6761 CPUPPCState *env = &cpu->env;
6762
6763 /*
6764 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable
6765 * between threads. powernv be in either mode, and it mostly affects
6766 * supervisor visible registers and instructions.
6767 */
6768 if (env->flags & POWERPC_FLAG_SMT) {
6769 env->flags |= POWERPC_FLAG_SMT_1LPAR;
6770 }
6771 }
6772 #endif /* !defined(CONFIG_USER_ONLY) */
6773
6774 #endif /* defined(TARGET_PPC64) */
6775
6776 /*****************************************************************************/
6777 /* Generic CPU instantiation routine */
init_ppc_proc(PowerPCCPU * cpu)6778 static void init_ppc_proc(PowerPCCPU *cpu)
6779 {
6780 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6781 CPUPPCState *env = &cpu->env;
6782 #if !defined(CONFIG_USER_ONLY)
6783 int i;
6784
6785 /* Set all exception vectors to an invalid address */
6786 for (i = 0; i < POWERPC_EXCP_NB; i++) {
6787 env->excp_vectors[i] = (target_ulong)(-1ULL);
6788 }
6789 env->ivor_mask = 0x00000000;
6790 env->ivpr_mask = 0x00000000;
6791 /* Default MMU definitions */
6792 env->nb_BATs = 0;
6793 env->nb_tlb = 0;
6794 env->nb_ways = 0;
6795 env->tlb_type = TLB_NONE;
6796 #endif
6797 /* Register SPR common to all PowerPC implementations */
6798 register_generic_sprs(cpu);
6799
6800 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
6801 (*pcc->init_proc)(env);
6802
6803 /* MSR bits & flags consistency checks */
6804 if (env->msr_mask & (1 << 25)) {
6805 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6806 case POWERPC_FLAG_SPE:
6807 case POWERPC_FLAG_VRE:
6808 break;
6809 default:
6810 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6811 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6812 exit(1);
6813 }
6814 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6815 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6816 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6817 exit(1);
6818 }
6819 if (env->msr_mask & (1 << 17)) {
6820 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6821 case POWERPC_FLAG_TGPR:
6822 case POWERPC_FLAG_CE:
6823 break;
6824 default:
6825 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6826 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6827 exit(1);
6828 }
6829 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6830 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6831 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6832 exit(1);
6833 }
6834 if (env->msr_mask & (1 << 10)) {
6835 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6836 POWERPC_FLAG_UBLE)) {
6837 case POWERPC_FLAG_SE:
6838 case POWERPC_FLAG_DWE:
6839 case POWERPC_FLAG_UBLE:
6840 break;
6841 default:
6842 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6843 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6844 "POWERPC_FLAG_UBLE\n");
6845 exit(1);
6846 }
6847 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6848 POWERPC_FLAG_UBLE)) {
6849 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6850 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6851 "POWERPC_FLAG_UBLE\n");
6852 exit(1);
6853 }
6854 if (env->msr_mask & (1 << 9)) {
6855 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6856 case POWERPC_FLAG_BE:
6857 case POWERPC_FLAG_DE:
6858 break;
6859 default:
6860 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6861 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6862 exit(1);
6863 }
6864 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6865 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6866 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6867 exit(1);
6868 }
6869 if (env->msr_mask & (1 << 2)) {
6870 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6871 case POWERPC_FLAG_PX:
6872 case POWERPC_FLAG_PMM:
6873 break;
6874 default:
6875 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6876 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6877 exit(1);
6878 }
6879 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6880 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6881 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6882 exit(1);
6883 }
6884 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
6885 fprintf(stderr, "PowerPC flags inconsistency\n"
6886 "Should define the time-base and decrementer clock source\n");
6887 exit(1);
6888 }
6889 /* Allocate TLBs buffer when needed */
6890 #if !defined(CONFIG_USER_ONLY)
6891 if (env->nb_tlb) {
6892 switch (env->tlb_type) {
6893 case TLB_6XX:
6894 /* 6xx has separate TLBs for instructions and data hence times 2 */
6895 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb);
6896 break;
6897 case TLB_EMB:
6898 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb);
6899 break;
6900 case TLB_MAS:
6901 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb);
6902 break;
6903 }
6904 /* Pre-compute some useful values */
6905 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6906 }
6907 #endif
6908 if (env->check_pow == NULL) {
6909 warn_report("no power management check handler registered."
6910 " Attempt QEMU to crash very soon !");
6911 }
6912
6913 if (env->check_attn == NULL) {
6914 warn_report("no attn check handler registered."
6915 " Attempt QEMU to crash very soon !");
6916 }
6917 }
6918
6919
ppc_cpu_realize(DeviceState * dev,Error ** errp)6920 static void ppc_cpu_realize(DeviceState *dev, Error **errp)
6921 {
6922 CPUState *cs = CPU(dev);
6923 PowerPCCPU *cpu = POWERPC_CPU(dev);
6924 CPUPPCState *env = &cpu->env;
6925 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6926 Error *local_err = NULL;
6927
6928 cpu_exec_realizefn(cs, &local_err);
6929 if (local_err != NULL) {
6930 error_propagate(errp, local_err);
6931 return;
6932 }
6933 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6934 cpu->vcpu_id = cs->cpu_index;
6935 }
6936
6937 if (tcg_enabled()) {
6938 if (ppc_fixup_cpu(cpu) != 0) {
6939 error_setg(errp, "Unable to emulate selected CPU with TCG");
6940 goto unrealize;
6941 }
6942 }
6943
6944 create_ppc_opcodes(cpu, &local_err);
6945 if (local_err != NULL) {
6946 error_propagate(errp, local_err);
6947 goto unrealize;
6948 }
6949 init_ppc_proc(cpu);
6950
6951 ppc_gdb_init(cs, pcc);
6952 qemu_init_vcpu(cs);
6953
6954 pcc->parent_realize(dev, errp);
6955
6956 if (!ppc_cpu_core_single_threaded(cs)) {
6957 env->flags |= POWERPC_FLAG_SMT;
6958 }
6959
6960 return;
6961
6962 unrealize:
6963 cpu_exec_unrealizefn(cs);
6964 }
6965
ppc_cpu_unrealize(DeviceState * dev)6966 static void ppc_cpu_unrealize(DeviceState *dev)
6967 {
6968 PowerPCCPU *cpu = POWERPC_CPU(dev);
6969 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6970
6971 pcc->parent_unrealize(dev);
6972
6973 cpu_remove_sync(CPU(cpu));
6974
6975 destroy_ppc_opcodes(cpu);
6976 }
6977
ppc_cpu_compare_class_pvr(gconstpointer a,gconstpointer b)6978 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
6979 {
6980 ObjectClass *oc = (ObjectClass *)a;
6981 uint32_t pvr = *(uint32_t *)b;
6982 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6983
6984 /* -cpu host does a PVR lookup during construction */
6985 if (unlikely(strcmp(object_class_get_name(oc),
6986 TYPE_HOST_POWERPC_CPU) == 0)) {
6987 return -1;
6988 }
6989
6990 return pcc->pvr == pvr ? 0 : -1;
6991 }
6992
ppc_cpu_class_by_pvr(uint32_t pvr)6993 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
6994 {
6995 GSList *list, *item;
6996 PowerPCCPUClass *pcc = NULL;
6997
6998 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6999 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
7000 if (item != NULL) {
7001 pcc = POWERPC_CPU_CLASS(item->data);
7002 }
7003 g_slist_free(list);
7004
7005 return pcc;
7006 }
7007
ppc_cpu_compare_class_pvr_mask(gconstpointer a,gconstpointer b)7008 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
7009 {
7010 ObjectClass *oc = (ObjectClass *)a;
7011 uint32_t pvr = *(uint32_t *)b;
7012 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
7013
7014 /* -cpu host does a PVR lookup during construction */
7015 if (unlikely(strcmp(object_class_get_name(oc),
7016 TYPE_HOST_POWERPC_CPU) == 0)) {
7017 return -1;
7018 }
7019
7020 if (pcc->pvr_match(pcc, pvr, true)) {
7021 return 0;
7022 }
7023
7024 return -1;
7025 }
7026
ppc_cpu_class_by_pvr_mask(uint32_t pvr)7027 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
7028 {
7029 GSList *list, *item;
7030 PowerPCCPUClass *pcc = NULL;
7031
7032 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7033 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7034 if (item != NULL) {
7035 pcc = POWERPC_CPU_CLASS(item->data);
7036 }
7037 g_slist_free(list);
7038
7039 return pcc;
7040 }
7041
ppc_cpu_lookup_alias(const char * alias)7042 static const char *ppc_cpu_lookup_alias(const char *alias)
7043 {
7044 int ai;
7045
7046 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7047 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7048 return ppc_cpu_aliases[ai].model;
7049 }
7050 }
7051
7052 return NULL;
7053 }
7054
ppc_cpu_class_by_name(const char * name)7055 ObjectClass *ppc_cpu_class_by_name(const char *name)
7056 {
7057 char *cpu_model, *typename;
7058 ObjectClass *oc;
7059 const char *p;
7060 unsigned long pvr;
7061
7062 /*
7063 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7064 * 0x prefix if present)
7065 */
7066 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7067 int len = p - name;
7068 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7069 if ((len == 8) && (*p == '\0')) {
7070 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
7071 }
7072 }
7073
7074 /*
7075 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
7076 * do not have a "max" CPU with all possible emulated features enabled.
7077 * Return the default CPU type for the machine because that has greater
7078 * chance of being useful as the "max" CPU.
7079 */
7080 #if !defined(CONFIG_USER_ONLY)
7081 if (strcmp(name, "max") == 0) {
7082 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
7083 if (mc) {
7084 return object_class_by_name(machine_class_default_cpu_type(mc));
7085 }
7086 }
7087 #endif
7088
7089 cpu_model = g_ascii_strdown(name, -1);
7090 p = ppc_cpu_lookup_alias(cpu_model);
7091 if (p) {
7092 g_free(cpu_model);
7093 cpu_model = g_strdup(p);
7094 }
7095
7096 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7097 oc = object_class_by_name(typename);
7098 g_free(typename);
7099 g_free(cpu_model);
7100
7101 return oc;
7102 }
7103
ppc_cpu_get_family_class(PowerPCCPUClass * pcc)7104 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7105 {
7106 ObjectClass *oc = OBJECT_CLASS(pcc);
7107
7108 while (oc && !object_class_is_abstract(oc)) {
7109 oc = object_class_get_parent(oc);
7110 }
7111 assert(oc);
7112
7113 return POWERPC_CPU_CLASS(oc);
7114 }
7115
7116 /* Sort by PVR, ordering special case "host" last. */
ppc_cpu_list_compare(gconstpointer a,gconstpointer b,gpointer d)7117 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b, gpointer d)
7118 {
7119 ObjectClass *oc_a = (ObjectClass *)a;
7120 ObjectClass *oc_b = (ObjectClass *)b;
7121 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7122 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7123 const char *name_a = object_class_get_name(oc_a);
7124 const char *name_b = object_class_get_name(oc_b);
7125
7126 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7127 return 1;
7128 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7129 return -1;
7130 } else {
7131 /* Avoid an integer overflow during subtraction */
7132 if (pcc_a->pvr < pcc_b->pvr) {
7133 return -1;
7134 } else if (pcc_a->pvr > pcc_b->pvr) {
7135 return 1;
7136 } else {
7137 return 0;
7138 }
7139 }
7140 }
7141
ppc_cpu_list_entry(gpointer data,gpointer user_data)7142 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7143 {
7144 ObjectClass *oc = data;
7145 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7146 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
7147 const char *typename = object_class_get_name(oc);
7148 char *name;
7149 int i;
7150
7151 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7152 return;
7153 }
7154
7155 name = cpu_model_from_type(typename);
7156 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr);
7157 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
7158 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
7159 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
7160
7161 if (alias_oc != oc) {
7162 continue;
7163 }
7164 /*
7165 * If running with KVM, we might update the family alias later, so
7166 * avoid printing the wrong alias here and use "preferred" instead
7167 */
7168 if (strcmp(alias->alias, family->desc) == 0) {
7169 qemu_printf(" %-16s (alias for preferred %s CPU)\n",
7170 alias->alias, family->desc);
7171 } else {
7172 qemu_printf(" %-16s (alias for %s)\n",
7173 alias->alias, name);
7174 }
7175 }
7176 g_free(name);
7177 }
7178
ppc_cpu_list(void)7179 static void ppc_cpu_list(void)
7180 {
7181 GSList *list;
7182
7183 qemu_printf("Available CPUs:\n");
7184 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7185 list = g_slist_sort_with_data(list, ppc_cpu_list_compare, NULL);
7186 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
7187 g_slist_free(list);
7188
7189 #ifdef CONFIG_KVM
7190 qemu_printf("\n");
7191 qemu_printf(" %s\n", "host");
7192 #endif
7193 }
7194
ppc_cpu_set_pc(CPUState * cs,vaddr value)7195 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7196 {
7197 PowerPCCPU *cpu = POWERPC_CPU(cs);
7198
7199 cpu->env.nip = value;
7200 }
7201
ppc_cpu_get_pc(CPUState * cs)7202 static vaddr ppc_cpu_get_pc(CPUState *cs)
7203 {
7204 PowerPCCPU *cpu = POWERPC_CPU(cs);
7205
7206 return cpu->env.nip;
7207 }
7208
7209 #ifdef CONFIG_TCG
ppc_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)7210 static void ppc_restore_state_to_opc(CPUState *cs,
7211 const TranslationBlock *tb,
7212 const uint64_t *data)
7213 {
7214 PowerPCCPU *cpu = POWERPC_CPU(cs);
7215
7216 cpu->env.nip = data[0];
7217 }
7218
ppc_cpu_mmu_index(CPUState * cs,bool ifetch)7219 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch)
7220 {
7221 return ppc_env_mmu_index(cpu_env(cs), ifetch);
7222 }
7223 #endif /* CONFIG_TCG */
7224
7225 #ifndef CONFIG_USER_ONLY
ppc_cpu_has_work(CPUState * cs)7226 static bool ppc_cpu_has_work(CPUState *cs)
7227 {
7228 return cs->interrupt_request & CPU_INTERRUPT_HARD;
7229 }
7230 #endif /* !CONFIG_USER_ONLY */
7231
ppc_cpu_reset_hold(Object * obj,ResetType type)7232 static void ppc_cpu_reset_hold(Object *obj, ResetType type)
7233 {
7234 CPUState *cs = CPU(obj);
7235 PowerPCCPU *cpu = POWERPC_CPU(cs);
7236 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj);
7237 CPUPPCState *env = &cpu->env;
7238 target_ulong msr;
7239 int i;
7240
7241 if (pcc->parent_phases.hold) {
7242 pcc->parent_phases.hold(obj, type);
7243 }
7244
7245 msr = (target_ulong)0;
7246 msr |= (target_ulong)MSR_HVB;
7247 msr |= (target_ulong)1 << MSR_EP;
7248 #if defined(DO_SINGLE_STEP) && 0
7249 /* Single step trace mode */
7250 msr |= (target_ulong)1 << MSR_SE;
7251 msr |= (target_ulong)1 << MSR_BE;
7252 #endif
7253 #if defined(CONFIG_USER_ONLY)
7254 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
7255 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7256 msr |= (target_ulong)1 << MSR_FE1;
7257 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
7258 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
7259 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7260 msr |= (target_ulong)1 << MSR_PR;
7261 #if defined(TARGET_PPC64)
7262 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7263 #endif
7264 #if !TARGET_BIG_ENDIAN
7265 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
7266 if (!((env->msr_mask >> MSR_LE) & 1)) {
7267 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7268 exit(1);
7269 }
7270 #endif
7271 #endif
7272
7273 #if defined(TARGET_PPC64)
7274 if (mmu_is_64bit(env->mmu_model)) {
7275 msr |= (1ULL << MSR_SF);
7276 }
7277 #endif
7278
7279 hreg_store_msr(env, msr, 1);
7280
7281 #if !defined(CONFIG_USER_ONLY)
7282 env->nip = env->hreset_vector | env->excp_prefix;
7283
7284 if (tcg_enabled()) {
7285 cpu_breakpoint_remove_all(cs, BP_CPU);
7286 cpu_watchpoint_remove_all(cs, BP_CPU);
7287 if (env->mmu_model != POWERPC_MMU_REAL) {
7288 ppc_tlb_invalidate_all(env);
7289 }
7290 pmu_mmcr01a_updated(env);
7291 }
7292
7293 /* clean any pending stop state */
7294 env->resume_as_sreset = 0;
7295 #endif
7296 hreg_compute_hflags(env);
7297 env->reserve_addr = (target_ulong)-1ULL;
7298 /* Be sure no exception or interrupt is pending */
7299 env->pending_interrupts = 0;
7300 cs->exception_index = POWERPC_EXCP_NONE;
7301 env->error_code = 0;
7302 ppc_irq_reset(cpu);
7303
7304 /* tininess for underflow is detected before rounding */
7305 set_float_detect_tininess(float_tininess_before_rounding,
7306 &env->fp_status);
7307 /* Similarly for flush-to-zero */
7308 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
7309
7310 /*
7311 * PowerPC propagation rules:
7312 * 1. A if it sNaN or qNaN
7313 * 2. B if it sNaN or qNaN
7314 * A signaling NaN is always silenced before returning it.
7315 */
7316 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
7317 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
7318 /*
7319 * NaN propagation for fused multiply-add:
7320 * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
7321 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
7322 * whereas QEMU labels the operands as (a * b) + c.
7323 */
7324 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
7325 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
7326 /*
7327 * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
7328 * to return an input NaN if we have one (ie c) rather than generating
7329 * a default NaN
7330 */
7331 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
7332 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
7333
7334 /* Default NaN: sign bit clear, set frac msb */
7335 set_float_default_nan_pattern(0b01000000, &env->fp_status);
7336 set_float_default_nan_pattern(0b01000000, &env->vec_status);
7337
7338 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7339 ppc_spr_t *spr = &env->spr_cb[i];
7340
7341 if (!spr->name) {
7342 continue;
7343 }
7344 env->spr[i] = spr->default_value;
7345 }
7346
7347 #if defined(TARGET_PPC64)
7348 bhrb_reset_state(env);
7349 #endif
7350 }
7351
7352 #ifndef CONFIG_USER_ONLY
7353
ppc_cpu_is_big_endian(CPUState * cs)7354 static bool ppc_cpu_is_big_endian(CPUState *cs)
7355 {
7356 cpu_synchronize_state(cs);
7357
7358 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE);
7359 }
7360
ppc_get_irq_stats(InterruptStatsProvider * obj,uint64_t ** irq_counts,unsigned int * nb_irqs)7361 static bool ppc_get_irq_stats(InterruptStatsProvider *obj,
7362 uint64_t **irq_counts, unsigned int *nb_irqs)
7363 {
7364 CPUPPCState *env = &POWERPC_CPU(obj)->env;
7365
7366 *irq_counts = env->excp_stats;
7367 *nb_irqs = ARRAY_SIZE(env->excp_stats);
7368 return true;
7369 }
7370
7371 #ifdef CONFIG_TCG
ppc_cpu_exec_enter(CPUState * cs)7372 static void ppc_cpu_exec_enter(CPUState *cs)
7373 {
7374 PowerPCCPU *cpu = POWERPC_CPU(cs);
7375
7376 if (cpu->vhyp) {
7377 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu);
7378 }
7379 }
7380
ppc_cpu_exec_exit(CPUState * cs)7381 static void ppc_cpu_exec_exit(CPUState *cs)
7382 {
7383 PowerPCCPU *cpu = POWERPC_CPU(cs);
7384
7385 if (cpu->vhyp) {
7386 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu);
7387 }
7388 }
7389
ppc_pointer_wrap(CPUState * cs,int mmu_idx,vaddr result,vaddr base)7390 static vaddr ppc_pointer_wrap(CPUState *cs, int mmu_idx,
7391 vaddr result, vaddr base)
7392 {
7393 return (cpu_env(cs)->hflags >> HFLAGS_64) & 1 ? result : (uint32_t)result;
7394 }
7395 #endif /* CONFIG_TCG */
7396
7397 #endif /* !CONFIG_USER_ONLY */
7398
ppc_cpu_instance_init(Object * obj)7399 static void ppc_cpu_instance_init(Object *obj)
7400 {
7401 PowerPCCPU *cpu = POWERPC_CPU(obj);
7402 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7403 CPUPPCState *env = &cpu->env;
7404
7405 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
7406
7407 env->msr_mask = pcc->msr_mask;
7408 env->mmu_model = pcc->mmu_model;
7409 env->excp_model = pcc->excp_model;
7410 env->bus_model = pcc->bus_model;
7411 env->insns_flags = pcc->insns_flags;
7412 env->insns_flags2 = pcc->insns_flags2;
7413 env->flags = pcc->flags;
7414 env->bfd_mach = pcc->bfd_mach;
7415 env->check_pow = pcc->check_pow;
7416 env->check_attn = pcc->check_attn;
7417
7418 /*
7419 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7420 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7421 * mode support will remain, thus enforcing that we cannot use
7422 * priv. instructions in guest in PAPR mode. For 970 we currently
7423 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7424 * 970. If we ever want to support 970 HV mode, we'll have to add
7425 * a processor attribute of some sort.
7426 */
7427 #if !defined(CONFIG_USER_ONLY)
7428 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7429 #endif
7430
7431 ppc_hash64_init(cpu);
7432 }
7433
ppc_cpu_instance_finalize(Object * obj)7434 static void ppc_cpu_instance_finalize(Object *obj)
7435 {
7436 PowerPCCPU *cpu = POWERPC_CPU(obj);
7437
7438 ppc_hash64_finalize(cpu);
7439 }
7440
ppc_pvr_match_default(PowerPCCPUClass * pcc,uint32_t pvr,bool best)7441 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7442 {
7443 return pcc->pvr == pvr;
7444 }
7445
ppc_disas_set_info(CPUState * cs,disassemble_info * info)7446 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7447 {
7448 CPUPPCState *env = cpu_env(cs);
7449
7450 if ((env->hflags >> MSR_LE) & 1) {
7451 info->endian = BFD_ENDIAN_LITTLE;
7452 } else {
7453 info->endian = BFD_ENDIAN_BIG;
7454 }
7455 info->mach = env->bfd_mach;
7456 if (!env->bfd_mach) {
7457 #ifdef TARGET_PPC64
7458 info->mach = bfd_mach_ppc64;
7459 #else
7460 info->mach = bfd_mach_ppc;
7461 #endif
7462 }
7463
7464 info->cap_arch = CS_ARCH_PPC;
7465 #ifdef TARGET_PPC64
7466 info->cap_mode = CS_MODE_64;
7467 #endif
7468 }
7469
7470 #ifndef CONFIG_USER_ONLY
7471 #include "hw/core/sysemu-cpu-ops.h"
7472
7473 static const struct SysemuCPUOps ppc_sysemu_ops = {
7474 .has_work = ppc_cpu_has_work,
7475 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
7476 .write_elf32_note = ppc32_cpu_write_elf32_note,
7477 .write_elf64_note = ppc64_cpu_write_elf64_note,
7478 .virtio_is_big_endian = ppc_cpu_is_big_endian,
7479 .legacy_vmsd = &vmstate_ppc_cpu,
7480 };
7481 #endif
7482
7483 #ifdef CONFIG_TCG
7484 #include "accel/tcg/cpu-ops.h"
7485
7486 static const TCGCPUOps ppc_tcg_ops = {
7487 .mttcg_supported = TARGET_LONG_BITS == 64,
7488 .guest_default_memory_order = 0,
7489 .initialize = ppc_translate_init,
7490 .translate_code = ppc_translate_code,
7491 .get_tb_cpu_state = ppc_get_tb_cpu_state,
7492 .restore_state_to_opc = ppc_restore_state_to_opc,
7493 .mmu_index = ppc_cpu_mmu_index,
7494
7495 #ifdef CONFIG_USER_ONLY
7496 .record_sigsegv = ppc_cpu_record_sigsegv,
7497 #else
7498 .tlb_fill = ppc_cpu_tlb_fill,
7499 .pointer_wrap = ppc_pointer_wrap,
7500 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
7501 .cpu_exec_halt = ppc_cpu_has_work,
7502 .cpu_exec_reset = cpu_reset,
7503 .do_interrupt = ppc_cpu_do_interrupt,
7504 .cpu_exec_enter = ppc_cpu_exec_enter,
7505 .cpu_exec_exit = ppc_cpu_exec_exit,
7506 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7507 .do_transaction_failed = ppc_cpu_do_transaction_failed,
7508 .debug_excp_handler = ppc_cpu_debug_excp_handler,
7509 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint,
7510 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint,
7511 #endif /* !CONFIG_USER_ONLY */
7512 };
7513 #endif /* CONFIG_TCG */
7514
ppc_cpu_class_init(ObjectClass * oc,const void * data)7515 static void ppc_cpu_class_init(ObjectClass *oc, const void *data)
7516 {
7517 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7518 CPUClass *cc = CPU_CLASS(oc);
7519 DeviceClass *dc = DEVICE_CLASS(oc);
7520 ResettableClass *rc = RESETTABLE_CLASS(oc);
7521
7522 device_class_set_parent_realize(dc, ppc_cpu_realize,
7523 &pcc->parent_realize);
7524 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
7525 &pcc->parent_unrealize);
7526 pcc->pvr_match = ppc_pvr_match_default;
7527
7528 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL,
7529 &pcc->parent_phases);
7530
7531 cc->class_by_name = ppc_cpu_class_by_name;
7532 cc->list_cpus = ppc_cpu_list;
7533 cc->dump_state = ppc_cpu_dump_state;
7534 cc->set_pc = ppc_cpu_set_pc;
7535 cc->get_pc = ppc_cpu_get_pc;
7536 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7537 cc->gdb_write_register = ppc_cpu_gdb_write_register;
7538 #ifndef CONFIG_USER_ONLY
7539 cc->sysemu_ops = &ppc_sysemu_ops;
7540 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats;
7541
7542 /* check_prot_access_type relies on MMU access and PAGE bits relations */
7543 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 &&
7544 MMU_INST_FETCH == 2 && PAGE_READ == 1 &&
7545 PAGE_WRITE == 2 && PAGE_EXEC == 4);
7546 #endif
7547
7548 cc->gdb_num_core_regs = 71;
7549 #ifdef USE_APPLE_GDB
7550 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7551 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7552 cc->gdb_num_core_regs = 71 + 32;
7553 #endif
7554
7555 cc->gdb_arch_name = ppc_gdb_arch_name;
7556 #if defined(TARGET_PPC64)
7557 cc->gdb_core_xml_file = "power64-core.xml";
7558 #else
7559 cc->gdb_core_xml_file = "power-core.xml";
7560 #endif
7561 cc->disas_set_info = ppc_disas_set_info;
7562
7563 dc->fw_name = "PowerPC,UNKNOWN";
7564
7565 #ifdef CONFIG_TCG
7566 cc->tcg_ops = &ppc_tcg_ops;
7567 #endif /* CONFIG_TCG */
7568 }
7569
7570 static const TypeInfo ppc_cpu_type_info = {
7571 .name = TYPE_POWERPC_CPU,
7572 .parent = TYPE_CPU,
7573 .instance_size = sizeof(PowerPCCPU),
7574 .instance_align = __alignof__(PowerPCCPU),
7575 .instance_init = ppc_cpu_instance_init,
7576 .instance_finalize = ppc_cpu_instance_finalize,
7577 .abstract = true,
7578 .class_size = sizeof(PowerPCCPUClass),
7579 .class_init = ppc_cpu_class_init,
7580 #ifndef CONFIG_USER_ONLY
7581 .interfaces = (const InterfaceInfo[]) {
7582 { TYPE_INTERRUPT_STATS_PROVIDER },
7583 { }
7584 },
7585 #endif
7586 };
7587
7588 #ifndef CONFIG_USER_ONLY
7589 static const TypeInfo ppc_vhyp_type_info = {
7590 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7591 .parent = TYPE_INTERFACE,
7592 .class_size = sizeof(PPCVirtualHypervisorClass),
7593 };
7594 #endif
7595
ppc_cpu_register_types(void)7596 static void ppc_cpu_register_types(void)
7597 {
7598 type_register_static(&ppc_cpu_type_info);
7599 #ifndef CONFIG_USER_ONLY
7600 type_register_static(&ppc_vhyp_type_info);
7601 #endif
7602 }
7603
ppc_cpu_dump_state(CPUState * cs,FILE * f,int flags)7604 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7605 {
7606 #define RGPL 4
7607 #define RFPL 4
7608
7609 CPUPPCState *env = cpu_env(cs);
7610 int i;
7611
7612 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7613 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7614 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7615 cs->cpu_index);
7616 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7617 "%08x iidx %d didx %d\n",
7618 env->msr, env->spr[SPR_HID0], env->hflags,
7619 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false));
7620 #if !defined(CONFIG_USER_ONLY)
7621 if (env->tb_env) {
7622 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7623 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7624 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7625 }
7626 #else
7627 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7628 cpu_ppc_load_tbl(env));
7629 #endif
7630 for (i = 0; i < 32; i++) {
7631 if ((i & (RGPL - 1)) == 0) {
7632 qemu_fprintf(f, "GPR%02d", i);
7633 }
7634 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7635 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7636 qemu_fprintf(f, "\n");
7637 }
7638 }
7639 qemu_fprintf(f, "CR ");
7640 for (i = 0; i < 8; i++)
7641 qemu_fprintf(f, "%01x", env->crf[i]);
7642 qemu_fprintf(f, " [");
7643 for (i = 0; i < 8; i++) {
7644 char a = '-';
7645 if (env->crf[i] & 0x08) {
7646 a = 'L';
7647 } else if (env->crf[i] & 0x04) {
7648 a = 'G';
7649 } else if (env->crf[i] & 0x02) {
7650 a = 'E';
7651 }
7652 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7653 }
7654 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n",
7655 (int)env->reserve_length, env->reserve_addr);
7656
7657 if (flags & CPU_DUMP_FPU) {
7658 for (i = 0; i < 32; i++) {
7659 if ((i & (RFPL - 1)) == 0) {
7660 qemu_fprintf(f, "FPR%02d", i);
7661 }
7662 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7663 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7664 qemu_fprintf(f, "\n");
7665 }
7666 }
7667 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7668 }
7669
7670 #if !defined(CONFIG_USER_ONLY)
7671 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7672 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7673 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7674 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7675
7676 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7677 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7678 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7679 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7680
7681 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7682 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7683 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7684 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7685
7686 switch (env->excp_model) {
7687 #if defined(TARGET_PPC64)
7688 case POWERPC_EXCP_POWER7:
7689 case POWERPC_EXCP_POWER8:
7690 case POWERPC_EXCP_POWER9:
7691 case POWERPC_EXCP_POWER10:
7692 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7693 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
7694 break;
7695 #endif
7696 case POWERPC_EXCP_BOOKE:
7697 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7698 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7699 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7700 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7701
7702 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7703 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7704 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7705 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7706
7707 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7708 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7709 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7710 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7711
7712 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7713 " EPR " TARGET_FMT_lx "\n",
7714 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7715 env->spr[SPR_BOOKE_EPR]);
7716
7717 /* FSL-specific */
7718 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7719 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7720 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7721 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7722
7723 /*
7724 * IVORs are left out as they are large and do not change often --
7725 * they can be read with "p $ivor0", "p $ivor1", etc.
7726 */
7727 break;
7728 case POWERPC_EXCP_40x:
7729 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7730 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7731 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7732 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7733
7734 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7735 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7736 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7737 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7738 break;
7739 default:
7740 break;
7741 }
7742
7743 #if defined(TARGET_PPC64)
7744 if (env->flags & POWERPC_FLAG_CFAR) {
7745 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7746 }
7747 #endif
7748
7749 if (env->spr_cb[SPR_LPCR].name) {
7750 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7751 }
7752
7753 switch (env->mmu_model) {
7754 case POWERPC_MMU_32B:
7755 case POWERPC_MMU_SOFT_6xx:
7756 #if defined(TARGET_PPC64)
7757 case POWERPC_MMU_64B:
7758 case POWERPC_MMU_2_03:
7759 case POWERPC_MMU_2_06:
7760 case POWERPC_MMU_2_07:
7761 case POWERPC_MMU_3_00:
7762 #endif
7763 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7764 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7765 }
7766 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7767 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7768 }
7769 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7770 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7771 break;
7772 case POWERPC_MMU_BOOKE206:
7773 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7774 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7775 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7776 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7777
7778 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7779 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7780 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7781 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7782
7783 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7784 " TLB1CFG " TARGET_FMT_lx "\n",
7785 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7786 env->spr[SPR_BOOKE_TLB1CFG]);
7787 break;
7788 default:
7789 break;
7790 }
7791 #endif
7792
7793 #undef RGPL
7794 #undef RFPL
7795 }
7796 type_init(ppc_cpu_register_types)
7797