1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AD7606 ADC driver 4 * 5 * Copyright 2011 Analog Devices Inc. 6 */ 7 8 #ifndef IIO_ADC_AD7606_H_ 9 #define IIO_ADC_AD7606_H_ 10 11 #define AD760X_MAX_CHANNELS 16 12 13 #define AD7616_CONFIGURATION_REGISTER 0x02 14 #define AD7616_OS_MASK GENMASK(4, 2) 15 #define AD7616_BURST_MODE BIT(6) 16 #define AD7616_SEQEN_MODE BIT(5) 17 #define AD7616_RANGE_CH_A_ADDR_OFF 0x04 18 #define AD7616_RANGE_CH_B_ADDR_OFF 0x06 19 /* 20 * Range of channels from a group are stored in 2 registers. 21 * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register. 22 * For channels from second group(8-15) the order is the same, only with 23 * an offset of 2 for register address. 24 */ 25 #define AD7616_RANGE_CH_ADDR(ch) ((ch) >> 2) 26 /* The range of the channel is stored in 2 bits */ 27 #define AD7616_RANGE_CH_MSK(ch) (0b11 << (((ch) & 0b11) * 2)) 28 #define AD7616_RANGE_CH_MODE(ch, mode) ((mode) << ((((ch) & 0b11)) * 2)) 29 30 #define AD7606_CONFIGURATION_REGISTER 0x02 31 #define AD7606_SINGLE_DOUT 0x00 32 33 /* 34 * Range for AD7606B channels are stored in registers starting with address 0x3. 35 * Each register stores range for 2 channels(4 bits per channel). 36 */ 37 #define AD7606_RANGE_CH_MSK(ch) (GENMASK(3, 0) << (4 * ((ch) & 0x1))) 38 #define AD7606_RANGE_CH_MODE(ch, mode) \ 39 ((GENMASK(3, 0) & (mode)) << (4 * ((ch) & 0x1))) 40 #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) 41 #define AD7606_OS_MODE 0x08 42 43 #define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all, \ 44 mask_sep_avail, mask_all_avail, bits) { \ 45 .type = IIO_VOLTAGE, \ 46 .indexed = 1, \ 47 .channel = num, \ 48 .address = num, \ 49 .info_mask_separate = mask_sep, \ 50 .info_mask_separate_available = \ 51 mask_sep_avail, \ 52 .info_mask_shared_by_type = mask_type, \ 53 .info_mask_shared_by_all = mask_all, \ 54 .info_mask_shared_by_all_available = \ 55 mask_all_avail, \ 56 .scan_index = num, \ 57 .scan_type = { \ 58 .sign = 's', \ 59 .realbits = (bits), \ 60 .storagebits = (bits) > 16 ? 32 : 16, \ 61 .endianness = IIO_CPU, \ 62 }, \ 63 } 64 65 #define AD7606_SW_CHANNEL(num, bits) \ 66 AD760X_CHANNEL(num, \ 67 /* mask separate */ \ 68 BIT(IIO_CHAN_INFO_RAW) | \ 69 BIT(IIO_CHAN_INFO_SCALE), \ 70 /* mask type */ \ 71 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 72 /* mask all */ \ 73 0, \ 74 /* mask separate available */ \ 75 BIT(IIO_CHAN_INFO_SCALE), \ 76 /* mask all available */ \ 77 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 78 bits) 79 80 #define AD7605_CHANNEL(num) \ 81 AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ 82 BIT(IIO_CHAN_INFO_SCALE), 0, 0, 0, 16) 83 84 #define AD7606_CHANNEL(num, bits) \ 85 AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW), \ 86 BIT(IIO_CHAN_INFO_SCALE), \ 87 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 88 0, 0, bits) 89 90 #define AD7616_CHANNEL(num) AD7606_SW_CHANNEL(num, 16) 91 92 #define AD7606_BI_CHANNEL(num) \ 93 AD760X_CHANNEL(num, 0, \ 94 BIT(IIO_CHAN_INFO_SCALE), \ 95 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 96 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 97 0, 0, 16) 98 99 #define AD7606_BI_SW_CHANNEL(num) \ 100 AD760X_CHANNEL(num, \ 101 /* mask separate */ \ 102 BIT(IIO_CHAN_INFO_SCALE), \ 103 /* mask type */ \ 104 0, \ 105 /* mask all */ \ 106 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 107 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 108 /* mask separate available */ \ 109 BIT(IIO_CHAN_INFO_SCALE), \ 110 /* mask all available */ \ 111 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 112 16) 113 114 struct ad7606_state; 115 116 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, 117 struct iio_chan_spec *chan, int ch); 118 typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); 119 120 /** 121 * struct ad7606_chip_info - chip specific information 122 * @channels: channel specification 123 * @max_samplerate: maximum supported samplerate 124 * @name device name 125 * @num_channels: number of channels 126 * @num_adc_channels the number of channels the ADC actually inputs. 127 * @scale_setup_cb: callback to setup the scales for each channel 128 * @sw_setup_cb: callback to setup the software mode if available. 129 * @oversampling_avail pointer to the array which stores the available 130 * oversampling ratios. 131 * @oversampling_num number of elements stored in oversampling_avail array 132 * @os_req_reset some devices require a reset to update oversampling 133 * @init_delay_ms required delay in milliseconds for initialization 134 * after a restart 135 */ 136 struct ad7606_chip_info { 137 const struct iio_chan_spec *channels; 138 unsigned int max_samplerate; 139 const char *name; 140 unsigned int num_adc_channels; 141 unsigned int num_channels; 142 ad7606_scale_setup_cb_t scale_setup_cb; 143 ad7606_sw_setup_cb_t sw_setup_cb; 144 const unsigned int *oversampling_avail; 145 unsigned int oversampling_num; 146 bool os_req_reset; 147 unsigned long init_delay_ms; 148 }; 149 150 /** 151 * struct ad7606_chan_scale - channel scale configuration 152 * @scale_avail pointer to the array which stores the available scales 153 * @num_scales number of elements stored in the scale_avail array 154 * @range voltage range selection, selects which scale to apply 155 * @reg_offset offset for the register value, to be applied when 156 * writing the value of 'range' to the register value 157 */ 158 struct ad7606_chan_scale { 159 #define AD760X_MAX_SCALES 16 160 const unsigned int (*scale_avail)[2]; 161 unsigned int num_scales; 162 unsigned int range; 163 unsigned int reg_offset; 164 }; 165 166 /** 167 * struct ad7606_state - driver instance specific data 168 * @dev pointer to kernel device 169 * @chip_info entry in the table of chips that describes this device 170 * @bops bus operations (SPI or parallel) 171 * @chan_scales scale configuration for channels 172 * @oversampling oversampling selection 173 * @cnvst_pwm pointer to the PWM device connected to the cnvst pin 174 * @base_address address from where to read data in parallel operation 175 * @sw_mode_en software mode enabled 176 * @oversampling_avail pointer to the array which stores the available 177 * oversampling ratios. 178 * @num_os_ratios number of elements stored in oversampling_avail array 179 * @write_scale pointer to the function which writes the scale 180 * @write_os pointer to the function which writes the os 181 * @lock protect sensor state from concurrent accesses to GPIOs 182 * @gpio_convst GPIO descriptor for conversion start signal (CONVST) 183 * @gpio_reset GPIO descriptor for device hard-reset 184 * @gpio_range GPIO descriptor for range selection 185 * @gpio_standby GPIO descriptor for stand-by signal (STBY), 186 * controls power-down mode of device 187 * @gpio_frstdata GPIO descriptor for reading from device when data 188 * is being read on the first channel 189 * @gpio_os GPIO descriptors to control oversampling on the device 190 * @complete completion to indicate end of conversion 191 * @trig The IIO trigger associated with the device. 192 * @data buffer for reading data from the device 193 * @d16 be16 buffer for reading data from the device 194 */ 195 struct ad7606_state { 196 struct device *dev; 197 const struct ad7606_chip_info *chip_info; 198 const struct ad7606_bus_ops *bops; 199 struct ad7606_chan_scale chan_scales[AD760X_MAX_CHANNELS]; 200 unsigned int oversampling; 201 struct pwm_device *cnvst_pwm; 202 void __iomem *base_address; 203 bool sw_mode_en; 204 const unsigned int *oversampling_avail; 205 unsigned int num_os_ratios; 206 struct iio_backend *back; 207 int (*write_scale)(struct iio_dev *indio_dev, int ch, int val); 208 int (*write_os)(struct iio_dev *indio_dev, int val); 209 210 struct mutex lock; /* protect sensor state */ 211 struct gpio_desc *gpio_convst; 212 struct gpio_desc *gpio_reset; 213 struct gpio_desc *gpio_range; 214 struct gpio_desc *gpio_standby; 215 struct gpio_desc *gpio_frstdata; 216 struct gpio_descs *gpio_os; 217 struct iio_trigger *trig; 218 struct completion completion; 219 220 /* 221 * DMA (thus cache coherency maintenance) may require the 222 * transfer buffers to live in their own cache lines. 223 * 16 * 16-bit samples + 64-bit timestamp - for AD7616 224 * 8 * 32-bit samples + 64-bit timestamp - for AD7616C-18 (and similar) 225 */ 226 union { 227 u16 buf16[20]; 228 u32 buf32[10]; 229 } data __aligned(IIO_DMA_MINALIGN); 230 __be16 d16[2]; 231 }; 232 233 /** 234 * struct ad7606_bus_ops - driver bus operations 235 * @iio_backend_config function pointer for configuring the iio_backend for 236 * the compatibles that use it 237 * @read_block function pointer for reading blocks of data 238 * @sw_mode_config: pointer to a function which configured the device 239 * for software mode 240 * @reg_read function pointer for reading spi register 241 * @reg_write function pointer for writing spi register 242 * @write_mask function pointer for write spi register with mask 243 * @update_scan_mode function pointer for handling the calls to iio_info's update_scan 244 * mode when enabling/disabling channels. 245 * @rd_wr_cmd pointer to the function which calculates the spi address 246 */ 247 struct ad7606_bus_ops { 248 /* more methods added in future? */ 249 int (*iio_backend_config)(struct device *dev, struct iio_dev *indio_dev); 250 int (*read_block)(struct device *dev, int num, void *data); 251 int (*sw_mode_config)(struct iio_dev *indio_dev); 252 int (*reg_read)(struct ad7606_state *st, unsigned int addr); 253 int (*reg_write)(struct ad7606_state *st, 254 unsigned int addr, 255 unsigned int val); 256 int (*update_scan_mode)(struct iio_dev *indio_dev, const unsigned long *scan_mask); 257 u16 (*rd_wr_cmd)(int addr, char isWriteOp); 258 }; 259 260 /** 261 * struct ad7606_bus_info - agregate ad7606_chip_info and ad7606_bus_ops 262 * @chip_info entry in the table of chips that describes this device 263 * @bops bus operations (SPI or parallel) 264 */ 265 struct ad7606_bus_info { 266 const struct ad7606_chip_info *chip_info; 267 const struct ad7606_bus_ops *bops; 268 }; 269 270 int ad7606_probe(struct device *dev, int irq, void __iomem *base_address, 271 const struct ad7606_chip_info *info, 272 const struct ad7606_bus_ops *bops); 273 274 int ad7606_reset(struct ad7606_state *st); 275 276 extern const struct ad7606_chip_info ad7605_4_info; 277 extern const struct ad7606_chip_info ad7606_8_info; 278 extern const struct ad7606_chip_info ad7606_6_info; 279 extern const struct ad7606_chip_info ad7606_4_info; 280 extern const struct ad7606_chip_info ad7606b_info; 281 extern const struct ad7606_chip_info ad7606c_16_info; 282 extern const struct ad7606_chip_info ad7606c_18_info; 283 extern const struct ad7606_chip_info ad7607_info; 284 extern const struct ad7606_chip_info ad7608_info; 285 extern const struct ad7606_chip_info ad7609_info; 286 extern const struct ad7606_chip_info ad7616_info; 287 288 #ifdef CONFIG_PM_SLEEP 289 extern const struct dev_pm_ops ad7606_pm_ops; 290 #define AD7606_PM_OPS (&ad7606_pm_ops) 291 #else 292 #define AD7606_PM_OPS NULL 293 #endif 294 295 #endif /* IIO_ADC_AD7606_H_ */ 296