1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 25 #include "hw/i386/x86-iommu.h" 26 #include "qemu/iova-tree.h" 27 #include "qom/object.h" 28 29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 30 OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE) 31 32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region" 33 34 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 35 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 36 37 #define VTD_PCI_BUS_MAX 256 38 #define VTD_PCI_SLOT_MAX 32 39 #define VTD_PCI_FUNC_MAX 8 40 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 41 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 42 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 43 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 44 45 #define DMAR_REG_SIZE 0x230 46 #define VTD_HOST_AW_39BIT 39 47 #define VTD_HOST_AW_48BIT 48 48 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_48BIT 49 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) 50 #define VTD_MGAW_FROM_CAP(cap) ((cap >> 16) & 0x3fULL) 51 52 #define DMAR_REPORT_F_INTR (1) 53 54 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 55 #define VTD_MSI_ADDR_HI_SHIFT (32) 56 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 57 58 typedef struct VTDContextEntry VTDContextEntry; 59 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 60 typedef struct VTDAddressSpace VTDAddressSpace; 61 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 62 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 63 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 64 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; 65 typedef struct VTDPASIDEntry VTDPASIDEntry; 66 67 /* Context-Entry */ 68 struct VTDContextEntry { 69 union { 70 struct { 71 uint64_t lo; 72 uint64_t hi; 73 }; 74 struct { 75 uint64_t val[4]; 76 }; 77 }; 78 }; 79 80 struct VTDContextCacheEntry { 81 /* The cache entry is obsolete if 82 * context_cache_gen!=IntelIOMMUState.context_cache_gen 83 */ 84 uint32_t context_cache_gen; 85 struct VTDContextEntry context_entry; 86 }; 87 88 /* PASID Directory Entry */ 89 struct VTDPASIDDirEntry { 90 uint64_t val; 91 }; 92 93 /* PASID Table Entry */ 94 struct VTDPASIDEntry { 95 uint64_t val[8]; 96 }; 97 98 struct VTDAddressSpace { 99 PCIBus *bus; 100 uint8_t devfn; 101 uint32_t pasid; 102 AddressSpace as; 103 IOMMUMemoryRegion iommu; 104 MemoryRegion root; /* The root container of the device */ 105 MemoryRegion nodmar; /* The alias of shared nodmar MR */ 106 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 107 MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ 108 IntelIOMMUState *iommu_state; 109 VTDContextCacheEntry context_cache_entry; 110 QLIST_ENTRY(VTDAddressSpace) next; 111 /* Superset of notifier flags that this address space has */ 112 IOMMUNotifierFlag notifier_flags; 113 /* 114 * @iova_tree traces mapped IOVA ranges. 115 * 116 * The tree is not needed if no MAP notifier is registered with current 117 * VTD address space, because all guest invalidate commands can be 118 * directly passed to the IOMMU UNMAP notifiers without any further 119 * reshuffling. 120 * 121 * The tree OTOH is required for MAP typed iommu notifiers for a few 122 * reasons. 123 * 124 * Firstly, there's no way to identify whether an PSI (Page Selective 125 * Invalidations) or DSI (Domain Selective Invalidations) event is an 126 * MAP or UNMAP event within the message itself. Without having prior 127 * knowledge of existing state vIOMMU doesn't know whether it should 128 * notify MAP or UNMAP for a PSI message it received when caching mode 129 * is enabled (for MAP notifiers). 130 * 131 * Secondly, PSI messages received from guest driver can be enlarged in 132 * range, covers but not limited to what the guest driver wanted to 133 * invalidate. When the range to invalidates gets bigger than the 134 * limit of a PSI message, it can even become a DSI which will 135 * invalidate the whole domain. If the vIOMMU directly notifies the 136 * registered device with the unmodified range, it may confuse the 137 * registered drivers (e.g. vfio-pci) on either: 138 * 139 * (1) Trying to map the same region more than once (for 140 * VFIO_IOMMU_MAP_DMA, -EEXIST will trigger), or, 141 * 142 * (2) Trying to UNMAP a range that is still partially mapped. 143 * 144 * That accuracy is not required for UNMAP-only notifiers, but it is a 145 * must-to-have for notifiers registered with MAP events, because the 146 * vIOMMU needs to make sure the shadow page table is always in sync 147 * with the guest IOMMU pgtables for a device. 148 */ 149 IOVATree *iova_tree; 150 }; 151 152 struct VTDIOTLBEntry { 153 uint64_t gfn; 154 uint16_t domain_id; 155 uint32_t pasid; 156 uint64_t pte; 157 uint64_t mask; 158 uint8_t access_flags; 159 uint8_t pgtt; 160 }; 161 162 /* VT-d Source-ID Qualifier types */ 163 enum { 164 VTD_SQ_FULL = 0x00, /* Full SID verification */ 165 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 166 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 167 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 168 VTD_SQ_MAX, 169 }; 170 171 /* VT-d Source Validation Types */ 172 enum { 173 VTD_SVT_NONE = 0x00, /* No validation */ 174 VTD_SVT_ALL = 0x01, /* Do full validation */ 175 VTD_SVT_BUS = 0x02, /* Validate bus range */ 176 VTD_SVT_MAX, 177 }; 178 179 /* Interrupt Remapping Table Entry Definition */ 180 union VTD_IR_TableEntry { 181 struct { 182 #if HOST_BIG_ENDIAN 183 uint64_t dest_id:32; /* Destination ID */ 184 uint64_t __reserved_1:8; /* Reserved 1 */ 185 uint64_t vector:8; /* Interrupt Vector */ 186 uint64_t irte_mode:1; /* IRTE Mode */ 187 uint64_t __reserved_0:3; /* Reserved 0 */ 188 uint64_t __avail:4; /* Available spaces for software */ 189 uint64_t delivery_mode:3; /* Delivery Mode */ 190 uint64_t trigger_mode:1; /* Trigger Mode */ 191 uint64_t redir_hint:1; /* Redirection Hint */ 192 uint64_t dest_mode:1; /* Destination Mode */ 193 uint64_t fault_disable:1; /* Fault Processing Disable */ 194 uint64_t present:1; /* Whether entry present/available */ 195 #else 196 uint64_t present:1; /* Whether entry present/available */ 197 uint64_t fault_disable:1; /* Fault Processing Disable */ 198 uint64_t dest_mode:1; /* Destination Mode */ 199 uint64_t redir_hint:1; /* Redirection Hint */ 200 uint64_t trigger_mode:1; /* Trigger Mode */ 201 uint64_t delivery_mode:3; /* Delivery Mode */ 202 uint64_t __avail:4; /* Available spaces for software */ 203 uint64_t __reserved_0:3; /* Reserved 0 */ 204 uint64_t irte_mode:1; /* IRTE Mode */ 205 uint64_t vector:8; /* Interrupt Vector */ 206 uint64_t __reserved_1:8; /* Reserved 1 */ 207 uint64_t dest_id:32; /* Destination ID */ 208 #endif 209 #if HOST_BIG_ENDIAN 210 uint64_t __reserved_2:44; /* Reserved 2 */ 211 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 212 uint64_t sid_q:2; /* Source-ID Qualifier */ 213 uint64_t source_id:16; /* Source-ID */ 214 #else 215 uint64_t source_id:16; /* Source-ID */ 216 uint64_t sid_q:2; /* Source-ID Qualifier */ 217 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 218 uint64_t __reserved_2:44; /* Reserved 2 */ 219 #endif 220 } QEMU_PACKED irte; 221 uint64_t data[2]; 222 }; 223 224 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 225 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 226 227 /* Programming format for MSI/MSI-X addresses */ 228 union VTD_IR_MSIAddress { 229 struct { 230 #if HOST_BIG_ENDIAN 231 uint32_t __head:12; /* Should always be: 0x0fee */ 232 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 233 uint32_t int_mode:1; /* Interrupt format */ 234 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 235 uint32_t index_h:1; /* Interrupt index bit 15 */ 236 uint32_t __not_care:2; 237 #else 238 uint32_t __not_care:2; 239 uint32_t index_h:1; /* Interrupt index bit 15 */ 240 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 241 uint32_t int_mode:1; /* Interrupt format */ 242 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 243 uint32_t __head:12; /* Should always be: 0x0fee */ 244 #endif 245 } QEMU_PACKED addr; 246 uint32_t data; 247 }; 248 249 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 250 #define VTD_IR_MSI_DATA (0) 251 252 /* The iommu (DMAR) device state struct */ 253 struct IntelIOMMUState { 254 X86IOMMUState x86_iommu; 255 MemoryRegion csrmem; 256 MemoryRegion mr_nodmar; 257 MemoryRegion mr_ir; 258 MemoryRegion mr_sys_alias; 259 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 260 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 261 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 262 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 263 uint32_t version; 264 265 bool caching_mode; /* RO - is cap CM enabled? */ 266 bool scalable_mode; /* RO - is Scalable Mode supported? */ 267 bool flts; /* RO - is stage-1 translation supported? */ 268 bool snoop_control; /* RO - is SNP filed supported? */ 269 270 dma_addr_t root; /* Current root table pointer */ 271 bool root_scalable; /* Type of root table (scalable or not) */ 272 bool dmar_enabled; /* Set if DMA remapping is enabled */ 273 274 uint16_t iq_head; /* Current invalidation queue head */ 275 uint16_t iq_tail; /* Current invalidation queue tail */ 276 dma_addr_t iq; /* Current invalidation queue pointer */ 277 uint16_t iq_size; /* IQ Size in number of entries */ 278 bool iq_dw; /* IQ descriptor width 256bit or not */ 279 bool qi_enabled; /* Set if the QI is enabled */ 280 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 281 282 /* The index of the Fault Recording Register to be used next. 283 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 284 */ 285 uint16_t next_frcd_reg; 286 287 uint64_t cap; /* The value of capability reg */ 288 uint64_t ecap; /* The value of extended capability reg */ 289 290 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 291 GHashTable *iotlb; /* IOTLB */ 292 293 GHashTable *vtd_address_spaces; /* VTD address spaces */ 294 VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space cache */ 295 /* list of registered notifiers */ 296 QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; 297 298 GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ 299 300 /* interrupt remapping */ 301 bool intr_enabled; /* Whether guest enabled IR */ 302 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 303 uint32_t intr_size; /* Number of IR table entries */ 304 bool intr_eime; /* Extended interrupt mode enabled */ 305 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 306 bool buggy_eim; /* Force buggy EIM unless eim=off */ 307 uint8_t aw_bits; /* Host/IOVA address width (in bits) */ 308 bool dma_drain; /* Whether DMA r/w draining enabled */ 309 bool dma_translation; /* Whether DMA translation supported */ 310 bool pasid; /* Whether to support PASID */ 311 bool fs1gp; /* First Stage 1-GByte Page Support */ 312 313 /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */ 314 bool stale_tm; 315 316 /* 317 * Protects IOMMU states in general. Currently it protects the 318 * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. 319 */ 320 QemuMutex iommu_lock; 321 }; 322 323 /* Find the VTD Address space associated with the given bus pointer, 324 * create a new one if none exists 325 */ 326 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, 327 int devfn, unsigned int pasid); 328 329 #endif 330